Integrated high-voltage power device and power switch comprising same

Abstract

The utility model discloses an integrated high-voltage power device and a power switch comprising the high-voltage power device. The high-voltage power device comprises a plurality of first transistors; the drain electrodes of the plurality of first transistors are electrically connected with the drain electrodes of the one or more second transistors, the grid electrodes of the plurality of first transistors are electrically connected, the grid electrodes of the one or more second transistors are electrically connected, and the drain electrodes of the plurality of first transistors are electrically connected with the drain electrodes of the one or more second transistors. The one or more second transistors are distributed at one or more locations of the high voltage power device and are configured to detect temperatures at the one or more locations.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor devices and circuits, and in particular to an integrated high-voltage power device and a power switch including the high-voltage power device. Background Technology

[0002] Intelligent power switches are circuits that integrate high-voltage devices and low-voltage logic, and are widely used in industrial automation, automotive electronics, and other fields. An intelligent power switch integrates high-voltage power devices capable of handling large currents with low-voltage control logic that provides control and protection functions. It enables intelligent control of the power devices and provides load drive and protection functions to external devices.

[0003] refer to Figure 1 The related system-in-package (SIP) solution for intelligent power switches uses a thermistor attached to the outside of the power transistor. Temperature monitoring is performed using a current sampling resistor. Current sampling and overcurrent protection are performed in series. The disadvantages of this approach are: the external thermistor and current sampling resistor are used separately, resulting in low system integration; furthermore, the external current sensing resistor should be a high-power, high-precision, low-resistance device to avoid power current exceeding the current sampling resistor's resistance. This results in significant power loss and voltage drop, and the small voltage on the order of millivolts (mV) across the current sensing resistor makes voltage detection in the subsequent stage difficult. Utility Model Content

[0004] In view of the above-mentioned technical problems, this application proposes an integrated high-voltage power device and a power switch including the integrated high-voltage power device to solve the problems of low integration, high power loss and difficulty in voltage detection of related power switches.

[0005] In a first aspect, this application provides an integrated high-voltage power device comprising: a plurality of first transistors; and one or more second transistors integrated with the plurality of first transistors, wherein the drains of the plurality of first transistors and the drains of the one or more second transistors are electrically connected, the gates of the plurality of first transistors are electrically connected, the gates of the one or more second transistors are electrically connected, and the one or more second transistors are distributed at one or more locations of the high-voltage power device and configured to detect the temperature at the one or more locations.

[0006] Optionally, the plurality of first transistors include: a main power transistor configured to allow external current to flow through the high-voltage power device; a current detection transistor configured to detect the current flowing through the high-voltage power device; and an overcurrent protection transistor configured to provide overcurrent protection for the main power transistor.

[0007] Optionally, the ratio between the area of ​​the active region of the main power transistor and the area of ​​the active region of the current sensing transistor is K:1; the ratio between the active region of the main power transistor and the active region of the overcurrent protection transistor is N:1, where both K and N are greater than 1.

[0008] Optionally, the main power transistor and the overcurrent protection transistor share a first chip substrate; the main power transistor and the current detection transistor share a second chip substrate.

[0009] Optionally, the first chip substrate and the second chip substrate are the same chip substrate.

[0010] Secondly, this application provides a power switch. The power switch includes a high-voltage power device according to the first aspect above and a driver chip. The driver chip includes: a gate drive circuit electrically connected to the plurality of first transistors and configured to provide a gate drive voltage to the gates of the plurality of first transistors; a current detection circuit electrically connected to the current detection transistor and configured to detect the current flowing through the main power transistor; an overcurrent protection circuit electrically connected to the overcurrent protection transistor and the gate drive circuit, and configured to cause the gate drive circuit to stop providing the drive voltage to the plurality of first transistors when the current in the main power transistor exceeds a current threshold, thereby achieving overcurrent protection; and one or more overtemperature protection circuits electrically connected to the gate drive circuit and the one or more second transistors, wherein each of the one or more overtemperature protection circuits is configured to cause the gate drive circuit to stop providing the drive voltage to the plurality of first transistors when the temperature at any of the one or more locations exceeds a temperature threshold, thereby achieving overtemperature protection.

[0011] Optionally, the gate driving circuit includes: a level shifting circuit configured to receive an input control signal and generate a first control signal based on the input control signal; protection logic, the input terminal of which is electrically connected to the overcurrent protection circuit and the one or more overtemperature protection circuits, and configured to receive an overcurrent protection signal from the overcurrent protection circuit, receive an overtemperature protection signal from the one or more overtemperature protection circuits, and generate a protection signal based on the overcurrent protection signal and the overtemperature protection signal; a driver electrically connected to the level shifting circuit and the protection logic, and configured to turn on or off the plurality of first transistors based on the protection signal and the first control signal; and a charge pump electrically connected to the driver and the level shifting circuit, and configured to supply power to the driver and the level shifting circuit.

[0012] Optionally, the current detection circuit includes: a first operational amplifier, wherein the two input terminals of the first operational amplifier are electrically connected to the source of the main power transistor and the source of the current detection transistor, respectively; a first current mirror, wherein the input terminal of the first current mirror is electrically connected to the source of the current detection transistor and the output terminal of the first operational amplifier; a second current mirror, wherein the input terminal of the second current mirror is electrically connected to the output terminal of the first current mirror; a first switch array, electrically connected to the output terminal of the second current mirror and including a plurality of first switches, wherein one or more of the plurality of first switches are selectively turned on or off; and a first detector, electrically connected to the first switch array and detecting the current flowing through the main power transistor.

[0013] Optionally, the overcurrent protection circuit includes: a second operational amplifier, wherein the two input terminals of the second operational amplifier are electrically connected to the source of the main power transistor and the source of the overcurrent protection transistor, respectively; a third current mirror, wherein the input terminal of the third current mirror is electrically connected to the source of the overcurrent protection transistor and the output terminal of the second operational amplifier; a fourth current mirror, wherein the input terminal of the fourth current mirror is electrically connected to the output terminal of the third current mirror; a second switch array, electrically connected to the output terminal of the fourth current mirror and including a plurality of second switches, wherein one or more of the plurality of second switches are selectively turned on or off; a first comparator, electrically connected to one end of the second switch array, and comparing the voltage at the one end of the second switch array with a reference voltage to obtain a comparison result; and overcurrent protection logic, electrically connected to the output terminal of the first comparator, and causing the gate drive circuit to stop providing drive voltage to the plurality of first transistors when the comparison result exceeds the current threshold.

[0014] Optionally, each of the one or more over-temperature protection circuits includes: a current source configured to generate a current independent of temperature changes; a fifth current mirror, wherein the input terminal of the fifth current mirror is electrically connected to the current source; a third switch array including a plurality of third switches, each of the plurality of third switches being electrically connected to a corresponding output terminal of the fifth current mirror; a first resistor, a first terminal of the first resistor being electrically connected to the source of a corresponding over-temperature protection transistor in the one or more over-temperature protection transistors; a second comparator electrically connected to a second terminal of the first resistor and configured to compare the voltage at the second terminal with a reference voltage to obtain a comparison result; and over-temperature protection logic electrically connected to the output terminal of the second comparator and configured to cause the gate drive circuit to stop providing drive voltage to the plurality of first transistors when the comparison result exceeds a specific threshold.

[0015] The integrated high-voltage power device and the power switch including the high-voltage power device provided by this utility model have the following beneficial effects:

[0016] By designing metal-oxide-semiconductor field-effect transistors (MOS) of varying sizes using a shielded gate trench SGT / Trench process, and integrating current sensing devices into vertically double-diffused metal-oxide-semiconductor (VDMOS) transistors, the current sensing accuracy is improved, and the system integration is enhanced. Similarly, by designing multiple MOS transistors of different sizes using the SGT / Trench process and integrating temperature sensing devices into the VDMOS transistors, temperature monitoring accuracy is improved. Furthermore, by placing the temperature sensing MOS transistors at different locations on the power transistor, errors caused by external temperature sensors due to positional deviations or thermal conduction delays are avoided, further enhancing system integration. In addition, the driver chip in the power switch of this application allows for programmable control of temperature protection, overcurrent protection, and current sensing ratios, increasing the flexibility and practical application range of the system. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 This is a schematic diagram of the relevant power switch structure;

[0019] Figure 2A This is a circuit diagram of the integrated high-voltage power device of this application;

[0020] Figure 2B This is a schematic cross-sectional view of the transistor structure of the integrated high-voltage power device of this application;

[0021] Figure 2C This is a simplified circuit diagram of the integrated high-voltage power device of this application;

[0022] Figure 3A This is a schematic diagram of the structure of the intelligent power switch of this application;

[0023] Figure 3B This is an external schematic diagram of the SIP package of the intelligent power switch of this application;

[0024] Figure 4 This is a schematic diagram of the gate drive circuit in the intelligent power switch of this application;

[0025] Figure 5A This is a schematic diagram of the charge pump in the gate drive circuit of the intelligent power switch of this application;

[0026] Figure 5B This is a schematic diagram of the driver in the gate drive circuit of the intelligent power switch of this application;

[0027] Figure 6 This is a schematic diagram of the programmable current detection circuit in the intelligent power switch of this application;

[0028] Figure 7 This is a schematic diagram of the programmable overcurrent protection circuit in the intelligent power switch of this application; and

[0029] Figure 8 This is a schematic diagram of the programmable over-temperature protection circuit in the intelligent power switch of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, and “multiple” generally includes at least two unless the context clearly indicates otherwise.

[0032] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0033] The purpose of this application is to propose a novel power device based on high-voltage technology. This high-voltage power device is an integrated chip that includes a temperature sensing transistor, a current sensing transistor, and an overcurrent protection transistor. At the same time, current detection, temperature detection, over-temperature protection, and overcurrent protection are performed in the driver chip section to solve the problems existing in related technologies.

[0034] refer to Figure 2A-2C , Figure 2A A circuit diagram of the on-chip integrated high-voltage power device 1 provided in this application is shown. Figure 2B A cross-sectional schematic diagram of the on-chip integrated high-voltage power device 1 of this application is shown. Figure 2CA simplified circuit diagram of the high-voltage power device 1 is shown. The high-voltage power device 1 includes a plurality of first transistors and one or more second transistors integrated with one or more first transistors. In embodiments of this application, the plurality of first transistors and one or more second transistors may use the same substrate, such as... Figure 2B Substrate 101 in. For example, in Figure 2A The diagram shows three first transistors M1-M3 and three second transistors M4-M6. It should be understood that, although in Figure 2A and Figure 2B Three second transistors M4-M6 are shown, but the number of one or more second transistors can be manufactured as needed, for example, P second transistors, where P is a positive integer greater than 3. This high-voltage power device 1 is manufactured using Vertical Double-Diffused Metal-Oxide-Semiconductor (VDMOS) technology, and employs trench or Shielded Gate Trench (SGT) processes to fabricate multiple first transistors and one or more second transistors. Specifically, the multiple second transistors M4-M6 are located on the same layer as the first transistors M1-M3, use the same substrate 101, and are integrated on the same chip. Figure 2B As shown, the second transistors M4-M6 are used for temperature detection and are arranged according to the requirements of the temperature detection location, for example, in the center of the chip or at the edge of the chip. VDMOS technology, as well as SGT and Trench technologies, are known to those skilled in the art and will not be described in detail here.

[0035] In some embodiments, each of the plurality of first transistors M1-M3 is a metal-oxide-semiconductor (MOS) transistor, the drains D of the plurality of first transistors M1-M3 share a common substrate 101, and their gates G1 are electrically connected to the same potential. Each of the one or more second transistors M4-M6 is a MOS transistor, the drains D of the plurality of second transistors M4-M6 share a common substrate 101, and their gates G are electrically connected to the same potential. The one or more second transistors M4-M6 are distributed at one or more locations of the high-voltage power device 1 and configured to detect the temperature at one or more locations.

[0036] In some embodiments, the plurality of first transistors M1-M3 include a main power transistor M1 configured to allow external current to flow through the high-voltage power device 1; a current sensing transistor M2 for detecting the external current flowing through the high-voltage power device 1; and an overcurrent protection transistor M3 for overcurrent protection of the main power transistor M1.

[0037] In some embodiments, the ratio of the area of ​​the active region of the main power transistor M1 to the area of ​​the active region of the current sensing transistor M2 is K:1, that is, the ratio of the number of cells in M1 to the number of cells in M2 is K:1. K is greater than 1, such as... Figure 6 As shown.

[0038] In some embodiments, the ratio of the area of ​​the active region of the main power transistor M1 to the area of ​​the active region of the overcurrent protection transistor M3 is N:1, that is, the ratio of the number of cells in M1 to the number of cells in M3 is N:1. N is greater than 1, such as... Figure 7 As shown.

[0039] In this application's technical solution, transistors M1-M6 of different sizes are designed on a high-voltage power device based on SGT / Trench technology. The current sensing transistor M2 and the main power transistor M1 are integrated using a VDMOS configuration. This improves both the accuracy of current sensing and the system integration. The high-voltage power device 1 of this application is suitable for high-voltage ranges, such as 30V-100V, 20V-200V, and 15V-250V. Furthermore, temperature sensing transistors M4-M6 are integrated with the main power transistor M1 using a VDMOS configuration. Since temperature sensing is not performed externally, temperature monitoring is more accurate. Moreover, by placing the temperature sensing transistors M4-M6 at different positions on the high-voltage power transistor M1, errors caused by external temperature sensors due to positional deviations or thermal conduction delays are avoided, further improving system integration.

[0040] The following is a schematic diagram of the structure of the intelligent power switch of this application. This intelligent power switch utilizes the high-voltage power device described in the above embodiments of this application.

[0041] refer to Figure 3A , Figure 3A This diagram illustrates the structure of the intelligent power switch described in this application. The intelligent power switch of this application includes the components described above. Figure 2A-2CThe high-voltage power device 1 and the driver chip 2 are shown. The driver chip 2 includes: a gate drive circuit 21 electrically connected to the gates of a plurality of first transistors M1-M3 and configured to provide a gate drive voltage to the gates of the plurality of first transistors M1-M3; a current detection circuit 22 electrically connected to a current detection transistor M2 and configured to detect the current flowing through the main power transistor M1; an overcurrent protection circuit 23 electrically connected to the overcurrent protection transistor M3 and the gate drive circuit 21 and configured to cause the gate drive circuit 21 to stop providing a drive voltage to the plurality of first transistors M1-M3 when the current of the main power transistor M1 exceeds a current threshold TH1, thereby generating overcurrent protection for the main power transistor M1; and an overtemperature protection circuit 24 electrically connected to the gate drive circuit 21 and one or more second transistors M4-M6 and configured to cause the gate drive circuit 21 to stop providing a drive voltage to the plurality of first transistors M1-M3 when the temperature of any one of the one or more locations of the one or more second transistors M4-M6 exceeds a temperature threshold TH1, thereby forming overtemperature protection for the main power transistor M1.

[0042] In the embodiments of this application, the driver chip 2 and the high-voltage power device 1 are packaged together using a system-in-package (SIP). The external structure of this SIP package is as follows: Figure 3B As shown,

[0043] The driver chip 2 is designed and fabricated using a BCD (Bipolar-CMOS-DMOS) high-voltage process, while the high-voltage power device 1 is designed and fabricated using an SGT or Trench process. Finally, the two are integrated using a SiP (System-in-Package) method. Figure 3B This diagram illustrates a SiP (System-in-Package) integration method for a high-voltage power device 1 and a driver chip 2. The back side of the high-voltage power device 1 is the drain (D) terminal. Figure 3B Terminals S1-S6 in the middle are respectively Figure 2A Terminals S1-S6, G1 is Figure 2A Gate terminals G1 and G2 are Figure 2A The gate terminal G2 in the circuit can be connected to the base island by wire bonding G2 (the gate of the MOS transistors M4-M6 used for temperature sensing). Other ports are connected to the corresponding pads on the driver chip 2 via wire bonding.

[0044] Optionally, in specific applications, the S1 terminal of the main power transistor M1 of the intelligent power switch is also connected in series with an external inductor L. load and external resistance R load Inductor L load and resistance R loadThe setup and parameters are similar to those of related smart power switches. This is achieved by setting the inductor L... load and resistance R load The voltage and inductance on the intelligent power switch can be adjusted, which will not be described in detail here.

[0045] The gate drive circuit 21 of the intelligent power switch of this application is described below. (Reference) Figure 4 , Figure 4 This is a schematic diagram of the gate drive circuit of the intelligent power switch of this application. The gate drive circuit 21 includes input control logic 211, level conversion circuit 212 and driver 215. The input control logic 211 is configured to receive the input control signal IN and output the input control signal IN to the level conversion circuit 212 when the input control signal IN of the input control logic 211 is at the first level.

[0046] Level conversion circuit 212 is configured to receive input control signal IN from input control logic 211 and generate a first control signal Dp based on input control signal IN. The first control signal Dp is used to turn driver 215 on or off multiple first transistors M1-M3. Vs is the system power supply, typically 4~28V, with a typical application value of 13.5V. Specifically, input control logic 211 receives input control signal IN from the outside. Input control signal IN is a low-voltage domain signal with a first level, such as a 0~5V signal. Level conversion circuit 212 receives input control signal IN from input control logic 211 and converts input control signal IN into a high-voltage domain level signal Dp (the high-voltage domain level signal Dp can be a level signal between Out and Vboot). The high-voltage domain level signal Dp can control driver 215 to turn on or off, and driver 215 drives the charging or discharging of the gate capacitance of MOSFETs M1-M3. When driver 215 is turned on, driver 215 outputs a high level, and the charging current charges the gate capacitance of MOSFETs M1-M3, turning S... G Pulling the voltage high to Vboot turns on power MOSFETs M1-M3. Driver 215 turns off (i.e., it outputs a low level), and the discharge current discharges the gate capacitance of MOSFETs M1-M3, thus turning on S... G Pull it low to Out to turn off power MOSFETs M1-M3.

[0047] Optionally, the gate drive circuit 21 further includes protection logic 213 and a charge pump 214. Protection logic 213 is electrically connected to one input of driver 215 and configured to receive an overcurrent protection signal Sc_p from overcurrent protection circuit 23 and an overtemperature protection signal St_p from overtemperature protection circuit 24, and generate a protection signal Sp based on the overcurrent protection signal Sc_p and the overtemperature protection signal St_p. The protection signal Sp can cause driver 215 to discharge the gate capacitance of main power transistor M1, pulling the gate-source voltage Vgs of main power transistor M1 down to 0, thereby turning off power MOSFETs M1-M3, thus achieving the purpose of protecting power MOSFETs M1-M3.

[0048] Optionally, the gate drive circuit further includes a charge pump 214, which includes an input terminal and an output terminal. The input terminal of the charge pump 214 is connected to the power supply Vs, and the output terminal of the charge pump 214 is connected to the driver 215 and the level conversion circuit 212. Figure 5A As shown. The charge pump 214 includes MOSFETs NM1 and NM2, MOSFETs PM1 and PM2, capacitors C1, C2, and Cout. The gates and drains of MOSFETs NM1 and NM2 are cross-connected, and the gates and drains of MOSFETs PM1 and PM2 in the charge pump 214 are also cross-connected. One end of capacitor C1 is electrically connected to the gate of MOSFET PM2, and one end of capacitor C2 is electrically connected to the gate of MOSFET PM1. The other end of capacitor C1 is connected to the first pulse signal input terminal clk1, and the other end of capacitor C2 is connected to the second pulse signal input terminal clk2. The charge pump 214 receives level pulse signals clk1 and clk2 from the outside through capacitors C1 and C2. The level pulse signals clk1 and clk2 have the same frequency but opposite phase. The voltage range of clk1 and clk2 is Vs to Vs-5V. Utilizing the characteristics of capacitors, capacitors C1 and C2 are charged through the power supply Vs, so that the storage voltage on C1 and C2 is 5V. During the charging process of the load capacitor Cout, capacitors C1 and C2 alternately discharge Cout, raising the voltage on Cout from Vs to Vboot = Vs + 5V. The charge pump 214 circuit adopts a cross-coupled charge pump structure. This circuit uses periodic level pulse signals clk1 and clk2 to alternately control the charging and discharging of capacitors C1 and C2. It utilizes the high-frequency clock signals clk1 and clk2 and the characteristics of the capacitors to generate a voltage Vboot that is higher than Vs, thus powering the driver 215 and the level conversion circuit 212.

[0049] refer to Figure 5B , Figure 5BThis is a schematic diagram of the gate driver 215. Driver 215 includes an AND gate and a cascade of multiple drivers with progressively increasing driving capabilities. When a drive signal is received (Dp is logic high) and the circuit is not under protection (Sp is logic low), the drive output is high, charging the gate capacitors of power transistors M1-M3, thus charging S... G When the output voltage is pulled high (Vboot), power MOSFETs M1-M3 are turned on. OUT is used to provide "floating ground" for the driver.

[0050] The current detection function, overcurrent protection function, and overtemperature protection function of the intelligent power switch of this application are described below.

[0051] Figure 6 This is a schematic diagram of the current detection circuit 22 of the driver chip in this application. Figure 6 As shown, the current detection circuit 22 of the driver chip 2 includes: a first operational amplifier 221, whose two input terminals are respectively connected to the source (S) terminal of the main power transistor M1 and the source (S) terminal of the current detection transistor M2, and configured to clamp the source (S) terminals of the main power transistor M1 and the current detection transistor M2 to the same voltage; and a first current mirror 222, whose input terminal is electrically connected to the source of the current detection transistor M2 and the output terminal of the first operational amplifier 221, and configured to measure the current I flowing through the current detection transistor M2. sense-load1 The current is mirrored to the output terminal; a second current mirror 225, the input terminal of which is electrically connected to the output terminal of the first current mirror 222 and mirrors the current at the input terminal to the output terminal; a first switch array 223, configured to be electrically connected to the second current mirror 225 and control the output current I of the current detection circuit 22. sense The first detector 224 is configured to detect the output current I of the current detection circuit 22. sense To obtain the current I flowing through the main power transistor. load .

[0052] Specifically, refer to Figure 6 The gate drive circuit 21 provides gate drive voltages to the main power transistor M1 and the current sensing transistor M2, thereby controlling the on and off states of the main power transistor M1 and the current sensing transistor M2. The positive input terminal In+ and the negative input terminal In- of the first operational amplifier 221 are connected to the source (S) terminals of the main power transistor M2 and the current sensing transistor M1, respectively. Figure 6In the original design, the positive input terminal In+ is connected to the source (S) terminal of the current sensing transistor M2, and the negative input terminal In- is connected to the source (S) terminal of the main power transistor M1. However, it is understood that the positive input terminal In+ of the first operational amplifier 211 in this application can also be connected to the source (S) terminal of the main power transistor M1, and the negative input terminal In- can be connected to the source (S) terminal of the current sensing transistor M2. This will not be described in detail here.

[0053] The output of the first operational amplifier 221 is connected to the control terminal of the first current mirror 222. The first operational amplifier 221 can control the switching on and off of the first current mirror 222. The input terminal of the first current mirror 222 is connected to the source (S) terminal of the current sensing transistor M2 and is configured to output the current I flowing through the current sensing transistor M2. sense_load1 Mirror to the output.

[0054] The input terminal of the second current mirror 225 is connected to the output terminal of the first current mirror 222. Specifically, the drain of the MOSFET at the input terminal of the second current mirror 225 is connected to the source of the MOSFET at the output terminal of the first current mirror 222, as shown below. Figure 6 As shown, in this case, the current at the output of the first current mirror 222 is the same as the current at the input of the second current mirror 225. Specifically, the second current mirror 225 is a binary current mirror array, which includes multiple MOSFETs. First, a 1:1 current mirror mirror is used to mirror the current in the NMOS transistor M2 in the high-voltage region of the input terminal to the current in the PMOS transistor in the low-voltage region of the output terminal. The multiple PMOS transistors in the second current mirror 225 in the low-voltage region use a binary ratio (1:2:4:8) channel width-to-length ratio W / L, thereby achieving a binary ratio current mirror (1:2:4:8). The working principle of the binary current mirror is a current replication mechanism. The drain-source current formula of the MOSFET is...

[0055]

[0056] in, This is the gate-source voltage; This is the threshold voltage of the MOSFET; This represents the electron mobility in the conductive channel. , where is the gate oxide potential and isotropic capacitance, and is a process-dependent parameter; W and L are the width and length of the MOS transistor. In the binary current mirror circuit, the five PMOS transistors have the same gate-source voltage. Using the same components in the same process, therefore The same applies, so the drain-source currents in these PMOS transistors can be obtained. The ratio is its width-to-length ratio. Thus, by setting the channel width-to-length ratio W / L to obtain a binary ratio (1:2:4:8), a binary ratio mirror current (1:2:4:8) is obtained.

[0057] The binary current mirror array 225 is connected to the first switch array 223. The first switch array 223 includes multiple switches SW0-SW3 and SWn0-SWn3. The current sensing circuit 22 specifically includes a current sensing switch selector 224, configured to control the opening or closing of switches SW0-SW3 and SWn0-SWn3, thereby generating a voltage V across the external resistor Rsense. sense By detecting the external resistance R sense Voltage V on sense It can monitor the current I on the main power transistor M1 in real time. load Furthermore, the output current Isense of the current sensing circuit 22 can be controlled by the current sensing switch selector 224, thereby allowing the output current of the current sensing circuit to be programmed.

[0058] In the embodiments of this application, since the drain (D) terminals of the current-sensing transistor M2 and the main power transistor M1 share a common chip substrate, their gate (G) terminals are connected to the same potential, and their source (S) terminals are clamped to the same voltage by the first operational amplifier 221 in the driver chip 2. Because the active area ratio of the main power transistor M1 to the current-sensing transistor M2 is set to K:1, that is, the cell ratio of the main power transistors M1 and M2 is K:1, where K is greater than 1, when current flows through the main power transistor M1... At this time, since the voltages at the drain (D), gate (G), and source (S) terminals of current sensing transistor M2 are the same as those at the drain (D), gate (G), and source (S) terminals of main power transistor M1, and the cell ratio is 1 / K, the current flowing through current sensing transistor M2 is... In the driver chip section 2, the current is generated using a current mirroring method. The image is mirrored to the second current mirror 225 and controlled by current switches SW0-SW3 or SWn0-SWn3. Finally, an external resistor... Voltage generated on .

[0059]

[0060] The current detection circuit 22 also includes a first detector 226, configured to detect external resistance. voltage on It can monitor in real time the current flowing through the main power transistor M1 (i.e., the current flowing through the load R). load ) current Optionally, external resistors The current passing through is controlled by current switches SW0-SW3 or SWn0-SWn3, thereby realizing programmable control functions.

[0061] Figure 7This is a schematic diagram of the overcurrent protection circuit 23 of the driver chip in this application. Figure 7 As shown, the overcurrent protection circuit 23 of the driver chip 2 includes: a second operational amplifier 231, the two input terminals of which are respectively connected to the source S terminal of the main power transistor M1 and the source S terminal of the overcurrent protection transistor M3, and configured to clamp the source S terminals of the main power transistor M1 and the overcurrent protection transistor M3 at the same voltage; and a third current mirror 232, which is electrically connected to the source of the overcurrent protection transistor M3 and the output terminal of the second operational amplifier 231 and configured to filter the current I in the overcurrent protection transistor M3. sense-load2 Mirroring to the output; a fourth current mirror 236, the input of which is connected to the output of the third current mirror 232 and configured to mirror the current I flowing through the overcurrent protection transistor M3. sense-load2 Mirroring to the output terminal; the second switch array 233 is configured to be electrically connected to the output terminal of the fourth current mirror 236 and control the output current I of the overcurrent protection circuit 23. oc The first comparator 234 is configured to compare the voltage on the external resistor Roc with the first reference voltage and output the comparison result; the overcurrent protection logic 235 is configured to be connected to the output of the first comparator 234 and to cause the gate drive circuit 21 to output a signal to turn off the first transistor M1 when the comparison result exceeds the temperature threshold TH2, thereby providing overcurrent protection for the main power transistor M1.

[0062] Specifically, refer to Figure 7 The gate drive circuit 21 provides gate drive voltages to the main power transistor M1 and the overcurrent protection transistor M3, thereby controlling the on and off states of the main power transistor M1 and the overcurrent protection transistor M3. The negative input terminal In- and the positive input terminal In+ of the second operational amplifier 231 are connected to the source (S) terminals of the main power transistor M1 and the overcurrent protection transistor M3, respectively. Figure 7 In the first operational amplifier, the positive input terminal In+ is connected to the source (S) terminal of the overcurrent protection transistor M3, and the negative input terminal In- is connected to the source (S) terminal of the main power transistor M1. However, it is understood that the positive input terminal In+ of the second operational amplifier 231 can also be connected to the source (S) terminal of the main power transistor M1, and the negative input terminal In- can be connected to the source (S) terminal of the overcurrent protection transistor M3. This will not be described in detail here. The output terminal of the second operational amplifier 231 is connected to the input terminal of the third current mirror 232. The input terminal of the third current mirror 232 is connected to the source (S) terminal of the overcurrent protection transistor M3 and is configured to reflect the current I flowing through the overcurrent protection transistor M3. sense_load2 Mirror to the output.

[0063] Specifically, the input terminal of the fourth current mirror 236 is connected to the output terminal of the third current mirror 232. The drain of the MOSFET at the input terminal of the fourth current mirror 236 is connected to the source of the MOSFET at the output terminal of the third current mirror 232, as shown below. Figure 7 As shown, in this case, the current at the output of the third current mirror 232 is the same as the current at the input of the fourth current mirror 236. Specifically, the fourth current mirror 236 is a binary current mirror array, which includes multiple MOSFETs. First, a 1:1 current mirror mirror is used to mirror the current in the PMOS transistors in the high-voltage region of the input terminal to the current in the PMOS transistors in the low-voltage region of the output terminal. The multiple PMOS transistors in the low-voltage region use a binary ratio (1:2:4:8) channel width-to-length ratio W / L, thereby achieving a binary ratio current mirror (1:2:4:8). The working principle of the binary current mirror is a current replication mechanism. The drain-source current formula of the MOSFET is...

[0064]

[0065] in, This is the gate-source voltage; This is the threshold voltage of the MOSFET; This represents the electron mobility in the conductive channel. , where is the gate oxide potential and isotropic capacitance, and is a process-dependent parameter; W and L are the width and length of the MOS transistor. In the binary current mirror circuit, the five PMOS transistors have the same gate-source voltage. Using the same components in the same process, therefore The same applies, so the drain-source currents in these PMOS transistors can be obtained. The ratio is its width-to-length ratio. Thus, by setting the channel width-to-length ratio W / L to obtain a binary ratio (1:2:4:8), a binary ratio mirror current (1:2:4:8) is obtained.

[0066] The binary current mirror array 236 is connected to the second switch array 233. The second switch array 233 includes multiple switches SW0-SW3 and SWn0-SWn3. The overcurrent protection circuit 23 specifically includes an overcurrent protection switch selector 234, configured to control the opening or closing of switches SW0-SW3 and SWn0-SWn3, thereby programmably controlling the magnitude of the current Ioc flowing through the external resistor Roc, so that a voltage V is generated across the external resistor Roc. oc The first comparator 234 compares the voltage Voc across the external resistor Roc with the first reference voltage V. refThe comparison is performed and the comparison result is output; the overcurrent protection logic 235 obtains the comparison result from the second comparator 234; when the comparison result exceeds the current threshold TH2, the gate drive circuit 21 outputs a signal to turn off the main power transistor M1, thereby providing overcurrent protection for the main power transistor M1.

[0067] In some embodiments, the overcurrent protection switch selector 234 can select the on or off state of switches SW0-SW3 or select the on or off state of switches SWn0-SWn3, thereby adjusting the output current of the overcurrent protection circuit.

[0068] In the embodiments of this application, since the drain (D) terminals of the overcurrent protection transistor M3 and the main power transistor M1 use a common chip substrate, their gate (G) terminals are connected to the same potential, and their source (S) terminals are clamped to the same voltage by the second operational amplifier 231 in the driver chip 2. Because the active region areas of the main power transistor M1 and the overcurrent protection transistor M3 are set to N:1, that is, the cell ratio of the main power transistors M1 and M3 is N:1, where N is greater than 1. When current flows through the main power transistor M1... At this time, since the voltages at the drain (D), gate (G), and source (S) terminals of the overcurrent protection transistor M3 are the same as those at the drain (D), gate (G), and source (S) terminals of the main power transistor M1, and the cell ratio is 1 / N, the current flowing through the overcurrent protection transistor M3 is... In driver chip 2, the current is generated using a current mirroring method. The image is mirrored to a binary and current mirror array 232 and controlled by current switches SW0-SW3 or SWn0-SWn3. Finally, an off-chip resistor is used. Voltage generated on .

[0069]

[0070] The second comparator 234 will convert the voltage With reference voltage The comparison is performed, and the comparison result is output to the overcurrent protection logic 235. When the voltage exceeds the current threshold TH2, the overcurrent protection logic 235 controls the gate drive circuit 21 to turn off the main power transistor M1, thereby providing overcurrent protection for the main power transistor M1.

[0071] Figure 8 This is a schematic diagram of the over-temperature protection circuit of this application. Figure 8As shown, the driver chip 2 includes one or more over-temperature protection circuits 24. The number of the one or more over-temperature protection circuits 24 is the same as the number of the one or more second transistors, and the one or more over-temperature protection circuits 24 correspond one-to-one with the one or more second transistors. Each over-temperature protection circuit 24 includes a current source 241 configured to generate a current independent of temperature changes. The current It can be in the microampere (µA) range (1µA~10µA); the fifth current mirror 242 is configured to reflect the current. Mirrored to the output terminal Iout. The output terminal Iout includes one or more third transistors, in Figure 8 In the fifth current mirror 242, the input terminal includes a transistor M7, and the output terminal includes three transistors M8-M10. The channel length ratio of the three transistors M8-M10 is 1:1:1, thus obtaining the same current (1:1:1). The channel length ratio of the first transistor M7 to the channel length ratio of the three transistors M8-M10 is 1:1:1:1, thus distributing the current... Mirrored onto transistors M8-M10.

[0072] In some embodiments, the over-temperature protection circuit 24 further includes a third switch array 243, which includes one or more switches. Figure 8 The diagram shows a third switch array 243 comprising three switches S8-S10, which are respectively connected to transistors M8-M10.

[0073] In some embodiments, the over-temperature protection circuit 24 further includes a load 244, with a first terminal connected to the source (S) terminal of the over-temperature protection transistor M4 and a second terminal connected to the source terminals of the third transistors M8-M10. By controlling the switches S8-S10, a load current can be generated on the over-temperature protection transistor M4. The over-temperature protection transistor M4 uses a diode connection, meaning its drain and gate are connected to a common electrode. This allows M4 to operate in the saturation region, resulting in a voltage V across its drain and source. DS ,

[0074]

[0075] in, This is the gate-source voltage; This refers to the drain-source current in M4; This represents the electron mobility in the conductive channel. , where is the gate oxide potential area capacitance, and is a process-dependent parameter; W and L are the width and length of the MOS; This is the threshold voltage of the MOSFET M4. It has a negative temperature coefficient. As the temperature increases, reduce, This decreases, thus increasing the voltage at the second terminal of load 244.

[0076] In some embodiments, the over-temperature protection circuit 24 further includes a second comparator 245 configured to input a temperature-independent reference voltage generated by the bandgap. The comparison is performed and a comparison result is generated; the over-temperature protection logic 246 is configured to obtain the comparison result from the second comparator 245, and when the temperature exceeds the temperature threshold TH2, the over-temperature protection logic 246 causes the gate drive circuit 21 to stop providing drive voltage to the main power transistor M1, thereby generating over-temperature protection for the main power transistor M1.

[0077] By designing metal-oxide-semiconductor field-effect transistors (MOS) of varying sizes using a shielded gate trench SGT / Trench process, and integrating current sensing devices into vertically double-diffused metal-oxide-semiconductor (VDMOS) transistors, the current sensing accuracy is improved, and the system integration is enhanced. Similarly, by designing multiple MOS transistors of different sizes using the SGT / Trench process and integrating temperature sensing devices into the VDMOS transistors, temperature monitoring accuracy is improved. Furthermore, by placing the temperature sensing MOS transistors at different locations on the power transistor, errors caused by external temperature sensors due to positional deviations or thermal conduction delays are avoided, further enhancing system integration. In addition, the driver chip in the power switch of this application allows for programmable control of temperature protection, overcurrent protection, and current sensing ratios, increasing the flexibility and practical application range of the system.

[0078] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An integrated high-voltage power device, characterized in that, include: Multiple first transistors; as well as One or more second transistors integrated with the plurality of first transistors, The drains of the plurality of first transistors and the drains of the one or more second transistors are electrically connected, the gates of the plurality of first transistors are electrically connected, and the gates of the one or more second transistors are electrically connected. The one or more second transistors are distributed at one or more locations on the high-voltage power device and configured to detect the temperature at the one or more locations.

2. The high-voltage power device according to claim 1, wherein, The plurality of first transistors include: The main power transistor is configured to allow external current to flow through the high-voltage power device; A current-sensing transistor configured to detect the current flowing through the high-voltage power device; and An overcurrent protection transistor is configured to provide overcurrent protection for the main power transistor.

3. The high-voltage power device according to claim 2, wherein, The ratio between the area of ​​the active region of the main power transistor and the area of ​​the active region of the current sensing transistor is K:

1. The ratio between the active region of the main power transistor and the active region of the overcurrent protection transistor is N:1, where both K and N are greater than 1.

4. The high-voltage power device according to claim 2, wherein, The main power transistor and the overcurrent protection transistor share the same first chip substrate; The main power transistor and the current detection transistor share a second chip substrate.

5. The high-voltage power device according to claim 4, wherein, The first chip substrate and the second chip substrate are the same chip substrate.

6. A power switch including a high-voltage power device, characterized in that, include: The high-voltage power device according to claim 2; as well as Driver chip, including: A gate drive circuit is electrically connected to the plurality of first transistors and configured to provide a gate drive voltage to the gates of the plurality of first transistors; A current detection circuit, electrically connected to the current detection transistor, is configured to detect the current flowing through the main power transistor; An overcurrent protection circuit, electrically connected to the overcurrent protection transistor and the gate drive circuit, is configured to stop the gate drive circuit from providing drive voltage to the plurality of first transistors when the current in the main power transistor exceeds a current threshold, thereby achieving overcurrent protection; and One or more over-temperature protection circuits are electrically connected to the gate drive circuit and the one or more second transistors, wherein each of the one or more over-temperature protection circuits is configured to cause the gate drive circuit to stop providing drive voltage to the plurality of first transistors when the temperature at any of the one or more locations exceeds a temperature threshold, thereby achieving over-temperature protection.

7. The power switch according to claim 6, wherein, The gate driving circuit includes: A level conversion circuit is configured to receive an input control signal and generate a first control signal based on the input control signal; The protection logic has its input terminal electrically connected to the overcurrent protection circuit and the one or more overtemperature protection circuits, and is configured to receive an overcurrent protection signal from the overcurrent protection circuit, receive an overtemperature protection signal from the one or more overtemperature protection circuits, and generate a protection signal based on the overcurrent protection signal and the overtemperature protection signal. A driver, electrically connected to the level shifting circuit and the protection logic, and configured to turn the plurality of first transistors on or off according to the protection signal and the first control signal; A charge pump is electrically connected to the driver and the level shifting circuit, and is configured to supply power to the driver and the level shifting circuit.

8. The power switch according to claim 6, wherein, The current detection circuit includes: A first operational amplifier, wherein the two input terminals of the first operational amplifier are electrically connected to the source of the main power transistor and the source of the current detection transistor, respectively. A first current mirror, wherein the input terminal of the first current mirror is electrically connected to the source of the current detection transistor and the output terminal of the first operational amplifier; The second current mirror, wherein the input terminal of the second current mirror is electrically connected to the output terminal of the first current mirror; A first switch array is electrically connected to the output terminal of the second current mirror and includes a plurality of first switches, wherein one or more of the plurality of first switches are selectively turned on or off. A first detector is electrically connected to the first switch array and detects the current flowing through the main power transistor.

9. The power switch according to claim 6, wherein, The overcurrent protection circuit includes: The second operational amplifier, wherein the two input terminals of the second operational amplifier are electrically connected to the source of the main power transistor and the source of the overcurrent protection transistor, respectively; The third current mirror, wherein the input terminal of the third current mirror is electrically connected to the source of the overcurrent protection transistor and the output terminal of the second operational amplifier; A fourth current mirror, wherein the input terminal of the fourth current mirror is electrically connected to the output terminal of the third current mirror; The second switch array is electrically connected to the output of the fourth current mirror and includes a plurality of second switches, wherein one or more of the plurality of second switches are selectively turned on or off. A first comparator is electrically connected to one end of the second switch array and compares the voltage at that end of the second switch array with a reference voltage to obtain a comparison result. An overcurrent protection logic is electrically connected to the output of the first comparator, and causes the gate drive circuit to stop providing drive voltage to the plurality of first transistors when the comparison result exceeds the current threshold.

10. The power switch according to claim 6, wherein, Each of the one or more over-temperature protection circuits includes: A current source configured to generate current independent of temperature changes; A fifth current mirror, wherein the input terminal of the fifth current mirror is electrically connected to the current source; The third switch array includes a plurality of third switches, each of which is electrically connected to one of the plurality of output terminals of the fifth current mirror; A first resistor, the first end of which is electrically connected to the source of one of the one or more over-temperature protection transistors; A second comparator is electrically connected to the second terminal of the first resistor and configured to compare the voltage at the second terminal with a reference voltage to obtain a comparison result; and An over-temperature protection logic is electrically connected to the output of the second comparator and configured to cause the gate drive circuit to stop providing drive voltage to the plurality of first transistors when the comparison result exceeds a specific threshold.

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