Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel. The array substrate comprises a substrate; the thin film transistors are arranged on the substrate, each thin film transistor comprises a first grid electrode, an active layer, a source electrode and a drain electrode, and the active layer comprises a source electrode contact part electrically connected with the source electrode, a drain electrode contact part electrically connected with the drain electrode and a channel part located between the source electrode contact part and the drain electrode contact part; the source electrode and the drain electrode are arranged on the same layer, and the orthographic projection of the source electrode and the drain electrode on the substrate and the orthographic projection of the first grid electrode on the substrate both have a first overlapping region; the first insulating layer is located between a layer where the first grid electrode is located and layers where the source electrode and the drain electrode are located; the first insulating layer comprises a first insulating part and a second insulating part, the orthographic projection of the first insulating part on the substrate is overlapped with the orthographic projection of the channel part on the substrate, the orthographic projection of the second insulating part on the substrate covers the first overlapping region, and the thickness of the second insulating part is greater than that of the first insulating part.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to an array substrate and a display panel. Background Technology

[0002] In a display panel, the display area is provided with multiple gate lines and multiple data lines. These gate lines and data lines intersect to define multiple pixel areas. Each pixel area is equipped with a thin-film transistor (TFT) and a pixel electrode. The gate of the TFT is electrically connected to the corresponding gate line, the source of the TFT is electrically connected to the corresponding data line, and the drain is electrically connected to the pixel electrode. When a working level signal is applied to the gate line, the source and drain of the corresponding TFT conduct, thereby transmitting the data signal on the data line to the pixel electrode, and thus adjusting the brightness of the pixel area. The electrical performance of the TFT has a significant impact on the display effect of the display panel. Utility Model Content

[0003] This disclosure provides an array substrate, comprising:

[0004] Substrate;

[0005] Multiple thin-film transistors are disposed on the substrate. Each thin-film transistor includes a first gate, an active layer, a source, and a drain. The active layer includes a source contact portion electrically connected to the source, a drain contact portion electrically connected to the drain, and a channel portion located between the source contact portion and the drain contact portion. The source and drain are disposed on the same layer, and the orthographic projections of the source and drain on the substrate and the orthographic projection of the first gate on the substrate both have a first overlap region.

[0006] A first insulating layer is located between the first gate layer and the source and drain layers. The first insulating layer includes a first insulating portion and a second insulating portion. The orthographic projection of the first insulating portion on the substrate overlaps with the orthographic projection of the channel portion on the substrate. The orthographic projection of the second insulating portion on the substrate covers the first overlapping area. The thickness of the second insulating portion is greater than the thickness of the first insulating portion.

[0007] In some embodiments, the edge of the orthographic projection of the second insulating portion onto the substrate does not contact the edge of the first overlapping region.

[0008] In some embodiments, the first gate is located on the side of the layer containing the source and the drain that is closer to the substrate; the array substrate further includes:

[0009] Multiple gate lines and multiple data lines are arranged intersectingly to define multiple pixel regions; each pixel region is provided with the thin-film transistor, the first gate is electrically connected to the gate line, and the source is electrically connected to the data line;

[0010] A plurality of first electrodes, wherein the first electrodes are located in the pixel region and are electrically connected to the drain of the thin-film transistor in the pixel region;

[0011] At least one second electrode, the second electrode and the first electrode are respectively located in different layers of insulating space, and the orthographic projection of the second electrode on the substrate and the orthographic projection of the first electrode on the substrate have a second overlap area.

[0012] In some embodiments, the first electrode and the second electrode are located on opposite sides of the first insulating layer along its thickness direction. The first insulating layer further includes a third insulating portion, the orthographic projection of the third insulating portion on the substrate overlapping the second overlapping region, and the thickness of the third insulating portion being less than the thickness of the second insulating portion.

[0013] In some embodiments, the array substrate further includes: a second insulating layer located on the side of the source and drain away from the substrate, one of the first electrode and the second electrode located on the side of the second insulating layer away from the substrate, and the other of the first electrode and the second electrode located between the first insulating layer and the second insulating layer.

[0014] In some embodiments, the gate line is disposed on the same layer as the first gate, the data line is disposed on the same layer as the source, the orthographic projections of the data line and the gate line on the substrate have a third overlapping region, the orthographic projection of the second insulating portion on the substrate covers the third overlapping region, and has no contact with the edge of the third overlapping region.

[0015] In some embodiments, the gate line is disposed on the same layer as the first gate, the data line is disposed on the same layer as the source, and the orthogonal projection of the data line on the substrate is located within the orthogonal projection range of the second insulating portion on the substrate.

[0016] In some embodiments, the source and the drain are located on the side of the active layer away from the substrate, the first insulating layer is located on the side of the layer containing the source and the drain away from the substrate, and the first gate is located on the side of the first insulating layer away from the substrate.

[0017] A second insulating layer is disposed between the active layer and the substrate. The thin-film transistor also includes a second gate, which is located between the second insulating layer and the substrate and is electrically connected to the first gate.

[0018] In some embodiments, the array substrate further includes:

[0019] Multiple gate lines and multiple data lines are arranged intersectingly to define multiple pixel regions; each pixel region is provided with the thin-film transistor, the second gate is electrically connected to the gate line, and the source is electrically connected to the data line;

[0020] A plurality of first electrodes, wherein the first electrodes are located in the pixel region and are electrically connected to the drain of the thin-film transistor in the pixel region;

[0021] At least one second electrode, the second electrode and the first electrode are respectively located on opposite sides of the first insulating layer along its thickness direction, and the orthographic projection of the second electrode on the substrate and the orthographic projection of the first electrode on the substrate have a second overlap area.

[0022] In some embodiments, the first insulating layer further includes a third insulating portion, wherein the orthographic projection of the third insulating portion on the substrate overlaps with the second overlapping region, and the thickness of the third insulating portion is less than the thickness of the second insulating portion.

[0023] In some embodiments, the orthographic projections of the source and drain on the substrate and the orthographic projection of the second gate on the substrate all have a fourth overlapping region;

[0024] The second insulating layer includes a fourth insulating portion and a fifth insulating portion. The orthographic projection of the fourth insulating portion on the substrate overlaps with the second overlapping area. The orthographic projection of the fifth insulating portion on the substrate overlaps with the fourth overlapping area. The thickness of the fifth insulating portion is greater than the thickness of the fourth insulating portion.

[0025] In some embodiments, the second insulating layer further includes a sixth insulating portion, the orthographic projection of the sixth insulating portion on the substrate overlaps with the orthographic projection of the channel portion on the substrate, and the thickness of the sixth insulating portion is less than the thickness of the fifth insulating portion.

[0026] In some embodiments, the array substrate further includes: a plurality of gate lines and a plurality of data lines, wherein the second gate is disposed on the same layer as the gate lines, and the source is disposed on the same layer as the data lines;

[0027] The data line and the gate line have a third overlapping area on the substrate, and the fifth insulating portion has its third overlapping area covered by its third overlapping area, and there is no contact between the fifth insulating portion and the edge of the third overlapping area.

[0028] In some embodiments, the array substrate further includes: a plurality of gate lines and a plurality of data lines, wherein the second gate is disposed on the same layer as the gate lines, and the source is disposed on the same layer as the data lines; the orthogonal projection of the data lines on the substrate is located within the orthogonal projection range of the fifth insulating portion on the substrate.

[0029] In some embodiments, the source and the drain are located on the side of the active layer away from the substrate;

[0030] The array substrate also includes multiple data lines, which are disposed on the same layer as the source and electrically connected. A redundant portion is provided on the side of the data line near the substrate. The redundant portion is disposed on the same layer as the active layer. The orthographic projection of the data line on the substrate is located within the orthographic projection range of the redundant portion on the substrate.

[0031] This disclosure also provides a display panel, including the array substrate described above. Attached Figure Description

[0032] Figure 1A This is a partial plan view of the array substrate provided in the first embodiment of this disclosure.

[0033] Figure 1B For along Figure 1A Sectional view of line A-A' and along Figure 1A A cross-sectional view of line B-B' in the middle.

[0034] Figure 1C This is a schematic diagram showing the connection between the source, drain, and active layer in some embodiments of this disclosure.

[0035] Figure 2 This is a schematic diagram showing a short circuit between the source or drain and the first gate.

[0036] Figures 3A to 3E This is a schematic diagram illustrating the fabrication process of the first array substrate provided in this disclosure.

[0037] Figure 4A This is a partial plan view of the array substrate provided in the second embodiment of this disclosure.

[0038] Figure 4B For along Figure 4A Sectional view of line A-A' and along Figure 4A A cross-sectional view of line B-B' in the middle.

[0039] Figures 5A to 5E This is a schematic diagram illustrating the fabrication process of the second type of array substrate provided in this disclosure.

[0040] Figure 6A This is a partial plan view of the array substrate provided in the third embodiment of this disclosure.

[0041] Figure 6B For along Figure 6A Sectional view of line A-A' and along Figure 6A A cross-sectional view of line B-B' in the middle.

[0042] Figures 7A to 7D This is a schematic diagram illustrating the fabrication process of the array substrate provided in the third embodiment of this disclosure.

[0043] Figure 8A This is a partial plan view of the array substrate provided in the fourth embodiment of this disclosure.

[0044] Figure 8B For along Figure 8A Sectional view of line A-A' and along Figure 8A A cross-sectional view of line B-B' in the middle.

[0045] Figures 9A to 9E This is a schematic diagram illustrating the fabrication process of the array substrate provided in the fourth embodiment of this disclosure.

[0046] Figure 10A This is a partial plan view of the array substrate provided in the fifth embodiment of this disclosure.

[0047] Figure 10B For along Figure 10A Sectional view of line A-A' and along Figure 10A A cross-sectional view of line B-B' in the middle.

[0048] Figures 11A to 11D This is a schematic diagram illustrating the fabrication process of the array substrate provided in the fifth embodiment of this disclosure.

[0049] Figure 12A This is a partial plan view of the array substrate provided in the sixth embodiment of this disclosure.

[0050] Figure 12B For along Figure 12A Sectional view of line A-A' and along Figure 12A A cross-sectional view of line B-B' in the middle.

[0051] Figure 13 A cross-sectional view of a display panel provided in an embodiment of this disclosure.

[0052] Figure 14 Another cross-sectional view of the display panel provided in an embodiment of this disclosure. Detailed Implementation

[0053] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this disclosure do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this disclosure are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to such processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this disclosure are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” in this disclosure refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can indicate: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," "third," etc., used in this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. "Above," "below," "left," "right," etc., are only used to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0055] In display panels, parasitic capacitances are generated between the gate, source, and drain of thin-film transistors (TFTs). When the parasitic capacitance is large, it can cause adverse effects such as signal delay and increased power consumption. Increasing the thickness of the insulating layer between the gate and the source / drain can reduce the parasitic capacitance, but it also increases the thickness of the insulating layer between the channel portion of the active layer and the gate, thus affecting the electrical characteristics of the TFT.

[0056] To address the aforementioned technical problems, embodiments of this disclosure provide an array substrate. Figure 1A This is a partial plan view of the array substrate provided in the first embodiment of this disclosure. Figure 1B For along Figure 1A Sectional view of line A-A' and along Figure 1A A cross-sectional view of line B-B', as shown Figure 1A and Figure 1BAs shown, the array substrate includes a substrate 10 and a plurality of thin-film transistors 60 disposed on the substrate 10. Each thin-film transistor 60 includes a first gate 60g1, an active layer 60a, a source 60s, and a drain 60d. The active layer 60a includes a source contact portion 60a1 electrically connected to the source 60s, a drain contact portion 60a2 electrically connected to the drain 60d, and a channel portion 60a3 located between the source contact portion 60a1 and the drain contact portion 60a2. The source 60s and drain 60d are disposed on the same layer, and the orthographic projections of the source 60s and drain 60d onto the substrate 10 and the orthographic projection of the first gate 60g1 onto the substrate 10 both have a first overlap region.

[0057] The array substrate also includes a first insulating layer 20, which is located between the layer containing the first gate 60g1 and the layers containing the source 60s and drain 60d. The first insulating layer 20 includes a first insulating portion 21 and a second insulating portion 22. The orthographic projection of the first insulating portion 21 on the substrate 10 overlaps with the orthographic projection of the channel portion 60a3 on the substrate 10. The orthographic projection of the second insulating portion 22 on the substrate 10 covers the first overlapping area. The thickness of the second insulating portion 22 is greater than the thickness of the first insulating portion 21.

[0058] In this embodiment, a first insulating layer 20 is provided between the layer containing the source 60s and drain 60d and the first gate 60g1. The thickness of the first insulating layer 20 in the region where the channel portion 60a3 of the active layer 60a is located is small, while the thickness of the first insulating layer 20 corresponding to the regions where the source 60s, drain 60d and gate are directly opposite is large. This allows the parasitic capacitance between the source 60s, drain 60d and the first gate 60g1 to be reduced while ensuring the electrical characteristics of the thin-film transistor 60.

[0059] exist Figure 1A In the illustrated embodiment, the first gate 60g1 is located on the substrate 10, the active layer 60a is located on the side of the first gate 60g1 away from the substrate 10, and the source 60s and drain 60d are located on the side of the active layer 60a away from the substrate 10. The source 60s and drain 60d can be in direct contact with the active layer 60a. The first insulating layer 20 is the gate insulating layer GI and is located between the first gate 60g1 and the active layer 60a.

[0060] like Figure 1AAs shown, the array substrate also includes multiple gate lines GL and multiple data lines DL. The gate lines GL and data lines DL are intersected and insulated from each other to define multiple pixel regions. Each pixel region has a thin-film transistor 60. The first gate 60g1 of the thin-film transistor 60 is disposed on the same layer as the gate line GL and electrically connected, and the source 60g1 is electrically connected to the data line DL. In addition, the array substrate may also include multiple first electrodes 40 and at least one second electrode 50. The first electrode 40 is located in the pixel region and is electrically connected to the drain 60d of the thin-film transistor 60 in the pixel region. For example, each pixel region has one first electrode 40. The second electrode 50 and the first electrode 40 are respectively located in different layers with insulating gaps, and the orthographic projection of the second electrode 50 on the substrate 10 and the orthographic projection of the first electrode 40 on the substrate 10 have a second overlap region. For example, there are multiple second electrodes 50, and each second electrode 50 corresponds to a first electrode 40; each second electrode 50 and the orthogonal projection of a first electrode 40 on the substrate 10 have a second overlapping area; or, for example, there are multiple second electrodes 50, and the orthogonal projections of one second electrode 50 and multiple first electrodes 40 on the substrate 10 have a second overlapping area.

[0061] Both the first electrode 40 and the second electrode 50 are made of transparent conductive materials. For example, the transparent conductive materials can be indium tin oxide (ITO), zinc oxide (IZO), and conductive metal oxide semiconductors.

[0062] For example, the first insulating layer 20 includes a first insulating portion 21 and a second insulating portion 22. The orthographic projection of the first insulating portion 21 on the substrate 10 overlaps with the orthographic projection of the channel portion 60a3 on the substrate 10. The orthographic projection of the second insulating portion 22 on the substrate 10 covers the first overlapping area. The thickness of the second insulating portion 22 is greater than the thickness of the first insulating portion 21.

[0063] For example, the edge of the orthographic projection of the second insulating portion 22 onto the substrate 10 does not contact the edge of the first overlapping region. Wherein, Figure 2 This is a schematic diagram showing a short circuit between the source 60s or drain 60d and the first gate, as shown below. Figure 2 As shown, when the first gate 60g1 is located on the side of the source 60s and drain 60d close to the substrate 10, a ramp will occur between the source 60s and drain 60d at the edge of the first gate 60g1. If the thickness of the first insulating layer 20 is thin, the first insulating layer 20 at the ramp position is prone to be missing, resulting in a short circuit between the source 60s, drain 60d and the first gate 60g1. However, in this embodiment, the thicker second insulating portion 22 covers the edge of the first overlapping area, which can prevent the source 60s and drain 60d from short-circuiting with the first gate 60g1 at the ramp position, thereby improving product yield.

[0064] In addition, the first electrode 40 and the second electrode 50 are located on opposite sides of the first insulating layer 20 along its thickness direction. The first insulating layer 20 also includes a third insulating portion 23. The orthographic projection of the third insulating portion 23 on the substrate 10 overlaps with the second overlapping area. The thickness of the third insulating portion 23 is less than the thickness of the second insulating portion 22.

[0065] As can be seen from the electric field strength formula E=U / d, when the electric field strength remains constant, a decrease in the spacing d leads to a decrease in the liquid crystal driving voltage, and under the same transmittance, the driving power consumption also decreases. In this embodiment, by making the second insulating portion 22 have a larger thickness and the third insulating portion 23 have a smaller thickness, the parasitic capacitance between the gate and the source 60s and the drain 60d can be reduced while simultaneously lowering the driving power consumption of the product.

[0066] For example, the thickness difference between the third insulating portion 23 and the second insulating portion 22 is between 0.05 micrometers and 0.25 micrometers, and / or, the thickness difference between the first insulating portion 21 and the second insulating portion 22 is between 0.05 micrometers and 0.25 micrometers. For example, the thickness difference between the third insulating portion 23 and the second insulating portion 22 is between 0.05 micrometers and 0.1 micrometers, and the thickness difference between the first insulating portion 21 and the second insulating portion 22 is between 0.05 micrometers and 0.1 micrometers; or, the thickness difference between the third insulating portion 23 and the second insulating portion 22 is between 0.1 micrometers and 0.15 micrometers, and the thickness difference between the first insulating portion 21 and the second insulating portion 22 is between 0.1 micrometers and 0.15 micrometers; or, the thickness difference between the third insulating portion 23 and the second insulating portion 22 is between 0.15 micrometers and 0.25 micrometers, and the thickness difference between the first insulating portion 21 and the second insulating portion 22 is between 0.15 micrometers and 0.25 micrometers.

[0067] For example, the orthographic projections of the data line DL and the gate line GL on the substrate 10 have a third overlapping area. The orthographic projection of the second insulating portion 22 on the substrate 10 covers the third overlapping area and does not contact the edge of the third overlapping area. Thus, a thick insulating layer is provided at the edge of the third overlapping area to separate the data line DL and the gate line GL, preventing the data line DL from short-circuiting with the gate line GL when it crosses the gate line GL to climb, thereby improving product yield.

[0068] For example, the orthogonal projection of the data line DL on the substrate 10 is located within the orthogonal projection range of the second insulating portion 22 on the substrate 10, thereby preventing the data line DL from short-circuiting with the gate line GL when it is climbing over the gate line GL.

[0069] For example, such as Figure 1A and Figure 1BAs shown, the array substrate further includes: a second insulating layer 30, the second insulating layer 30 being located on the side of the source electrode 60s and the drain electrode 60d away from the substrate 10, one of the first electrode 40 and the second electrode 50 being located on the side of the second insulating layer 30 away from the substrate 10, and the other of the first electrode 40 and the second electrode 50 being located between the first insulating layer 20 and the substrate 10. Figure 1A and Figure 1B The following description uses an example where the first electrode 40 is located on the side of the second insulating layer 30 away from the substrate 10, and the second electrode 50 is located between the first insulating layer 20 and the substrate 10. The first electrode 40 may have a slit SL, and the first electrode 40 can be electrically connected to the drain 60d of the thin-film transistor 60 through a fourth via V4 penetrating the second insulating layer 30.

[0070] For example, the second electrode 50 is electrically connected to the common electrode line CL. For instance, as shown... Figure 1A and Figure 1B As shown, the second electrode 50 and the common electrode line CL can be arranged in the same layer.

[0071] For example, both the gate line GL and the first gate 60g1 may include a single layer or multiple layers of metal; for instance, both the gate line GL and the first gate 60g1 may be metal stacks of molybdenum-aluminum-molybdenum (Mo / AL / Mo), molybdenum-copper (Mo / Cu), molybdenum-niobium-copper (MoNb / Cu), or molybdenum-niobium-copper-molybdenum-titanium (MoNb / Cu / MoTi). Alternatively, the gate line GL and the first gate 60g1 may include a metal layer and a transparent conductive layer, wherein the transparent conductive layer is made of the same material as the second electrode 50. In this case, the gate line GL, the first gate 60g1, the second electrode 50, and the common electrode line CL can be formed using a single patterning process to simplify the fabrication process. This patterning process may include steps such as exposure using a half-tone mask, development, first etching, photoresist ashing, second etching, and photoresist stripping.

[0072] Figure 1C This is a schematic diagram illustrating the connection between the source, drain, and active layer in some embodiments of this disclosure, exemplarily, as shown below. Figure 1CThe active layer 60a shown may include a semiconductor layer and a first ohmic contact layer a12 and a second ohmic contact layer a22 located on the side of the semiconductor layer away from the substrate 10. The semiconductor layer includes a first semiconductor portion a11 disposed opposite to the first ohmic contact layer a12, a second semiconductor portion a21 disposed opposite to the second ohmic contact layer a22, and a channel portion 60a3 located between the first semiconductor portion a11 and the second semiconductor portion a21. The first semiconductor portion a11 and the first ohmic contact layer a12 serve as the source contact portion 60a1, and the second semiconductor portion a21 and the second ohmic contact layer a22 serve as the drain contact portion 60a2. The source 60s is electrically connected to the first ohmic contact layer a12, and the drain 60d is electrically connected to the second ohmic contact layer a22, thereby reducing the contact resistance between the source 60s, the drain 60d and the active layer 60a.

[0073] For example, the semiconductor layer can be made of polycrystalline silicon (a-Si), and the first ohmic contact layer a12 and the second ohmic contact layer a22 can be made of doped polycrystalline silicon, such as heavily doped n-type doped polycrystalline silicon (n+a-Si), or heavily doped p-type doped polycrystalline silicon (p+a-Si). The n-type doping material can be arsenic (As), phosphorus (P), etc., and the p-type doping material can be aluminum (Al), indium (In), etc.

[0074] For example, the source 60s, drain 60d, and data line DL can be a multilayer metal structure, and the film layer combination can be selected from one of Mo / AL / Mo, Mo / Cu, MoNb / Cu, MoNb / Cu / MoTi or a stack thereof.

[0075] For example, such as Figure 1A and Figure 1BAs shown, a redundancy portion 70 is provided on the side of the data line DL closest to the substrate 10. The redundancy portion 70 is disposed on the same layer as the active layer 60a, and the orthogonal projection of the data line DL onto the substrate 10 is within the orthogonal projection range of the redundancy portion 70 onto the substrate 10. In this case, the data line DL, the source electrode 60s, the drain electrode 60d, and the active layer 60a can be fabricated using the same patterning process. Specifically, an active material layer and a source / drain metal layer can be formed sequentially. The active material layer includes a semiconductor material layer and an ohmic contact material layer formed sequentially along the direction away from the substrate 10. Next, a photoresist layer is formed, and the photoresist is exposed and developed using a halftone mask to form a fully retained area and a partially retained area. Then, the exposed source / drain metal layer is subjected to a first wet etching process to obtain the first source / drain electrode film and the data line DL. Next, the photoresist layer is ashed to remove the partially retained area, ensuring that the orthographic projection of the fully retained area on the substrate 10 coincides with the edge of the orthographic projection of the first source / drain electrode layer film on the substrate 10. Then, the exposed active material layer is subjected to a first dry etching process to form a redundant area 70 and an intermediate active area located below the first source / drain electrode film. Finally, the exposed... The source and drain metal layers are subjected to a second wet etching to form the source 60s and drain 60d. Then, the completely retained portion is removed, and the exposed active material layer is subjected to a second dry etching to remove the exposed ohmic contact material layer and part of the semiconductor material layer. The remaining ohmic contact material layer forms the first ohmic contact layer and the second ohmic contact layer. The unetched semiconductor material layer located between the first ohmic contact layer and the second ohmic contact layer forms the channel portion 60a3. The first ohmic contact layer is substantially aligned with the orthographic projection of the source 60s onto the substrate 10, and the second ohmic contact layer is substantially aligned with the orthographic projection of the drain 60d onto the substrate 10.

[0076] The fabrication method of the array substrate in the first embodiment is described below. Specifically, it includes:

[0077] S11, such as Figure 3A As shown, a gate line GL, a first gate electrode 60g1, a second electrode 50, and a common electrode line CL are formed on a substrate 10. Specifically, a transparent conductive material layer and a metal material layer can be formed sequentially. Then, through processes such as photoresist coating, exposure using a halftone mask, development, first etching, photoresist ashing, second etching, and photoresist stripping, the gate line GL, the first gate electrode 60g1, the second electrode 50, and the common electrode line CL are formed. The gate line GL and the first gate electrode 60g1 include a metal layer and a transparent conductive layer, while the second electrode 50 and the common electrode line CL include a transparent conductive layer.

[0078] S12, such as Figure 3BAs shown, a first insulating material layer is formed, and a photolithography process is performed on the first insulating material layer to form a first groove Va1 at the position corresponding to the channel portion 60a3 of the thin-film transistor 60, and a second groove Va2 at the position corresponding to the position opposite to the first electrode 40 and the second electrode 50. The first insulating material layer remaining below the first groove serves as a first insulating portion 21, the first insulating material layer remaining below the second groove Va2 serves as a third insulating portion 23, and the first insulating material layer in other areas serves as a second insulating portion 22. For example, the depth of at least one of the first groove Va1 and the second groove Va2 can be 0.05 to 0.25 micrometers.

[0079] S13, such as Figure 3C As shown, an active layer 60a is formed, along with a pattern including a data line DL, a source 60s, and a drain 60d. The specific fabrication process can be found in the description above.

[0080] S14. A second insulating layer 30 is formed, and a fourth via V4 is formed on the second insulating layer 30 by photolithography patterning process. The fourth via V4 exposes part of the drain 60d of the thin film transistor 60.

[0081] S15. A first electrode 40 is formed in each pixel region. The first electrode 40 is electrically connected to the drain 60d of the corresponding thin-film transistor 60 through a fourth via V4. The first electrode 40 has a plurality of slits SL.

[0082] Figure 4A This is a partial plan view of the array substrate provided in the second embodiment of this disclosure. Figure 4B For along Figure 4A Sectional view of line A-A' and along Figure 4A Sectional view of line B-B' in the middle. Figure 4A and Figure 4B The array substrate shown and Figure 1A and Figure 1B The array substrates shown are similar, the only difference being that... Figure 4A and Figure 4B In the array substrate shown, one of the first electrode 40 and the second electrode 50 is located between the first insulating layer 20 and the second insulating layer 30, and the other is located on the side of the second insulating layer 30 away from the substrate 10.

[0083] Specifically, the first electrode 40 is located between the first insulating layer 20 and the second insulating layer 30, and the second electrode 50 is located on the side of the second insulating layer 30 away from the substrate 10. The second electrode 50 has a plurality of slits SL.

[0084] For example, the array substrate may further include multiple adapters 80, which are disposed on the same layer as the second electrode 50. One end of the adapter 80 is electrically connected to the first electrode 40 through a first via V1 penetrating the second insulating layer 30, and the other end is electrically connected to the drain electrode 60d through a second via V2 penetrating the second insulating layer 30, thereby realizing the electrical connection between the first electrode 40 and the drain electrode 60d. The common electrode line CL may be disposed on the same layer as the second electrode 50 and electrically connected.

[0085] and Figure 1A and Figure 1B Compared to the array substrate shown, in Figure 4A and Figure 4B In the array substrate shown, the insulating layer between the first electrode 40 and the second electrode 50 is only the second insulating layer 30, thereby further reducing the thickness of the insulating layer between the first electrode 40 and the second electrode 50, and thus reducing the driving power consumption. It should be noted that in Figure 4B The morphology of the second insulating layer 30 is only schematic; in reality, the thickness of the second insulating layer 30 can be uniformly distributed.

[0086] Figures 5A to 5E This is a schematic diagram illustrating the fabrication process of the second type of array substrate provided in this disclosure, specifically including:

[0087] S21, such as Figure 5A As shown, a first gate 60g1 and a gate line GL are formed. Both the first gate 60g1 and the gate line GL can be a single conductive layer or a stack of multiple conductive layers, such as a stack of molybdenum-aluminum-molybdenum (Mo / AL / Mo), a stack of molybdenum-copper (Mo / Cu), a stack of molybdenum-niobium-copper (MoNb / Cu), a stack of molybdenum-niobium-copper-molybdenum-titanium (MoNb / Cu / MoTi), or a stack of indium tin copper oxide (ITO / Cu).

[0088] S22, such as Figure 5B As shown, a first insulating material layer is formed, and a photolithography process is performed on the first insulating material layer to form a first insulating layer 20 including a first insulating portion 21, a second insulating portion 22 and a third insulating portion 23. The specific process is the same as S12, and will not be described again here.

[0089] S23, such as Figure 5C As shown, an active layer 60a and a pattern including a data line DL, a source 60s, and a drain 60d are formed. The specific fabrication process is the same as that in S13.

[0090] S24, such as Figure 5C As shown, a first electrode 40 is formed in each pixel region.

[0091] S25, such as Figure 5D As shown, a second insulating layer 30 is formed, and a first via V1 and a second via V2 are formed by photolithography.

[0092] S26, such as Figure 5E As shown, a common electrode line CL is formed, and a second electrode 50 and an adapter 80 are formed in each pixel area. The second electrode 50 is electrically connected to the common electrode line CL and has multiple slits SL. One end of the adapter 80 is electrically connected to the first electrode 40 through a first via V1, and the other end is electrically connected to the drain 60d of the thin-film transistor 60 through a second via V2.

[0093] Figure 6A This is a partial plan view of the array substrate provided in the third embodiment of this disclosure. Figure 6B For along Figure 6A Sectional view of line A-A' and along Figure 6A A cross-sectional view along line B-B'. Similar to the first embodiment, in... Figure 6A and Figure 6B In the first embodiment shown, the array substrate includes a plurality of thin-film transistors 60 and a first insulating layer 20. The first insulating layer 20 is located between the layer containing the first gate 60g1 of the thin-film transistors 60 and the layers containing the source 60s and drain 60d. The first insulating layer 20 includes a first insulating portion 21 and a second insulating portion 22. The orthographic projection of the first insulating portion 21 on the substrate 10 overlaps with the orthographic projection of the channel portion 60a3 on the substrate 10. The orthographic projection of the second insulating portion 22 on the substrate 10 covers the first overlapping area. The thickness of the second insulating portion 22 is greater than the thickness of the first insulating portion 21.

[0094] The edge of the orthogonal projection of the second insulating portion 22 on the substrate 10 may not overlap with the edge of the first overlapping region to prevent the first gate 60g1 from short-circuiting with the source 60s and the drain 60d.

[0095] In addition, the array substrate also includes multiple gate lines GL, multiple data lines DL, multiple first electrodes 40, and at least one second electrode 50. The multiple gate lines GL and multiple data lines DL define multiple pixel regions. Each pixel region is provided with a first electrode 40. The orthogonal projections of the first electrode 40 and the second electrode 50 on the substrate 10 have a second overlap region. The first electrode 40 and the second electrode 50 are located in different layers with insulating gaps, respectively. The gate of the thin-film transistor 60 is electrically connected to the gate line GL, the source 60s is electrically connected to the data line DL, and the drain 60d is electrically connected to the first electrode 40.

[0096] Unlike the first embodiment, in Figure 6A and 6BIn the third embodiment shown, the source 60s and drain 60d of the thin-film transistor 60 are located on the side of the active layer 60a away from the substrate 10, the first insulating layer 20 is located on the side of the layer containing the source 60s and drain 60d away from the substrate 10, and the first gate 60g1 is located on the side of the first insulating layer 20 away from the substrate 10. A second insulating layer 30 is also disposed between the active layer 60a and the substrate 10. The thin-film transistor 60 also includes a second gate 60g2, which is located between the second insulating layer 30 and the substrate 10 and is electrically connected to the first gate 60g1. Figure 6A and Figure 6B In this structure, the first insulating layer 20 serves as the passivation layer PVX, and the second insulating layer 30 serves as the gate insulating layer GI.

[0097] For example, the second gate 60g2 is disposed on the same layer as the gate line GL and electrically connected thereto, and the first gate 60g1 is electrically connected to the second gate 60g2 through a third via V3 penetrating the first insulating layer 20; or, the first gate 60g1 and the second gate 60g2 are electrically connected using an adapter 80. The data line DL is disposed on the same layer as the source 60s and the drain 60d.

[0098] exist Figure 6A and Figure 6B In the first insulating layer 20, the first electrode 40 and the second electrode 50 are located on opposite sides of the first insulating layer 20. In addition to the first insulating portion 21 and the second insulating portion 22, the first insulating layer 20 also includes a third insulating portion 23. The orthographic projection of the third insulating portion 23 onto the substrate 10 overlaps with the second overlapping area. The thickness of the third insulating portion 23 is less than the thickness of the second insulating portion 22, thereby reducing the thickness of the insulating layer between the first electrode 40 and the second electrode 50, and thus reducing the driving power consumption of the display product.

[0099] For example, one of the first electrode 40 and the second electrode 50 is located between the second insulating layer 30 and the substrate 10, and the other is located on the side of the first insulating layer 20 away from the substrate 10. For instance, the second electrode 50 is located between the second insulating layer 30 and the substrate 10, and the first electrode 40 is located on the side of the first insulating layer 20 away from the substrate 10. The first electrode 40 is electrically connected to the drain electrode 60d through a fourth via V4, and the second electrode 50 is electrically connected to a common electrode line CL, which can be disposed in the same layer as the second electrode 50.

[0100] For example, in Figure 6A and Figure 6B In the array substrate shown, the thickness of the second insulating layer 30 can be uniformly distributed at each location.

[0101] Figures 7A to 7D This is a schematic diagram of the fabrication process of the array substrate provided in the third embodiment of this disclosure, specifically including:

[0102] S31, such as Figure 7A As shown, a gate line GL, a second gate 60g2, a common electrode line CL, and a second electrode 50 are formed on the substrate 10. The specific process can be referred to in S11, and will not be repeated here.

[0103] S32, such as Figure 7B As shown, a second insulating layer 30 is formed.

[0104] S33, such as Figure 7B As shown, an active layer 60a, a source electrode 60s, a drain electrode 60d, and a data line DL are formed on the side of the second insulating layer 30 away from the substrate 10. The specific process is described in S13 and will not be repeated here.

[0105] S34, such as Figure 7C As shown, a first insulating material layer is formed, and a photolithography process is performed on the first insulating material layer to form a first groove at the position corresponding to the channel portion 60a3 of the thin-film transistor 60, a second groove at the position corresponding to the position opposite to the first electrode 40 and the second electrode 50, a fourth via V4 penetrating the first insulating material layer at the position corresponding to the drain 60d, and a third via V3 penetrating the first insulating material layer and the second insulating layer 30 at the position corresponding to the second gate 60g2. The first insulating material layer remaining below the first groove serves as the first insulating portion 21, the first insulating material layer remaining below the second groove serves as the third insulating portion 23, and the first insulating material layer in other areas serves as the second insulating portion 22. For example, the depth of at least one of the first groove and the second groove can be 0.05 to 0.25 micrometers.

[0106] S35, such as Figure 7D As shown, a first electrode 40 and a first gate 60g1 are formed in each pixel region. The first electrode 40 is electrically connected to the drain 60d of the corresponding thin-film transistor 60 through a fourth via V4. The first electrode 40 has multiple slits SL. The first gate 60g1 is electrically connected to the second gate 60g2 through a third via V3.

[0107] Figure 8A This is a partial plan view of the array substrate provided in the fourth embodiment of this disclosure. Figure 8B For along Figure 8A Sectional view of line A-A' and along Figure 8A A cross-sectional view of line B-B' in the middle. Figure 8A and Figure 8B The array substrate shown and Figure 6A and Figure 6B The array substrates shown are similar, the difference being that, in Figure 8A and Figure 8BIn this design, the second insulating layer 30 is no longer a film with uniform thickness distribution. Specifically, the orthographic projections of the source electrode 60s and drain electrode 60d onto the substrate 10, as well as the orthographic projection of the second gate electrode 60g2 onto the substrate 10, all exhibit a fourth overlapping region. The second insulating layer 30 includes a fourth insulating portion 31 and a fifth insulating portion 32. The orthographic projection of the fourth insulating portion 31 onto the substrate 10 overlaps with the second overlapping region, and the orthographic projection of the fifth insulating portion 32 onto the substrate 10 also overlaps with the fourth overlapping region. The thickness of the fifth insulating portion 32 is greater than the thickness of the fourth insulating portion 31. By adjusting the thickness of the second insulating layer 30 at different locations, the parasitic capacitance between the source electrode 60s, drain electrode 60d, and second gate electrode 60g2 can be reduced. Simultaneously, the insulation layer thickness between the first electrode 40 and the second electrode 50 can be further reduced, thereby further reducing the driving power consumption of the product.

[0108] In addition, the second insulating layer 30 may also include a sixth insulating portion 33. The orthographic projection of the sixth insulating portion 33 on the substrate 10 overlaps with the orthographic projection of the channel portion 60a3 on the substrate 10. The thickness of the sixth insulating portion 33 is less than the thickness of the fifth insulating portion 32, thereby reducing the parasitic capacitance between the source 60s, the drain 60d and the second gate 60g2 while ensuring the electrical characteristics of the thin film transistor 60.

[0109] For example, the thickness difference between the fourth insulating portion 31 and the fifth insulating portion 32 is between 0.05 micrometers and 0.25 micrometers, and / or the thickness difference between the sixth insulating portion 33 and the fifth insulating portion 32 is between 0.05 micrometers and 0.25 micrometers.

[0110] For example, the second gate 60g2 is disposed on the same layer as the gate line GL, and the source 60s is disposed on the same layer as the data line DL. The orthogonal projections of the data line DL and the gate line GL onto the substrate 10 have a third overlapping region. The orthogonal projection of the fifth insulating portion 32 onto the substrate 10 covers the third overlapping region and does not contact the edge of the third overlapping region. Therefore, a thicker insulating layer is disposed at the edge of the third overlapping region to separate the data line DL and the gate line GL, preventing a short circuit between the data line DL and the gate line GL when the data line DL crosses the gate line GL during ramping.

[0111] For example, the orthogonal projection of the data line DL on the substrate 10 is located within the orthogonal projection range of the fifth insulating portion 32 on the substrate 10, thereby preventing the data line DL from short-circuiting with the gate line GL when it is climbing over the gate line GL.

[0112] Figures 9A to 9E This is a schematic diagram of the fabrication process of the array substrate provided in the fourth embodiment of this disclosure, specifically including:

[0113] S41, such as Figure 9AAs shown, a second gate 60g2, a gate line GL, a second electrode 50, and a common electrode line CL are formed. The specific process can be referred to in S11, and will not be repeated here.

[0114] S42, such as Figure 9B As shown, a second insulating material layer is formed, and the second insulating material layer is patterned using a photolithography process to form a second insulating layer 30, which includes a fourth insulating portion 31, a fifth insulating portion 32, and a sixth insulating portion 33.

[0115] S43, such as Figure 9C As shown, an active layer 60a, a source electrode 60s, a drain electrode 60d, and a data line DL are formed on the side of the second insulating layer 30 away from the substrate 10. The specific process is described in S13 and will not be repeated here.

[0116] S44, such as Figure 9D As shown, a first insulating material layer is formed, and the first insulating material layer is patterned using a photolithography process to form a first insulating layer 20. The first insulating layer 20 includes a first insulating portion 21, a second insulating portion 22, and a third insulating portion 23. The first insulating layer 20 is etched to form a fourth via V4, which exposes a portion of the drain electrode 60d. The first insulating layer 20 and the second insulating layer 30 are etched to form a third via V3, which exposes a portion of the second gate electrode 60g2.

[0117] S45, such as Figure 9E As shown, a first electrode 40 and a first gate 60g1 are formed in each pixel region. The first electrode 40 is electrically connected to the drain 60d through a fourth via V4. The first gate 60g1 is electrically connected to the second gate 60g2 through a third via V3.

[0118] Figure 10A This is a partial plan view of the array substrate provided in the fifth embodiment of this disclosure. Figure 10B For along Figure 10A Sectional view of line A-A' and along Figure 10A A cross-sectional view of line B-B' in the middle. Figure 10A and Figure 10B The array substrate shown and Figure 4A and Figure 4B The array substrates shown are similar, except that the positions of the first electrode 40 and the second electrode 50 are different. Figure 10A and Figure 10B In the array substrate shown, the first electrode 40 is located between the second insulating layer 30 and the first insulating layer 20, and the second electrode 50 and the common electrode line CL are located on the side of the second insulating layer 30 away from the substrate 10.

[0119] In addition, the array substrate may also include an adapter 80, which is disposed on the same layer as the second electrode 50. One end of the adapter 80 is electrically connected to the first electrode 40 through a first via V1 penetrating the passivation layer PVX, and the other end is electrically connected to the drain 60d through a second via V2 penetrating the passivation layer PVX.

[0120] Figures 11A to 11D This is a schematic diagram of the fabrication process of the array substrate provided in the fifth embodiment of this disclosure, specifically including:

[0121] S51, such as Figure 11A As shown, a first gate 60g1 and a gate line GL are formed, as detailed in step S21.

[0122] S52, such as Figure 11B As shown, a second insulating layer 30 is formed, and then, the source 60s, drain 60d, active layer 60a and data line DL are formed in accordance with step S13.

[0123] S53, such as Figure 11C As shown, a first insulating material layer is formed, and a patterning process is performed on the first insulating material layer to form a first insulating layer 20 including a first insulating portion 21, a second insulating portion 22 and a third insulating portion 23; and a first via V1 and a second via V2 penetrating the first insulating layer 20, and a third via V3 penetrating the first insulating layer 20 and the second insulating layer 30 are formed.

[0124] S54, such as Figure 11D As shown, a second electrode 50, a common electrode line CL, a connector 80, and a first gate 60g1 are formed on the side of the first insulating layer 20 away from the substrate 10. One end of the connector 80 is electrically connected to the first electrode 40 through a first via V1, and the other end is electrically connected to the drain 60d through a second via V2. The first gate 60g1 is electrically connected to the second gate 60g2 through a third via V3.

[0125] Figure 12A This is a partial plan view of the array substrate provided in the sixth embodiment of this disclosure. Figure 12B For along Figure 12A Sectional view of line A-A' and along Figure 12A A cross-sectional view of line B-B' in the middle. Figure 12A and Figure 12B The array substrate shown and Figure 8A and Figure 8B The array substrates shown are similar, except that the positions of the first electrode 40 and the second electrode 50 are different. Figure 12A and Figure 12BIn the array substrate shown, the first electrode 40 is located between the second insulating layer 30 and the first insulating layer 20, and the second electrode 50 and the common electrode line CL are located on the side of the second insulating layer 30 away from the substrate 10.

[0126] In addition, the array substrate may also include an adapter 80, which is disposed on the same layer as the second electrode 50. One end of the adapter 80 is electrically connected to the first electrode 40 through a first via V1 penetrating the passivation layer PVX, and the other end is electrically connected to the drain 60d through a second via V2 penetrating the passivation layer PVX.

[0127] Figure 12A and Figure 12B The fabrication process of the array substrate shown is similar to steps S51 to S54 above. The only difference is that when forming the second insulating layer 30 in step S52, the second insulating material layer is formed first, and then the second insulating material layer is patterned to form the second insulating layer 30 including the fourth insulating part 31, the fifth insulating part 32 and the sixth insulating part 33. Then the source electrode 60s, the drain electrode 60d, the active layer 60a and the data line DL are formed.

[0128] Figure 13 This is a cross-sectional view of a display panel provided in an embodiment of the present disclosure. Figure 14 Another cross-sectional view of the display panel provided in the embodiments of this disclosure, such as Figure 13 and Figure 14 As shown, this disclosure also provides a display panel, including the array substrate of any of the above embodiments. Additionally, the display panel further includes a cell substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the cell substrate.

[0129] The substrate includes a substrate 90, a color filter layer on the substrate 90, and a black matrix 91. The color filter layer may include multiple color filters, each of which overlaps with the orthographic projection of a pixel region onto the substrate 10. The orthographic projection of the black matrix 91 onto the substrate 10 covers the orthographic projection of the data line DL onto the substrate 10 and also covers the orthographic projection of the thin-film transistor 60 onto the substrate 10. Furthermore, the orthographic projection of the black matrix 91 onto the substrate 10 may partially overlap with the orthographic projection of the second electrode 50 onto the substrate 10 to prevent light leakage.

[0130] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. An array substrate, characterized by, The array substrate comprises: a substrate; a plurality of thin film transistors disposed on the substrate, the thin film transistors comprising a first gate, an active layer, a source and a drain, the active layer comprising a source contact portion electrically connected to the source, a drain contact portion electrically connected to the drain, and a channel portion between the source contact portion and the drain contact portion; the source and the drain are disposed in the same layer, and the orthographic projection of the source and the drain on the substrate and the orthographic projection of the first gate on the substrate both have a first overlapping area; a first insulating layer between the layer where the first gate is located and the layer where the source and the drain are located; the first insulating layer comprises a first insulating portion and a second insulating portion, the orthographic projection of the first insulating portion on the substrate overlaps with the orthographic projection of the channel portion on the substrate, and the orthographic projection of the second insulating portion on the substrate covers the first overlapping area, and the thickness of the second insulating portion is greater than the thickness of the first insulating portion.

2. The array substrate of claim 1, wherein, The edge of the orthographic projection of the second insulating portion on the substrate is not in contact with the edge of the first overlapping area.

3. The array substrate of claim 1, wherein, The first gate is located on the side of the layer where the source and the drain are located close to the substrate; the array substrate further comprises: a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are disposed in a cross manner to define a plurality of pixel areas; the thin film transistors are disposed in each of the pixel areas, the first gate is electrically connected to the gate line, and the source is electrically connected to the data line; a plurality of first electrodes, the first electrodes are located in the pixel areas and are electrically connected to the drains of the thin film transistors in the pixel areas; at least one second electrode, the second electrode and the first electrode are located in different layers in an insulating and spaced manner, and the orthographic projection of the second electrode on the substrate and the orthographic projection of the first electrode on the substrate have a second overlapping area.

4. The array substrate of claim 3, wherein, The first electrode and the second electrode are respectively located on opposite sides of the first insulating layer along the thickness direction of the first insulating layer, and the first insulating layer further comprises a third insulating portion, the orthographic projection of the third insulating portion on the substrate overlaps with the second overlapping area, and the thickness of the third insulating portion is less than the thickness of the second insulating portion.

5. The array substrate of claim 3, wherein, The array substrate further comprises a second insulating layer, the second insulating layer is located on the side of the source and the drain away from the substrate, one of the first electrode and the second electrode is located on the side of the second insulating layer away from the substrate, and the other of the first electrode and the second electrode is located between the first insulating layer and the second insulating layer.

6. The array substrate according to any one of claims 3 to 5, wherein, The gate lines and the first gate are disposed in the same layer, the data lines and the source are disposed in the same layer, the orthographic projection of the data lines on the substrate and the orthographic projection of the gate lines on the substrate have a third overlapping area, the orthographic projection of the second insulating portion on the substrate covers the third overlapping area and is not in contact with the edge of the third overlapping area.

7. The array substrate according to any one of claims 3 to 5, wherein, The gate lines and the first gate are disposed in the same layer, the data lines and the source are disposed in the same layer, and the orthographic projection of the data lines on the substrate is located within the range of the orthographic projection of the second insulating portion on the substrate.

8. The array substrate of claim 1, wherein, The source and the drain are located on a side of the active layer away from the substrate, the first insulating layer is located on a side of the layer where the source and the drain are located away from the substrate, and the first gate is located on a side of the first insulating layer away from the substrate; The second insulating layer is further arranged between the layer where the active layer is located and the substrate, and the thin film transistor further comprises a second gate, which is located between the second insulating layer and the substrate and is electrically connected with the first gate.

9. The array substrate of claim 8, wherein, The array substrate further comprises: a plurality of gate lines and a plurality of data lines, the gate lines and the data lines are arranged in a cross manner to define a plurality of pixel regions; the thin film transistor is arranged in each of the pixel regions, the second gate is electrically connected with the gate line, and the source is electrically connected with the data line; a plurality of first electrodes, the first electrodes are located in the pixel regions and are electrically connected with the drain of the thin film transistor in the pixel regions; at least one second electrode, the second electrode is located on the opposite side of the first insulating layer along the thickness direction of the first insulating layer, and the orthographic projection of the second electrode on the substrate and the orthographic projection of the first electrode on the substrate have a second overlapping area.

10. The array substrate of claim 9, wherein, The first insulating layer further comprises a third insulating part, the orthographic projection of the third insulating part on the substrate and the second overlapping area have an overlap, and the thickness of the third insulating part is smaller than the thickness of the second insulating part.

11. The array substrate of claim 9, wherein, The orthographic projection of the source and the drain on the substrate and the orthographic projection of the second gate on the substrate have a fourth overlapping area; The second insulating layer comprises a fourth insulating part and a fifth insulating part, the orthographic projection of the fourth insulating part on the substrate and the second overlapping area have an overlap, the orthographic projection of the fifth insulating part on the substrate and the fourth overlapping area have an overlap, and the thickness of the fifth insulating part is greater than the thickness of the fourth insulating part.

12. The array substrate of claim 11, wherein, The second insulating layer further comprises a sixth insulating part, the orthographic projection of the sixth insulating part on the substrate and the orthographic projection of the channel part on the substrate have an overlap, and the thickness of the sixth insulating part is smaller than the thickness of the fifth insulating part.

13. The array substrate of claim 11, wherein, The array substrate further comprises a plurality of gate lines and a plurality of data lines, the second gate is arranged in the same layer as the gate line, and the source is arranged in the same layer as the data line; The orthographic projection of the data line on the substrate and the orthographic projection of the gate line on the substrate have a third overlapping area, the orthographic projection of the fifth insulating part on the substrate covers the third overlapping area and has no contact with the edge of the third overlapping area.

14. The array substrate of claim 11, wherein, The array substrate further comprises a plurality of gate lines and a plurality of data lines, the second gate is arranged in the same layer as the gate line, and the source is arranged in the same layer as the data line; the orthographic projection of the data line on the substrate is located in the range of the orthographic projection of the fifth insulating part on the substrate.

15. The array substrate of any one of claims 1 to 5, 8 to 14, wherein, The source and the drain are located on a side of the active layer away from the substrate; The array substrate further comprises a plurality of data lines, the data lines are arranged in the same layer as the source electrodes and are electrically connected, the data lines are provided with a redundant part close to one side of the substrate, the redundant part is arranged in the same layer as the active layer, and the orthographic projection of the data lines on the substrate is located in the orthographic projection range of the redundant part on the substrate.

16. A display panel, characterized by An array substrate as claimed in any of claims 1 to 15.

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