Semiconductor device and semiconductor structure

Abstract

An optical modulator structure in a photonic integrated circuit includes a U-shaped P-N junction at an optical mode of the optical modulator structure (e.g., a region of the optical modulator structure that produces light). The U-shaped P-N junction provides an increased P-N junction overlap area in optical mode relative to another type of junction (e.g., a horizontal junction or an I-junction). The increased overlapping area enables the optical modulator structure to achieve higher modulation efficiency.

Description

Technical Field

[0001] Embodiments of this utility model relate to semiconductor devices and semiconductor structures. Background Technology

[0002] Semiconductor devices may include photonic integrated circuits configured to use optical signals for high-speed and secure data transmission between multiple integrated circuits and / or multiple semiconductor dies within the semiconductor device. Optical signals enable high-performance computing systems to continuously and rapidly scale their performance to meet the growing demands of telecommunications (e.g., 5G, 6G), machine learning, artificial intelligence, and / or data center applications. Utility Model Content

[0003] This utility model provides a semiconductor device including a dielectric layer; and an optical modulator structure located in the dielectric layer, including: a first region including a first dopant type; a second region on the bottom surface of the first region including a second dopant type; and a third region on the bottom surface of the second region including the first dopant type, wherein the first region, the second region and the third region correspond to the PN junction diode of the optical modulator structure.

[0004] This utility model embodiment provides a semiconductor structure: a dielectric layer; and an optical modulator structure located in the dielectric layer, comprising: a first portion of a PN junction diode of the optical modulator structure, wherein the first portion includes a first dopant type; and a second portion of the PN junction diode, wherein the second portion includes a second dopant type, and wherein the second portion includes: a first segment in contact with the bottom surface of the first portion; a second segment in contact with the side surface of the first portion; and a third segment in contact with the top surface of the first portion. Attached Figure Description

[0005] The best understanding of all aspects of this invention will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figure 1 This is a diagram of an example environment in which the systems and / or methods described in this paper can be implemented.

[0007] Figure 2A-2B This is a diagram of the example semiconductor device described in this article.

[0008] Figures 3A-3B This is a diagram of the example semiconductor structure described in this article.

[0009] Figure 4A-4MThis is a diagram of an example implementation described herein.

[0010] Figure 5A-5J This is a diagram of an example implementation described herein.

[0011] Figure 6 This is what is described in this article Figure 1 A diagram of example components of one or more devices.

[0012] Figure 7 This is a flowchart of an example process related to forming the semiconductor structure described in this article.

[0013] [Explanation of Symbols]

[0014] 100: Environment

[0015] 102: Deposition tools / Semiconductor processing tools

[0016] 104: Exposure tools / Semiconductor processing tools

[0017] 106: Developing tools / Semiconductor processing tools

[0018] 108: Etching tools / Semiconductor processing tools

[0019] 110: Planarization tools / Semiconductor processing tools

[0020] 112: Plating tools / Semiconductor processing tools

[0021] 114: Photoresist removal tools / Semiconductor processing tools

[0022] 116: Ion Implantation Tools / Semiconductor Processing Tools

[0023] 118: Wafer / Die Delivery Tools

[0024] 200, 250: Semiconductor devices

[0025] 202: Optical Modulator Structure

[0026] 204: Waveguide Structure

[0027] 204a: Input waveguide

[0028] 204b: Output waveguide

[0029] 206: Coupling Region

[0030] 208, 210, 316, 318: Contact Area

[0031] 212, 214, 218, 220, 222: Connecting areas

[0032] 216: PN junction diode

[0033] 224: External Area

[0034] 226: Substrate

[0035] 228, 424, 430: Dielectric region

[0036] 300, 350, 400, 500: Example Implementation Methods

[0037] 302: Interface

[0038] 304a, 304b, 306, 308, 310a, 310b: Zone

[0039] 312, 314: Support Zones

[0040] 320, 322: Buffer zones

[0041] 402: Semiconductor layer

[0042] 404: Hard mask layer

[0043] 406, 408, 410, 412, 414: Photoresist layer

[0044] 416, 420: Silicate layers

[0045] 418, 422: Contact structure

[0046] 426, 428, 432, 434: Metallization layers

[0047] 600: Device

[0048] 610: Bus

[0049] 620: Processor

[0050] 630: Memory

[0051] 640: Input Component

[0052] 650: Output component

[0053] 660: Communication Components

[0054] 700: Process

[0055] 710, 720, 730: Squares Detailed Implementation

[0056] The following disclosure provides numerous different implementations or examples for achieving various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include implementations in which the first and second features are formed in direct contact, and may further include implementations in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various implementations and / or configurations discussed.

[0057] Furthermore, for ease of description, this document uses spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0058] Optical signals can be transmitted through waveguides in photonic integrated circuits. Waveguides confine optical signals, reducing optical loss and improving propagation efficiency. Data can be encoded into optical signals by modulating light into optical pulses in an optical modulator within the photonic integrated circuit. An optical modulator may include a PN junction, which modulates the electrical signal into an optical signal using a voltage signal applied to the PN junction. When a voltage is applied to the PN junction, the junction depletion width changes, resulting in changes in the electron and hole concentrations within the waveguide. These changes in electron and hole concentrations lead to changes in the effective refractive index of the waveguide, which in turn alters the light intensity within the waveguide. In other words, the voltage signal causes a change in the optical signal.

[0059] Increasing the modulation speed of a photonic integrated circuit can increase the bandwidth of the optical signal and / or the data transmission rate. In some cases, the optical bandwidth and / or electrical bandwidth of the photonic integrated circuit can be increased by reducing the electron / hole lifetime in the waveguide and / or introducing a high dose of impurities into the region connecting the optical waveguide and the optical modulator.

[0060] However, reducing the electron / hole lifetime in the waveguide can lead to a decrease in the Q-factor of the photonic integrated circuit, which may increase the full-width at half-maximum (FWHM) resonant wavelength line shape of the optical modulator. This increased FWHM resonant wavelength line shape can reduce the optical modulation amplitude of the optical modulator, which can lead to an increase in the bit error rate at the receiver receiving the optical signal generated by the optical modulator.

[0061] Some embodiments described herein provide techniques and apparatus for optical modulators in photonic integrated circuits, including a U-shaped PN junction. The U-shaped PN junction includes a p-type portion overlapping an n-type portion on both a first side and a second side opposite to the first side. Thus, the n-type portion includes a first volume contacting the top side of the p-type portion and a second volume contacting the bottom side of the p-type portion.

[0062] The U-shaped PN junction provides an increased overlap area between the junction and the optical mode (e.g., compared to a horizontal or I-shaped junction), which allows the optical modulator to achieve greater modulation efficiency due to the change in charge carrier concentration around the U-shaped PN junction. Higher modulation efficiency can lead to an increase in the modulation amplitude of the optical modulator. A larger modulation amplitude results in a lower bit error rate at the receiver receiving the optical signal generated by the optical modulator, particularly in high-bandwidth applications such as telecommunications (e.g., 5G, 6G, etc.), machine learning, artificial intelligence, and / or data center applications.

[0063] Figure 1 This is a diagram of an example environment 100 in which the systems and / or methods described herein can be implemented. (See diagram for example.) Figure 1 As shown, environment 100 may include multiple semiconductor processing tools 102-116 and wafer / die delivery tools 118. The multiple semiconductor processing tools 102-116 may include deposition tool 102, exposure tool 104, developing tool 106, etching tool 108, planarization tool 110, plating tool 112, photoresist removal tool 114, ion implantation tool 116, and / or another semiconductor processing tool. The tools included in the example environment 100 may be located in a semiconductor cleanroom, semiconductor foundry, semiconductor processing and / or manufacturing facility, or other location.

[0064] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more means for depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coater capable of depositing a photoresist layer on a substrate such as a wafer. In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low-pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, an epitaxial tool, or another type of CVD tool. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some embodiments, the example environment 100 includes multiple types of deposition tools 102.

[0065] Exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., deep UV, extreme UV (EUV), and / or similar), an X-ray source, an electron beam source, etc. Exposure tool 104 exposes the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. This pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, patterns for forming one or more structures of a semiconductor device, patterns for etching various portions of a semiconductor device, etc. In some embodiments, exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0066] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer exposed to a radiation source to develop a pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer.

[0067] Etching tool 108 is a semiconductor processing tool capable of etching various types of materials, including substrates, wafers, or semiconductor devices. For example, etching tool 108 may include wet etching tools, dry etching tools, etc. In some embodiments, etching tool 108 includes a chamber filled with an etchant, and a substrate is placed in the chamber for a specific time period to remove a specific amount of one or more portions of the substrate. In some embodiments, etching tool 108 may use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which may involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0068] Planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing layers of a wafer or semiconductor device. For example, planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for polishing or planarizing layers or surfaces of deposited or plated material. Planarization tool 110 can utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing) to polish or planarize the surface of the semiconductor device. Planarization tool 110 may combine a polishing pad and a retaining ring (e.g., typically having a diameter larger than the semiconductor device) to utilize abrasive and corrosive chemical polishing fluids. The polishing pad and semiconductor device can be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head can rotate on different axes of rotation to remove material and smooth any irregularities in the semiconductor device, making the semiconductor device flat or planar.

[0069] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, semiconductor device, etc.) or portions thereof with one or more metals. For example, the plating tool 112 may include a copper plating apparatus, an aluminum plating apparatus, a nickel plating apparatus, a tin plating apparatus, a compound material or alloy (e.g., tin-silver, tin-lead, etc.) plating apparatus, and / or an apparatus for plating one or more other types of conductive materials, metals, and / or similar materials.

[0070] Photoresist removal tool 114 is a semiconductor processing tool capable of removing the remaining portion of the photoresist layer from the substrate after a portion of the substrate has been removed by etching tool 108. For example, photoresist removal tool 114 may use chemical stripping agents and / or other techniques to remove the photoresist layer from the substrate.

[0071] The ion implantation tool 116 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 116 can generate ions from a source material, such as a gas or solid, in an arc chamber. The source material can be supplied to the arc chamber, and an arc voltage is discharged between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed toward the substrate, such that the ions are implanted below the surface of the substrate.

[0072] The wafer / die delivery tool 118 may be included in a clustering tool or another type of tool comprising multiple processing chambers, and may be configured to deliver substrates and / or semiconductor devices between multiple processing chambers, deliver substrates and / or semiconductor devices between processing chambers and buffers, transfer substrates and / or semiconductor devices between processing chambers and an interface tool such as an equipment front end module (EFEM), and / or transfer substrates and / or semiconductor devices between processing chambers and delivery carriers (e.g., front-opening unified pods, FOUPs). In some embodiments, the wafer / die delivery tool 118 may be included in a multi-chamber (or cluster) deposition tool 102, which may include pre-cleaning processing chambers (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from the substrate and / or semiconductor device), and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations).

[0073] In some embodiments, one or more of the semiconductor processing tools 102-116 and / or the wafer / die delivery tool 118 may perform one or more of the semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-116 and / or the wafer / die delivery tool 118 may use a first mask to form a first support region using a first dopant type, and may use a second mask to form a second support region using a second dopant type. Additionally, one or more of the semiconductor processing tools 102-116 and / or the wafer / die delivery tool 118 may use a third mask to dope a first region having a first dopant type, a second region having a second dopant type located below the first region, and a third region having a first dopant type located below the second region. The first, second, and third regions correspond to a PN junction diode and form the U-shaped interface of the PN junction diode.

[0074] Figure 1 The number and arrangement of the tools shown are provided as one or more examples. In reality, there may be... Figure 1 The tools shown are compared to additional tools, fewer tools, different tools, or tools arranged in a different way. Furthermore, Figure 1 The two or more tools shown can be implemented within a single tool, or Figure 1 The single tool shown can be implemented as multiple distributed tools. Alternatively, a set of tools in environment 100 (e.g., one or more tools) can perform one or more functions described as being performed by another set of tools in environment 100.

[0075] Figure 2A This is a diagram of the example semiconductor device 200 described herein. Specifically, Figure 2A A top view of semiconductor device 200 is shown. Semiconductor device 200 may include a semiconductor photonic device and / or another type of semiconductor device including one or more photonic integrated circuits.

[0076] Semiconductor device 200 can be configured to perform high-speed and secure data transmission between multiple integrated circuits and / or multiple semiconductor dies using optical signals. Therefore, semiconductor device 200 may include an optical modulator structure 202 and a waveguide structure 204 coupled to the optical modulator structure 202 in coupling region 206. Optical signals can be transmitted in semiconductor device 200 through waveguide structure 204. Waveguide structure 204 can confine optical signals, which can reduce optical loss and improve the propagation efficiency of optical signals. Data can be encoded into optical signals by modulating light into optical pulses in optical modulator structure 202. The optical pulses are then transmitted to waveguide structure 204 to propagate to other regions of semiconductor device 200. Optical modulator structure 202 and waveguide structure 204 can be adjacent and / or side-by-side in semiconductor device 200 to enable coupling of optical signals from optical modulator structure 202 to waveguide structure 204 (and vice versa for demodulation of optical signals).

[0077] The optical modulator structure 202 may include an approximately circular or approximately ring-shaped structure and may be referred to as a micro-ring modulator (MRM). The optical modulator structure 202 can serve as a resonance chamber and can modulate an input signal from an optical mode to generate an optical signal (e.g., a modulated optical signal). The optical signal may be coupled to a waveguide structure 204 in coupling region 206 based on an optical signal that satisfies a threshold modulation frequency and / or an optical signal that satisfies a threshold signal strength. The waveguide structure 204 can facilitate the propagation of the optical signal to another device or a region within semiconductor device 200.

[0078] like Figure 2A As further shown, the optical modulator structure 202 may include multiple regions. For example, the optical modulator structure 202 may include a contact region 208 and an opposing contact region 210. The contact region 208 may be located at the outer perimeter of the optical modulator structure 202, and the contact region 210 may be located at the inner perimeter of the optical modulator structure 202. The contact regions 208 and 210 may be multiple regions of the optical modulator structure 202, which are electrically and / or physically coupled to the contacts of the semiconductor device 200.

[0079] The optical modulator structure 202 may further include connection region 212 and connection region 214. Connection region 212 may be electrically coupled and / or physically coupled to contact region 208 and PN junction diode 216 of the optical modulator structure 202. Connection region 212 may electrically couple PN junction diode 216 to contact region 208. Connection region 214 may be electrically coupled and / or physically coupled to contact region 210 and PN junction diode 216 of the optical modulator structure 202. Connection region 214 may electrically couple PN junction diode 216 to contact region 210.

[0080] PN junction diode 216 is located in the optical mode of optical modulator structure 202. PN junction diode 216 includes p-type and n-type regions coupled at an interface. As described herein, the interface may be referred to as a U-shaped interface. The interface may be referred to as a U-shaped interface because the interface includes at least two directional segments. For example, the interface may include a generally vertical segment in which p-type and n-type regions are coupled, a generally horizontal first segment in which p-type and n-type regions are coupled, and a generally horizontal second segment in which p-type and n-type regions are coupled. The generally horizontal segments may be parallel or at least substantially parallel (e.g., within an error range of 5° or 10°). The connection between the generally vertical segment and the generally horizontal segments may be an approximately 90-degree interface or a similar angle, such that in the generally horizontal first segment, the n-type region overlaps the p-type region (or the p-type region overlaps the n-type region) (e.g., on top of it), and in the generally horizontal second segment, the p-type region overlaps the n-type region (or the n-type region overlaps the p-type region) (e.g., on top of it). The U-shaped interface increases the overlap area between the n-type and p-type regions (e.g., increases the overlap area between the PN junction diode 216 and the optical mode), which allows the optical modulator structure 202 to achieve higher modulation efficiency due to the change in charge carrier concentration around the U-shaped interface. Higher modulation efficiency leads to an increase in the modulation amplitude of the optical modulator structure 202. This can result in a lower bit error rate at the receiver receiving the optical signal generated by the optical modulator structure 202.

[0081] like Figure 2A As further shown, in coupling region 206, the optical modulator structure 202 may include a contact region 210, a connection region 218 coupling the contact region 210 to the optical modulator structure 202, a connection region 220 coupling the optical modulator structure 202 to the waveguide structure 204, and a connection region 222 coupling the waveguide structure 204 to the external region 224. In semiconductor device 200, the optical modulator structure 202 and the waveguide structure 204 are partially integrated in connection region 220. Other examples may include an optical modulator structure 202 separate from the waveguide structure 204.

[0082] Semiconductor device 200 may include a substrate 226 and a dielectric region 228 including an optical modulator structure 202 and a waveguide structure 204. The substrate 226 may be formed of silicon (Si), a silicon-containing material, a III-V compound semiconductor material such as gallium arsenide (GaAs), and / or another type of semiconductor material. The dielectric region 228 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y The dielectric materials used may include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide, and / or other dielectric materials. Waveguide structure 204 may include an undoped semiconductor structure (e.g., an undoped silicon structure) in dielectric region 228. Optical modulator structure 202 may include one or more doped semiconductor regions in the dielectric region, such as one or more p-type regions (e.g., semiconductor regions, such as silicon regions, which include one or more p-type dopants) and one or more n-type regions (e.g., semiconductor regions, such as silicon regions, which include one or more n-type dopants).

[0083] Figure 2B This is a diagram of the example semiconductor device 250 described herein. Specifically, Figure 2B A top view of semiconductor device 250 is shown. Semiconductor device 250 may include a semiconductor photonic device and / or another type of semiconductor device including one or more photonic integrated circuits. Specifically, semiconductor device 250 may include an optical modulator structure 202 coupled to an input waveguide 204a and an output waveguide 204b. Optical modulator structure 202 may include a Mach-Zehnder modulator (MZM) structure. Furthermore, optical modulator structure 202 may include a U-shaped interface in the PN junction diode 216 of optical modulator structure 202, such as combined with... Figure 3A and Figure 3B As described. The optical modulator structure 202 contained in the semiconductor device 250 can be used in combination with Figure 4A-4M and / or Figure 5A-5J The technology described is used to form it.

[0084] The MZM structure of the optical modulator structure 202 enables it to generate modulated light output from input light supplied to it via input waveguide 204a. The input light can be split and supplied to different arms of the optical modulator structure 202 and modulated using the optical mode of the PN junction diode 216. This allows the input light to be phase-modulated by multiple phase shifters in the optical modulator structure 202 and then recombined in the output waveguide 204b to form the modulated light output.

[0085] As mentioned above, providing Figure 2A and Figure 2B As an example. Other examples can be related to... Figure 2A and Figure 2B The descriptions are different.

[0086] Figure 3A This is a diagram of an exemplary embodiment 300 of the optical modulator structure 202 described herein. The optical modulator structure 202 may be included in the semiconductor photonic circuitry of a semiconductor photonic device, for example... Figure 2A Semiconductor device 200 or Figure 2B Semiconductor devices such as 250.

[0087] Figure 3A A cross-sectional view of the optical modulator structure 202 is shown. The optical modulator structure 202 may be contained in a dielectric region 228. The dielectric region 228 may be included on and / or on a substrate 226, and may include one or more dielectric layers, one or more shallow trench isolation (STI) regions, one or more etchstop layers (ESL), and / or one or more other dielectric structures.

[0088] like Figure 3A As further shown, the optical modulator structure 202 may include multiple doped semiconductor regions. These multiple doped regions can form the interface 302 of a PN junction diode. For example... Figure 3A As shown, interface 302 can be a U-shaped interface.

[0089] Multiple doped regions may comprise silicon (and / or another semiconductor material) doped with one or more types of dopants (e.g., n-type and / or p-type dopants). The optical modulator structure 202 may include regions 304a and 304b of a PN junction diode, which include a first dopant type. The optical modulator structure 202 may further include region 306 of a PN junction diode, which includes a second dopant type (e.g., different from the first dopant type). Region 306 may be located between regions 304a and 304b and may be coupled to regions 304a and 304b at interface 302.

[0090] The optical modulator structure 202 may further include region 308 of a PN junction diode. Region 308 may be adjacent to region 306 and may include a first dopant type. The optical modulator structure 202 may include regions 310a and 310b of a PN junction diode. Regions 310a and 310b may include a first dopant type. Region 310a may be adjacent to region 304a, and region 310b may be adjacent to region 304b. Region 308 may be located below and / or beneath region 310a and may be located above and / or on region 310b.

[0091] In some embodiments, region 306 may correspond to the first region of a PN junction diode, while regions 304a, 304b, and 308 may be multiple segments of the second region of a PN junction diode. For example, region 306 may include a p-type region (where the second dopant type may be a p-type dopant), and regions 304a, 304b, and 308 may include an n-type region (where the first dopant type may be an n-type dopant) such that the n-type region surrounds the p-type region. The p-type dopant may include p-type ions of a p-type material (e.g., boron (B) or germanium (Ge)). The n-type dopant may include n-type ions of an n-type material (e.g., phosphorus (P) or arsenic (As)). Alternatively, region 306 may include an n-type region (where the second dopant type may be an n-type dopant), and regions 304a, 304b, and 308 may include p-type regions (where the first dopant type may be a p-type dopant) such that the p-type region surrounds the n-type region. Interface 302 may be a U-shaped interface (or two-dimensional interface) between the first and second regions of a PN junction diode, comprising a first segment between region 304b and region 306, a second segment between region 308 and region 306, and a third segment between region 304a and region 306. The U-shaped interface may correspond to a lateral “U” (e.g., a “U” rotated approximately 90 degrees) in a cross-sectional view of interface 302, wherein the first and third segments are parallel to the surface of substrate 226, and the second segment connects to the first and third segments at opposite ends of the second segment. The second segment may be approximately perpendicular to the surface of substrate 226 and perpendicular to the first and third segments. The U-shaped interface may also be referred to as a C-shaped interface. Alternatively or additionally, interface 302 may comprise a lateral “J” shape in a cross-sectional view of interface 302, wherein the first segment is longer than the third segment or the third segment is longer than the first segment.

[0092] like Figure 3A As further shown, except for the first and third sections (which are generally horizontal), sections 304a and 304b both contact section 306 along generally vertical sections. For example, by using a combination Figure 5A-5J The described technique forms multiple approximately vertical segments and further increases the surface area associated with interface 302.

[0093] In some embodiments, the ratio of the height of the support region 312 to the height of the PN junction diode (i.e., the heights of regions 304a, 304b, and 306 at interface 302) is in the range of approximately 0.25 to approximately 0.40. For example, when the height of the PN junction diode can be 270 nanometers (nm), the height of the support region 312 can range from approximately 70 nm to approximately 110 nm. Choosing a ratio of at least 0.25 will reduce the resistance from the junction region 316 to the PN junction diode—a smaller ratio will suppress the flow of charge carriers. Choosing a ratio not exceeding 0.40 reduces light loss due to the support region 312—a larger ratio will result in more light being absorbed and lost by the support region 312. A similar ratio also applies to the support region 314. However, other values ​​and / or ranges of this ratio, the height of the support region 312, and / or the height of the PN junction diode are also within the scope of this disclosure.

[0094] In some embodiments, the ratio of the height of region 306 (at interface 302) to the height of the PN junction diode can range from about 0.3 to about 0.5. For example, when the height of the PN junction diode can be 270 nm, the height of region 306 can range from about 90 nm to about 130 nm. Choosing a ratio of at least 0.3 improves the modulation efficiency at the PN junction diode—a smaller ratio would result in insufficient charge carriers from region 306. Choosing a ratio of no more than 0.5 improves the modulation efficiency at the PN junction diode—a larger ratio would result in insufficient charge carriers from regions 304a and 304b. However, other values ​​and / or ranges of this ratio, the height of region 306, and / or the height of the PN junction diode are also within the scope of this disclosure.

[0095] In some implementations, the ratio of the height of region 304a (at interface 302) to the height of the PN junction diode can range from about 0.22 to about 0.37. For example, when the height of the PN junction diode can be 270 nm, the height of region 304a can range from about 60 nm to about 100 nm. Choosing a ratio of at least 0.22 improves the modulation efficiency at the PN junction diode—a smaller ratio would result in insufficient charge carriers from region 304a. Choosing a ratio of no more than 0.37 improves the modulation efficiency at the PN junction diode—a larger ratio would result in insufficient charge carriers from region 306. Therefore, the thickness of region 306 (at interface 302) can be greater than the thickness of region 304a (at interface 302) to ensure a sufficient number of charge carriers from region 306 at interface 302. Furthermore, a similar ratio applies to region 304b. However, some implementations may include region 304a that is thinner than region 304b. Region 304b can be thicker than region 304a because more charge carriers accumulate at the overlap of region 306 with region 304b than at the overlap of region 306 with region 304a. As a result, region 304b can be thicker to ensure a sufficient number of charge carriers from region 304b at interface 302. Additionally, the thickness of region 306 (at interface 302) can be greater than the thickness of region 304b (at interface 302) to ensure a sufficient number of charge carriers from region 306 at interface 302. In some embodiments, the thickness of region 306 (at interface 302) can be greater than the sum of the thicknesses of region 304a and region 304b because region 306 is also connected to region 308 (and therefore should provide more charge carriers than regions 304a and 304b). However, other values ​​and / or ranges of this ratio, the height of region 304a, and / or the height of the PN junction diode are also within the scope of this disclosure.

[0096] In some embodiments, the ratio of the width of region 310a (similarly, the width of region 308 at the top portion of region 308) to the width of the PN junction diode (i.e., the widths of regions 310a, 304a, and 306 along the top surface of dielectric region 228) can range from about 0.12 to about 0.50. For example, when the width of the PN junction diode can be 400 nm, the width of region 310a can range from about 50 nm to about 200 nm. Choosing a ratio of at least 0.12 will reduce the resistance from junction region 316 to the PN junction diode—a smaller ratio will suppress the flow of charge carriers. Choosing a ratio not exceeding 0.50 improves modulation efficiency—a larger ratio will reduce the surface area of ​​interface 302 and suppress modulation. A similar ratio applies to the width of the portion of region 306 that does not overlap with region 304a. However, other values ​​and / or ranges of this ratio, the width of region 310a, and / or the width of the PN junction diode are also within the scope of this disclosure.

[0097] The optical modulator structure 202 may further include a support region 312 physically and / or electrically coupled to regions 308 and 310b. The support region 312 may include a first dopant type, such that regions 304a, 304b, 308, 310a, and 310b include the same dopant type as the support region 312 (e.g., n-type or p-type dopant). The optical modulator structure 202 may further include a support region 314 physically and / or electrically coupled to region 306. The support region 314 may include a second dopant type, such that region 306 includes the same dopant type as the support region 314 (e.g., n-type or p-type dopant).

[0098] The optical modulator structure 202 may further include a contact region 316 physically and / or electrically coupled to the support region 312. The contact region 316 may include a first dopant type, such that regions 304a, 304b, 308, 310a, and 310b include the same dopant type as the support region 312 and the contact region 316 (e.g., n-type or p-type dopant). The optical modulator structure 202 may further include a contact region 318 physically and / or electrically coupled to the support region 314. The contact region 318 may include a second dopant type, such that region 306 includes the same dopant type as the support region 314 and the contact region 318 (e.g., n-type or p-type dopant). The dopant concentrations in regions 304a, 304b, 308, 310a and 310b, support region 312, and junction region 316 can be configured to promote and / or facilitate the flow of charge carriers (e.g., electrons, holes) from junction region 316 through support region 312 to regions 304a, 304b, 308, 310a, and 310b. Different dopant concentrations create dopant gradients that favor charge carrier flow. Similarly, the dopant concentrations in region 306, support region 314, and junction region 318 can be configured to promote and / or facilitate the flow of charge carriers (e.g., electrons, holes) from region 306 through support region 314 to junction region 318. Different dopant concentrations create dopant gradients that favor charge carrier flow.

[0099] like Figure 3A As further shown, buffer 320 can provide a dopant gradient between junction region 316 and support region 312. Similarly, buffer 322 can provide a dopant gradient between junction region 318 and support region 314. For example, by using bonding Figure 5A-5J The described technique forms a buffer zone 322 to provide better control over the flow of charge carriers from the support region 314 to the junction region 318.

[0100] Contact area 208 and contact area 210 (if combined) Figure 2A and 2B The described areas can correspond to contact areas 316 and 318, respectively. Similarly, connection areas 212 and 214 (as combined) Figure 2A and 2B The described regions can correspond to support regions 312 and 314, respectively. Finally, the PN junction diode 216 (as described) Figure 2A and 2B The described area can correspond to zones 304a, 304b, 306, 308, 310a, and 310b.

[0101] Figure 3BThis is a figure of an exemplary embodiment 350 of the optical modulator structure 202 described herein. The optical modulator structure 202 may be included in the semiconductor photonic circuitry of a semiconductor photonic device, for example... Figure 2A Semiconductor device 200 or Figure 2B Semiconductor devices such as 250.

[0102] Example implementation 350 is similar to example implementation 300. In example implementation 350, region 304a extends along the entire top surface of region 306 and therefore does not contact region 306 along approximately vertical segments. For example, by using a bonding Figure 4A-4M In the described technique, region 304a is formed prior to region 306, such that region 304a extends along the entire top surface of region 306. As a result, the segment between region 304a and region 306 may be longer than the segment between region 304b and region 306.

[0103] In addition, such as Figure 3B As shown, buffer 322 does not exist. For example, by using combination Figure 4A-4M The described technique uses a single implantation operation instead of two implantation operations to form the support region 314, and therefore does not have a buffer 322 between the support region 314 and the contact region 318.

[0104] As mentioned above, providing Figure 3A and Figure 3B As an example. Other examples can be related to... Figure 3A and 3B The descriptions are different.

[0105] Figure 4A-4M This is a diagram illustrating an exemplary embodiment 400 of the semiconductor device (or a portion thereof) described herein. Specifically, among other examples, exemplary embodiment 400 may include examples of forming an optical modulator structure 202 in semiconductor device 200 and / or semiconductor device 250. In some embodiments, one or more of the semiconductor processing operations described in connection with exemplary embodiment 400 may be performed by one or more of semiconductor processing tools 102-116 and / or by wafer / die delivery tool 118. In some embodiments, one or more semiconductor processing operations described in connection with exemplary embodiment 400 may be performed by another semiconductor processing tool.

[0106] like Figure 4A As shown, a substrate 226 (e.g., as a semiconductor wafer) may be provided. The deposition tool 102 may form dielectric regions 228 on and / or on the substrate 226 (e.g., using CVD, PVD, oxidation and / or another type of deposition technique).

[0107] Alternatively, substrate 226 and dielectric region 228 may be provided as part of a silicon-on-insulator (SOI) substrate. For example, dielectric region 228 may be a buried oxide or bottom oxide (BOX) layer and / or another type of insulating layer on and / or on substrate 226.

[0108] like Figure 4B As shown, a semiconductor layer 402 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) can be formed on and / or on the dielectric region 228. For example, the deposition tool 102 can form the semiconductor layer 402 (e.g., using CVD, PVD, epitaxial technology, and / or another type of deposition technology). Alternatively, the semiconductor layer 402 can be provided as part of the SOI substrate (e.g., as described above).

[0109] like Figure 4B As further shown, a hard mask layer 404 may be formed on and / or on the semiconductor layer 402, and the pattern in the hard mask layer 404 may be used to pattern the semiconductor layer 402. A deposition tool 102 may form the hard mask layer 404 on the semiconductor layer 402 (e.g., using CVD, PVD, and / or another type of deposition technique) and may form a photoresist layer on the hard mask layer 404 (e.g., using spin coating and / or another type of deposition technique). The hard mask layer 404 may include silicon nitride (Si). x N y Materials such as Si3N4 or another hard mask material.

[0110] Exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer. Development tool 106 develops and removes portions of the photoresist layer to expose the pattern. Etching tool 108 etches a hard mask layer 404 to transfer the pattern from the photoresist layer to the hard mask layer 404. The etching tool 108 then etches the semiconductor layer 402 based on the pattern in the hard mask layer 404. In some embodiments, plasma etching, wet chemical etching, and / or another type of etching operation is used to etch the semiconductor layer 402. In some embodiments, photoresist removal tool 114 removes the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0111] like Figure 4CAs shown, a photoresist layer 406 can be formed on and / or on the dielectric region 228. The deposition tool 102 can use spin coating and / or another type of deposition technique to form the photoresist layer 406. An exposure tool 104 can expose the photoresist layer 406 to a radiation source, and a developing tool 106 can develop and remove portions of the photoresist layer 406 to pattern the photoresist layer 406 (e.g., as shown). Figure 4C (As shown).

[0112] like Figure 4C As further shown, a portion of the semiconductor layer 402 may be doped with a first dopant type (e.g., one or more dopant materials classified as the first type) to form a doped semiconductor region. For example, the ion implantation tool 116 may use a combination of the hard mask layer 404 and the photoresist layer 406 as an implantation mask to perform one or more doping or ion implantation operations. Thus, a support region 312 may be formed.

[0113] In some embodiments, the first dopant type includes an n-type dopant, such as phosphorus (P). In these embodiments, phosphorus ions are implanted into the semiconductor layer 402 using an implantation energy ranging from approximately 80 keV to approximately 130 keV, and the dose of phosphorus ions used can include approximately 1 × 10⁻⁶. 14 ions / cm³ 3 Up to approximately 6×10 14 ions / cm 3 However, other values ​​within these ranges are also within the ranges disclosed herein.

[0114] Alternatively or concurrently, the first dopant type may include arsenic (As). In these embodiments, arsenic ions are implanted into the semiconductor layer 402 using an implantation energy ranging from approximately 40 keV to approximately 60 keV, and the dose of arsenic ions used may include approximately 5 × 10⁻⁶ kilovolts. 13 ions / cm 3 Up to approximately 5×10 14 ions / cm 3 However, other values ​​within these ranges are also within the scope of this disclosure.

[0115] In some embodiments, the ion implantation tool 116 bombards the surface of the semiconductor layer 402 at one or more angles to implant ions into a plurality of exposed sidewalls of the semiconductor layer 402. Here, the ion implantation in the plurality of sidewalls is self-aligned with the hard mask layer 404, meaning that the hard mask layer 404 acts as an implantation barrier. Ions can be implanted into the plurality of sidewalls at tilt angles ranging from about 45 degrees to about -45 degrees. However, other values ​​in this range are also within the scope of this disclosure. The tilt angle may refer to the bombardment angle relative to an angle substantially perpendicular to the substrate 226.

[0116] like Figure 4D As shown, the carrier concentration in the support region 312 can be increased. For example, the ion implantation tool 116 can implant additional n-type dopant material, such as phosphorus (P). In some embodiments, implantation energies ranging from about 10 keV to about 30 keV are used to implant additional phosphorus ions into the semiconductor layer 402, and the dose of phosphorus ions used can include about 1 × 10⁻⁶. 14 ions / cm 3 Approximately 3×10 15 ions / cm 3 However, other values ​​within these ranges are also within the scope of this disclosure. Additionally, phosphate ions can be implanted at tilt angles ranging from about 0 degrees to about 30 degrees. However, other values ​​within this range are also within the scope of this disclosure.

[0117] like Figure 4D As further shown, increasing the carrier concentration at support region 312 creates buffer zone 320 (with a smaller doping concentration than support region 312). Additionally, increasing the carrier concentration at support region 312 creates region 308 (with a smaller doping concentration than support region 312).

[0118] The carrier concentration can be increased using the same mask (i.e., the same photoresist layer 406) used to form the support region 312. Alternatively, the photoresist layer 406 can be repatterned (e.g., to protect region 308) before the carrier concentration is increased. After the carrier concentration is increased, the photoresist removal tool 114 can then remove the remaining portion of the photoresist layer 406 (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0119] like Figure 4EAs shown, another photoresist layer 408 can be formed on and / or on the dielectric region 228. The deposition tool 102 can use spin coating and / or another type of deposition technique to form the photoresist layer 408. The exposure tool 104 can expose the photoresist layer 408 to a radiation source, and the developing tool 106 can develop and remove portions of the photoresist layer 408 to pattern the photoresist layer 408 (e.g., as shown). Figure 4E (As shown). The support region 312 can be covered by the photoresist layer 408, allowing a second dopant type to be implanted into another region of the semiconductor layer 402.

[0120] like Figure 4E As further shown, a portion of the semiconductor layer 402 may be doped with a second type of dopant (e.g., one or more dopant materials classified as a second type) to form a doped semiconductor region. For example, the ion implantation tool 116 may use a combination of the hard mask layer 404 and the photoresist layer 408 as an implantation mask to perform one or more doping or ion implantation operations. Thus, a support region 314 may be formed.

[0121] In some embodiments, the second dopant type includes a p-type dopant, such as boron (B). In these embodiments, boron ions are implanted into the semiconductor layer 402 using an implantation energy ranging from about 10 keV to about 30 keV, and the dose of boron ions used can include about 1 × 10⁻⁶. 14 ions / cm 3 Approximately 3×10 15 ions / cm 3 However, other values ​​within these ranges are also within the scope of this disclosure. Additionally, boron ions can be implanted at tilt angles ranging from about 0 degrees to about 30 degrees. However, other values ​​within this range are also within the scope of this disclosure.

[0122] After the support region 314 is formed, a photoresist removal tool can subsequently remove the remaining portion of the photoresist layer 408 (e.g., using chemical strippers, plasma ashing, and / or other techniques). By forming the support region 314 using a single implantation operation, power, processing resources, and raw materials can be saved. Additionally, the manufacturing time for forming the optical modulator structure 202 is reduced.

[0123] like Figure 4FAs shown, additional material can be deposited for dielectric region 228. For example, deposition tool 102 can use CVD, PVD, oxidation techniques (e.g., thermal oxidation), and / or another type of deposition technique to deposit additional material for dielectric region 228. In some embodiments, STI liner oxidation operation and / or high-density plasma (HDP) deposition operation can be used to deposit additional material for dielectric region 228. In some embodiments, planarization tool 110 can perform CMP operation and / or another type of planarization operation to planarize dielectric region 228 after depositing additional material for dielectric region 228. CMP operation can additionally remove hard mask layer 404. Additionally and / or alternatively, etching tool 108 can remove hard mask layer 404 (e.g., using dry etching and / or wet / chemical etching).

[0124] like Figure 4G As shown, another photoresist layer 410 can be formed on and / or on the dielectric region 228. The deposition tool 102 can use spin coating and / or another type of deposition technique to form the photoresist layer 410. The exposure tool 104 can expose the photoresist layer 410 to a radiation source, and the developing tool 106 can develop and remove portions of the photoresist layer 410 to pattern the photoresist layer 410 (e.g., as shown). Figure 4G (As shown). A portion of the semiconductor layer 402 that forms the PN junction diode can be exposed through the pattern of the photoresist layer 410.

[0125] like Figure 4G As further shown, a portion of semiconductor layer 402 may be doped with a first dopant type (e.g., one or more dopant materials classified as the first type) to form a doped semiconductor region. For example, ion implantation tool 116 may use photoresist layer 410 as an implantation mask to perform one or more doping or ion implantation operations. Thus, region 304b can be formed. Figure 4G As further shown, the ion implantation in region 304b results in region 310b (with a higher doping concentration than region 308).

[0126] In some embodiments, the first dopant type includes an n-type dopant, such as phosphorus (P). In these embodiments, phosphorus ions are implanted into the semiconductor layer 402 using an implantation energy ranging from approximately 140 keV to approximately 180 keV, and the dose of phosphorus ions used can include approximately 5 × 10⁻⁶. 13 ions / cm 3 Approximately 5×10 14 ions / cm 3However, other values ​​within these ranges are also within the scope of this disclosure.

[0127] like Figure 4H As shown, additional doping operations can be performed. In the first implantation operation, the ion implantation tool 116 can implant additional n-type dopant material, such as phosphorus (P). In some embodiments, implantation energies ranging from approximately 25 keV to approximately 50 keV are used to implant additional phosphorus ions into the semiconductor layer 402, and the dose of phosphorus ions used can include approximately 5 × 10⁻⁶. 13 ions / cm 3 Approximately 5×10 14 ions / cm 3 However, other values ​​within these ranges also fall within the scope of this disclosure. Therefore, region 304a can be formed. For example... Figure 4H As further shown, the ion implantation formation region 304a results in region 310a (where the doping concentration is greater than that in region 308 due to the migration of ions from region 304a to region 310a).

[0128] In the second implantation operation, the ion implantation tool 116 can implant a p-type dopant material, such as boron (B). In some embodiments, boron ions are implanted into the semiconductor layer 402 using an implantation energy ranging from about 30 keV to about 50 keV. Using a higher implantation energy than that used for the n-type dopant to form region 304a allows a PN junction to be formed at the bottom surface of region 304a. The dose of boron ions used can include about 5 × 10⁻⁶. 13 ions / cm 3 Approximately 5×10 14 ions / cm 3 Within the range. However, other values ​​within these ranges are also within the range disclosed herein. Therefore, a zone 306 connected to zone 304a can be formed.

[0129] In the third implantation operation, the ion implantation tool 116 can implant additional p-type dopant material, such as boron (B). In some embodiments, an implantation energy ranging from about 50 keV to about 70 keV is used to implant additional boron ions into the semiconductor layer 402. Using an implantation energy greater than that used in the second implantation operation allows a PN junction to be formed at the top surface of region 304b. The dose of boron ions used can include about 5 × 10⁻⁶. 13 ions / cm 3 Approximately 5×10 14 ions / cm 3 However, other values ​​within these ranges are also within the range disclosed herein. Therefore, zone 306 can be extended to be connected to zone 304b.

[0130] Regions 304a and 306 can be formed using the same mask (i.e., the same photoresist layer 410) used to form regions 304b and 310b. Alternatively, the photoresist layer 410 can be repatterned (e.g., to protect region 308). After the carrier concentration is increased, the photoresist removal tool 114 can subsequently remove the remaining portion of the photoresist layer 410 (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0131] like Figure 4I As shown, another photoresist layer 412 can be formed on and / or on the dielectric region 228. The deposition tool 102 can use spin coating and / or another type of deposition technique to form the photoresist layer 412. The exposure tool 104 can expose the photoresist layer 412 to a radiation source, and the developing tool 106 can develop and remove portions of the photoresist layer 412 to pattern the photoresist layer 412 (e.g., as shown). Figure 4I (As shown). A portion of the semiconductor layer 402 forming the contact region can be exposed through the pattern of the photoresist layer 412.

[0132] like Figure 4I As further shown, a portion of the semiconductor layer 402 may be doped with a first dopant type (e.g., one or more dopant materials classified as the first type) to form a doped semiconductor region. For example, the ion implantation tool 116 may use the photoresist layer 412 as an implantation mask to perform one or more doping or ion implantation operations. Thus, a contact region 316 may be formed.

[0133] The photoresist removal tool can then remove the remaining portion of the photoresist layer 412 (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, rapid thermal annealing (RTA) and / or furnace thermal activation operations are used to promote the activation and / or absorption of dopants in the junction region 316.

[0134] like Figure 4J As shown, another photoresist layer 414 may be formed on and / or on the dielectric region 228. The deposition tool 102 may use spin coating and / or another type of deposition technique to form the photoresist layer 414. The exposure tool 104 may expose the photoresist layer 414 to a radiation source, and the developing tool 106 may develop and remove portions of the photoresist layer 414 to pattern the photoresist layer 414 (e.g., as shown). Figure 4J (As shown). A portion of the semiconductor layer 402 forming the contact region can be exposed through the pattern of the photoresist layer 414.

[0135] like Figure 4JAs further shown, a portion of semiconductor layer 402 may be doped with a second type of dopant (e.g., one or more dopant materials classified as a second type) to form a doped semiconductor region. For example, ion implantation tool 116 may use photoresist layer 414 as an implantation mask to perform one or more doping or ion implantation operations. Thus, contact region 318 may be formed.

[0136] The photoresist removal tool can then remove any remaining portion of the photoresist layer 414 (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, RTA operations and / or furnace activation operations are used to promote the activation and / or absorption of dopants in the junction region 318.

[0137] like Figure 4K As shown, silicide layer 416 may be formed on and / or on the top surface of contact region 316, and silicide layer 420 may be formed on and / or on the top surface of contact region 318. Silicide layer 416 and silicide layer 420 may each comprise a metal silicide layer. Deposition tool 102 may use CVD, PVD, ALD, silicide technology, and / or another deposition technique to deposit silicide layer 416 and silicide layer 420. In some embodiments, deposition tool 102 may perform a pre-cleaning operation to remove oxides (e.g., native oxides) from the top surfaces of contact region 316 and contact region 318 before forming silicide layer 416 and silicide layer 420.

[0138] like Figure 4K As further shown, additional material can be deposited for dielectric region 228. For example, deposition tool 102 can use CVD, PVD, oxidation (e.g., thermal oxidation) and / or another type of deposition technique to deposit the additional material for dielectric region 228. In some embodiments, planarization tool 110 can perform CMP operations and / or another type of planarization operations to planarize dielectric region 228 after depositing additional material.

[0139] like Figure 4KAs shown, contact structures 418 and 422 can be formed in dielectric region 228. Contact structure 418 can be formed over contact region 316 and rest on silicide layer 416. Contact structure 422 can be formed over contact region 318 and rest on silicide layer 420. Contact structures 418 and 422 can be formed in multiple grooves formed over contact regions 316 and 318, respectively. In some embodiments, a pattern in the photoresist layer is used to etch dielectric region 228 to form multiple grooves. In these embodiments, deposition tool 102 forms a photoresist layer on dielectric region 228, exposure tool 104 exposes the photoresist layer to a radiation source to pattern the photoresist layer, development tool 106 develops and removes portions of the photoresist layer to expose the pattern, and etching tool 108 etches dielectric region 228 based on the pattern to form multiple grooves. The dielectric region 228 can be etched using plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, the photoresist removal tool 114 removes the remaining portion of the photoresist layer after forming multiple grooves (e.g., using chemical strippers, plasma ashing, and / or other techniques). A hard mask layer can be used as an alternative to etching the dielectric region 228.

[0140] The deposition tool 102 and / or plating tool 112 can deposit contact structures 418 and 422 in multiple grooves (e.g., using CVD, PVD, ALD, electroplating, and / or another type of deposition technique).

[0141] like Figure 4L As shown, dielectric region 424 may be formed on and / or on dielectric region 228. For example, deposition tool 102 may use CVD technology, PVD technology, oxidation technology (e.g., thermal oxidation technology) and / or another type of deposition technology to deposit dielectric region 424.

[0142] like Figure 4LAs further shown, metallization layers 426 and 428 can be formed in the dielectric region 424. Metallization layer 426 can be formed over the contact structure 418. Metallization layer 428 can be formed over the contact structure 422. Metallization layers 426 and 428 can each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), as well as other examples of conductive materials. Metallization layers 426 and 428 can include vias, trenches, contact plugs, and / or another type of metallization layer. In some embodiments, etching tool 108 can remove a portion of the dielectric region 424 to expose contact structures 418 and 422. Deposition tool 102 and / or plating tool 112 can deposit metallization layers 426 and 428 in CVD operations, PVD operations, ALD operations, electroplating techniques, and / or another type of deposition technique. In some embodiments, a seed layer is first deposited, and metallization layers 426 and 428 are deposited on the seed layer. In some embodiments, a planarization tool 110 planarizes metallization layers 426 and 428.

[0143] like Figure 4M As shown, dielectric region 430 may be formed on and / or on dielectric region 424. For example, deposition tool 102 may use CVD technology, PVD technology, oxidation technology (e.g., thermal oxidation technology) and / or another type of deposition technology to deposit dielectric region 430.

[0144] like Figure 4M As further shown, metallization layers 432 and 434 can be formed in the dielectric region 430. Metallization layer 432 can be formed over metallization layer 426. Metallization layer 434 can be formed over metallization layer 428. Metallization layers 432 and 434 can each include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), as well as other examples of conductive materials. Metallization layers 432 and 434 can include vias, trenches, contact plugs, and / or another type of metallization layer. In some embodiments, etching tool 108 can remove a portion of the dielectric region 430 to expose metallization layers 426 and 428. Deposition tool 102 and / or plating tool 112 can deposit metallization layers 432 and 434 in CVD operations, PVD operations, ALD operations, electroplating techniques, and / or another type of deposition technique. In some embodiments, a seed layer is first deposited, and metallization layers 432 and 434 are then deposited on the seed layer. In some embodiments, a planarization tool 110 planarizes the metallization layers 432 and 434.

[0145] Additional dielectric regions and / or additional metallization layers can be formed until a sufficient or target amount of metallization layer is formed.

[0146] As mentioned above, providing Figure 4A-4M As an example. Other examples can be related to... Figure 4A-4M The descriptions are different.

[0147] Figure 5A-5J This is a diagram illustrating an exemplary embodiment 500 of the semiconductor device (or a portion thereof) described herein. Specifically, among other examples, exemplary embodiment 500 may include examples of forming an optical modulator structure 202 in semiconductor device 200 and / or semiconductor device 250. In some embodiments, one or more of the semiconductor processing operations described in connection with exemplary embodiment 500 may be performed by one or more of semiconductor processing tools 102-116 and / or by wafer / die delivery tool 118. In some embodiments, one or more semiconductor processing operations described in connection with exemplary embodiment 500 may be performed by another semiconductor processing tool.

[0148] like Figure 5A As shown, example implementation 500 may include combining Figures 4A-4C The described process. (e.g.) Figure 5A As further shown, another photoresist layer 408 may be formed on and / or on the dielectric region 228. The deposition tool 102 may use spin coating and / or another type of deposition technique to form the photoresist layer 408. The exposure tool 104 may expose the photoresist layer 408 to a radiation source, and the developing tool 106 may develop and remove portions of the photoresist layer 408 to pattern the photoresist layer 408 (e.g., as shown). Figure 5A (As shown). The support region 312 can be covered by the photoresist layer 408, allowing a second dopant type to be implanted into another region of the semiconductor layer 402.

[0149] like Figure 5A As further shown, a portion of the semiconductor layer 402 may be doped with a second type of dopant (e.g., one or more dopant materials classified as a second type) to form a doped semiconductor region. For example, the ion implantation tool 116 may use a combination of the hard mask layer 404 and the photoresist layer 408 as an implantation mask to perform one or more doping or ion implantation operations. Thus, a support region 314 may be formed.

[0150] In some embodiments, the second dopant type includes a p-type dopant, such as boron (B). In these embodiments, boron ions are implanted into the semiconductor layer 402 using an implantation energy ranging from approximately 20 keV to approximately 40 keV, and the dose of boron ions used can include approximately 1 × 10⁻⁶.14 ions / cm 3 Approximately 5×10 14 ions / cm 3 However, other values ​​within these ranges are also within the scope of this disclosure.

[0151] In some embodiments, the ion implantation tool 116 bombards the surface of the semiconductor layer 402 at one or more angles to implant ions into a plurality of exposed sidewalls of the semiconductor layer 402. Here, the ion implantation in the plurality of sidewalls is self-aligned with the hard mask layer 404, meaning that the hard mask layer 404 acts as an implantation barrier. Ions can be implanted into the plurality of sidewalls at tilt angles ranging from about 45 degrees to about -45 degrees. However, other values ​​in this range are also within the scope of this disclosure. The tilt angle may refer to the bombardment angle relative to an angle substantially perpendicular to the substrate 226.

[0152] After the support region 314 is formed, the photoresist removal tool can then remove the remaining portion of the photoresist layer 408 (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0153] like Figure 5B As shown, the carrier concentration in the support region 312 can be increased. For example, the ion implantation tool 116 can implant additional n-type dopant material, such as phosphorus (P). In some embodiments, implantation energies ranging from about 10 keV to about 30 keV are used to implant additional phosphorus ions into the semiconductor layer 402, and the dose of phosphorus ions used can include about 1 × 10⁻⁶. 14 ions / cm 3 Approximately 3×10 15 ions / cm 3 However, other values ​​within these ranges are also within the scope of this disclosure. Additionally, phosphate ions can be implanted at tilt angles ranging from about 0 degrees to about 30 degrees. However, other values ​​within this range are also within the scope of this disclosure.

[0154] like Figure 5B As further shown, increasing the carrier concentration at support region 312 creates buffer zone 320 (with a smaller doping concentration than support region 312). Additionally, increasing the carrier concentration at support region 312 creates region 308 (with a smaller doping concentration than support region 312).

[0155] The same mask (i.e., the same photoresist layer 406) used to form the support region 312 can be used to increase the carrier concentration. In some embodiments, the photoresist layer 406 can be redeposited and repatterned after the support region 314 is formed. After the carrier concentration is increased, the remaining portion of the photoresist layer 406 can then be removed by the photoresist removal tool 114 (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0156] like Figure 5C As shown, the carrier concentration in the support region 314 can be increased. For example, the ion implantation tool 116 can implant additional p-type dopant material, such as boron (B). In some embodiments, implantation energies ranging from about 10 keV to about 30 keV are used to implant additional boron ions into the semiconductor layer 402, and the dose of boron ions used can include about 1 × 10⁻⁶. 14 ions / cm 3 Approximately 3×10 15 ions / cm 3 However, other values ​​within these ranges are also within the scope of this disclosure. Additionally, boron ions can be implanted at tilt angles ranging from about 0 degrees to about 30 degrees. However, other values ​​within this range are also within the scope of this disclosure.

[0157] like Figure 5C As further shown, increasing the carrier concentration at support region 314 creates buffer zone 322 (with a smaller doping concentration than support region 314). Additionally, increasing the carrier concentration at support region 314 creates region 306 (with a smaller doping concentration than support region 314). Therefore, by using two implantation operations to form support region 314, the dopant gradient associated with support region 314 is improved, which increases the mobility of charge carriers.

[0158] The same mask (i.e., the same photoresist layer 408) used to form the support region 314 can be used to increase the carrier concentration. In some embodiments, after increasing the carrier concentration in the support region 312, the photoresist layer 408 can be redeposited and repatterned. After the carrier concentration is increased, the photoresist removal tool 114 can then remove the remaining portion of the photoresist layer 408 (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0159] like Figure 5DAs shown, additional material can be deposited for dielectric region 228. For example, deposition tool 102 can use CVD, PVD, oxidation (e.g., thermal oxidation) and / or another type of deposition technique to deposit additional material for dielectric region 228. In some embodiments, STI pad oxidation and / or HDP deposition operations can be used to deposit additional material for dielectric region 228. In some embodiments, planarization tool 110 can perform CMP and / or another type of planarization operation to planarize dielectric region 228 after depositing additional material. CMP operation can additionally remove hard mask layer 404. Additionally and / or alternatively, etching tool 108 can remove hard mask layer 404 (e.g., using dry etching and / or wet / chemical etching).

[0160] like Figure 5E As shown, another photoresist layer 410 can be formed on and / or on the dielectric region 228. The deposition tool 102 can use spin coating and / or another type of deposition technique to form the photoresist layer 410. The exposure tool 104 can expose the photoresist layer 410 to a radiation source, and the developing tool 106 can develop and remove portions of the photoresist layer 410 to pattern the photoresist layer 410 (e.g., as shown). Figure 5E (As shown). A portion of the semiconductor layer 402 that forms the PN junction diode can be exposed through the pattern of the photoresist layer 410.

[0161] like Figure 5E As further shown, a portion of semiconductor layer 402 may be doped with a first dopant type (e.g., one or more dopant materials classified as the first type) to form a doped semiconductor region. For example, ion implantation tool 116 may use photoresist layer 410 as an implantation mask to perform one or more doping or ion implantation operations. Thus, region 304b can be formed. Figure 5E As further shown, the ion implantation in region 304b results in region 310b (with a higher doping concentration than region 308).

[0162] like Figure 5E As shown, a portion of semiconductor layer 402 may be doped with a second dopant type (e.g., a p-type dopant material, such as boron (B)) to form a doped semiconductor region. For example, ion implantation tool 116 may use photoresist layer 410 as an implantation mask to perform one or more doping or ion implantation operations. Additionally, ion implantation tool 116 may implant additional p-type dopant material, such as indium (In). Thus, region 306 can be formed.

[0163] In the third implantation operation, the ion implantation tool 116 can implant additional n-type dopant material. For example, the ion implantation tool 116 can use the photoresist layer 410 as an implantation mask to perform one or more doping or ion implantation operations. Therefore, region 304a can be formed. Figure 5E As further shown, the ion implantation formation region 304a results in region 310a (where the doping concentration is greater than that in region 308 due to the migration of ions from region 304a to region 310a).

[0164] The photoresist removal tool 114 can then remove the remaining portion of the photoresist layer 410 (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0165] like Figure 5F As shown, another photoresist layer 412 can be formed on and / or on the dielectric region 228. The deposition tool 102 can use spin coating and / or another type of deposition technique to form the photoresist layer 412. The exposure tool 104 can expose the photoresist layer 412 to a radiation source, and the developing tool 106 can develop and remove portions of the photoresist layer 412 to pattern the photoresist layer 412 (e.g., as shown). Figure 5F (As shown). A portion of the semiconductor layer 402 forming the contact region can be exposed through the pattern of the photoresist layer 412.

[0166] like Figure 5F As further shown, a portion of the semiconductor layer 402 may be doped with a first dopant type (e.g., one or more dopant materials classified as the first type) to form a doped semiconductor region. For example, the ion implantation tool 116 may use the photoresist layer 412 as an implantation mask to perform one or more doping or ion implantation operations. Thus, a contact region 316 may be formed.

[0167] The photoresist removal tool can then remove any remaining portion of the photoresist layer 412 (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, RTA operations and / or furnace thermal activation operations are used to promote the activation and / or absorption of dopants in the junction region 316.

[0168] like Figure 5G As shown, another photoresist layer 414 can be formed on and / or on the dielectric region 228. The deposition tool 102 can use spin coating and / or another type of deposition technique to form the photoresist layer 414. The exposure tool 104 can expose the photoresist layer 414 to a radiation source, and the developing tool 106 can develop and remove portions of the photoresist layer 414 to pattern the photoresist layer 414 (e.g., as shown). Figure 5G (As shown). A portion of the semiconductor layer 402 forming the contact region can be exposed through the pattern of the photoresist layer 414.

[0169] like Figure 5G As further shown, a portion of semiconductor layer 402 may be doped with a second type of dopant (e.g., one or more dopant materials classified as a second type) to form a doped semiconductor region. For example, ion implantation tool 116 may use photoresist layer 414 as an implantation mask to perform one or more doping or ion implantation operations. Thus, contact region 318 may be formed.

[0170] The photoresist removal tool can then remove any remaining portion of the photoresist layer 414 (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, RTA operations and / or furnace activation operations are used to promote the activation and / or absorption of dopants in the junction region 318.

[0171] like Figure 5H As shown, silicide layer 416 may be formed on and / or on the top surface of contact region 316, and silicide layer 420 may be formed on and / or on the top surface of contact region 318. Silicide layer 416 and silicide layer 420 may be bonded as follows: Figure 4K The formation described.

[0172] like Figure 5H As further shown, additional material can be deposited for dielectric region 228. For example, deposition tool 102 can use CVD, PVD, oxidation (e.g., thermal oxidation) and / or another type of deposition technique to deposit the additional material for dielectric region 228. In some embodiments, planarization tool 110 can perform CMP operations and / or another type of planarization operations to planarize dielectric region 228 after depositing additional material.

[0173] like Figure 5H As shown, contact structures 418 and 422 can be formed in dielectric region 228. Contact structures 418 and 422 can be combined as follows: Figure 4K The formation described.

[0174] like Figure 5I As shown, dielectric region 424 may be formed on and / or on dielectric region 228. For example, deposition tool 102 may use CVD technology, PVD technology, oxidation technology (e.g., thermal oxidation technology) and / or another type of deposition technology to deposit dielectric region 424.

[0175] like Figure 5I As further shown, metallization layers 426 and 428 can be formed in dielectric region 424. Metallization layers 426 and 428 can be bonded as follows: Figure 4L The formation described.

[0176] like Figure 5J As shown, dielectric region 430 may be formed on and / or on dielectric region 424. For example, deposition tool 102 may use CVD technology, PVD technology, oxidation technology (e.g., thermal oxidation technology) and / or another type of deposition technology to deposit dielectric region 430.

[0177] like Figure 5J As further shown, metallization layers 432 and 434 can be formed in the dielectric region 430. Metallization layers 432 and 434 can be bonded as follows: Figure 4M The formation described.

[0178] Additional dielectric regions and / or additional metallization layers can be formed until a sufficient or target amount of metallization layer is formed.

[0179] As mentioned above, providing Figure 5A-5J As an example. Other examples can be related to... Figure 5A-5J The descriptions are different.

[0180] Figure 6 This is a diagram of example components of the apparatus 600 described herein. In some embodiments, one or more of the semiconductor processing tools 102-116 and / or the wafer / die delivery tool 118 may include one or more apparatuses 600 and / or one or more components of apparatus 600. Figure 6 As shown, device 600 may include bus 610, processor 620, memory 630, input component 640, output component 650 and / or communication component 660.

[0181] Bus 610 may include one or more components capable of wired and / or wireless communication between multiple components of device 600. Bus 610 can... Figure 6 Two or more components are coupled together, for example via operational coupling, communication coupling, electronic coupling, and / or electrical coupling. For example, bus 610 may include electrical connections (e.g., wires, traces, and / or leads) and / or wireless buses. Processor 620 may include a central processing unit, graphics processing unit, microprocessor, controller, microcontroller, digital signal processor, field-programmable gate array, application-specific integrated circuit, and / or another type of processing component. Processor 620 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 620 may include one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

[0182] Memory 630 may include volatile and / or non-volatile memory. For example, memory 630 may include random access memory (RAM), read-only memory (ROM), hard disk drive, and / or other types of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 630 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 630 may be a non-transitory computer-readable medium. Memory 630 may store information related to the operation of device 600, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 630 may include one or more memories, such as those coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 620) via bus 610. The communication coupling between the processor 620 and the memory 630 enables the processor 620 to read and / or process information stored in the memory 630 and / or store messages in the memory 630.

[0183] Input component 640 enables device 600 to receive input, such as user input and / or sensed input. For example, input component 640 may include a touchscreen, keyboard, keypad, mouse, button, microphone, switch, sensor, GPS sensor, GNSS sensor, accelerometer, gyroscope, and / or actuator. Output component 650 enables device 600 to provide output, such as via a display, speaker, and / or LED. Communication component 660 enables device 600 to communicate with other devices via wired and / or wireless connections. For example, communication component 660 may include a receiver, transmitter, transceiver, modem, network interface card, and / or antenna.

[0184] Device 600 may perform one or more of the operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 630) may store a set of instructions (e.g., one or more instructions or program code) for execution by processor 620. Processor 620 may execute the set of instructions to perform one or more of the operations or processes described herein. In some embodiments, execution of the set of instructions by one or more processors 620 causes one or more processors 620 and / or device 600 to perform one or more of the operations or processes described herein. In some embodiments, hardwired circuitry may be used in place of or in combination with instructions to perform one or more of the operations or processes described herein. Alternatively or additionally, processor 620 may be configured to perform one or more of the operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardware circuitry and software.

[0185] Figure 6 The number and arrangement of components shown are provided for illustrative purposes only. Figure 6 Compared to the components shown, device 600 may include additional components, fewer components, different components, or components arranged in a different manner. Alternatively, a set of components of device 600 (e.g., one or more components) may perform one or more functions described as being performed by another set of components of device 600.

[0186] Figure 7 This is a flowchart of an example process 700 related to the formation of a semiconductor photonic device. In some embodiments, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-116) are used to perform the process. Figure 7 One or more process blocks. Alternatively, Figure 7 One or more process blocks may be executed using one or more components of device 600, such as processor 620, memory 630, input component 640, output component 650 and / or communication component 660.

[0187] like Figure 7 As shown, process 700 may include forming a first support region (block 710) using a first mask and employing a first dopant type. For example, one or more of semiconductor processing tools 102-116 may be used to form the first support region 312 using a first dopant type using a first mask (e.g., photoresist layer 406), as described herein.

[0188] like Figure 7As further shown, process 700 may include forming a second support region (block 720) using a second mask and employing a second dopant type. For example, one or more of semiconductor processing tools 102-116 may be used to form a second support region 314 using a second dopant type using a second mask (e.g., photoresist layer 408), as described herein.

[0189] like Figure 7 As further shown, process 700 may include doping the first region, the second region, and the third region using a third mask (block 730). For example, one or more of semiconductor processing tools 102-116 may be used to dope the first region 304a, the second region 306, and the third region 304b using a third mask (e.g., photoresist layer 410), as described herein. The first region 304a may be doped with a first dopant type, the second region 306 may be below the first region 304a and may be doped with a second dopant type, and the third region 304b may be below the second region 306 and may be doped with a first dopant type. The first region 304a, the second region 306, and the third region 304b correspond to PN junction diodes and form the U-shaped interface 302 of the PN junction diodes.

[0190] Process 700 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0191] In a first embodiment, doping the third region 304b involves using an implantation energy greater than that used in doping the second region 306 or the first region 304a to dope the third region 304b.

[0192] In the second embodiment, either alone or in combination with the first embodiment, the doped second region 306 includes a first portion of the second region 306 doped with a first implantation energy and a second portion of the second region 306 doped with a second implantation energy.

[0193] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the doped second region 306 includes a first portion of the second region 306 doped with a first dopant material and a second portion of the second region 306 doped with a second dopant material.

[0194] In the fourth embodiment, forming the first support region 312, either alone or in combination with one or more of the first to third embodiments, includes doping the first support region 312 with a first dopant material and doping the first support region 312 with a second dopant material.

[0195] In the fifth embodiment, forming the second support region 314, either alone or in combination with one or more of the first to fourth embodiments, includes doping the second support region 314 during the first implantation operation and increasing the carrier concentration in the second support region 314 using a second implantation operation after the first implantation operation.

[0196] although Figure 7 Several example blocks of process 700 are shown, but in some embodiments, process 700 includes... Figure 7 The blocks depicted in the diagram are those that are additional, fewer, different, or arranged differently. Alternatively, two or more blocks in process 700 can be executed in parallel.

[0197] Thus, the optical modulator structure in the photonic integrated circuit includes a U-shaped PN junction in the optical mode of the optical modulator structure (e.g., the region of the optical modulator structure that generates light). The U-shaped PN junction includes a first portion comprising a first dopant type (e.g., p-type or n-type dopant) overlapping with a second portion, and a second portion comprising a second dopant type different from the first dopant type. A first segment of the second portion contacts the bottom surface of the first portion, a second segment of the second portion contacts the side surface of the first portion, and a third segment of the second portion contacts the top surface of the first portion. Compared to another type of junction (e.g., a horizontal junction or an I-junction), the U-shaped PN junction provides an increased PN junction overlap area in the optical mode. This increased overlap area enables the optical modulator structure to achieve higher modulation efficiency.

[0198] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a dielectric layer. The semiconductor device includes an optical modulator structure located within the dielectric layer. This optical modulator structure includes a first region containing a first dopant type. This optical modulator structure includes a second region, on the bottom surface of the first region, containing a second dopant type. This optical modulator structure includes a third region on the bottom surface of the second region, containing the first dopant type. The first, second, and third regions correspond to a PN junction diode of the optical modulator structure. In some embodiments, the semiconductor device further includes: a first support region containing the first dopant type, connecting the first region and the third region to a first contact. In some embodiments, the semiconductor device further includes: a second support region containing the second dopant type, connecting the second region to a second contact. In some embodiments, the first dopant type includes at least one p-type dopant, and the second dopant type includes at least one n-type dopant. In some embodiments, the first dopant type includes at least one n-type dopant, and the second dopant type includes at least one p-type dopant. In some embodiments, the optical modulator structure includes a microring modulator structure. In some embodiments, the optical modulator structure includes a Mach-Zehnder modulator structure.

[0199] As described in more detail above, some embodiments described herein provide a method. This method includes forming a first support region using a first dopant type using a first mask. This method includes forming a second support region using a second dopant type using a second mask. This method includes doping using a third mask by: doping the first region with the first dopant type; doping the second region with the second dopant type, wherein the second region is located below the first region; and doping a third region with the first dopant type, wherein the third region is located below the second region. The first, second, and third regions correspond to a PN junction diode, and the first, second, and third regions form a U-shaped interface of the PN junction diode. In some embodiments, doping the third region includes using an implantation energy greater than that used to dope the second region or the first region. In some embodiments, doping the second region includes: doping a first portion of the second region with a first implantation energy; and doping a second portion of the second region with a second implantation energy. In some embodiments, doping the second region includes: doping a first portion of the second region with a first dopant material; and doping a second portion of the second region with a second dopant material. In some embodiments, forming the first support region includes: doping the first support region with a first dopant material; and doping the first support region with a second dopant material. In some embodiments, forming the second support region includes: doping the second support region during a first implantation operation; and increasing the carrier concentration in the second support region using a second implantation operation after the first implantation operation.

[0200] As described in more detail above, some embodiments described herein provide semiconductor structures. The semiconductor structure includes a dielectric layer. The semiconductor structure includes an optical modulator structure located within the dielectric layer. The optical modulator structure includes a first portion of a PN junction diode of the optical modulator structure, wherein the first portion includes a first dopant type. The optical modulator structure includes a second portion of a PN junction diode, wherein the second portion includes a second dopant type. The second portion includes a first segment contacting a bottom surface of the first portion, a second segment contacting a side surface of the first portion, and a third segment contacting a top surface of the first portion. In some embodiments, the semiconductor structure further includes a U-shaped interface between the first portion and the second portion. In some embodiments, the thickness of the first portion is greater than the thickness of the first segment and the third segment. In some embodiments, the thickness of the first segment is greater than the thickness of the third segment. In some embodiments, the semiconductor structure further includes a contact region electrically connected to the first portion of the PN junction diode. In some embodiments, the semiconductor structure further includes a buffer zone located between the contact region and the first portion of the PN junction diode. In some embodiments, the semiconductor structure further includes: a contact region electrically connected to the second portion of the PN junction diode; and a buffer zone located between the contact region and the second portion of the PN junction diode.

[0201] As used in this article, "meeting the threshold" can refer to a value that is greater than the threshold, greater than or equal to the threshold, less than the threshold, less than or equal to the threshold, equal to the threshold, not equal to the threshold, etc., depending on the context.

[0202] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of the present invention. Those skilled in the art should understand that the present invention can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a dielectric layer; and a light modulator structure located in the dielectric layer, comprising: a first region comprising a first dopant type; a second region on a bottom surface of the first region comprising a second dopant type; and a third region on a bottom surface of the second region comprising the first dopant type, wherein the first region, the second region, and the third region correspond to a P-N junction diode of the light modulator structure.

2. The semiconductor device according to claim 1, wherein Further comprising: a first support region comprising the first dopant type connecting the first region and the third region to a first contact.

3. The semiconductor device according to claim 2, wherein Further comprising: a second support region comprising the second dopant type connecting the second region to a second contact.

4. The semiconductor device according to claim 1, wherein The light modulator structure comprises a Mach-Zehnder modulator structure.

5. A semiconductor structure, characterized by Comprising: a dielectric layer; and a light modulator structure located in the dielectric layer, comprising: a first portion of a P-N junction diode of the light modulator structure, wherein the first portion comprises a first dopant type; and a second portion of the P-N junction diode, wherein the second portion comprises a second dopant type, and wherein the second portion comprises: a first section in contact with a bottom surface of the first portion; a second section in contact with a side surface of the first portion; and a third section in contact with a top surface of the first portion.

6. The semiconductor structure of claim 5, wherein, Further comprising: a U-shaped interface between the first portion and the second portion.

7. The semiconductor structure of claim 5, wherein, A thickness of the first portion is greater relative to a thickness of the first section and the third section.

8. The semiconductor structure of claim 5, wherein, A thickness of the first section is greater relative to a thickness of the third section.

9. The semiconductor structure of claim 5, wherein, Further comprising: a contact region electrically connected to the first portion of the P-N junction diode.

10. The semiconductor structure of claim 5, wherein, Further comprising: a contact region electrically connected to the second portion of the P-N junction diode; and a buffer region located between the contact region and the second portion of the P-N junction diode.

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