Scanning driving circuit and electronic device

Abstract

The utility model relates to a scan driving circuit and an electronic device. The scan driving circuit includes an input circuit, second and third transistors, and first and second capacitors. The input circuit is connected between a carry input terminal and a first node, and the input circuit operates in response to a first clock signal received through a first clock input terminal. The second transistor is connected between a first voltage terminal and an output terminal, and the second transistor includes a gate electrode connected to the first clock input terminal. The third transistor is connected between the output terminal and a second clock input terminal, and the third transistor includes a gate electrode connected to the first node. The first capacitor is connected between the output terminal and the first node. The second capacitor is connected between the first node and a second voltage terminal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0011863, filed on January 25, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The embodiments of this disclosure described herein relate to scan driving circuits and electronic devices, and more specifically, to electronic devices including scan driving circuits. Background Technology

[0004] The electronic device includes a display device, which includes a plurality of pixels connected to data lines and scan lines. Each of the plurality of pixels includes a light-emitting element and a pixel circuit for controlling the light-emitting element. The pixel circuit can supply a current corresponding to a data signal to the light-emitting element. At this time, in response to the current flowing through the light-emitting element, the light-emitting element can generate light with a predetermined brightness.

[0005] The scan drive circuit outputs a scan signal to sequentially drive the scan lines. Utility Model Content

[0006] Embodiments of this disclosure may provide a scan drive circuit capable of minimizing circuit area and an electronic device including the scan drive circuit.

[0007] According to an embodiment, a scan driving circuit includes: an input circuit connected between a carry input terminal and a first node, the input circuit operating in response to a first clock signal received via a first clock input terminal; a second transistor connected between a first voltage terminal and an output terminal, the second transistor including a gate electrode connected to the first clock input terminal; a third transistor connected between the output terminal and the second clock input terminal, the third transistor including a gate electrode connected to the first node; a first capacitor connected between the output terminal and the first node; and a second capacitor connected between the first node and the second voltage terminal.

[0008] In an embodiment, the first voltage supplied to the first voltage terminal may have a higher voltage level than the second voltage supplied to the second voltage terminal.

[0009] In an embodiment, the first clock signal provided to the first clock input terminal may have the same frequency and a different phase from the second clock signal provided to the second clock input terminal.

[0010] In one embodiment, during a first cycle, each of the carry signal and the first clock signal provided to the carry input terminal may be at a first level. During a second cycle, different from the first cycle, the second clock signal may be at the first level. During the second cycle, the scan signal output to the output terminal may be at the same first level as the second clock signal.

[0011] In one embodiment, the input circuit may include a first transistor connected between the carry input terminal and the first node, and the input circuit may include a gate electrode connected to the first clock input terminal.

[0012] In an embodiment, the input circuit may include a first transistor and a second transistor, the first transistor and the second transistor being sequentially connected in series between the carry input terminal and the first node, and each of the first transistor and the second transistor includes a gate electrode connected to the first clock input terminal.

[0013] In an embodiment, the input circuit may include: a first transistor and a second transistor, the first transistor and the second transistor being sequentially connected in series between the carry input terminal and the second node, and each of the first transistor and the second transistor including a gate electrode connected to the first clock input terminal; and a fourth transistor connected between the first node and the second node, and the fourth transistor including a gate electrode connected to the second voltage terminal.

[0014] In an embodiment, the scan driving circuit may further include a fourth transistor connected between the first clock input terminal and the first node, and the fourth transistor includes a gate electrode connected to the carry input terminal.

[0015] In an embodiment, the scan driving circuit may further include: a fourth transistor connected between the first clock input terminal and the second node, and the fourth transistor including a gate electrode connected to the carry input terminal; and a fifth transistor connected between the second node and the first node, and the fifth transistor including a gate electrode connected to the second voltage terminal.

[0016] In an embodiment, the input circuit may include: a first transistor connected between the carry input terminal and the first node, and the first transistor including a gate electrode connected to a second node; a fourth transistor connected between a third voltage terminal and the second node, and the fourth transistor including a gate electrode connected to the first clock input terminal; and a fifth transistor connected between the fourth voltage terminal and the second node, and the fifth transistor including a gate electrode connected to the first clock input terminal.

[0017] In an embodiment, the first voltage supplied to the first voltage terminal may have a higher voltage level than the second voltage supplied to the second voltage terminal. The third voltage supplied to the third voltage terminal may have a higher voltage level than the first voltage. The fourth voltage supplied to the fourth voltage terminal may have a lower voltage level than the second voltage.

[0018] In one embodiment, the input circuit may include: a first transistor connected between the carry input terminal and the third node, and the first transistor including a gate electrode connected to the second node; a fourth transistor connected between the third voltage terminal and the second node, and the fourth transistor including a gate electrode connected to the first clock input terminal; a fifth transistor connected between the fourth voltage terminal and the second node, and the fifth transistor including a gate electrode connected to the first clock input terminal; and a sixth transistor connected between the third node and the first node, and the sixth transistor including a gate electrode connected to the second voltage terminal.

[0019] In an embodiment, the first voltage supplied to the first voltage terminal may have a higher voltage level than the second voltage supplied to the second voltage terminal. The third voltage supplied to the third voltage terminal may have a higher voltage level than the first voltage. The fourth voltage supplied to the fourth voltage terminal may have a lower voltage level than the second voltage.

[0020] In an embodiment, the input circuit may include: a first transistor connected between the second node and the second voltage terminal, and the first transistor including a gate electrode connected to the carry input terminal; a fourth transistor connected between the carry input terminal and the second node, and the fourth transistor including a gate electrode connected to the first clock input terminal; and a fifth transistor connected between the second node and the first node, and the fifth transistor including a gate electrode connected to the second voltage terminal.

[0021] According to an embodiment, an electronic device includes a display device comprising: a display panel including pixels; a scan driving circuit configured to provide a scan signal to the pixels; a drive controller configured to provide a start signal, a first clock signal, and a second clock signal to the scan driving circuit; and a voltage generator configured to provide a first voltage and a second voltage to the scan driving circuit. The scan driving circuit includes: an input circuit connected between a carry input terminal configured to receive the start signal and a first node, and the input circuit being configured to operate in response to a first clock signal received through the first clock input terminal; a second transistor connected between a first voltage terminal configured to receive the first voltage and an output terminal outputting the scan signal, and the second transistor including a gate electrode connected to the first clock input terminal; a third transistor connected between the output terminal and a second clock input terminal configured to receive the second clock signal, and the third transistor including a gate electrode connected to the first node; a first capacitor connected between the output terminal and the first node; and a second capacitor connected between the first node and a second voltage terminal configured to receive the second voltage.

[0022] In one embodiment, during a first cycle, each of the start signal and the first clock signal may be at a first level. During a second cycle, different from the first cycle, the second clock signal may be at the first level. During the second cycle, the scan signal may be at the same first level as the second clock signal.

[0023] In one embodiment, the input circuit may be connected between the carry input terminal and the first node, and the input circuit may include a gate electrode connected to the first clock input terminal.

[0024] In an embodiment, the scan driving circuit may further include a fourth transistor connected between the first clock input terminal and the first node, and the fourth transistor includes a gate electrode connected to the carry input terminal.

[0025] In an embodiment, the input circuit may include: a first transistor connected between the carry input terminal and the first node, and the first transistor including a gate electrode connected to a second node; a fourth transistor connected between a third voltage terminal and the second node, and the fourth transistor including a gate electrode connected to the first clock input terminal; and a fifth transistor connected between the fourth voltage terminal and the second node, and the fifth transistor including a gate electrode connected to the first clock input terminal.

[0026] In an embodiment, the display device may further include a data driving circuit configured to provide a data signal. The pixel may include: a light-emitting element; a first pixel transistor including a first electrode, a second electrode connected to the light-emitting element, and a gate electrode; and a second pixel transistor connected between a data line configured to receive the data signal and the first electrode of the first pixel transistor, the second pixel transistor including a gate electrode configured to receive the scan signal. Attached Figure Description

[0027] The above and other objects and features of this disclosure will become apparent from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0028] Figure 1 A display device according to an embodiment of the present disclosure is shown.

[0029] Figure 2 This is a block diagram of a display device according to an embodiment of the present disclosure.

[0030] Figure 3 This is a circuit diagram of a pixel according to an embodiment of the present disclosure.

[0031] Figure 4 It is used to describe Figure 3 The timing diagram shows the operation of the pixels shown.

[0032] Figure 5 This is a block diagram of a scan drive circuit according to an embodiment of the present disclosure.

[0033] Figure 6 This is a block diagram of a first scan drive circuit according to an embodiment of the present disclosure.

[0034] Figure 7 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0035] Figures 8A to 8E It is a circuit diagram used to describe the operation of the driver level.

[0036] Figures 9A to 9E It is a timing diagram used to describe the operation of the driver level.

[0037] Figure 10 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0038] Figure 11 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0039] Figure 12 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0040] Figures 13A to 13E It is used to describe Figure 12 The circuit diagram shown illustrates the operation of the drive stage.

[0041] Figure 14 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0042] Figure 15 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0043] Figure 16 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0044] Figures 17A to 17E It is used to describe Figure 16 The circuit diagram shown illustrates the operation of the drive stage.

[0045] Figure 18 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0046] Figure 19 This is a circuit diagram of the driver stage according to an embodiment of the present disclosure.

[0047] Figures 20A to 20E It is used to describe Figure 19 The circuit diagram shown illustrates the operation of the drive stage.

[0048] Figure 21 This is a block diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0049] In the specification, the statements that the first component (or area, layer, part, etc.) is "on" the second component, the first component is "connected" to the second component, or the first component is "coupled" to the second component mean that the first component is directly on the second component, the first component is directly connected to the second component, or the first component is directly coupled to the second component, or that the third component is located between the first component and the second component.

[0050] The same reference numerals refer to the same components. Furthermore, in the accompanying drawings, the thickness, proportions, and dimensions of the components are exaggerated for the sake of clarity in describing the technical content.

[0051] Although terms such as “first” and “second” may be used to describe various components, these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope and spirit of this disclosure, “first component” may be referred to as “second component,” and similarly, “second component” may be referred to as “first component.” The articles “a,” “a,” and “the” are in the singular form because they have a single referent, but the use of the singular form in the specification should not preclude the existence of more than one referent.

[0052] Furthermore, the terms "below," "under," "on," and "above" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative and are described with reference to the directions indicated in the drawings.

[0053] It will be understood that the terms “include,” “comprises,” “has,” “have,” “having,” etc., specify the presence of the features, numbers, steps, operations, elements, or components described in the specification, or combinations thereof, without excluding the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, or components, or combinations thereof.

[0054] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted as having an idealized or overly formal meaning.

[0055] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0056] Figure 1 A display device DD according to an embodiment of the present disclosure is shown.

[0057] Reference Figure 1 The portable terminal is shown as an example of a display device DD according to an embodiment of the present disclosure. Portable terminals may include tablet personal computers (PCs), smartphones, personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, and wristwatch-type electronic devices, etc. However, the present disclosure is not limited thereto. In addition to large electronic devices such as televisions or outdoor billboards, the present disclosure can also be used for small and medium-sized electronic devices such as personal computers, laptop computers, kiosks, vehicle navigation units, and cameras. The examples above are provided merely as embodiments, and it will be apparent that the display device DD can be applied to any other electronic device without departing from the concept of the present disclosure.

[0058] like Figure 1As shown, the display surface for displaying the image is parallel to a plane defined by a first direction DR1 and a second direction DR2. The display device DD includes a plurality of regions separated in the display surface. The display surface includes a display area DA in which the image is displayed and a non-display area NDA adjacent to the display area DA. The non-display area NDA may be referred to as a border area. For example, the display area DA may have a rectangular shape. The non-display area NDA surrounds the display area DA. Furthermore, although not shown, the display device DD may, for example, include a shape that is partially curved.

[0059] Figure 2 This is a block diagram of a display device DD according to an embodiment of the present disclosure.

[0060] Reference Figure 2 The display device DD includes a display panel DP, a drive controller 100, a data drive circuit 200, a scan drive circuit 300, a transmission drive circuit 400, and a voltage generator 500.

[0061] The drive controller 100 receives the image signal RGB and the control signal CTRL. The drive controller 100 converts the image signal RGB into an image data signal DS and outputs the image data signal DS. The drive controller 100 outputs a scan control signal SCS, a data control signal DCS, and a transmit control signal ECS.

[0062] The data drive circuit 200 receives the data control signal DCS and the image data signal DS from the drive controller 100. The data drive circuit 200 converts the image data signal DS into a data signal and then outputs the data signal to multiple data lines DL1 to DLm, which will be described later. In this document, m can be a natural number greater than 0.

[0063] The scan drive circuit 300 receives the scan control signal SCS from the drive controller 100. In response to the scan control signal SCS, the scan drive circuit 300 outputs scan signals to scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1. In this document, n can be a natural number greater than 0.

[0064] The transmit drive circuit 400 receives the transmit control signal ECS from the drive controller 100. The transmit drive circuit 400 can output the transmit signal to the transmit lines EML1 to EMLn in response to the transmit control signal ECS.

[0065] Voltage generator 500 generates voltages to operate the display panel DP. In one embodiment, voltage generator 500 may generate a first drive voltage ELVDD, a second drive voltage ELVSS, a first initialization voltage VINT1, and a second initialization voltage VINT2 for the operation of the display panel DP. In another embodiment, voltage generator 500 may generate a first voltage VGH and a second voltage VGL for the operation of the scan drive circuit 300.

[0066] The display panel DP includes scan lines GIL1 to GILn, GCL1 to GCLn and GWL1 to GWLn+1, emission lines EML1 to EMLn, data lines DL1 to DLm and pixels PX.

[0067] The display panel (DP) includes active areas (AA) and passive areas (NAA). Active areas (AA) can correspond to... Figure 1 The display device DD shown has a display area DA, and the non-active area NAA can correspond to the non-display area NDA.

[0068] In this embodiment, pixel PX can be placed in the active region AA of the display panel DP. Scan driving circuit 300 and emission driving circuit 400 can be placed in the non-active region NAA of the display panel DP. In this embodiment, scan driving circuit 300 is arranged adjacent to a first side of the active region AA. Scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1 extend from scan driving circuit 300 in a first direction DR1. Emission driving circuit 400 is arranged adjacent to a second side of the active region AA. Emission lines EML1 to EMLn extend from emission driving circuit 400 in a direction opposite to the first direction DR1.

[0069] Scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, as well as transmit lines EML1 to EMLn, are arranged spaced apart from each other in the second direction DR2. Data lines DL1 to DLm extend from the data drive circuit 200 in the opposite direction to the second direction DR2 and are arranged spaced apart from each other in the first direction DR1.

[0070] exist Figure 2 In the example shown, the scan driving circuit 300 and the emission driving circuit 400 are arranged facing each other, with the pixel PX located between them; however, this disclosure is not limited thereto. For example, the scan driving circuit 300 and the emission driving circuit 400 may be placed adjacent to each other in the non-active area NAA of the display panel DP. In an embodiment, the scan driving circuit 300 and the emission driving circuit 400 may be implemented using a single circuit.

[0071] Multiple pixels (PX) are electrically connected to scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, emission lines EML1 to EMLn, and data lines DL1 to DLm. Each of the multiple pixels (PX) can be electrically connected to four scan lines and one emission line. For example, as... Figure 2 As shown, the pixels in the first row can be connected to scan lines GIL1, GCL1, GWL1, and GWL2, and the emission line EML1. Furthermore, the pixels in the i-th row can be connected to scan lines GILi, GCLi, GWLi, and GWLi+1, and the emission line EML1. In this text, i can be a natural number greater than 0 and less than or equal to n. The pixels in the n-th row can be connected to scan lines GILn, GCLn, GWLn, and GWLn+1, and the emission line EMLn.

[0072] Each of the multiple pixels PX includes a light-emitting element ED (see Figure 3 ) and the pixel circuit PXC (see) used to control the emission of the light-emitting element ED. Figure 3 The pixel circuit PXC may include one or more transistors and one or more capacitors. The scan drive circuit 300 and the emitter drive circuit 400 may include transistors formed using the same process as the pixel circuit PXC.

[0073] The scan driving circuit 300 according to an embodiment of the present disclosure is placed in the non-active region NAA of the display panel DP. The scan driving circuit 300 according to an embodiment of the present disclosure can minimize the circuit area by including a minimum number of transistors. Therefore, the non-display area NDA of the display device DD corresponding to the non-active region NAA of the display panel DP (see...) can be minimized. Figure 1 The area of ​​).

[0074] Figure 3 This is a circuit diagram of a pixel PX according to an embodiment of the present disclosure.

[0075] Figure 3 It shows the connection to Figure 2 The diagram shows the circuit diagram of pixel PX for the j-th data line DLj among data lines DL1 to DLm, the i-th scan lines GILi, GCLi, and GWLi (also called scan lines GILi, GCLi, and GWLi) among scan lines GIL1 to GILn, GCL1 to GCLn, and GWL1 to GWLn+1, and the (i+1)-th scan line GWLi+1 (also called scan line GWLi+1), and the i-th emission line EMLi (also called emission line EMLi) among emission lines EML1 to EMLn. In this document, j can be a natural number greater than 0 and less than or equal to m.

[0076] Figure 2 Each of the multiple pixels PX shown can be associated with Figure 3 The pixels PX shown have the same circuit configuration.

[0077] Reference Figure 3 According to an embodiment, a pixel PX of a display device includes a pixel circuit PXC and at least one light-emitting element ED. In an embodiment, the light-emitting element ED may be a light-emitting diode. In an embodiment, a pixel PX is described as including one light-emitting element ED. The pixel circuit PXC includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor Cst.

[0078] In the embodiments, each of the first transistor T1 to the seventh transistor T7 is a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, this disclosure is not limited thereto. For example, each of the first transistor T1 to the seventh transistor T7 may be an N-type transistor using oxide semiconductor as the semiconductor layer.

[0079] In an embodiment, at least one of the first transistor T1 to the seventh transistor T7 may be an N-type transistor, and the others may be P-type transistors. Furthermore, the circuit configuration of the pixel PX according to embodiments of this disclosure is not limited to... Figure 3 The embodiments described herein can be implemented in a modified manner.

[0080] Scan lines GILi, GCLi, GWLi, and GWLi+1 can transmit scan signals GIi, GCI, GWi, and GWi+1, respectively. Transmit line EMLi can transmit transmit signal EMi. Data line DLj transmits data signal Dj. Data signal Dj can have a corresponding input to the display device DD (see...). Figure 2 The image signal RGB voltage level. The first driving voltage line VL1, the second driving voltage line VL2, the third driving voltage line VL3, and the fourth driving voltage line VL4 can respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the first initialization voltage VINT1, and the second initialization voltage VINT2.

[0081] The first transistor T1 includes a first electrode connected to the first drive voltage line VL1 via a fifth transistor T5, a second electrode electrically connected to the anode of the light-emitting element ED via a sixth transistor T6, and a gate electrode connected to one end of the capacitor Cst. The first transistor T1 can receive the data signal Dj transmitted via the data line DLj according to the switching operation of the second transistor T2, and can then supply the drive current Id to the light-emitting element ED.

[0082] The second transistor T2 includes a first electrode connected to the data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the scan line GWLi. The second transistor T2 can be turned on in response to the scan signal GWi transmitted through the scan line GWLi, and can transmit the data signal Dj transmitted through the data line DLj to the first electrode of the first transistor T1.

[0083] The third transistor T3 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a gate electrode connected to the scan line GCLi. The third transistor T3 can be turned on in response to the scan signal GCI transmitted through the scan line GCLi, and therefore, the gate electrode and the second electrode of the first transistor T1 can be connected, that is, the first transistor T1 can be connected in a diode manner.

[0084] The fourth transistor T4 includes a first electrode connected to the gate electrode of the first transistor T1, a second electrode connected to the third driving voltage line VL3 through which the first initialization voltage VINT1 is transmitted, and a gate electrode connected to the scan line GILi. The fourth transistor T4 can be turned on in response to the scan signal GIi transmitted through the scan line GILi, causing the first initialization voltage VINT1 to be transmitted to the gate electrode of the first transistor T1. Therefore, an initialization operation can be performed to initialize the voltage of the gate electrode of the first transistor T1.

[0085] The fifth transistor T5 includes a first electrode connected to the first drive voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a gate electrode connected to the emitter line EMLi.

[0086] The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode of the light-emitting element ED, and a gate electrode connected to the emission line EMLi.

[0087] The fifth transistor T5 and the sixth transistor T6 can be turned on simultaneously in response to the transmit signal EMi transmitted via the transmit line EMi. In this way, the first drive voltage ELVDD can be compensated by the diode-connected transistor T1 so as to supply the light-emitting element ED.

[0088] The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth drive voltage line VL4, and a gate electrode connected to the scan line GWLi+1. The seventh transistor T7 is turned on in response to the scan signal GWi+1 transmitted through the scan line GWLi+1, and bypasses the current of the anode of the light-emitting element ED to the fourth drive voltage line VL4.

[0089] As described above, one end of capacitor Cst is connected to the gate electrode of the first transistor T1, and the other end of capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light-emitting element ED can be connected to the second driving voltage line VL2, and the second driving voltage ELVSS is supplied to the second driving voltage line VL2. The pixel circuit PXC according to the embodiment is not limited to... Figure 3 The pixel circuit shown is illustrated. The number of transistors, capacitors, and their connections within the pixel circuit (PXC) can be modified in various ways.

[0090] Figure 4 It is used to describe Figure 3 The timing diagram shows the operation of the pixels shown.

[0091] Reference Figure 3 and Figure 4 A frame Fs can include an initialization period, a data programming and compensation period, and a transmission period.

[0092] When a scan signal GIi with a low level is provided through scan line GILi during the initialization cycle, the fourth transistor T4 is turned on. The first initialization voltage VINT1 is supplied to the gate electrode of the first transistor T1 through the fourth transistor T4 in order to initialize the first transistor T1.

[0093] Next, when a low-level scan signal GCI is supplied via scan line GCLi during the data programming and compensation cycle, the third transistor T3 is turned on. The first transistor T1 is connected to the third transistor T3 via a diode, thus being turned on and forward biased. At this time, when a low-level scan signal GWi is supplied via scan line GWLi, the second transistor T2 is turned on. In this case, a compensation voltage obtained by reducing the voltage of the data signal Dj supplied from data line DLj to the threshold voltage of the first transistor T1 is applied to the gate electrode of the first transistor T1. That is, the gate voltage applied to the gate electrode of the first transistor T1 can be the compensation voltage.

[0094] Since the first driving voltage ELVDD and the compensation voltage are applied to opposite ends of the capacitor Cst, the charge corresponding to the difference between the first driving voltage ELVDD and the compensation voltage can be stored in the capacitor Cst.

[0095] Simultaneously, when a low-level scan signal GWi+1 is provided to the gate electrode of the seventh transistor T7 through scan line GWLi+1, the seventh transistor T7 is turned on. When the seventh transistor T7 is turned on, the anode of the light-emitting element ED is electrically connected to the fourth driving voltage line VL4. Therefore, the anode of the light-emitting element ED can be initialized to the second initialization voltage VINT2.

[0096] Next, during the emission cycle, the emission signal EMi supplied from the emission line EMi changes from a high level to a low level. During the emission cycle, the fifth transistor T5 and the sixth transistor T6 are turned on by the emission signal EMi with a low level. In this case, the drive current Id is generated based on the voltage difference between the gate voltage of the gate electrode of the first transistor T1 and the first drive voltage ELVDD, and is supplied to the light-emitting element ED through the sixth transistor T6, and the drive current Id flows through the light-emitting element ED. The light-emitting element ED can emit light with a brightness corresponding to the drive current Id.

[0097] Figure 5 This is a block diagram of a scan drive circuit 300 according to an embodiment of the present disclosure.

[0098] Reference Figure 5 The scan drive circuit 300 includes a first scan drive circuit 310, a second scan drive circuit 320, and a third scan drive circuit 330.

[0099] The first scan drive circuit 310 outputs scan signals GW1 to GWn+1 in response to the scan control signal SCS. In an embodiment, the scan signals GW1 to GWn+1 can be sequentially transitioned to a first level (e.g., a low level).

[0100] The second scan drive circuit 320 outputs scan signals GC1 to GCn in response to the scan control signal SCS. The scan signals GC1 to GCn can be sequentially transitioned to a first level (e.g., a low level).

[0101] The third scan drive circuit 330 outputs scan signals GI1 to GIn in response to the scan control signal SCS. The scan signals GI1 to GIn can be sequentially transitioned to a first level (e.g., a low level).

[0102] Figure 6 This is a block diagram of a first scan drive circuit 310 according to an embodiment of the present disclosure.

[0103] Reference Figure 6 The first scan drive circuit 310 includes drive stages ST1 to STn+1.

[0104] Drive level ST1 to STn+1 from Figure 2The drive controller 100 shown receives a scan control signal SCS. The scan control signal SCS includes a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2. Each of the drive stages ST1 to STn+1 receives the first clock signal CLK1 and the second clock signal CLK2. Each of the drive stages ST1 to STn+1 receives a first voltage VGH and a second voltage VGL. The first voltage VGH and the second voltage VGL can be obtained from... Figure 2 The voltage generator 500 shown in the figure is provided.

[0105] In this embodiment, drive stages ST1 to STn+1 output scan signals GW1 to GWn+1, respectively. Scan signals GW1 to GWn+1 can be provided to... Figure 2 The scan lines shown are GWL1 to GWLn+1.

[0106] Driver stage ST1 receives the start signal FLM as a carry signal. Each of driver stages ST2 through STn+1 has a subordinate connection indicating that a scan signal output from the previous driver stage is received as a carry signal. For example, the second driver stage ST2 receives the scan signal GW1 output from the first driver stage ST1 as a carry signal. The third driver stage ST3 receives the scan signal GW2 output from the second driver stage ST2 as a carry signal. However, this disclosure is not limited thereto.

[0107] although Figure 6 Only the first scan drive circuit 310 is shown in the figure, but Figure 5 The second scan drive circuit 320 and the third scan drive circuit 330 shown may also include the same components as the first scan drive circuit 310.

[0108] Figure 7 This is a circuit diagram of the driver stage ST1 according to an embodiment of the present disclosure.

[0109] Reference Figure 7 The driver stage ST1 includes a first transistor M1, a second transistor M2, and a third transistor M3, as well as a first capacitor C1 and a second capacitor C2. Furthermore, the driver stage ST1 also includes a first clock input terminal CK1 and a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1 and a second voltage terminal VIN2, and an output terminal OUT.

[0110] The driver stage ST1 responds to the first clock signal CLK1 and the second clock signal CLK2 received through the first clock input terminal CK1 and the second clock input terminal CK2, and the carry signal (i.e., the start signal FLM) received through the carry input terminal CIN, and outputs the scan signal GW1 to the output terminal OUT.

[0111] Each of the first voltage VGH and the second voltage VGL received through the first voltage terminal VIN1 and the second voltage terminal VIN2 can be a direct current (DC) voltage having a predetermined voltage level. In an embodiment, the first voltage VGH may have a higher voltage level than the second voltage VGL.

[0112] In an embodiment, the first transistor M1 may be connected between the carry input terminal CIN and the first node Q1, and may be referred to as an input circuit that operates in response to a first clock signal received through the first clock input terminal CK1.

[0113] In an embodiment, the first clock signal CLK1 and the second clock signal CLK2 may have the same frequency and different phases.

[0114] The first transistor M1 can be connected between the carry input terminal CIN and the first node Q1, and can include a gate electrode connected to the first clock input terminal CK1.

[0115] The second transistor M2 can be connected between the first voltage terminal VIN1 and the output terminal OUT, and can include a gate electrode connected to the first clock input terminal CK1.

[0116] The third transistor M3 can be connected between the output terminal OUT and the second clock input terminal CK2, and can include a gate electrode connected to the first node Q1.

[0117] The first capacitor C1 is connected between the first node Q1 and the output terminal OUT.

[0118] The second capacitor C2 is connected between the first node Q1 and the second voltage terminal VIN2.

[0119] In an embodiment, each of the first transistor M1, the second transistor M2, and the third transistor M3 is a P-type transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, this disclosure is not limited thereto. In an embodiment, at least one of the first transistor M1, the second transistor M2, and the third transistor M3 may be a P-type transistor, and the others may be N-type transistors using oxide semiconductor as the semiconductor layer. In an embodiment, the first transistor M1, the second transistor M2, and the third transistor M3 may be N-type transistors.

[0120] The driver stage ST1 may include three transistors (i.e., first transistor M1, second transistor M2, and third transistor M3) and two capacitors (i.e., first capacitor C1 and second capacitor C2) to output the scan signal GW1. The scan driver circuit 300 (see...) Figure 2The circuit area can be minimized by minimizing the number of transistors and capacitors included in the drive stage ST1.

[0121] although Figure 7 Only the driver level ST1 is shown in the diagram, but Figure 6 Each of the drive stages ST1 to STn+1 shown may include, with Figure 7 The circuit configuration is similar to that of the drive stage ST1 shown.

[0122] Figure 6 Each of some of the drive levels ST1 to STn+1 shown (e.g., odd drive levels ST1, ST3... and STn+1) can be connected to... Figure 7 The drive stage ST1 shown includes the same circuit configuration.

[0123] Figure 6 Each of the other drive levels among the drive levels ST1 to STn+1 shown (e.g., even-numbered drive levels ST2, ST4... and STn) can be connected with... Figure 7 The driver stage ST1 shown includes several different circuit configurations. For example, the first clock input terminal CK1 of each of the even-numbered driver stages ST2, ST4, ..., STn can receive the second clock signal CLK2, and their second clock input terminal CK2 can receive the first clock signal CLK1.

[0124] Figures 8A to 8E This is a circuit diagram used to describe the operation of the driver stage ST1.

[0125] Figures 9A to 9E It is a timing diagram used to describe the operation of driver-level ST1.

[0126] Reference Figure 8A and Figure 9A During the first cycle P1, each of the carry signal (i.e., the start signal FLM) and the first clock signal CLK1 is at a low level L, and the second clock signal CLK2 is at a high level H.

[0127] When the first clock signal CLK1 is at a low level L, each of the first transistor M1 and the second transistor M2 is turned on.

[0128] Because the second transistor M2 is turned on, the scan signal GW1 corresponding to the high level H of the first voltage VGH can be output to the output terminal OUT.

[0129] Simultaneously, because the first transistor M1 is turned on, the low-level start signal FLM can be transmitted to the first node Q1. Therefore, the first signal S_Q1 of the first node Q1 can be the first low voltage level LV1 corresponding to the low-level start signal FLM.

[0130] When the first signal S_Q1 is at the first low voltage level LV1, the third transistor M3 can be turned on. With the third transistor M3 turned on, the second clock signal CLK2, which is at a high level H, is output to the output terminal OUT through the third transistor M3. Therefore, in the first cycle P1, the scan signal GW1 is at a high level H.

[0131] During the first cycle P1, the first voltage VGH, which is the DC voltage, can be supplied to the output terminal OUT through the second transistor M2. Therefore, during the first cycle P1, the scan signal GW1 of the output terminal OUT can be kept at a stable high level H.

[0132] Reference Figure 8B and Figure 9B During the second cycle P2, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0133] When the first clock signal CLK1 is at a high level H, each of the first transistor M1 and the second transistor M2 is turned off.

[0134] The first signal S_Q1 of the first node Q1 can be held at a first low voltage level LV1 by the second capacitor C2. Because the third transistor M3 remains on while the first signal S_Q1 is held at the first low voltage level LV1, the second clock signal CLK2, which is at a high level H, is output to the output terminal OUT through the third transistor M3. Therefore, in the second cycle P2, the scan signal GW1 is at a high level H.

[0135] Reference Figure 8C and Figure 9C During the third cycle P3, each of the start signal FLM and the first clock signal CLK1 is at a high level H, and the second clock signal CLK2 is at a low level L.

[0136] When the first clock signal CLK1 is at a high level H, each of the first transistor M1 and the second transistor M2 is turned off.

[0137] The first signal S_Q1 of the first node Q1 can be held at a first low voltage level LV1 by the second capacitor C2. Because the third transistor M3 remains on while the first signal S_Q1 is held at the first low voltage level LV1, the second clock signal CLK2, which is at a low level L, is output to the output terminal OUT through the third transistor M3. Therefore, in the third cycle P3, the scan signal GW1 is at a low level L.

[0138] As the scan signal GW1 at the output terminal OUT changes from high level H to low level L, the first signal S_Q1 of the first node Q1 can be changed by the first capacitor C1 to a second low voltage level LV2, which is lower than the first low voltage level LV1.

[0139] As the voltage level of the first signal S_Q1 goes low, the third transistor M3 can be fully turned on. Therefore, in the third cycle P3, the scan signal GW1 can remain at the low level L of the second clock signal CLK2.

[0140] Reference Figure 8D and Figure 9D During the fourth cycle P4, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0141] When the first clock signal CLK1 is at a high level H, each of the first transistor M1 and the second transistor M2 is turned off.

[0142] When the third transistor M3 is turned on in the third cycle P3, and then the second clock signal CLK2 changes from low level L to high level H in the fourth cycle P4, the second clock signal CLK2 at high level H is output to the output terminal OUT through the third transistor M3. Therefore, in the fourth cycle P4, the scan signal GW1 is at high level H.

[0143] As the scan signal GW1 at the output terminal OUT changes from low level L to high level H, the first signal S_Q1 of the first node Q1 can be changed by the first capacitor C1 to a first low voltage level LV1 that is higher than the second low voltage level LV2.

[0144] Because even if the voltage level of the first signal S_Q1 changes to the first low voltage level LV1, the third transistor M3 remains on, so in the fourth cycle P4, the level of the scan signal GW1 can be equal to the high level H of the second clock signal CLK2.

[0145] Reference Figure 8E and Figure 9EDuring the fifth cycle P5, each of the start signal FLM and the second clock signal CLK2 is at a high level H, and the first clock signal CLK1 is at a low level L.

[0146] When the first clock signal CLK1 is at a low level L, each of the first transistor M1 and the second transistor M2 is turned on.

[0147] Because the first transistor M1 is turned on, the high-level start signal FLM can be transmitted to the first node Q1. Therefore, the first signal S_Q1 of the first node Q1 can be at the high voltage level HV corresponding to the high-level start signal FLM.

[0148] When the first signal S_Q1 is at a high voltage level HV, the third transistor M3 can be turned off.

[0149] Simultaneously, because the second transistor M2 is turned on, the scan signal GW1, corresponding to the high level H of the first voltage VGH, can be output to the output terminal OUT. Therefore, in the fifth cycle P5, the scan signal GW1 is at the high level H.

[0150] During the fifth cycle P5, the first voltage VGH, which is the DC voltage, can be supplied to the output terminal OUT. Therefore, during the fifth cycle P5, the scan signal GW1 of the output terminal OUT can remain at a stable high level H.

[0151] Figure 10 This is a circuit diagram of the driver stage ST1a according to an embodiment of the present disclosure.

[0152] Reference Figure 10 The driver stage ST1a includes transistor M1-1 (first-1), transistor M1-2 (first-2), transistor M2 (second), and transistor M3 (third), as well as capacitor C1 (first) and capacitor C2 (second). The driver stage ST1a also includes a first clock input terminal CK1, a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1, a second voltage terminal VIN2, and an output terminal OUT.

[0153] The second transistor M2 and the third transistor M3 of the drive stage ST1a, as well as the first capacitor C1 and the second capacitor C2, are connected to... Figure 7 The second transistor M2 and the third transistor M3 of the drive stage ST1 shown are similar to the first capacitor C1 and the second capacitor C2. Therefore, the same reference numerals are used with respect to... Figure 7 The components shown are similar to those in the drive level ST1, and additional descriptions have been omitted to avoid redundancy.

[0154] In an embodiment, the input circuit may include transistor M1-1 (first-first transistor) and transistor M1-2 (first-second transistor).

[0155] Transistor M1-1 (1-1) and transistor M1-2 (1-2) are connected in series between the carry input terminal CIN and the first node Q1. The gate electrode of each of transistors M1-1 (1-1) and M1-2 (1-2) is connected to the first clock input terminal CK1.

[0156] like Figures 9A to 9E As shown, the first signal S_Q1 of the first node Q1 changes from a high voltage level HV to a second low voltage level LV2.

[0157] Specifically, such as Figure 8C and Figure 9C As shown, in the third cycle P3, the start signal FLM is at a high level H (i.e., a high voltage level HV), and the first node Q1 is at a second low voltage level LV2. In this situation, the voltage difference between the first electrode (i.e., the source electrode) and the second electrode (i.e., the drain electrode) of the first transistor M1 increases. Furthermore, as the voltage difference between the first electrode and the second electrode of the first transistor M1 changes significantly and periodically, the first transistor M1 may be damaged due to high stress.

[0158] like Figure 10 As shown, because transistors M1-1 and M1-2 are connected in series between the carry input terminal CIN and the first node Q1, the stress caused by the voltage difference between the first and second electrodes of each of transistors M1-1 and M1-2 can be reduced.

[0159] According to embodiments of this disclosure, damage to the first-1 transistor M1-1 and the first-2 transistor M1-2 can be minimized, thereby improving the reliability of the drive stage ST1a.

[0160] Figure 11 This is a circuit diagram of the driver stage ST1b according to an embodiment of the present disclosure.

[0161] Reference Figure 11 The driver stage ST1b includes transistors M1-1 (first-1), M1-2 (first-2), M2 (second), M3 (third), and M4 (fourth), as well as capacitors C1 and C2. The driver stage ST1b also includes a first clock input terminal CK1, a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1, a second voltage terminal VIN2, and an output terminal OUT.

[0162] The first transistor M1-1, the first transistor M1-2, the second transistor M2, and the third transistor M3 of the driver stage ST1b, as well as the first capacitor C1 and the second capacitor C2, are connected to... Figure 10 The first transistor M1-1, the first transistor M1-2, the second transistor M2, and the third transistor M3 of the drive stage ST1a shown are similar to the first capacitor C1 and the second capacitor C2. Therefore, the same reference numerals are used with respect to... Figure 10 The components shown are similar to those in the drive level ST1a, and additional descriptions have been omitted to avoid redundancy.

[0163] In an embodiment, the first transistor M1-1, the first transistor M1-2, and the fourth transistor M4 may be included in the input circuit.

[0164] Transistor M1-1 (1-1) and transistor M1-2 (1-2) are connected in series sequentially between the carry input terminal CIN and the second node Q2. The gate electrode of each of transistors M1-1 (1-1) and M1-2 (1-2) is connected to the first clock input terminal CK1.

[0165] The fourth transistor M4 is connected between the second node Q2 and the first node Q1, and includes a gate electrode connected to the second voltage terminal VIN2.

[0166] The fourth transistor M4 can always be turned on by the second voltage VGL received at the gate electrode.

[0167] Because transistors M1-1, M1-2, and M4 are connected in series between the carry input terminal CIN and the first node Q1, the stress caused by the voltage difference between the first and second electrodes of each of transistors M1-1, M1-2, and M4 can be reduced.

[0168] According to this circuit configuration, damage to transistors M1-1 (first-first stage), M1-2 (first-second stage), and M4 (fourth stage) can be minimized, thereby improving the reliability of the drive stage ST1b.

[0169] Figure 12 This is a circuit diagram of the driver stage ST1-1 according to an embodiment of the present disclosure.

[0170] Reference Figure 12The driver stage ST1-1 includes a first transistor S1, a second transistor S2, a third transistor S3, and a fourth transistor S4, as well as a first capacitor C1 and a second capacitor C2. The driver stage ST1-1 also includes a first clock input terminal CK1 and a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1 and a second voltage terminal VIN2, and an output terminal OUT.

[0171] The first transistor S1, the second transistor S2, and the third transistor S3 of the drive stage ST1-1, the first capacitor C1, and the second capacitor C2 are connected to... Figure 7 The first transistor M1, second transistor M2, and third transistor M3, the first capacitor C1, and the second capacitor C2 in the driver stage ST1 shown are similar. Therefore, additional descriptions are omitted to avoid redundancy.

[0172] The fourth transistor S4 is connected between the first clock input terminal CK1 and the first node Q1, and includes a gate electrode connected to the carry input terminal CIN. The first transistor S1 and the fourth transistor S4 can be referred to as the input circuit.

[0173] Figures 13A to 13E It is used to describe Figure 12 The circuit diagram shown below illustrates the operation of the drive stage ST1-1.

[0174] Reference Figure 9A and Figure 13A During the first cycle P1, each of the carry signal (i.e., the start signal FLM) and the first clock signal CLK1 is at a low level L, and the second clock signal CLK2 is at a high level H.

[0175] When the first clock signal CLK1 is at a low level L, each of the first transistor S1 and the second transistor S2 is turned on.

[0176] Because the second transistor S2 is turned on, the scan signal GW1 corresponding to the high level H of the first voltage VGH can be output to the output terminal OUT.

[0177] Because the first transistor S1 is turned on, the low-level start signal FLM can be transmitted to the first node Q1.

[0178] Meanwhile, because the start signal FLM is at a low level L, the fourth transistor S4 is turned on. With the fourth transistor S4 turned on, the low-level clock signal CLK1 can be transmitted to the first node Q1.

[0179] The first signal S_Q1 of the first node Q1 can be the first low voltage level LV1 corresponding to the start signal FLM and the clock signal CLK1 of the low level L.

[0180] When the first signal S_Q1 is at the first low voltage level LV1, the third transistor S3 can be turned on. With the third transistor S3 turned on, the second clock signal CLK2, which is at a high level H, is output to the output terminal OUT through the third transistor S3. Therefore, in the first cycle P1, the scan signal GW1 is at a high level H.

[0181] During the first cycle P1, a first voltage VGH, which is a DC voltage, can be supplied to the output terminal OUT. Therefore, during the first cycle P1, the scan signal GW1 of the output terminal OUT can remain at a stable high level H.

[0182] Reference Figure 9B and Figure 13B During the second cycle P2, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0183] When the first clock signal CLK1 is at a high level H, each of the first transistor S1 and the second transistor S2 is turned off.

[0184] When the start signal FLM is at a high level H, the fourth transistor S4 is turned off.

[0185] The first signal S_Q1 of the first node Q1 can be held at a first low voltage level LV1 by the second capacitor C2. Because the third transistor S3 remains on while the first signal S_Q1 is held at the first low voltage level LV1, the second clock signal CLK2, which is at a high level H, is output to the output terminal OUT through the third transistor S3. Therefore, in the second cycle P2, the scan signal GW1 is at a high level H.

[0186] Reference Figure 9C and Figure 13C During the third cycle P3, each of the start signal FLM and the first clock signal CLK1 is at a high level H, and the second clock signal CLK2 is at a low level L.

[0187] When the first clock signal CLK1 is at a high level H, each of the first transistor S1 and the second transistor S2 is turned off.

[0188] When the start signal FLM is at a high level H, the fourth transistor S4 is turned off.

[0189] The first signal S_Q1 of the first node Q1 can be held at a first low voltage level LV1 by the second capacitor C2. Because the third transistor S3 remains on while the first signal S_Q1 is held at the first low voltage level LV1, the second clock signal CLK2, which is at a low level L, is output to the output terminal OUT through the third transistor S3. Therefore, in the third cycle P3, the scan signal GW1 is at a low level L.

[0190] As the scan signal GW1 at the output terminal OUT changes from high level H to low level L, the first signal S_Q1 of the first node Q1 can be changed by the first capacitor C1 to a second low voltage level LV2, which is lower than the first low voltage level LV1.

[0191] As the voltage level of the first signal S_Q1 goes low, the third transistor S3 can be fully turned on. Therefore, in the third cycle P3, the scan signal GW1 can remain at the low level L of the second clock signal CLK2.

[0192] Reference Figure 9D and Figure 13D During the fourth cycle P4, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0193] When the first clock signal CLK1 is at a high level H, each of the first transistor S1 and the second transistor S2 is turned off.

[0194] When the start signal FLM is at a high level H, the fourth transistor S4 is turned off.

[0195] When the third transistor S3 is turned on in the third cycle P3, and then the second clock signal CLK2 changes from low level L to high level H in the fourth cycle P4, the second clock signal CLK2 at high level H is output to the output terminal OUT through the third transistor S3. Therefore, in the fourth cycle P4, the scan signal GW1 is at high level H.

[0196] As the scan signal GW1 at the output terminal OUT changes from low level L to high level H, the first signal S_Q1 of the first node Q1 can be changed by the first capacitor C1 to a first low voltage level LV1 that is higher than the second low voltage level LV2.

[0197] Because even if the voltage level of the first signal S_Q1 changes to the first low voltage level LV1, the third transistor S3 remains on, so in the fourth cycle P4, the level of the scan signal GW1 can be equal to the high level H of the second clock signal CLK2.

[0198] Reference Figure 9E and Figure 13EDuring the fifth cycle P5, each of the start signal FLM and the second clock signal CLK2 is at a high level H, and the first clock signal CLK1 is at a low level L.

[0199] When the first clock signal CLK1 is at a low level L, each of the first transistor S1 and the second transistor S2 is turned on.

[0200] When the start signal FLM is at a high level H, the fourth transistor S4 is turned off.

[0201] Because the first transistor S1 is turned on, the high-level start signal FLM can be transmitted to the first node Q1. Therefore, the first signal S_Q1 of the first node Q1 can be at the high voltage level HV corresponding to the high-level start signal FLM.

[0202] When the first signal S_Q1 is at a high voltage level HV, the third transistor S3 can be turned off.

[0203] Simultaneously, because the second transistor S2 is turned on, the scan signal GW1, corresponding to the high level H of the first voltage VGH, can be output to the output terminal OUT. Therefore, in the fifth cycle P5, the scan signal GW1 is at the high level H.

[0204] During the fifth cycle P5, the first voltage VGH, which is the DC voltage, can be supplied to the output terminal OUT. Therefore, during the fifth cycle P5, the scan signal GW1 of the output terminal OUT can remain at a stable high level H.

[0205] The first electrode of the fourth transistor S4 is connected to the first clock input terminal CK1; the second electrode of the fourth transistor S4 is connected to the first node Q1; and the gate electrode of the fourth transistor S4 is connected to the carry input terminal CIN.

[0206] like Figure 13B , Figure 13C and Figure 13E As shown, in each of the second cycle, the third cycle P3, and the fourth cycle P4, the first transistor S1 and the fourth transistor S4 remain off. At this time, due to the coupling capacitance formed between the gate electrode and the second electrode (i.e., the first node Q1) of the fourth transistor S4, the first signal S_Q1 of the first node Q1 can be more stably maintained at the first low voltage level LV1 and the second low voltage level LV2.

[0207] Figure 14 This is a circuit diagram of the driver stage ST1-1a according to an embodiment of the present disclosure.

[0208] Reference Figure 14The driver stage ST1-1a includes a first transistor S1, a second transistor S2, a third transistor S3, a fourth transistor S4, and a fifth transistor S5, as well as a first capacitor C1. The driver stage ST1-1a also includes a first clock input terminal CK1 and a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1 and a second voltage terminal VIN2, and an output terminal OUT.

[0209] The first transistor S1, the second transistor S2, the third transistor S3, and the fourth transistor S4 of the drive stage ST1-1a, as well as the first capacitor C1 and Figure 12 The first transistor S1, second transistor S2, third transistor S3, and fourth transistor S4, as well as the first capacitor C1, in the drive stage ST1-1 shown are similar. Therefore, the same reference numerals are used with respect to... Figure 12 The components shown are similar to those in the drive level ST1-1, and additional descriptions have been omitted to avoid redundancy.

[0210] The fourth transistor S4 includes a first electrode connected to the first clock input terminal CK1, a second electrode connected to the second node Q2, and a gate electrode connected to the carry input terminal CIN.

[0211] The fifth transistor S5 includes a first electrode connected to the second node Q2, a second electrode connected to the first node Q1, and a gate electrode connected to the second voltage terminal VIN2.

[0212] Figure 12 The drive stage ST1-1 shown includes a second capacitor C2. On the other hand, Figure 14 The drive stage ST1-1a shown does not include the second capacitor C2, but does include the fifth transistor S5. The first transistor S1, the second transistor S2, and the fifth transistor S5 can be referred to as the input circuit.

[0213] The coupling capacitor Cc can be formed between the second electrode and the gate electrode of the fifth transistor S5. The coupling capacitor Cc between the second electrode and the gate electrode of the fifth transistor S5 can be the same as the capacitor connected between the first node Q1 and the second voltage terminal VIN2. Therefore, in Figures 9A to 9E In each of the second period P2, the third period P3, and the fourth period P4 shown, the first node Q1 can be stably maintained at a predetermined voltage level (i.e., the first low voltage level LV1 or the second low voltage level LV2) by the coupling capacitor Cc.

[0214] At the same time, the first signal S_Q1 of the first node Q1 has a huge change from a high voltage level HV to a second low voltage level LV2.

[0215] like Figure 9C and Figure 13C As shown, when a signal with a high level H is provided to the first clock input terminal CK1 during the third cycle P3 and the first node Q1 is at the second low voltage level LV2, the voltage difference between the first electrode and the second electrode of the fourth transistor S4 increases.

[0216] like Figure 9E and Figure 13E As shown, when a low-level L signal is provided to the first clock input terminal CK1 during the fifth cycle P5 and the first node Q1 is at a high voltage level HV, the voltage difference between the first electrode and the second electrode of the fourth transistor S4 is close to 0.

[0217] Thus, as the voltage difference between the first and second electrodes of the fourth transistor S4 changes significantly and periodically, the fourth transistor S4 may be damaged due to high stress.

[0218] exist Figure 14 In the embodiment shown, because the fourth transistor S4 and the fifth transistor S5 are sequentially connected in series between the first clock input terminal CK1 and the first node Q1, the stress caused by the voltage difference between the first and second electrodes of each of the fourth transistor S4 and the fifth transistor S5 can be reduced.

[0219] According to embodiments of this disclosure, damage to the fourth transistor S4 and the fifth transistor S5 can be minimized, thereby improving the reliability of the drive stage ST1-1a.

[0220] Figure 15 This is a circuit diagram of the driver stage ST1-1b according to an embodiment of the present disclosure.

[0221] Reference Figure 15 The driver stage ST1-1b includes a first transistor S1, a second transistor S2, a third transistor S3, a fourth transistor S4, and a fifth transistor S5, as well as a first capacitor C1 and a second capacitor C2. The driver stage ST1-1b also includes a first clock input terminal CK1 and a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1 and a second voltage terminal VIN2, and an output terminal OUT.

[0222] The first transistor S1, the second transistor S2, the third transistor S3, the fourth transistor S4, and the fifth transistor S5 of the drive stage ST1-1b, as well as the first capacitor C1 and Figure 14 The first transistor S1, second transistor S2, third transistor S3, fourth transistor S4, and fifth transistor S5, as well as the first capacitor C1, of the drive stage ST1-1a shown are similar. Therefore, the same reference numerals are used with respect to... Figure 14The components shown are similar to those in the drive level ST1-1a, and additional descriptions have been omitted to avoid redundancy.

[0223] The second capacitor C2 is connected between the first node Q1 and the second voltage terminal VIN2.

[0224] The drive stage ST1-1b may also include a second capacitor C2, and therefore in Figures 9A to 9E In each of the second period P2, the third period P3, and the fourth period P4 shown, the first node Q1 can be stably maintained at a predetermined voltage level (i.e., the first low voltage level LV1 or the second low voltage level LV2).

[0225] Figure 16 This is a circuit diagram of the driver stage ST1-2 according to an embodiment of the present disclosure.

[0226] Reference Figure 16 The driver stage ST1-2 includes a first transistor W1, a second transistor W2, and a third transistor W3, a switching circuit SW1, a first capacitor C1, and a second capacitor C2. The driver stage ST1-2 also includes a first clock input terminal CK1 and a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1, a second voltage terminal VIN2, a third voltage terminal VIN3, a fourth voltage terminal VIN4, and an output terminal OUT.

[0227] The first transistor W1, the second transistor W2, and the third transistor W3 of the driver stage ST1-2, the first capacitor C1, and the second capacitor C2 are connected to... Figure 7 The first transistor M1, second transistor M2, and third transistor M3, the first capacitor C1, and the second capacitor C2 in the driver stage ST1 shown are similar. Therefore, additional descriptions are omitted to avoid redundancy.

[0228] The input circuit includes a first transistor W1 and a switching circuit SW1. The input circuit can operate in response to a clock signal CLK1 from the first clock input terminal CK1.

[0229] The switching circuit SW1 includes a fourth transistor W4 and a fifth transistor W5.

[0230] The fourth transistor W4 is connected between the third voltage terminal VIN3 and the second node Q2, and includes a gate electrode connected to the first clock input terminal CK1.

[0231] The fifth transistor W5 is connected between the fourth voltage terminal VIN4 and the second node Q2, and includes a gate electrode connected to the first clock input terminal CK1.

[0232] In one embodiment, the fourth transistor W4 is an N-type transistor, and the fifth transistor W5 is a P-type transistor. However, this disclosure is not limited thereto.

[0233] In one embodiment, a third voltage VGH2 can be received at the third voltage terminal VIN3, and a fourth voltage VGL2 can be received at the fourth voltage terminal VIN4. In another embodiment, the third voltage VGH2 can be a voltage level higher than or equal to the first voltage VGH. In yet another embodiment, the fourth voltage VGL2 can be a voltage level lower than or equal to the second voltage VGL.

[0234] The third voltage VGH2 and the fourth voltage VGL2 can be obtained from Figure 2 The voltage generator 500 shown is provided.

[0235] Figures 17A to 17E It is used for Figure 16 The circuit diagram shown describes the operation of the drive stage ST1-2.

[0236] Reference Figure 9A and Figure 17A During the first cycle P1, each of the carry signal (i.e., the start signal FLM) and the first clock signal CLK1 is at a low level L, and the second clock signal CLK2 is at a high level H.

[0237] When the first clock signal CLK1 is at a low level L, the fourth transistor W4 is turned off and the fifth transistor W5 is turned on.

[0238] Because the fifth transistor W5 is turned on, the fourth voltage VGL2 is supplied to the second node Q2. Since the fourth voltage VGL2 is lower than the second voltage VGL, the second transistor W2 is turned on. Therefore, the scan signal GW1, corresponding to the high level H of the first voltage VGH, can be output to the output terminal OUT.

[0239] Simultaneously, because the first transistor W1 is turned on in response to the signal from the second node Q2, the low-level start signal FLM can be transmitted to the first node Q1. Therefore, the first signal S_Q1 of the first node Q1 can be the first low voltage level LV1 corresponding to the low-level start signal FLM.

[0240] When the first signal S_Q1 is at the first low voltage level LV1, the third transistor W3 can be turned on. With the third transistor W3 turned on, the second clock signal CLK2, which is at a high level H, is output to the output terminal OUT through the third transistor W3. Therefore, in the first cycle P1, the scan signal GW1 is at a high level H.

[0241] During the first cycle P1, a first voltage VGH, which is a DC voltage, can be supplied to the output terminal OUT. Therefore, during the first cycle P1, the scan signal GW1 of the output terminal OUT can remain at a stable high level H.

[0242] Reference Figure 9B and Figure 17B During the second cycle P2, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0243] When the first clock signal CLK1 is high (H), the fourth transistor W4 is turned on, and the fifth transistor M5 is turned off.

[0244] When the fourth transistor W4 is turned on, a signal is delivered to the second node Q2, which has a third voltage VGH2 that is higher than the first voltage VGH, and thus each of the first transistor W1 and the second transistor W2 is turned off.

[0245] The first signal S_Q1 of the first node Q1 can be held at a first low voltage level LV1 by the second capacitor C2. Because the third transistor W3 remains on while the first signal S_Q1 is held at the first low voltage level LV1, the second clock signal CLK2, which is at a high level H, is output to the output terminal OUT through the third transistor W3. Therefore, in the second cycle P2, the scan signal GW1 is at a high level H.

[0246] Reference Figure 9C and Figure 17C During the third cycle P3, each of the start signal FLM and the first clock signal CLK1 is at a high level H, and the second clock signal CLK2 is at a low level L.

[0247] When the first clock signal CLK1 is high (H), the fourth transistor W4 is turned on, and the fifth transistor M5 is turned off.

[0248] When the fourth transistor W4 is turned on, a signal is delivered to the second node Q2, which has a third voltage VGH2 that is higher than the first voltage VGH, and thus each of the first transistor W1 and the second transistor W2 remains off.

[0249] The first signal S_Q1 of the first node Q1 can be held at a first low voltage level LV1 by the second capacitor C2. Because the third transistor W3 remains on while the first signal S_Q1 is held at the first low voltage level LV1, the second clock signal CLK2, which is at a low level L, is output to the output terminal OUT through the third transistor W3. Therefore, in the third cycle P3, the scan signal GW1 is at a low level L.

[0250] As the scan signal GW1 at the output terminal OUT changes from high level H to low level L, the first signal S_Q1 of the first node Q1 can be changed by the first capacitor C1 to a second low voltage level LV2, which is lower than the first low voltage level LV1.

[0251] As the voltage level of the first signal S_Q1 goes low, the third transistor W3 can be fully turned on. Therefore, in the third cycle P3, the scan signal GW1 can remain at the low level L of the second clock signal CLK2.

[0252] Reference Figure 9D and Figure 17D During the fourth cycle P4, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0253] When the first clock signal CLK1 is high (H), the fourth transistor W4 is turned on, and the fifth transistor M5 is turned off.

[0254] When the third transistor W3 is turned on in the third cycle P3, and then the second clock signal CLK2 changes from low level L to high level H in the fourth cycle P4, the second clock signal CLK2 at high level H is output to the output terminal OUT through the third transistor W3. Therefore, in the fourth cycle P4, the scan signal GW1 is at high level H.

[0255] As the scan signal GW1 at the output terminal OUT changes from low level L to high level H, the first signal S_Q1 of the first node Q1 can be changed by the first capacitor C1 to a first low voltage level LV1 that is higher than the second low voltage level LV2.

[0256] Because even if the voltage level of the first signal S_Q1 changes to the first low voltage level LV1, the third transistor W3 remains on, so in the fourth cycle P4, the level of the scan signal GW1 can be equal to the high level H of the second clock signal CLK2.

[0257] Reference Figure 9E and Figure 17E During the fifth cycle P5, each of the start signal FLM and the second clock signal CLK2 is at a high level H, and the first clock signal CLK1 is at a low level L.

[0258] When the first clock signal CLK1 is at a low level L, the fourth transistor W4 is turned off and the fifth transistor M5 is turned on.

[0259] Because the fifth transistor W5 is turned on, the fourth voltage VGL2 is supplied to the second node Q2. Because the fourth voltage VGL2 is lower than the second voltage VGL, the second transistor W2 is turned on. Therefore, during the fifth cycle P5, the scan signal GW1 corresponding to the high level H of the first voltage VGH can be output to the output terminal OUT.

[0260] Simultaneously, because the first transistor W1 is turned on in response to the signal from the second node Q2, the high-level start signal FLM can be transmitted to the first node Q1. Therefore, the first signal S_Q1 of the first node Q1 can be at the high voltage level HV corresponding to the high-level start signal FLM.

[0261] Because the first signal S_Q1 of the first node Q1 is a high voltage level HV, the third transistor W3 is turned off.

[0262] like Figure 9E and Figure 17E As shown, when the first clock signal CLK1 is at a low level L in the fifth cycle P5, the fifth transistor W5 is turned on, and therefore the second node Q2 can be stably maintained at the fourth voltage VGL2. Consequently, the second transistor W2 remains on, and therefore the scan signal GW1, corresponding to the high level H of the first voltage VGH, can be stably output to the output terminal OUT. Specifically, because the fourth voltage VGL2 is a voltage level lower than the second voltage VGL, the second transistor W2 can remain fully on.

[0263] In addition, in response to the signal of the second node Q2, the first transistor W1 can also be fully turned on, while the third transistor W3 can be stably kept off.

[0264] Figure 3 The second transistor T2 of the pixel PX shown operates in response to the scan signal GWi. When the voltage level of the scan signal GWi is unstable in the section where the second transistor T2 needs to be kept off, the data signal Dj, which is sent to the data line DLj, is sent to the pixel PX, and thus the desired image can be displayed.

[0265] like Figure 17E As shown, in the fifth cycle P5, the second transistor W2 remains fully on, and therefore the scan signal GW1 can be stably maintained at a high level H corresponding to the first voltage VGH. Therefore, the display device DD (see...) can be improved. Figure 1 The reliability of ).

[0266] At the same time, such as Figure 17B , Figure 17C and Figure 17DAs shown, when the first clock signal CLK1 is at a high level H in each of the second cycle P2, the third cycle P3, and the fourth cycle P4, the fourth transistor W4 is turned on. With the fourth transistor W4 turned on, a signal for the second node Q2 with a third voltage VGH2 higher than the first voltage VGH is delivered, and therefore each of the first transistor W1 and the second transistor W2 is completely turned off.

[0267] Figure 18 This is a circuit diagram of the driver stage ST1-2a according to an embodiment of the present disclosure.

[0268] Reference Figure 18 The driver stage ST1-2a includes a first transistor W1, a second transistor W2, a third transistor W3, and a sixth transistor W6, a switching circuit SW1, and a first capacitor C1. The driver stage ST1-2a also includes a first clock input terminal CK1 and a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1, a second voltage terminal VIN2, a third voltage terminal VIN3, and a fourth voltage terminal VIN4, and an output terminal OUT.

[0269] The first transistor W1, the second transistor W2, the third transistor W3, the switching circuit SW1, and the first capacitor C1 of the drive stage ST1-2a are connected to... Figure 16 The first transistor W1, second transistor W2, third transistor W3, switching circuit SW1, and first capacitor C1 of the drive stage ST1-2 shown are similar. Therefore, the same reference numerals are used with respect to... Figure 16 The components shown are similar to those in the drive level ST1-2, and additional descriptions have been omitted to avoid redundancy.

[0270] The input circuit includes a first transistor W1, a sixth transistor W6, and a switching circuit SW1. The input circuit is operable in response to a clock signal CLK1 from a first clock input terminal CK1. The switching circuit SW1 includes a fourth transistor W4 and a fifth transistor W5. In an embodiment, the fourth transistor W4 is an N-type transistor, and the fifth transistor W5 is a P-type transistor. However, this disclosure is not limited thereto.

[0271] The first transistor W1 includes a first electrode connected to the carry input terminal CIN, a second electrode connected to the third node Q3, and a gate electrode connected to the second node Q2.

[0272] The sixth transistor W6 includes a first electrode connected to the third node Q3, a second electrode connected to the first node Q1, and a gate electrode connected to the second voltage terminal VIN2.

[0273] Figure 16The drive stage ST1-2 shown includes a second capacitor C2. On the other hand, Figure 18 The drive stage ST1-2a shown does not include the second capacitor C2, but does include the sixth transistor W6.

[0274] The coupling capacitor Cc can be formed between the second electrode and the gate electrode of the sixth transistor W6. The coupling capacitor Cc between the second electrode and the gate electrode of the sixth transistor W6 can be the same as the capacitor connected between the first node Q1 and the second voltage terminal VIN2. Therefore, in Figures 9A to 9E In each of the second period P2, the third period P3, and the fourth period P4 shown, the first node Q1 can be stably maintained at a predetermined voltage level (i.e., the first low voltage level LV1 or the second low voltage level LV2) by the coupling capacitor Cc.

[0275] At the same time, the first signal S_Q1 of the first node Q1 has a huge change from a high voltage level HV to a second low voltage level LV2.

[0276] like Figure 9C and Figure 17C As shown, when a high-level signal H is provided to the carry input terminal CIN during the third cycle P3 and the first node Q1 is at the second low voltage level LV2, the voltage difference between the first electrode and the second electrode of the first transistor W1 increases.

[0277] like Figure 9E and Figure 17E As shown, when a high-level signal H is provided to the first clock input terminal CK1 during the fifth cycle P5 and the first node Q1 is at a high voltage level HV, the voltage difference between the first electrode and the second electrode of the first transistor W1 is close to 0.

[0278] Thus, as the voltage difference between the first and second electrodes of the first transistor W1 changes significantly and periodically, the first transistor W1 may be damaged due to high stress.

[0279] exist Figure 18 In the embodiment shown, because the first transistor W1 and the sixth transistor W6 are sequentially connected in series between the carry input terminal CIN and the first node Q1, the stress caused by the voltage difference between the first electrode and the second electrode of each of the first transistor W1 and the sixth transistor W6 can be reduced.

[0280] According to embodiments of this disclosure, damage to the first transistor W1 and the sixth transistor W6 can be minimized, thereby improving the reliability of the drive stage ST1-2a.

[0281] In an embodiment, the drive stage ST1-2a may further include a second capacitor connected between the first node Q1 and the second voltage terminal VIN2.

[0282] Figure 19 This is a circuit diagram of the driver stage ST1-3 according to an embodiment of the present disclosure.

[0283] Reference Figure 19 The driver stage ST1-3 includes a second transistor Y2 and a third transistor Y3, an input circuit INC, and a first capacitor C1. The driver stage ST1-3 also includes a first clock input terminal CK1 and a second clock input terminal CK2, a carry input terminal CIN, a first voltage terminal VIN1 and a second voltage terminal VIN2, and an output terminal OUT.

[0284] The second transistor Y2 and the third transistor Y3 of the drive stage ST1-3, as well as the first capacitor C1 and Figure 7 The second transistor M2 and the third transistor M3 of the drive stage ST1 shown are similar to the first capacitor C1. Therefore, additional descriptions are omitted to avoid redundancy.

[0285] The input circuit INC includes a first transistor Y1, a fourth transistor Y4, and a fifth transistor Y5.

[0286] The first transistor Y1 is connected between the second node Q2 and the second voltage terminal VIN2, and includes a gate electrode connected to the carry input terminal CIN.

[0287] The fourth transistor Y4 is connected between the carry input terminal CIN and the second node Q2, and includes a gate electrode connected to the first clock input terminal CK1.

[0288] The fifth transistor Y5 is connected between the second node Q2 and the first node Q1, and includes a gate electrode connected to the second voltage terminal VIN2.

[0289] In an embodiment, the drive stage ST1-3 may further include a second capacitor connected between the first node Q1 and the second voltage terminal VIN2.

[0290] Figures 20A to 20E It is used to describe Figure 19 The circuit diagram shown is for the operation of the drive stage ST1-3.

[0291] Reference Figure 9A and Figure 20A During the first cycle P1, each of the carry signal (i.e., the start signal FLM) and the first clock signal CLK1 is at a low level L, and the second clock signal CLK2 is at a high level H.

[0292] When the first clock signal CLK1 is at a low level L, each of the second transistor Y2 and the fourth transistor Y4 is turned on.

[0293] Because the second transistor Y2 is turned on, the scan signal GW1, corresponding to the high level H of the first voltage VGH, can be output to the output terminal OUT. Furthermore, because the fourth transistor Y4 is turned on, the low level L start signal FLM can be transmitted to the second node Q2.

[0294] When the start signal FLM is at a low level L, the first transistor Y1 is turned on. Therefore, the second voltage VGL can be transmitted to the second node Q2 through the first transistor Y1.

[0295] Since the fifth transistor Y5 is always on, the first signal S_Q1 of the first node Q1 can be the first low voltage level LV1 corresponding to the second voltage VGL.

[0296] During the first cycle P1, the first voltage VGH, which is the DC voltage, can be supplied to the output terminal OUT through the second transistor Y2. Therefore, during the first cycle P1, the scan signal GW1 of the output terminal OUT can be kept at a stable high level H.

[0297] Furthermore, during the first cycle P1, the second voltage VGL, which is a DC voltage, can be supplied to the first node Q1 through the fifth transistor Y5. Therefore, during the first cycle P1, the third transistor Y3 remains on, and the high-level second clock signal CLK2 can be output as the scan signal GW1 of the output terminal OUT.

[0298] Reference Figure 9B and Figure 20B During the second cycle P2, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0299] When the first clock signal CLK1 is at a high level H, each of the second transistor Y2 and the fourth transistor Y4 is turned off.

[0300] When the start signal FLM is at a high level H, the first transistor Y1 is turned off.

[0301] The coupling capacitor Cc can be formed between the second electrode and the gate electrode of the fifth transistor Y5, that is, between the first node Q1 and the second voltage terminal VIN2.

[0302] The first signal S_Q1 of the first node Q1 can be held at a first low voltage level LV1 by the coupling capacitor Cc. Because the third transistor Y3 remains on while the first signal S_Q1 is held at the first low voltage level LV1, the second clock signal CLK2, which is at a high level H, is output to the output terminal OUT through the third transistor Y3. Therefore, in the second cycle P2, the scan signal GW1 is at a high level H.

[0303] Reference Figure 9C and Figure 20C During the third cycle P3, each of the start signal FLM and the first clock signal CLK1 is at a high level H, and the second clock signal CLK2 is at a low level L.

[0304] When the first clock signal CLK1 is at a high level H, each of the second transistor Y2 and the fourth transistor Y4 is turned off.

[0305] When the start signal FLM is at a high level H, the first transistor Y1 is turned off.

[0306] The coupling capacitor Cc can be formed between the second electrode and the gate electrode of the fifth transistor Y5, that is, between the first node Q1 and the second voltage terminal VIN2.

[0307] The first signal S_Q1 of the first node Q1 can be held at a first low voltage level LV1 by the coupling capacitor Cc. Because the third transistor Y3 remains on while the first signal S_Q1 is held at the first low voltage level LV1, the second clock signal CLK2, which is at a low level L, is output to the output terminal OUT through the third transistor Y3. Therefore, in the third cycle P3, the scan signal GW1 is at a low level L.

[0308] As the scan signal GW1 at the output terminal OUT changes from high level H to low level L, the first signal S_Q1 of the first node Q1 can be changed by the first capacitor C1 to a second low voltage level LV2, which is lower than the first low voltage level LV1.

[0309] As the voltage level of the first signal S_Q1 goes low, the third transistor Y3 can be fully turned on. Therefore, in the third cycle P3, the scan signal GW1 can remain at the low level L of the second clock signal CLK2.

[0310] Reference Figure 9D and Figure 20D During the fourth cycle P4, each of the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 is at a high level H.

[0311] When the first clock signal CLK1 is at a high level H, each of the second transistor Y2 and the fourth transistor Y4 is turned off.

[0312] When the start signal FLM is at a high level H, the first transistor Y1 is turned off.

[0313] When the third transistor Y3 is turned on in the third cycle P3, and then the second clock signal CLK2 changes from low level L to high level H in the fourth cycle P4, the second clock signal CLK2 at high level H is output to the output terminal OUT through the third transistor Y3. Therefore, in the fourth cycle P4, the scan signal GW1 is at high level H.

[0314] As the scan signal GW1 at the output terminal OUT changes from low level L to high level H, the first signal S_Q1 of the first node Q1 can be changed by the first capacitor C1 to a first low voltage level LV1 that is higher than the second low voltage level LV2.

[0315] Because even if the voltage level of the first signal S_Q1 changes to the first low voltage level LV1, the third transistor M3 remains on, so in the fourth cycle P4, the level of the scan signal GW1 can be equal to the high level H of the second clock signal CLK2.

[0316] Reference Figure 9E and Figure 20E During the fifth cycle P5, each of the start signal FLM and the second clock signal CLK2 is at a high level H, and the first clock signal CLK1 is at a low level L.

[0317] When the first clock signal CLK1 is at a low level L, each of the second transistor Y2 and the fourth transistor Y4 is turned on.

[0318] When the start signal FLM is at a high level H, the first transistor Y1 is turned off.

[0319] Because the fourth transistor Y4 is turned on, the high-level start signal FLM can be transmitted to the first node Q1 through the fourth transistor Y4 and the fifth transistor Y5. Therefore, the first signal S_Q1 of the first node Q1 can be at the high voltage level HV corresponding to the high-level start signal FLM. When the first signal S_Q1 is at the high voltage level HV, the third transistor Y3 can be turned off.

[0320] Simultaneously, because the second transistor Y2 is turned on, the scan signal GW1, corresponding to the high level H of the first voltage VGH, can be output to the output terminal OUT. Therefore, in the fifth cycle P5, the scan signal GW1 is at the high level H.

[0321] During the fifth cycle P5, the first voltage VGH, which is the DC voltage, can be supplied to the output terminal OUT. Therefore, during the fifth cycle P5, the scan signal GW1 of the output terminal OUT can remain at a stable high level H.

[0322] Figure 21 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0323] Reference Figure 21 The electronic device 10 according to embodiments of the present disclosure may include a processor PP, a power module PM, a display device DD, and a memory MM.

[0324] The processor PP may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0325] The display device DD may include and Figures 1 to 20E The configuration shown is the same.

[0326] According to an embodiment, Figure 1 The drive controller 100 of the display device DD shown can receive image signals RGB and control signals CTRL from the processor PP.

[0327] The memory MM can store the data information required for the operation of the processor PP or the display device DD. When the processor PP executes the application stored in the memory MM, image data signals and / or input control signals are sent to the display device DD, which can process the received signals and output image information through the display screen.

[0328] The power module PM may include: a power module, such as a power adapter or battery device; and a power conversion module that converts the power supplied by the power module to generate the power required for the operation of the electronic device 10.

[0329] Although embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications and substitutions can be made without departing from the scope and spirit of this disclosure as disclosed in the appended claims. Therefore, the technical scope of this disclosure is not limited to the detailed description in the specification, but should be defined by the claims.

[0330] According to embodiments of this disclosure, a scan drive circuit comprising a minimum number of transistors can be implemented. Therefore, the circuit area of ​​the scan drive circuit can be minimized. As the circuit area of ​​the scan drive circuit is minimized, the bezel area of ​​the display device can be minimized.

[0331] Although this disclosure has been described with reference to embodiments thereof, various changes and modifications may be made thereto without departing from the spirit and scope of this disclosure as set forth in the appended claims, which will be apparent to those skilled in the art.

Claims

1. A scan driving circuit, characterized by comprising: The scan driving circuit includes: an input circuit connected between the carry-in terminal and the first node, and the input circuit is configured to operate in response to a first clock signal received through a first clock input terminal; a second transistor connected between the first voltage terminal and the output terminal, and the second transistor includes a gate electrode connected to the first clock input terminal; a third transistor connected between the output terminal and a second clock input terminal, and the third transistor includes a gate electrode connected to the first node; a first capacitor connected between the output terminal and the first node; and a second capacitor connected between the first node and a second voltage terminal.

2. The scan driving circuit according to claim 1, wherein The input circuit includes: a first transistor connected between the carry-in terminal and the first node and including a gate electrode connected to the first clock input terminal.

3. The scan driving circuit according to claim 1, wherein The input circuit includes: first and second transistors connected in series between the carry-in terminal and the first node, and each of the first and second transistors includes a gate electrode connected to the first clock input terminal.

4. The scan driving circuit according to claim 1, wherein The input circuit includes: first and second transistors connected in series between the carry-in terminal and a second node, and each of the first and second transistors includes a gate electrode connected to the first clock input terminal; and a fourth transistor connected between the first node and the second node, and the fourth transistor includes a gate electrode connected to the second voltage terminal.

5. The scan driving circuit according to claim 1, wherein The scan driving circuit further includes: a fourth transistor connected between the first clock input terminal and the first node, and the fourth transistor includes a gate electrode connected to the carry-in terminal.

6. The scan driving circuit according to claim 1, wherein The scan driving circuit further includes: a fourth transistor connected between the first clock input terminal and a second node, and the fourth transistor includes a gate electrode connected to the carry-in terminal; and a fifth transistor connected between the second node and the first node, and the fifth transistor includes a gate electrode connected to the second voltage terminal.

7. The scan driving circuit according to claim 1, wherein The input circuit includes: a first transistor connected between the carry-in terminal and the first node, and the first transistor includes a gate electrode connected to a second node; a fourth transistor connected between a third voltage terminal and the second node, and the fourth transistor includes a gate electrode connected to the first clock input terminal; and a fifth transistor connected between a fourth voltage terminal and the second node, and the fifth transistor includes a gate electrode connected to the first clock input terminal.

8. The scan driving circuit according to claim 1, wherein The input circuit includes: a first transistor connected between the carry-in terminal and a third node, and the first transistor includes a gate electrode connected to a second node; a fourth transistor connected between a third voltage terminal and the second node, and including a gate electrode connected to the first clock input terminal; a fifth transistor connected between a fourth voltage terminal and the second node, and including a gate electrode connected to the first clock input terminal; and a sixth transistor connected between the third node and the first node, and including a gate electrode connected to the second voltage terminal.

9. The scan driving circuit according to claim 1, wherein The input circuit includes: a first transistor connected between a second node and the second voltage terminal, and including a gate electrode connected to the carry input terminal; a fourth transistor connected between the carry input terminal and the second node, and including a gate electrode connected to the first clock input terminal; and a fifth transistor connected between the second node and the first node, and including a gate electrode connected to the second voltage terminal.

10. An electronic device, comprising: The electronic device includes: a display panel including pixels; a scan driving circuit configured to provide a scan signal to the pixels; a driving controller configured to provide a start signal, a first clock signal, and a second clock signal to the scan driving circuit; and a voltage generator configured to provide a first voltage and a second voltage to the scan driving circuit, wherein the scan driving circuit includes: an input circuit connected between a carry input terminal configured to receive the start signal and a first node, and configured to operate in response to a first clock signal received through a first clock input terminal; a second transistor connected between a first voltage terminal configured to receive the first voltage and an output terminal configured to output the scan signal, and including a gate electrode connected to the first clock input terminal; a third transistor connected between the output terminal and a second clock input terminal configured to receive the second clock signal, and including a gate electrode connected to the first node; a first capacitor connected between the output terminal and the first node; and a second capacitor connected between the first node and a second voltage terminal configured to receive the second voltage.

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