GaN chip sealing and testing structure

Abstract

The utility model provides a GaN chip sealing and testing structure, which is characterized in that during sealing and testing, a high-thermal-conductivity metal substrate is prepared, a GaN chip is welded on the substrate in a flip-chip manner through high-thermal-conductivity elargol, chip installation is completed, flat plated low-resistance metal layer pins which are manufactured in advance are installed, and an access seat is installed on the substrate and electrically connected with the chip through ultrasonic gold wire bonding. Mounting a micro-channel radiator at the bottom of the substrate, injecting cooling liquid to realize heat dissipation, mounting a heat conducting plate to optimize a heat dissipation path, arranging a reinforcing rib and an electromagnetic shielding layer when the outer shell is manufactured, finally fixing the chip above the substrate, and arranging a stress buffer layer on a contact interface between the chip and the substrate as well as between the chip and the outer shell. According to the packaging and testing structure, through cooperation of multiple structures, the problems of heat dissipation, electrical connection, interference resistance and reliability of the GaN chip are effectively solved, and the performance and stability of the chip are improved.

Description

Technical Field

[0001] This utility model relates to the field of chip packaging and testing technology, specifically a GaN chip packaging and testing structure. Background Technology

[0002] With the development of semiconductor technology, GaN chips have been widely used in fields such as 5G communication, new energy vehicles, and high-efficiency power supplies due to their excellent characteristics such as high electron mobility and high breakdown electric field strength.

[0003] However, the packaging and testing process for GaN chips faces numerous challenges, such as: 1. GaN chips generate a large amount of heat during operation, and traditional packaging structures have poor heat dissipation efficiency, leading to excessively high chip temperatures, performance degradation, and even chip damage; 2. Given the high-frequency characteristics of GaN chips, the stability and low resistance requirements of electrical connections are extremely stringent. Existing packaging structures' pin configurations and internal connections are ill-suited to the demands of high-frequency signal transmission, easily causing signal attenuation and distortion; 3. During prolonged use, the significant difference in thermal expansion coefficients between the chip and the packaging material can easily lead to interface stress concentration, reducing the reliability of the packaging structure.

[0004] Therefore, a GaN chip packaging and testing structure needs to be designed to solve the problems mentioned above. Utility Model Content

[0005] The purpose of this invention is to provide a GaN chip packaging and testing structure to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, this utility model provides the following technical solution:

[0007] A GaN chip packaging and testing structure includes a substrate, on which an access socket, a GaN chip, and pins are respectively disposed. The access socket is also provided with an access terminal. A housing is fixedly connected to the upper outer side of the substrate, and a microchannel heat sink is fixedly installed on the bottom of the substrate.

[0008] As a preferred embodiment of this utility model, the substrate is a high thermal conductivity metal substrate, and the GaN chip is flip-chip bonded to the substrate by high thermal conductivity silver paste to improve the heat dissipation efficiency of the chip.

[0009] As a preferred embodiment of this utility model, an electromagnetic shielding layer is provided inside the outer casing to reduce the impact of external electromagnetic interference on the signal transmission of the GaN chip.

[0010] As a preferred embodiment of this utility model, the pins are designed to be flat and have a low-resistance metal layer plated on their surface to reduce resistance and inductance when connected to external circuits.

[0011] As a preferred embodiment of this invention, the access socket and the GaN chip are electrically connected by ultrasonic gold wire bonding to ensure the stability of signal transmission.

[0012] As a preferred embodiment of this utility model, the microchannel heat sink has multiple heat dissipation microholes at the bottom, an inlet microhole at the top, and several microchannels inside, through which coolant can circulate, thereby enhancing the heat dissipation effect.

[0013] As a preferred embodiment of this utility model, a heat-conducting plate is further provided on the substrate, and the heat-conducting plate is closely attached to the microchannel heat sink to further optimize the heat dissipation path.

[0014] As a preferred embodiment of this utility model, the outer shell is provided with reinforcing ribs to improve the mechanical strength and impact resistance of the outer shell.

[0015] As a preferred embodiment of this utility model, a stress buffer layer is provided at the contact interface between the GaN chip and the substrate and the outer shell to alleviate stress concentration caused by the difference in thermal expansion coefficient.

[0016] Compared with the prior art, the beneficial effects of this utility model are:

[0017] In this invention, the following effects can be achieved through a GaN chip packaging and testing structure:

[0018] 1. The GaN chip is flip-chip bonded to a high thermal conductivity metal substrate using high thermal conductivity silver paste, creating a good heat conduction path. A microchannel heat sink is installed at the bottom of the substrate, with multiple heat dissipation micro-holes at the bottom and an inlet micro-hole at the top. The internal microchannels allow coolant to flow, quickly removing heat from the chip. High thermal conductivity silicone grease is filled between the chip and the package shell to further enhance heat dissipation, reduce chip operating temperature, and improve stability and lifespan. 2. A multi-layer ceramic package shell is used, integrating a low-resistance, low-inductance metal wiring layer. The chip electrodes are connected to the wiring layer via ultrasonic gold wire bonding and then led out by pins, ensuring stable signal transmission. The pins adopt a flat design and are plated with a low-resistance metal layer to increase the contact area with external circuits, reduce resistance and inductance, and reduce signal attenuation and distortion. An electromagnetic shielding layer is set inside the ceramic shell to effectively resist external electromagnetic interference and ensure stable transmission of high-frequency signals. 3. A stress buffer layer is set at the contact interface between the chip, the substrate, and the shell to alleviate stress concentration caused by differences in thermal expansion coefficients. The outer shell is hermetically sealed to prevent the intrusion of external moisture and impurities, ensuring long-term stable operation of the chip. 4. The heat-conducting plate on the substrate is closely attached to the microchannel heat sink to further optimize the heat dissipation path; the outer shell is reinforced with ribs to improve the mechanical strength and impact resistance of the outer shell and protect the internal chip and structure. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall three-dimensional structure of this utility model;

[0020] Figure 2 This is a three-dimensional structural diagram of the present invention after partial disassembly;

[0021] Figure 3 This is a schematic diagram of the internal structure of this utility model;

[0022] Figure 4 This is a side view of the structure of this utility model;

[0023] Figure 5 This is a schematic diagram of the bottom structure of this utility model.

[0024] In the diagram: 1. Substrate; 2. Connector; 3. GaN chip; 4. Pin; 5. Connector terminal; 6. Housing; 7. Microchannel heat sink; 8. Heat dissipation micropore; 9. Inlet micropore; 10. Reinforcing rib; 11. Stress buffer layer; 12. Heat-conducting plate; 13. Electromagnetic shielding layer; 14. Microchannel. Detailed Implementation

[0025] The technical solutions of the present utility model will be clearly and completely described below with reference to the embodiments of the present utility model. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the protection scope of the present utility model.

[0026] To facilitate understanding of this utility model, a more comprehensive description will be given below with reference to the accompanying drawings. Several embodiments of this utility model are provided. However, this utility model can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this utility model will be more thorough and complete.

[0027] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0029] For examples, please refer to Figure 1-5 This utility model provides a technical solution:

[0030] A GaN chip packaging and testing structure includes a substrate 1, on which an access socket 2, a GaN chip 3, and pins 4 are respectively disposed. The access socket 2 is also provided with an access terminal 5. A housing 6 is fixedly connected to the upper outer side of the substrate 1. A microchannel heat sink 7 is also fixedly installed on the bottom of the substrate 1. During the assembly of the packaging and testing structure, the GaN chip 3 is flip-chip placed and soldered onto the substrate 1 using high thermal conductivity silver paste.

[0031] Specifically, substrate 1 is a high thermal conductivity metal substrate, and GaN chip 3 is flip-chip bonded to substrate 1 using high thermal conductivity silver paste to improve the chip's heat dissipation efficiency. The high thermal conductivity metal substrate 1 can quickly conduct away the heat generated by GaN chip 3 during operation. The flip-chip bonding method combined with high thermal conductivity silver paste greatly improves the chip's heat dissipation efficiency, reduces the chip's operating temperature, ensures stable chip performance, and extends the chip's lifespan.

[0032] Specifically, an electromagnetic shielding layer 13 is provided inside the housing 6 to reduce the impact of external electromagnetic interference on the signal transmission of the GaN chip 3. During the fabrication of the housing 6, the electromagnetic shielding layer 13 is placed inside the housing 6, and then the housing 6 is fixedly connected to the substrate 1. The electromagnetic shielding layer 13 can effectively block external electromagnetic interference from entering, reduce the impact on the signal transmission of the GaN chip 3, ensure that the chip can stably transmit signals in a complex electromagnetic environment, and improve the accuracy and reliability of signal transmission.

[0033] Specifically, pin 4 adopts a flat design and is plated with a low-resistance metal layer to reduce resistance and inductance when connected to external circuits. When manufacturing pin 4, it is designed to be flat and plated with a low-resistance metal layer, and then pin 4 is mounted on substrate 1. The flat design increases the contact area between pin 4 and external circuits, and the low-resistance metal layer on the surface reduces resistance and inductance when connected to external circuits, which is conducive to efficient signal transmission, reduces signal attenuation and distortion during transmission, and improves electrical connection performance.

[0034] Specifically, the access socket 2 and the GaN chip 3 are electrically connected by ultrasonic gold wire bonding to ensure the stability of signal transmission. After the GaN chip 3 and the access socket 2 are installed on the substrate 1, ultrasonic gold wire bonding technology is used to electrically connect the access socket 2 and the GaN chip 3. Ultrasonic gold wire bonding can ensure the stability of the electrical connection between the access socket 2 and the GaN chip 3, build a stable path for chip signal transmission, reduce fluctuations in the signal transmission process, and ensure the electrical connection stability required for the normal operation of the chip.

[0035] Specifically, the microchannel heat sink 7 has multiple heat dissipation micro-holes 8 at the bottom and an inlet micro-hole 9 at the top, and several microchannels 14 inside, through which coolant can circulate, enhancing the heat dissipation effect. The microchannel heat sink 7 is fixedly installed at the bottom of the substrate 1, and coolant is injected into the microchannels 14 through the inlet micro-hole 9. The coolant circulates within the microchannels 14, exchanging heat with the outside environment, and the heat is dissipated through the heat dissipation micro-holes 8 at the bottom. The circulation of coolant within the microchannels 14 efficiently removes the heat conducted down from the GaN chip 3 through the substrate 1. The multiple heat dissipation micro-holes 8 at the bottom increase the heat dissipation area, significantly enhancing the heat dissipation effect, further reducing the chip's operating temperature, and maintaining chip performance.

[0036] Specifically, a heat-conducting plate 12 is also provided on the substrate 1. The heat-conducting plate 12 is in close contact with the microchannel heat sink 7 to further optimize the heat dissipation path. After the microchannel heat sink 7 is installed, the heat-conducting plate 12 is installed on the substrate 1, and it is ensured that the heat-conducting plate 12 is in close contact with the microchannel heat sink 7. The heat-conducting plate 12 can optimize the heat dissipation path from the substrate 1 to the microchannel heat sink 7, so that the heat generated by the chip can be transferred to the microchannel heat sink 7 more efficiently, further improving the heat dissipation performance of the entire packaging and testing structure, and working together to ensure the stable operation of the chip.

[0037] Specifically, the outer casing 6 is provided with reinforcing ribs 10 to improve the mechanical strength and impact resistance of the outer casing 6. When manufacturing the outer casing 6, the reinforcing ribs 10 are provided on its surface, and then the outer casing 6 is fixed to the upper outer side of the substrate 1. The reinforcing ribs 10 increase the mechanical strength and impact resistance of the outer casing 6, effectively protecting the internal GaN chip 3, access socket 2 and other structures, preventing damage to the internal structure due to external impact, and improving the overall reliability and durability of the packaging and testing structure.

[0038] Specifically, stress buffer layers 11 are provided at the contact interfaces between the GaN chip 3 and the substrate 1 and the housing 6 to alleviate stress concentration caused by the difference in thermal expansion coefficients. Before flip-chip bonding the GaN chip 3 to the substrate 1 and installing the housing 6, stress buffer layers 11 are provided at the contact interfaces between the GaN chip 3 and the substrate 1 and the housing 6. The stress buffer layers 11 can effectively alleviate stress concentration caused by the difference in thermal expansion coefficients of the GaN chip 3, the substrate 1, and the housing 6 when the temperature changes, avoid chip damage and packaging structure failure due to excessive stress, and improve the long-term stability and reliability of the packaging structure.

[0039] The workflow of this utility model is as follows: When using this GaN chip packaging and testing structure, firstly, a high thermal conductivity metal substrate 1 is prepared. Then, the GaN chip 3 is flip-chip soldered onto the substrate 1 using high thermal conductivity silver paste to achieve good thermal connection and improve heat dissipation efficiency. Next, the pre-fabricated flat pins 4 with a low-resistance metal layer plated on the surface are installed on the substrate 1 to optimize the electrical connection. Then, the connector 2 is installed on the substrate 1, and ultrasonic gold wire bonding technology is used to complete the electrical connection between the connector 2 and the GaN chip 3 to ensure stable signal transmission. A microchannel heat sink 7 is fixedly installed at the bottom of the substrate 1. Coolant is injected into the microchannel 14 through the inlet microhole 9. The coolant circulates in the microchannel 14, and the heat is dissipated through the heat dissipation microhole 8 at the bottom to enhance the heat dissipation effect. After installing the microchannel heat sink 7, the heat conduction plate 12 is installed on the substrate 1, ensuring that the heat conduction plate 12 is in close contact with the microchannel heat sink 7 to further optimize the heat dissipation path. When manufacturing the outer shell 6, reinforcing ribs 10 are set to improve mechanical strength and impact resistance. An electromagnetic shielding layer 13 is set inside to reduce electromagnetic interference. Then, the outer shell 6 is fixed on the upper outer side of the substrate 1. Before flip-chip soldering the GaN chip 3 to the substrate 1 and installing the outer shell 6, stress buffer layers 11 are set at the contact interfaces between the GaN chip 3 and the substrate 1 and the outer shell 6 to alleviate stress concentration caused by the difference in thermal expansion coefficients.

[0040] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A GaN die encapsulation structure comprising a substrate (1), characterized in that: The substrate (1) is provided with an access seat (2), a GaN chip (3) and a pin (4) respectively, the access seat (2) is further provided with an access terminal (5), the upper outer side of the substrate (1) is fixedly connected with an outer shell (6), and the bottom of the substrate (1) is further fixedly installed with a micro-channel radiator (7).

2. The GaN die encapsulation structure of claim 1, wherein: The substrate (1) is a high-thermal-conductivity metal substrate, the GaN chip (3) is flip-chip soldered on the substrate (1) through high-thermal-conductivity silver glue, so as to improve the heat dissipation efficiency of the chip.

3. The GaN die encapsulation structure of claim 1, wherein: The outer shell (6) is internally provided with an electromagnetic shielding layer (13), which is used for reducing the influence of external electromagnetic interference on signal transmission of the GaN chip (3).

4. The GaN die encapsulation structure of claim 1, wherein: The pin (4) adopts a flat design and is plated with a low-resistance metal layer on the surface, so as to reduce the resistance and inductance when connected with an external circuit.

5. The GaN die encapsulation structure of claim 1, wherein: The access seat (2) and the GaN chip (3) are electrically connected through ultrasonic gold wire bonding, so as to ensure the stability of signal transmission.

6. The GaN die encapsulation structure of claim 1, wherein: The bottom of the micro-channel radiator (7) is provided with a plurality of heat dissipation micro-holes (8), the top is provided with an inlet micro-hole (9), and the inside is provided with a plurality of micro-channels (14), the micro-channels (14) can circulate cooling liquid, and the heat dissipation effect is enhanced.

7. The GaN die encapsulation structure of claim 1, wherein: The substrate (1) is further provided with a heat-conducting plate (12), the heat-conducting plate (12) is closely attached to the micro-channel radiator (7), and the heat dissipation path is further optimized.

8. The GaN die encapsulation structure of claim 1, wherein: The outer shell (6) is provided with a reinforcing rib (10), so as to improve the mechanical strength and impact resistance of the outer shell (6).

9. The GaN die encapsulation structure of claim 1, wherein: The contact interfaces of the GaN chip (3) and the substrate (1) and the outer shell (6) are all provided with a stress buffer layer (11), which is used for relieving stress concentration caused by differences in thermal expansion coefficients.

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