Integrated circuit package

Abstract

Various embodiments of the utility model relate to a packaging member. The packaging member comprises a first tube core and a second tube core. The first die includes a first interconnect structure on a first side of a first semiconductor substrate, the first interconnect structure including a plurality of first dielectric layers, a second dielectric layer, and a dielectric liner layer. A first conductive pad is disposed to extend through the dielectric liner layer and the second dielectric layer, and a first substrate via is disposed to extend through the plurality of first dielectric layers and the first semiconductor substrate. The dielectric liner is also disposed on sidewalls of the first substrate via. The second die is over and bonded to the first die. The second die includes a first bonding layer and a first bonding pad. A first bonding layer is over the second semiconductor substrate. The first bonding pad is disposed in the first bonding layer. A bond between the first bonding layer of the second die and the dielectric liner is an oxide-to-oxide bond, and a bond between the first bonding pad of the second die and the first conductive pad is a metal-to-metal bond.

Description

Technical Field

[0001] This utility model relates to an integrated circuit package. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit components and elements. Tens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. Individual dies are individually diced by sawing the integrated circuits along dicing lines. The individual dies are then separately packaged in, for example, multi-chip modules or other types of packages.

[0003] The semiconductor industry continuously increases the integrated density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. Utility Model Content

[0004] According to an embodiment, the package includes a first die, the first die including a first interconnect structure on a first side of a first semiconductor substrate, the first interconnect structure including a plurality of first dielectric layers; a second dielectric layer above the plurality of first dielectric layers; a dielectric liner above the second dielectric layer, wherein a first conductive pad is disposed extending through the dielectric liner and the second dielectric layer, and a first substrate through-hole (TSV) is disposed extending through the plurality of first dielectric layers and the first semiconductor substrate, wherein the dielectric liner is also disposed on a sidewall of the first TSV, and wherein the first TSV and the first conductive pad are in physical contact; a second die above the first die and bonded to the first die, the second die including a first bonding layer above the second semiconductor substrate; and a first bonding pad disposed in the first bonding layer, wherein the bonding between the first bonding layer of the second die and the dielectric liner is an oxide-to-oxide bonding, and the bonding between the first bonding pad of the second die and the first conductive pad is a metal-to-metal bonding. Attached Figure Description

[0005] The following detailed description, taken in conjunction with the accompanying drawings, will best convey the various aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0006] Figure 1 and 2 A cross-sectional view is shown during an intermediate step in the process of forming a semiconductor die according to some embodiments.

[0007] Figures 3 to 11A A cross-sectional view is shown during an intermediate step in the process of forming a semiconductor wafer according to some embodiments.

[0008] Figure 11B A cross-sectional view is shown during an intermediate step in a process for forming a semiconductor wafer according to another embodiment.

[0009] Figure 12 A cross-sectional view is shown during an intermediate step in the process of forming a semiconductor wafer according to some embodiments.

[0010] Figures 13A to 16 A cross-sectional view is shown during an intermediate step in the process of forming an integrated chip package according to some embodiments.

[0011] Figures 17 to 19 A cross-sectional view is shown during an intermediate step in the process of forming an integrated chip package according to other embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or feature and another element(s) shown in the diagrams. Besides the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0014] Various embodiments provide methods for forming substrate vias (TSVs) extending through a bottom semiconductor device (e.g., a bottom die). A top semiconductor device (e.g., a top die) is then bonded to the bottom semiconductor device (e.g., a bottom die) to form a vertical stack to provide a 3D integrated chip (3DIC) package, such as a system-on-a-chip (SoIC) package. The TSV can be used for signal or power transmission between the bottom and top semiconductor devices. The TSV can be formed as a semiconductor substrate extending through the bottom semiconductor device and can also extend through portions of an interconnect structure formed above the semiconductor substrate. A first metallization layer (e.g., including conductive wiring, conductive pads, or the like) is formed simultaneously with and disposed within the interconnect structure such that the process used to form the TSV is also used to form the first metallization layer. The first metallization layer and the TSV can comprise similar materials and can be in physical contact with each other, wherein the first metallization layer is used to electrically connect the TSV to other metallization layers, external devices, or other dies disposed within the interconnect structure. The beneficial features of one or more embodiments disclosed herein allow for the simultaneous formation of the TSV and the first metallization layer, such that the process used to form the TSV is also used to form the first metallization layer. This reduces the number of process steps required to form the TSV and the first metallization layer (e.g., including metal plating and planarization steps) compared to if the TSV and the first metallization layer needed to be formed using separate processes at different times. As a result, manufacturing costs can be significantly reduced. Furthermore, simultaneously forming the TSV and the first metallization layer using the same process allows for physical contact between the TSV and the first metallization layer, eliminating the need for a barrier layer between them. Therefore, the resistivity between the TSV and the first metallization layer is reduced, resulting in more efficient conductivity, enhanced device performance, and reduced power consumption.

[0015] The embodiments are described in the specific context of substrate through-hole (TSV) formation applied to a system-on-chip (SoIC) package. However, other embodiments can also be applied to other packages, including chip-on-wafer-on-substrate (SoC) packages. This includes either a packaged or integrated fan-out (InFO) package. The embodiments discussed herein provide examples of how the subject matter of this disclosure can be implemented or used, and modifications that can be made without departing from the intended scope of the different embodiments will be readily understood by those skilled in the art. Similar reference numerals and characters below refer to the same components. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logically consistent order.

[0016] Figures 1 to 16 A cross-sectional view is shown during an intermediate step in the process of forming an integrated chip package 100, according to some embodiments. Figure 1 and 2 A cross-sectional view is shown during an intermediate step in the process of forming a semiconductor die 150, according to some embodiments. The semiconductor die 150 (also referred to as the top die) is then bonded to a wafer 20 (also referred to as the bottom die). Wafer 20 is... Figures 3 to 12 Further details are provided below. Figure 1The image shows a wafer 10. Wafer 10 includes a semiconductor die 150. Each semiconductor die 150 may be a logic die (e.g., an application processor (AP), a central processing unit, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC) die, a static random access memory (SRAM) die, a wide input / output (wide IO) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC)), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), or a front-end die (e.g., an analog front-end). Semiconductor dies (front-end; AFE), biomedical dies, etc. Each semiconductor die 150 can also be a system-on-chip (SoC) die, etc. The wafer 10 may include a substrate 117 (e.g., a semiconductor substrate), an interconnect structure 119 disposed on the substrate 117, a bonding layer 121 disposed on the interconnect structure 119, and bonding pads 123 disposed in the bonding layer 121 and exposed on the front side of the wafer 10.

[0017] The substrate 117 of wafer 10 may include a crystalline silicon wafer. Depending on design requirements, substrate 117 may include various doped regions (e.g., p-type or n-type substrates). In some embodiments, the doped regions may be doped with p-type or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and / or combinations thereof. The doped regions may be configured for n-type fin field-effect transistors (FinFETs) and / or p-type FinFETs. In some alternative embodiments, substrate 117 may include an active layer of a semiconductor-on-insulator (SOI) substrate. Substrate 117 may include other semiconductor materials, such as germanium; compound semiconductors comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0018] Active and / or passive components, such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on substrate 117. Devices may be interconnected via interconnect structures 119. Interconnect structures 119 are electrically connected to devices on substrate 117 to form one or more integrated circuits. Interconnect structures 119 may include one or more dielectric layers (for example, one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, or the like) and metallization patterns 125 embedded in the one or more dielectric layers (which may also be referred to as interconnect wiring). The material of the one or more dielectric layers may include silicon oxide (SiO₂). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y (where x>0 and y>0) or other suitable dielectric material. The metallization pattern 125 may include metal wiring. For example, the metallization pattern 125 includes copper wiring, copper pads, aluminum pads, or combinations thereof formed by one or more single damascene processes, double damascene processes, etc.

[0019] The bonding layer 121 may include a dielectric layer. Bonding pads 123 are embedded in the bonding layer 121, and the bonding pads 123 allow for connection to the interconnect structure 119 and devices on the substrate 117. The material of the bonding layer 121 may be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO)x N y The bonding layer 121 may be formed by depositing a dielectric material over the interconnect structure 119 using a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable process); patterning the dielectric material to form the bonding layer 121 including openings or vias; and filling the openings or vias defined in the bonding layer 121 with conductive material to form the bonding pad 123 embedded in the bonding layer 121. In various embodiments, the back side of the wafer 10 may refer to the side of the wafer 10 that exposes the surface of the substrate 117, and the front side of the wafer 10 may refer to the side of the wafer 10 on which the means and the interconnect structure 119 are disposed.

[0020] exist Figure 2 In the middle, along Figure 1 The dicing process is performed along dicing path 129. The dicing process separates the semiconductor dies 150 from each other along dicing path 129. Each dicing path 129 is positioned between adjacent semiconductor dies 150. The dicing process may include, for example, a blade cutting process that uses a high-speed rotating grinding disc or blade saw to cut along each dicing path 129. The blade tip may include abrasive grains or a thin diamond layer. The semiconductor die 150 (also referred to as the top die) is then bonded to wafer 20 (also referred to as the bottom die), as... Figures 13A to 13B As shown. Chip 20 is below. Figures 3 to 12 A more detailed description is provided below.

[0021] Figure 3 Semiconductor wafer 20 is shown. Wafer 20 may also be referred to as bottom chip. Wafer 20 includes a first package region 200A and a second package region 200B, and encapsulates one or more integrated chip packages 100 (e.g., as will be described later in the diagram). Figure 15(As shown) to form an integrated circuit package in each of package regions 200A and 200B. In wafer 20, the materials and formation processes of the features can be found by referring to similar features in wafer 10. In wafer 10, similar features begin with the number "1", these features correspond to the features in wafer 20, and have reference numbers beginning with the number "2". For example, wafer 20 may include a substrate 217 on which devices (e.g., transistors, capacitors, diodes, resistors, or the like) are formed, and an interconnect structure 219. The interconnect structure 219 is electrically connected to the devices on substrate 217 to form one or more integrated circuits. The interconnect structure 219 includes one or more dielectric layers (e.g., one or more interlayer dielectric (ILD) layers, intermetallic dielectric (IMD) layers, or the like) and metallization patterns 225 embedded in said one or more dielectric layers (which may also be referred to as interconnect wiring).

[0022] Wafer 20 may include a dielectric layer 227 formed over interconnect structure 219. Dielectric layer 227 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, spin-coated polymers, silicon-carbon materials, compounds thereof, composites thereof, combinations thereof, or the like. Dielectric layer 227 may be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), spin coating, etc.

[0023] The wafer 20 also includes a substrate through-hole (TSV) 211 that extends through the substrate 217 and partially through the interconnect structure 219 (and subsequently also...). Figures 11A to 12 (As shown in the diagram). Additionally, wafer 20 includes a first metallization layer (e.g., including conductive wiring, conductive pads, or the like). For example, the first metallization layer may include subsequently also... Figures 11A to 12 The conductive pad 212 is shown in the diagram. The conductive pad 212 extends through the interconnect structure 219 and is formed simultaneously with the TSV 211, such that the process used to form the TSV 211 is also used to form the conductive pad 212. In embodiments, conductive wiring is used instead of the conductive pad 212. The conductive pad 212 and TSV 211 may comprise similar materials, and a portion of the conductive pad 212 may be in physical contact with the corresponding TSV 211, wherein the conductive pad 212 is used to electrically connect the TSV 211 to other external devices, other dies, or metallization patterns 225 in the interconnect structure 219. In various embodiments, the back side of the wafer 20 may refer to the side of the wafer 20 that exposes the substrate 217, and the front side of the wafer 20 may refer to the side of the wafer 20 on which the devices and interconnect structure 219 are disposed.

[0024] Figures 4 to 12 It shows Figure 3 The wafer 20 shown is region 218, and intermediate steps during the process of forming the wafer 20 are also shown according to some embodiments. Figures 4 to 11A The formation of the first portion 219a of the interconnect structure of wafer 20 is shown. Additionally, Figures 4 to 11A This illustrates the formation of TSV 211 in region 218 of wafer 20. It should be noted that... Figures 4 to 11A The description of the formation process of TSV211 can be applied to the formation of each TSV 211 in wafer 20. In the embodiment, the following can be used: Figures 4 to 11A The fabrication process described herein simultaneously forms multiple TSVs 211 of wafer 20 (e.g., such as...). Figure 3 (As shown). Figure 12 The formation of the second portion 219b of the interconnect structure of wafer 20 is shown. Figure 4 In the image, region 218 of chip 20 is shown (previously in...). Figure 3 (as shown in the image). Figure 4 A substrate 217 and one or more dielectric layers 226 formed over the substrate 217 are further shown. A guard ring structure 230 is formed such that the guard ring structure 230 is embedded in the one or more dielectric layers 226, wherein the guard ring structure 230 is stacked in the one or more dielectric layers 226 to extend vertically through the one or more dielectric layers 226. The material of the one or more dielectric layers 226 may include silicon oxide or the like formed using CVD processes, atomic layer deposition (ALD) processes, etc. Each dielectric layer 226 can be patterned using acceptable photolithography and etching techniques to form openings corresponding to the desired pattern of the respective guard ring structure 230 to be formed extending along the main surface of the dielectric layer 226 and through the dielectric layer 226. Conductive material is then formed in the openings in the dielectric layers 226 using, for example, physical vapor deposition (PVD) processes, electroplating, electroless plating, combinations thereof, etc., to form the respective guard ring structure 230. Conductive materials may include metals such as copper, titanium, tungsten, aluminum, and combinations thereof. The guard ring structure 230 surrounds each of the subsequently formed TSVs 211 (in...). Figure 3 and Figures 11A to 12 (As shown in the diagram). The guard ring structure 230 can have various functions, such as isolation, stress relief, prevention of current leakage, electrostatic discharge (ESD) protection, or combinations thereof. For example, to help prevent current leakage protection, the guard ring structure 230 can be grounded to help prevent or reduce electrical interference caused by the current flowing through each TSV 211.

[0025] One or more contact pads 228 are also formed in one or more dielectric layers 226, electrically connected to devices in and / or on the substrate 217. One or more contact pads 228 may be embedded within one or more dielectric layers 226. To form the contact pads 228, openings for the contact pads 228 are first formed in one or more dielectric layers 226 using acceptable photolithography and etching techniques. A conductive material can then be formed in the openings using deposition processes such as sputtering, evaporation, CVD, plasma-enhanced chemical vapor deposition (PECVD), electroplating, electroless plating, or combinations thereof. The conductive material may include copper, aluminum, or other conductive materials. A planarization process is then performed to remove excess conductive material, leaving the remaining conductive material in the openings to form the contact pads 228.

[0026] After forming one or more dielectric layers 226, one or more contact pads 228, and a guard ring structure 230 as described above, a dielectric layer 232 is formed over the dielectric layers 226, contact pads 228, and guard ring structure 230. The dielectric layer 232 may comprise undoped silicate glass (USG) or the like, and may be formed using a CVD process or similar. After forming the dielectric layer 232, a dielectric layer 234 is formed over the dielectric layer 232. The dielectric layer 234 may comprise silicon nitride or the like. The dielectric layer 234 may be deposited by any suitable method, such as CVD, ALD, etc. In an embodiment, an additional dielectric layer (not shown in the figures) may be formed over the dielectric layer 232 using any suitable method (e.g., CVD, ALD, etc.) before forming the dielectric layer 234. The additional dielectric layer may comprise silicon carbide or the like. After forming the dielectric layer 234, a dielectric layer 236 is formed over the dielectric layer 234. In this embodiment, the material of dielectric layer 236 may be similar to that of dielectric layer 232 described above. In this embodiment, dielectric layer 236 may be formed using a process similar to that used to form dielectric layer 232 described above.

[0027] exist Figure 5 In this process, a mask layer 238 (e.g., photoresist) is formed over the wafer 20, for example, over the dielectric layer 236. The mask layer 238 is patterned using suitable development and exposure techniques to form openings in the mask layer that expose the top surface of the dielectric layer 236.

[0028] exist Figure 6In this process, a mask layer 238 is used as an etching mask to form openings 240 in the wafer 20. Each opening 240 may extend through dielectric layers 236, 234, 232, and one or more dielectric layers 226. Additionally, the openings 240 may extend partially through the substrate 217. In an embodiment, each opening 240 may be surrounded by a corresponding guard ring structure 230. In an embodiment, the etching process may include wet etching, dry etching, or combinations thereof. For example, the etching process may include a dry plasma process, such as a deep reactive ion etching (DRIE) process using plasma gases including sulfur hexafluoride (SF6), octafluorocyclobutane (C4F8), fluoroform (CHF3), etc. The etching process may include a wet etching process, which includes hydrogen fluoride (HF) or the like as an etchant. After the openings 240 are formed, the mask layer 238 is removed using an acceptable ashing or stripping process.

[0029] exist Figure 7 In this embodiment, a dielectric liner 242 is conformally deposited over wafer 20, for example, over the top surface of dielectric layer 236 and within opening 240. For example, dielectric liner 242 is deposited on the bottom surface of opening 240 and on the sidewalls of substrate 217 in opening 240, one or more dielectric layers 226, 232, 234, and 236. Dielectric liner 242 may comprise silicon oxide or the like and may be formed using suitable processes such as CVD, ALD, etc. In embodiments, dielectric liner 242 may have a thickness T1 ranging from 50 nm to 400 nm. In embodiments, after deposition of dielectric liner 242, the width W1 of each opening 240 may range from 0.5 μm to 14 μm.

[0030] exist Figure 8 In this process, a bottom anti-reflective coating (BARC) layer 244 is formed above the dielectric substrate 242 and in the opening 240 to fill the opening 240. The BARC layer 244 can be formed using a spin coating process or the like. After the BARC layer 244 is formed, a planarization process is then performed to remove excess portions of the BARC layer 244, making the top surface of the dielectric substrate 242 flush with the top surface of the BARC layer 244 in the opening 240 (within the range of process variations). The planarization process can include an etch-back process or the like.

[0031] Further reference Figure 8After performing a planarization process, a mask layer, such as photoresist or the like (not shown), is formed over dielectric substrate 242 and BARC layer 244. The mask layer is then patterned using suitable development and exposure techniques to form openings within it. A suitable etching process is then performed to transfer the pattern of the mask layer to dielectric substrate 242, dielectric layer 236, dielectric layer 234, and dielectric layer 232, forming opening 246. Opening 246 extends through dielectric substrate 242, dielectric layer 236, dielectric layer 234, and dielectric layer 232, exposing the top surface of one or more contact pads 228. Opening 246 corresponds to subsequent etching... Figures 11A to 12 The intended pattern of via 255 is shown. The etching process may include a dry etching process, which includes tetrafluoromethane (CF4), sulfur hexafluoride (SF6), fluoroform (CHF3), or similar etchants as etchants. After the opening 246 is formed, an acceptable ashing or stripping process is used to remove the mask layer.

[0032] exist Figure 9 In this process, a bottom anti-reflective coating (BARC) layer 248 is formed above the dielectric substrate 242, the BARC layer 244, and in the opening 246 to fill the opening 246. The BARC layer 248 can be formed using a spin coating process or the like. After forming the BARC layer 248, a planarization process is performed to remove excess portions of the BARC layer 248, making the top surfaces of the dielectric substrate 242 and the BARC layer 244 flush with the top surface of the BARC layer 248 in the opening 246 (within the range of process variations). The planarization process can include an etch-back process or the like.

[0033] Figure 10The diagram illustrates the formation of a mask layer (not shown) such as photoresist or the like over dielectric substrate 242, BARC layer 244, and BARC layer 248 after a planarization process. The mask layer is then patterned using suitable development and exposure techniques to form openings within it. A suitable etching process is then performed to transfer the pattern of the mask layer onto dielectric substrate 242, dielectric layer 236, and dielectric layer 234 to form openings 250 and 252. A portion of BARC layer 244, BARC layer 248, dielectric substrate 242, dielectric layer 236, and dielectric layer 234 is etched using an etching process to form openings 250 and 252 extending through dielectric substrate 242, dielectric layer 236, and dielectric layer 234, exposing the top surface of dielectric layer 232. Each opening 250 overlaps with a corresponding contact pad 228 and exposes the remainder of a BARC layer 248, which fills the corresponding remainder of an opening 246 extending through a dielectric layer 232. Each opening 252 overlaps with and exposes the remainder of a BARC layer 244, which fills the corresponding remainder of an opening 240 extending through a dielectric layer 232, one or more dielectric layers 226, and a substrate 217. In an embodiment, each opening 252 may have a width W2, where the width W2 is greater than the width W1. In an embodiment, during the formation of the opening 252, an etching process may also be used to etch portions of the dielectric layer 232 that overlap with the guard ring structure 230. In this way, each opening 252 may also extend through the dielectric layer 232 and expose the top surface of the guard ring structure 230. The etching process may include a dry etching process, which uses tetrafluoromethane (CF4), sulfur hexafluoride (SF6), fluoroform (CHF3), or similar substances as etchants. After forming openings 250 and 252, an acceptable ashing or stripping process is used to remove the mask layer.

[0034] exist Figure 11A In this process, a suitable etching process is used to remove the BARC layer 248, causing the remaining portion of the opening 246 in the dielectric layer 232 to be reformed in each corresponding opening 250. Furthermore, the etching process further removes the BARC layer 244, causing the remaining portions of the opening 240 in the dielectric layer 232, one or more dielectric layers 226, and substrate 217 to be reformed in their respective openings 252.

[0035] After removing BARC layers 244 and 248, a barrier layer 254 can be conformally deposited over the dielectric substrate 242 and in the remaining portions of openings 250, 246, 252, and 240. The deposition of the barrier layer 254 can be performed using appropriate processes, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, or combinations thereof. The barrier layer 254 may include nitrides or oxides of nitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, or combinations thereof. In embodiments, the thickness T2 of the barrier layer 254 can range from 10 nanometers to 50 nanometers. Conductive material is deposited over the barrier layer 254 and in the remaining portions of openings 250, 246, 252, and 240. The conductive material can be formed by electrochemical plating, CVD, ALD, PVD, and combinations thereof and / or similar processes, such that the conductive material fills the remaining portions of openings 250, 246, 252, and 240. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, and combinations thereof. Excess conductive material and barrier layer 254 can be removed from above dielectric substrate 242 by performing a planarization process (e.g., chemical mechanical polishing). After performing the planarization process, the top surface of the conductive material, barrier layer 254, and dielectric substrate 242 can be horizontal (within process variations). Further, after the planarization process, the conductive material and barrier layer 254 in the remaining portions of opening 246 of dielectric layer 232 form vias 255, and the conductive material and barrier layer 254 in the remaining portions of opening 240 form TSVs 211. Each contact pad 228 can be physically and electrically connected to the corresponding plurality of vias 255. The conductive material and barrier layer 254 formed in openings 250 and 252 constitute a first metallization layer that may include conductive wiring, conductive pads, etc. For example, a first portion of the first metallization layer formed in each opening 250 may include a conductive pad 258, and a second portion of the first metallization layer formed in each opening 252 may include a conductive pad 212. Each conductive pad 258 is electrically connected to devices in and / or on the substrate 217 through corresponding vias 255 and corresponding contact pads 228. Furthermore, each conductive pad 212 is physically and electrically connected to a corresponding TSV 211. In an embodiment, the conductive pad 212 overlaps with the corresponding TSV 211. In an embodiment, each conductive pad 212 also overlaps with a corresponding guard ring structure 230, wherein the conductive pad 212 is electrically and physically connected to the corresponding guard ring structure 230. In an embodiment, each TSV 211 may have a height H1, wherein the ratio of height H1 to width W1 (hereinafter also referred to as aspect ratio) may be in the range of 2:1 to 15:1.

[0036] This can be due to the formation of a structure including TSV 211 and interconnect structure 219 (subsequently in...). Figure 12The wafer 20 (shown in the figure) achieves advantages, wherein each TSV 211 is electrically and physically connected to a corresponding conductive pad 212 in the interconnect structure 219. Forming the wafer 20 includes an etching process to form an opening 240 extending through dielectric layers 236, 234, 232, and one or more dielectric layers 226. The opening 240 also extends partially through the substrate 217, wherein dielectric layers 236, 234, 232, and one or more dielectric layers 226 are part of the interconnect structure 219. A dielectric liner 242 is then conformally deposited on the bottom surface and sidewalls in the opening 240, wherein the dielectric liner 242 comprises oxide and has a thickness T1 in the range of 50 nm to 400 nm. A BARC layer 244 is formed over the dielectric liner 242 in the opening 240, wherein the BARC layer 244 fills the opening 240. Next, portions of the BARC layer 244, dielectric substrate 242, dielectric layer 236, and dielectric layer 234 are etched to form openings 252 extending through the dielectric substrate 242, dielectric layer 236, and dielectric layer 234, exposing the top surface of dielectric layer 232. Each opening 252 overlaps and exposes the BARC layer 244, which fills the corresponding remaining portion of the opening 240 extending through dielectric layer 232, one or more dielectric layers 226, and substrate 217. Then, another etching process is performed to remove the remaining portion of the BARC layer 244, causing the remaining portion of the opening 240 in dielectric layer 232, one or more dielectric layers 226, and substrate 217 to be reformed in each corresponding opening 252. After the remaining portion of the opening 240 is reformed, a barrier layer 254 is simultaneously formed in each opening 252 and its corresponding remaining portion using the same process. After the barrier layer 254 is formed, conductive material is simultaneously formed in each opening 252 and the remainder of its corresponding opening 240 using the same process. The barrier layer 254 and conductive material in the remainder of the opening 240 form a TSV 211, and the barrier layer 254 and conductive material in the opening 252 form a conductive pad 212, wherein each TSV 211 has a width W1, each conductive pad 212 has a width W2, and wherein the width W2 is greater than the width W1. Advantageous features of one or more embodiments disclosed herein allow for the simultaneous formation of each TSV 211 and its corresponding conductive pad 212, such that the process used to form the TSV 211 is also used to form the corresponding conductive pad 212. This reduces the number of process steps required to form the TSV and the corresponding conductive pad 212 (e.g., including metal plating and planarization steps) compared to if the TSV and the corresponding conductive pad 212 needed to be formed using separate processes at different times. As a result, manufacturing costs can be significantly reduced.Furthermore, using the same process to simultaneously form the TSV and the corresponding conductive pad 212 allows for physical contact between the TSV and the corresponding conductive pad 212, and the barrier layer 254 is not disposed between the TSV and the corresponding conductive pad 212. Therefore, the resistivity between the TSV and the corresponding conductive pad 212 is reduced, resulting in more efficient conductivity, enhanced device performance, and reduced power consumption.

[0037] Figure 11B Alternative embodiments are shown. Unless otherwise stated, similar reference numerals in this embodiment (and those discussed later) are represented by [reference numeral]. Figures 1 to 11A The similar components in the embodiments shown are formed using the same process. Therefore, process steps and applicable materials may not be described again here. Figure 11B The illustrated embodiments and Figure 11A The difference in the illustrated embodiment is that, Figure 11B In the illustrated embodiment, the conductive pad 212 has no electrical connection or physical connection to the guard ring structure 230. No portion of the conductive pad 212 extends through the dielectric layer 232 to make physical contact with the guard ring structure 230.

[0038] Figure 12 The formation of a second portion 219b of the interconnect structure above a first portion 219a is shown. The second portion 219b of the interconnect structure includes one or more dielectric layers (for example, one or more inter-layer dielectric (ILD) layers, inter-metal dielectric (IMD) layers, or the like) and a metallization pattern 225 (hereinafter also referred to as interconnect wiring) embedded in the one or more dielectric layers. The material of the one or more dielectric layers may include silicon oxide (SiO₂). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y The metallization pattern 225 may include metal wiring. For example, the metallization pattern 225 may include copper wiring, copper pads, aluminum pads, or combinations thereof formed by one or more single damascene processes, double damascene processes, etc. Each conductive pad 258 electrically connects a corresponding plurality of vias 255 and a corresponding contact pad 228 to the metallization pattern 225. In addition, each conductive pad 212 electrically connects a corresponding TSV 211 to the metallization pattern 225.

[0039] Further reference Figure 12 After forming the second portion 219b of the interconnect structure, a dielectric layer 227 is formed over the second portion 219b of the interconnect structure to complete the formation of the wafer 20 (as previously described). Figure 3(As shown in the diagram). Dielectric layer 227 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, spin-coated polymers, silicon-carbon materials, compounds thereof, composites thereof, combinations thereof, etc. Dielectric layer 227 may be deposited by any suitable method, such as CVD, PECVD, spin coating, etc.

[0040] exist Figure 13A In this process, a thinning process is performed on the back side of wafer 20 (e.g., the exposed surface of substrate 217) to expose TSV 211 and dielectric liner 242. The thinning process on the back side of wafer 20 can be performed by a planarization process such as CMP, grinding, or etching. The thinning process can result in the exposed surface of TSV 211 being flush with the surfaces of substrate 217 and dielectric liner 242.

[0041] After a thinning process is performed on the back side of wafer 20, a bonding layer 221 is formed over the back side of wafer 20, for example, over dielectric liner 242, substrate 217, and TSV 211. Bonding layer 221 may include a dielectric layer. Bonding pads 223 are formed in bonding layer 221 such that the bonding pads 223 are in physical contact with the corresponding TSV 211. Bonding pads 223 allow electrical connections via TSV 211 to interconnect structures 219 and devices on substrate 217. The material of bonding layer 221 may be silicon oxide (SiO2). x (where x>0), silicon nitride (SiN) x (where x>0), silicon oxynitride (SiO) x N y The bonding layer 221 may comprise conductive pads (e.g., copper pads), conductive vias (e.g., copper vias), or combinations thereof, wherein x>0 and y>0, tetraethylsilicate (TEOS), or other suitable dielectric materials. The bonding layer 221 may be formed by depositing a dielectric material on the back side of the wafer 20 using a chemical vapor deposition (CVD) process (e.g., plasma-enhanced CVD or other suitable process); patterning the dielectric material to form the bonding layer 221 including openings or vias; and filling the openings or vias defined in the bonding layer 221 with conductive material to form the bonding pads 223 embedded in the bonding layer 221.

[0042] Further reference Figure 13A Semiconductor die 150 (previously in Figure 2 (As shown in the diagram) it is bonded to wafer 20 in, for example, a hybrid bonding configuration. Each semiconductor die 150 may also be referred to as a top die. Semiconductor dies 150 are configured face down and bonded to wafer 20 in a face-to-back (F2B) bonding configuration, as shown in the diagram. Figure 13A and 13B As shown, the front side of each semiconductor die 150 (e.g., interconnect structure 119) is bonded to the back side of the wafer 20. For example, Figure 13B It showed the previous Figure 13A The structure shown includes region 296, which comprises portions of a semiconductor die 150 and a wafer 20 to which it is bonded. The semiconductor die 150 is bonded to a bonding layer 221 and bonding pads 223 in the bonding layer 221 on the back side of the wafer 20. For example, the bonding layer 121 of the semiconductor die 150 may be directly bonded to the bonding layer 221 on the wafer 20, and the bonding pads 123 of the semiconductor die 150 may be directly bonded to the bonding pads 223 on the wafer 20. In embodiments, the bonding between the bonding layers 121 and 221 may be oxide-to-oxide bonding, etc. A hybrid bonding process further directly bonds the bonding pads 123 of the semiconductor die 150 to the bonding pads 223 of the wafer 20 via direct metal-to-metal bonding. Therefore, the electrical connection between the semiconductor die 150 and the wafer 20 is provided through the physical connection of the bonding pads 123 to 223.

[0043] As an example, the hybrid bonding process may begin by aligning the semiconductor die 150 to the wafer 20 by surface treatment of one or more of bonding layers 121 or 221. Surface treatment may include plasma treatment. Plasma treatment may be performed in a vacuum environment. After plasma treatment, surface treatment may also include a cleaning process (e.g., rinsing with deionized water or the like) that may be applied to one or more of bonding layers 121 or 221. The hybrid bonding process may then continue to align bonding pad 123 to bonding pad 223. Next, the hybrid bonding includes a pre-bonding step during which the semiconductor die 150 contacts the wafer 20. Pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). Annealing may be performed, for example, at a temperature between about 150°C and about 400°C to continue the hybrid bonding process for a duration between about 0.5 hours and about 3 hours, causing the metal (e.g., copper) in bonding pad 123 and the metal (e.g., copper) in bonding pad 223 to diffuse into each other, thus forming a direct metal-to-metal bond. Although four semiconductor dies 150 are shown bonded to wafer 20, other embodiments may include any number of semiconductor dies 150 bonded to wafer 20. Wafer 20 may include a first package region 200A and a second package region 200B, and encapsulate one or more integrated chip packages 100 to form an integrated circuit package in each of package regions 200A and 200B.

[0044] exist Figure 14In this process, an encapsulation 130 is formed over the wafer 20 and the semiconductor die 150 to encapsulate the semiconductor die 150. The encapsulation 130 can be formed using compression molding, transfer molding, or other methods. The encapsulation 130 can be an epoxy resin or molding material, such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyether sulfone (PES), heat-resistant crystalline resin, or combinations thereof.

[0045] Figure 14 The diagram further illustrates a thinning process for the encapsulation 130 to expose the top surface of the semiconductor die 150. The thinning process can be performed, for example, using mechanical polishing, chemical methods, or chemical mechanical polishing (CMP) processes, where chemical etchants and abrasives are used to react and remove the encapsulation 130, thereby exposing the top surface of the semiconductor die 150. After the thinning process, the top surface of the semiconductor die 150 can also have a flat surface coplanar with the top surface of the encapsulation 130.

[0046] After the encapsulation 130 is thinned, a carrier substrate 134 is bonded to the top surface of the semiconductor die 150 and the encapsulation 130. In embodiments, the carrier substrate 134 comprises, for example, a silicon-based material (e.g., glass or silicon oxide), or other materials (e.g., aluminum oxide), or any combination thereof. The carrier substrate 134 is planar to accommodate the connection between the semiconductor die 150 and the encapsulation 130, and it can be connected using a release layer 132. The release layer 132 may be formed of a polymer-based material, which can be removed from the overlying structure along with the carrier substrate 134 in a subsequent step. In some embodiments, the release layer 132 is an epoxy-based thermal release material that loses its adhesive properties upon heating, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 132 may be an ultraviolet (UV) adhesive that loses its adhesive properties upon exposure to ultraviolet light. Release layer 132 can be dispensed and cured as a liquid, and can be a laminated film laminated onto the carrier substrate 134, or the like. The top surface of release layer 132 can be flat and can have a high degree of flatness.

[0047] Figure 15The patterning of dielectric layer 227 is shown to form openings extending through dielectric layer 227 and exposing portions of metallized pattern 225 (e.g., conductive pads of metallized pattern 225) in interconnect structure 219. In embodiments, dielectric layer 227 can be patterned using, for example, laser drilling methods. In such methods, for example, photothermal conversion (LTHC) layers (not in...) Figure 15 A protective layer (shown separately) is first deposited on dielectric layer 227. Once protected, a laser is directed at the portions of dielectric layer 227 that need to be removed to expose portions of the underlying metallization pattern 225.

[0048] In another embodiment, the dielectric layer 227 may be patterned to form openings that expose portions of the metallization pattern 225, by: first applying photoresist (in...) Figure 15 A patterned energy source (e.g., a patterned light source, not shown separately) is applied to dielectric layer 227, and then the photoresist is exposed to a patterning energy source (e.g., a patterned light source) to initiate a chemical reaction, thereby causing physical changes in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to utilize the physical changes and selectively remove the exposed or unexposed portions of the photoresist according to the desired pattern, and the exposed portions of the underlying dielectric layer 227 are removed using, for example, a dry etching process. However, any other suitable method for patterning dielectric layer 227 can be used to form openings.

[0049] Then, conductive connectors 260 are formed over dielectric layer 227 and in openings in dielectric layer 227. Conductive connectors 260 are electrically coupled to semiconductor die 150 via interconnect structures 219 (e.g., including conductive pads 212 and TSV 211). Conductive connectors 260 are also electrically coupled to contact pads 228 via interconnect structures 219 (e.g., including vias 255 and conductive pads 258). Conductive connectors 260 may include controlled collapse chip connection (C4) bumps, ball grid array (BGA) connectors, solder balls, etc. Conductive connectors 260 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 260 are formed by first forming a solder layer through vapor deposition, electroplating, printing, solder transfer, balling, etc. Once the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape.

[0050] exist Figure 16Next, debonding of the carrier substrate 134 is performed to separate (or “debond”) the carrier substrate 134 from the semiconductor die 150 and the encapsulation 130. According to some embodiments, debonding involves projecting light, such as laser or UV light, onto the release layer 132, causing the release layer 132 to decompose under the heat of the light. The carrier substrate 134 can then be mechanically removed from the integrated chip package 100.

[0051] After the carrier substrate 134 is debonded from the semiconductor die 150 and the encapsulation 130, along the dicing region 202 (e.g., between the first package region 200A and the second package region 200B (previously in...) Figure 15 The diagram shows a sawing process used to perform the separation process. The sawing separates the first package area 200A from the second package area 200B, thereby separating the device stack from each of the first package area 200A and the second package area 200B.

[0052] Further reference Figure 16 The package substrate 270 is coupled to one of a separate device stack from either the first package region 200A or the second package region 200B. The package substrate 270 may include an interposer, a package, a core substrate, a coreless substrate, a printed circuit board (PCB), etc. In an embodiment, the package substrate 270 includes a substrate core 290 and bonding pads 276 above the substrate core 290. The substrate core 290 may be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, and combinations thereof may be used. Additionally, the substrate core 290 may be an SOI substrate. Generally, an SOI substrate includes layers of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, silicon-on-insulator (SOI), silicon germanium on insulator (SGOI), or combinations thereof. In an alternative embodiment, the substrate core 290 is based on an insulating core, such as a fiberglass-reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternatives to the core material include bismaleimide-triazine (BT) resin, or other PCB materials or films. The substrate core 290 can use a laminated film such as an Ajinomoto build-up film (ABF) or other laminated materials.

[0053] The substrate core 290 may include active and passive devices (not shown). Various devices such as transistors, capacitors, resistors, and combinations thereof can be used to generate the structural and functional requirements of the device stack design. The devices can be formed using any suitable method.

[0054] The substrate core 290 may also include a metallization layer and vias (not shown), wherein bonding pads 276 are physically and / or electrically coupled to the metallization layer and vias. The metallization layer may be formed over active and passive devices and is designed to connect different devices to form a functional circuit. The metallization layer may be formed from alternating layers of dielectric material (e.g., a low-k dielectric material) and conductive material (e.g., copper), wherein vias interconnect layers of conductive material and can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In some embodiments, the substrate core 290 is substantially devoid of active and passive devices.

[0055] In some embodiments, conductive connector 260 is reflowed to connect interconnect structure 219 to bonding pad 276. Conductive connector 260 electrically couples and / or physically couples package substrate 270 (including the metallization layer in substrate core 290) to interconnect structure 219. In some embodiments, solder resist 268 is formed on substrate core 290. Conductive connector 260 may be disposed in openings in solder resist 268 for electrical and mechanical coupling to bonding pad 276. Solder resist 268 may be used to protect areas of substrate core 290 from external damage.

[0056] The conductive connector 260 may have an epoxy flux layer (not shown) formed on the interconnect structure 219, which is connected to the package substrate 270, before reflow. After the interconnect structure 219 is connected to the package substrate 270, at least some of the epoxy portion of the epoxy flux remains. The remaining epoxy portion can act as an underfill to reduce stress and protect the contacts created by reflowing the conductive connector 260. In some embodiments, an underfill 280 may be formed between the interconnect structure 219 and the package substrate 270 and around the conductive connector 260. The underfill 280 may be formed by a capillary flow process after the interconnect structure 219 is coupled to the package substrate 270, or it may be formed by a suitable deposition method before the package substrate 270 is coupled to the interconnect structure 219.

[0057] In some embodiments, the package substrate 270 may include bonding pads 282 above the substrate die 290. Conductive connections 284 may be coupled to the bonding pads 282 to allow the package substrate 270 to be electrically coupled to external circuitry or devices. Conductive connections 284 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using an electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. Conductive connections 284 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, solder resist 268 is formed on the substrate die 290, and conductive connections 284 may be disposed in openings in the solder resist 268 to be electrically and mechanically coupled to the bonding pads 282. Solder resist 268 may be used to protect areas of the substrate die 290 from external damage.

[0058] In some embodiments, passive components (e.g., surface mount devices (SMDs), not shown) may also be bonded to the package substrate 270 (e.g., to bonding pads 276). For example, passive components may be bonded to the same surface of the package substrate 270 as the conductive connector 260.

[0059] Figures 17 to 19 A cross-sectional view of an intermediate step during the process for forming an integrated chip package 300 is shown according to an alternative embodiment. Unless otherwise stated, similar reference numerals in this embodiment (and embodiments discussed later) are designated by [reference numerals]. Figures 1 to 16 The similar components in the illustrated embodiments are formed using the same process. Therefore, process steps and applicable materials may not be described again here. The initial steps of this embodiment are similar to... Figures 1 to 11B The basic structure is the same as shown. However, elements such as... Figure 12 The second portion 219b of the interconnect structure is formed above the first portion 219a of the interconnect structure, such that the wafer 20 does not include the second portion 219b of the interconnect structure above the dielectric substrate 242, conductive pad 212 and dielectric substrate 242 of the first portion 219a of the interconnect structure.

[0060] exist Figure 17In this configuration, semiconductor dies 150 are bonded to wafer 20, for example, in a hybrid bonding configuration. Each semiconductor die 150 may also be referred to as a top die. Semiconductor dies 150 are configured face down and bonded to wafer 20 such that the front side of each semiconductor die 150 is bonded to the front side of wafer 20. Semiconductor dies 150 are bonded to the dielectric liner 242 of the first portion 219a of the interconnect structure (previously in...). Figures 7 to 11B (as described in the text) and conductive pad 212 (previously in...) Figures 7 to 11B (As described in the text). For example, the bonding layer 121 of the semiconductor die 150 can be directly bonded to the dielectric substrate 242 of the wafer 20, and the bonding pad 123 of the semiconductor die 150 can be directly bonded to the conductive pad 212 of the wafer 20. In an embodiment, one or more of the bonding pads 123 of the semiconductor die 150 can also be directly bonded to the corresponding conductive pad 258 of the wafer 20. In an embodiment, the bonding between the bonding layer 121 and the dielectric substrate 242 can be oxide-to-oxide bonding, etc. A hybrid bonding process further directly bonds the bonding pads 123 of the semiconductor die 150 to the conductive pads 212 of the wafer 20 via direct metal-to-metal bonding. Therefore, the electrical connection between the semiconductor die 150 and the wafer 20 is provided through the physical connection of the bonding pads 123 to the conductive pads 212.

[0061] As an example, the hybrid bonding process may begin by aligning the semiconductor die 150 to the wafer 20 by surface treatment of one or more of the bonding layers 121 or dielectric liner 242. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. Following the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water or the like) that may be applied to one or more of the bonding layers 121 or dielectric liner 242. The hybrid bonding process may then continue to align the bonding pad 123 to the conductive pad 212. Next, the hybrid bonding includes a pre-bonding step during which the semiconductor die 150 contacts the wafer 20. The pre-bonding may be performed at room temperature (e.g., between about 21°C and about 25°C). Annealing may be performed, for example, at a temperature between about 150°C and about 400°C to continue the hybrid bonding process for a duration between about 0.5 hours and about 3 hours, allowing the metal (e.g., copper) in the bonding pad 123 and the metal (e.g., copper) in the conductive pad 212 to diffuse into each other, thus forming a direct metal-to-metal bond. Although four semiconductor dies 150 are shown bonded to wafer 20, other embodiments may include any number of semiconductor dies 150 bonded to wafer 20. Wafer 20 may include a first package region 200A and a second package region 200B, and one or more integrated chip packages 300 are packaged to form an integrated circuit package in each of package regions 200A and 200B.

[0062] This can be due to the formation of a structure including TSV 211 and interconnect structure 219c (in Figures 17 to 19The wafer 20 (shown in the figure) achieves advantages, wherein each TSV 211 is electrically and physically connected to a corresponding conductive pad 212 in the interconnect structure 219c. Forming the wafer 20 includes an etching process to form an opening 240 extending through dielectric layers 236, 234, 232, and one or more dielectric layers 226. The opening 240 also extends partially through the substrate 217, wherein dielectric layers 236, 234, 232, and one or more dielectric layers 226 are part of the interconnect structure 219c. A dielectric liner 242 is then conformally deposited on the bottom surface and sidewalls in the opening 240, wherein the dielectric liner 242 comprises oxide and has a thickness T1 in the range of 50 nm to 400 nm. A BARC layer 244 is formed over the dielectric liner 242 in the opening 240, wherein the BARC layer 244 fills the opening 240. Next, portions of the BARC layer 244, dielectric substrate 242, dielectric layer 236, and dielectric layer 234 are etched to form openings 252 extending through the dielectric substrate 242, dielectric layer 236, and dielectric layer 234, exposing the top surface of dielectric layer 232. Each opening 252 overlaps and exposes the BARC layer 244, which fills the corresponding remaining portion of the opening 240 extending through dielectric layer 232, one or more dielectric layers 226, and substrate 217. Then, another etching process is performed to remove the remaining portion of the BARC layer 244, resulting in the reforming of the remaining portions of the opening 240 in dielectric layer 232, one or more dielectric layers 226, and the remaining portions of the opening 240 in substrate 217 in each corresponding opening 252. After the remaining portions of the opening 240 are reformed, a barrier layer 254 is simultaneously formed in each opening 252 and its corresponding remaining portion using the same process. After the barrier layer 254 is formed, conductive material is simultaneously formed in the remainder of each opening 252 and its corresponding opening 240 using the same process. The barrier layer 254 and conductive material in the remainder of the opening 240 form a TSV 211, and the barrier layer 254 and conductive material in the opening 252 form a conductive pad 212, wherein each TSV 211 has a width W1, each conductive pad 212 has a width W2, and wherein the width W2 is greater than the width W1. Advantageous features of one or more embodiments disclosed herein allow for the simultaneous formation of each TSV 211 and its corresponding conductive pad 212, such that the process used to form the TSV 211 is also used to form the corresponding conductive pad 212. This reduces the number of process steps required to form the TSV 211 and the corresponding conductive pad 212 (e.g., including metal plating and planarization steps) compared to if forming the TSV 211 and the corresponding conductive pad 212 required to be performed using separate processes at different times. As a result, manufacturing costs can be significantly reduced.Furthermore, using the same process to simultaneously form TSV 211 and the corresponding conductive pad 212 allows for physical contact between TSV 211 and the corresponding conductive pad 212, without the barrier layer 254 being disposed between TSV 211 and the corresponding conductive pad 212. Therefore, the resistivity between TSV 211 and the corresponding conductive pad 212 is reduced, resulting in more efficient conductivity, enhanced device performance, and reduced power consumption.

[0063] exist Figure 18 In, use the same as previously in Figure 14 The encapsulation 130 described herein is formed over the wafer 20 and semiconductor die 150 using similar materials and processes. After the encapsulation 130 is formed, a thinning process is performed on the encapsulation 130 to expose the top surface of the semiconductor die 150. Materials and processes similar to those previously used in [the previous process] can be used. Figure 14 A similar process to that described herein is used to perform a thinning process to reduce the thickness of the encapsulation 130. After the thinning process, the top surface of the semiconductor die 150 may also have a flat surface that is coplanar with the top surface of the encapsulation 130.

[0064] After the thinning process of the encapsulation 130, it is used in the same way as previously... Figure 14 Similar processes and materials described earlier bond the carrier substrate 134 to the top surface of the semiconductor die 150 and the encapsulation 130. For example, as previously described... Figure 14 As described above, a release layer 132 is used to connect a carrier substrate 134 to the top surface of the semiconductor die 150 and the encapsulation 130.

[0065] Further reference Figure 18 A back-side thinning process is performed on wafer 20 (e.g., the exposed surface of substrate 217) to expose TSV 211 and dielectric liner 242. The back-side thinning process of wafer 20 can be performed using planarization processes such as CMP, grinding, or etching. The thinning process can result in the exposed surface of TSV 211 being flush with the surfaces of substrate 217 and dielectric liner 242.

[0066] After performing a thinning process to expose TSV 211, a dielectric layer 327 can be formed on the back side of wafer 20, for example, over the exposed TSV 211, dielectric liner 242, and substrate 217. The dielectric layer 327 may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, spin-coated polymers, silicon-carbon materials, compounds thereof, composites thereof, combinations thereof, etc. The dielectric layer 327 can be deposited by any suitable method, such as CVD, PECVD, spin coating, etc. Figure 18 The patterning of dielectric layer 327 is also shown to form openings exposing TSV211. In embodiments, dielectric layer 327 can be patterned using, for example, laser drilling methods. In such methods, for example, a photothermal conversion (LTHC) layer (not in...) Figure 18 A protective layer (shown separately) is first deposited on dielectric layer 327. Once protected, the laser is directed at the portions of dielectric layer 327 that need to be removed to expose the underlying TSV 211.

[0067] In another embodiment, the dielectric layer 327 can be patterned to form openings exposing the TSV 211 by: first applying photoresist (on...) Figure 18 A patterned energy source (e.g., a patterned light source, not shown separately) is applied to dielectric layer 327, and then the photoresist is exposed to a patterning energy source (e.g., a patterned light source) to initiate a chemical reaction, thereby causing physical changes in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to utilize the physical changes and selectively remove the exposed or unexposed portions of the photoresist according to the desired pattern, and the exposed portions of the underlying dielectric layer 327 are removed using, for example, a dry etching process. However, any other suitable method for patterning dielectric layer 327 can be used to form openings.

[0068] Then, conductive connectors 360 are formed over dielectric layer 327 and in openings within dielectric layer 327. Conductive connectors 360 are electrically coupled to semiconductor die 150 via TSV 211 and conductive pad 212. Conductive connectors 360 may include controlled-collapse chip connection (C4) bumps, ball grid array (BGA) connectors, solder balls, etc. Conductive connectors 360 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or combinations thereof. In some embodiments, conductive connectors 360 are formed by first forming a solder layer through vapor deposition, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer is structurally formed, reflow can be performed to shape the material into the desired bump shape.

[0069] exist Figure 19 Next, debonding of the carrier substrate 134 is performed to separate (or “debond”) the carrier substrate 134 from the semiconductor die 150 and the encapsulation 130. According to some embodiments, debonding involves projecting light, such as laser or UV light, onto the release layer 132, causing the release layer 132 to decompose under the heat of the light. The carrier substrate 134 can then be mechanically removed from the integrated chip package 300.

[0070] After the carrier substrate 134 is debonded from the semiconductor die 150 and the encapsulation 130, along the dicing region 302 (e.g., between the first package region 200A and the second package region 200B (previously in...) Figure 18 The diagram shows a sawing process used to perform the separation process. The sawing separates the first package area 200A from the second package area 200B, thereby separating the device stack from each of the first package area 200A and the second package area 200B.

[0071] Further reference Figure 19 Packaging substrate 270 (previously in Figure 16 (As described in the text) Coupled to one of a separate device stack from either the first package region 200A or the second package region 200B. In some embodiments, conductive connector 360 is reflowed to connect the wafer 20 to the bonding pad 276. Conductive connector 360 electrically and / or physically couples the package substrate 270 (including the metallization layer in the substrate core 290) to the TSV 211 and the conductive pad 212. In some embodiments, solder resist 268 is formed on the substrate core 290. Conductive connector 360 may be disposed in openings in the solder resist 268 to electrically and mechanically couple to the bonding pad 276. Solder resist 268 may be used to protect areas of the substrate core 290 from external damage.

[0072] The conductive connector 360 may have an epoxy flux layer (not shown) formed on it before reflowing the wafer 20 connected to the package substrate 270. After the wafer 20 is connected to the package substrate 270, at least some of the epoxy resin portion of the epoxy flux remains. The remaining epoxy resin portion can act as an underfill to reduce stress and protect the contacts created by reflowing the conductive connector 360. In some embodiments, an underfill 280 may be formed between the wafer 20 and the package substrate 270 and surrounding the conductive connector 360. The underfill 280 may be formed by a capillary process after the wafer 20 is coupled to the package substrate 270, or it may be formed by a suitable deposition method before the package substrate 270 is coupled to the wafer 20.

[0073] The embodiments disclosed herein have several advantageous features. The embodiments include a method for forming a substrate through-hole (TSV) extending through a bottom semiconductor device (e.g., a bottom die). A top semiconductor device (e.g., a top die) is then bonded to a bottom semiconductor device (e.g., a bottom die) to form a vertical stack to provide a three-dimensional integrated chip (3DIC) package. The TSV can be used for signal or power transmission between the bottom semiconductor device and the top semiconductor element. The TSV can be formed as a semiconductor substrate extending through the bottom semiconductor device and can also extend through portions of an interconnect structure formed above the semiconductor substrate. A first metallization layer (e.g., including conductive wiring, conductive pads, or the like) is formed simultaneously with the TSV and disposed in the interconnect structure such that the process used to form the TSV is also used to form the first metallization layer. The first metallization layer and the TSV can comprise similar materials and can be in physical contact with each other, wherein the first metallization layer is used to electrically connect the TSV to other metallization layers, external devices, or other dies disposed in the interconnect structure. As a result, the TSV and the first metallization layer can be formed simultaneously such that the process used to form the TSV is also used to form the first metallization layer. Compared to the number of process steps required if the TSV and the first metallization layer needed to be formed using separate processes at different times, this reduces the number of process steps required to form the TSV and the first metallization layer (e.g., including metal plating and planarization steps). As a result, manufacturing costs can be significantly reduced. Furthermore, forming the TSV and the first metallization layer simultaneously using the same process allows for physical contact between the TSV and the first metallization layer, eliminating the need for a barrier layer between them. Therefore, the resistivity between the TSV and the first metallization layer is reduced, resulting in more efficient conductivity, enhanced device performance, and reduced power consumption.

[0074] According to an embodiment, a method of manufacturing a semiconductor device includes forming a first wafer, wherein forming the first wafer includes forming a plurality of first dielectric layers above a first surface of a semiconductor substrate, the first surface being located on a first side of the semiconductor substrate; depositing a second dielectric layer above the plurality of first dielectric layers; forming a first opening extending through the second dielectric layer and the plurality of first dielectric layers and partially through the semiconductor substrate; filling the first opening with a first bottom anti-reflective coating (BARC) layer; etching a portion of the first BARC layer and the second dielectric layer to form a second opening, wherein the second opening overlaps and exposes a remaining portion of the first BARC layer in the remaining portion of the first opening; removing the first BARC layer; and simultaneously forming a first substrate via (TSV) in the remaining portion of the first opening and forming a first conductive pad in the second opening. In an embodiment, forming the first wafer further includes conformally depositing a dielectric liner on the bottom surface and sidewalls of the first opening before filling the first opening with the first BARC layer. In one embodiment, simultaneously forming a first TSV in the remaining portion of the first opening and a first conductive pad in the second opening includes conformally depositing a barrier layer in the first opening and the second opening using a first process; and depositing a conductive material over the barrier layer in the first opening and the second opening using a second process. In one embodiment, the first TSV has a first width, and the first conductive pad has a second width, the second width being greater than the first width. In one embodiment, the method further includes planarizing a second surface of the semiconductor substrate to expose the first TSV, the second surface being located on a second side of the semiconductor substrate, the second side being located on a side of the semiconductor substrate opposite to the first side. In one embodiment, the method further includes forming a first bonding layer over the exposed first TSV and on the second side of the semiconductor substrate; forming a first bonding pad in the first bonding layer; bonding a first semiconductor die to a first wafer, wherein the bonding includes bonding the first bonding layer to a second bonding layer of the first semiconductor die using direct oxide-to-oxide bonding; and bonding the first bonding pad to the second bonding pad of the first semiconductor die using direct metal-to-metal bonding, wherein the first bonding pad is in physical contact with the first TSV. In one embodiment, forming the first wafer further includes forming a protective ring structure in the plurality of first dielectric layers, wherein the protective ring structure surrounds the first TSV and is in physical contact with the first conductive pad.

[0075] According to an embodiment, a method of manufacturing a semiconductor device includes forming a first wafer, the first wafer including a first interconnect structure over a semiconductor substrate, wherein forming the first wafer includes forming a plurality of first dielectric layers over the semiconductor substrate; depositing a second dielectric layer over the plurality of first dielectric layers; forming a first opening extending through the second dielectric layer, the plurality of first dielectric layers, and partially through the semiconductor substrate; depositing a dielectric liner over the second dielectric layer and on the bottom surface and sidewalls of the first opening; etching portions of the dielectric liner and the second dielectric layer to form a second opening, wherein the second opening overlaps with the remainder of the first opening; and simultaneously forming a first substrate via (TSV) in the remainder of the first opening and forming a first conductive pad in the second opening. In an embodiment, forming the first wafer further includes filling the first opening with a first bottom anti-reflective coating (BARC) layer; etching a top portion of the first BARC layer, wherein after etching the top portion of the first BARC layer and after etching portions of the dielectric liner and the second dielectric layer to form the second opening, the topmost surface of the remaining portion of the first BARC layer in the remainder of the first opening is flush with the bottom surface of the second opening. In an embodiment, forming the first TSV in the remaining portion of the first opening and forming the first conductive pad in the second opening includes removing the remaining portion of the first BARC layer in the remaining portion of the first opening; and depositing conductive material in the second opening and the remaining portion of the first opening. In an embodiment, the first TSV has a first width, and the first conductive pad has a second width, the second width being greater than the first width. In an embodiment, forming the first wafer further includes forming contact pads in the plurality of first dielectric layers; forming a third opening extending through the second dielectric layer and the dielectric substrate; and forming a second conductive pad in the third opening during the simultaneous formation of the first TSV in the remaining portion of the first opening and the formation of the first conductive pad in the second opening, the second conductive pad being electrically connected to the contact pads in the plurality of first dielectric layers. In an embodiment, the method further includes bonding a first semiconductor die to the first wafer, wherein the bonding includes bonding a first bonding layer of the first semiconductor die to the dielectric substrate using direct oxide-to-oxide bonding; and bonding a first bonding pad of the first semiconductor die to the first conductive pad using direct metal-to-metal bonding. In an embodiment, the method further includes forming a guard ring structure in the plurality of first dielectric layers, wherein the guard ring structure surrounds the first TSV, and wherein the guard ring structure is electrically connected to the first conductive pad.

[0076] According to an embodiment, the package includes a first die, the first die including a first interconnect structure on a first side of a first semiconductor substrate, the first interconnect structure including a plurality of first dielectric layers; a second dielectric layer above the plurality of first dielectric layers; a dielectric liner above the second dielectric layer, wherein a first conductive pad is disposed extending through the dielectric liner and the second dielectric layer, and a first substrate through-hole (TSV) is disposed extending through the plurality of first dielectric layers and the first semiconductor substrate, wherein the dielectric liner is also disposed on a sidewall of the first TSV, and wherein the first TSV and the first conductive pad are in physical contact; a second die above the first die and bonded to the first die, the second die including a first bonding layer above the second semiconductor substrate; and a first bonding pad disposed in the first bonding layer, wherein the bonding between the first bonding layer of the second die and the dielectric liner is an oxide-to-oxide bonding, and the bonding between the first bonding pad of the second die and the first conductive pad is a metal-to-metal bonding. In one embodiment, the first conductive pad is disposed above the first TSV, wherein each of the first TSV and the first conductive pad comprises a conductive material; and a barrier layer on the sidewall of the conductive material, wherein the barrier layer is not disposed between the conductive material of the first TSV and the conductive material of the first conductive pad, and wherein the barrier layer is disposed on a portion of the bottom surface of the conductive material of the first conductive pad. In one embodiment, the first width of the first conductive pad is greater than the second width of the first TSV. In one embodiment, the package further includes a package substrate coupled to a second side of the first semiconductor substrate using conductive connectors, wherein the second side is located on the side of the first semiconductor substrate opposite to the first side. In one embodiment, the material of the dielectric liner is different from the material of the second dielectric layer. In one embodiment, the package further includes a guard ring structure disposed in the plurality of first dielectric layers, wherein the guard ring structure surrounds the first TSV, and wherein the guard ring structure is electrically coupled to the first conductive pad.

[0077] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or benefits of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A package, characterized by Comprising: a first die comprising a first interconnect structure on a first side of a first semiconductor substrate, the first interconnect structure comprising: a plurality of first dielectric layers; a second dielectric layer over the plurality of first dielectric layers; a dielectric liner over the second dielectric layer, wherein a first conductive pad is disposed to extend through the dielectric liner and the second dielectric layer, and a first substrate via is disposed to extend through the plurality of first dielectric layers and the first semiconductor substrate, wherein the dielectric liner is further disposed on sidewalls of the first substrate via, and wherein the first substrate via and the first conductive pad are in physical contact; a second die bonded to the first die over the first die, the second die comprising: a first bonding layer over a second semiconductor substrate; and a first bonding pad disposed in the first bonding layer, wherein a bond between the first bonding layer of the second die and the dielectric liner is an oxide-to-oxide bond, and a bond between the first bonding pad of the second die and the first conductive pad is a metal-to-metal bond.

2. The package of claim 1, wherein the first conductive pad is disposed over the first substrate via, wherein each of the first substrate via and the first conductive pad comprises: a conductive material; and a barrier layer on sidewalls of the conductive material, wherein the barrier layer is not disposed between the conductive material of the first substrate via and the conductive material of the first conductive pad, and wherein the barrier layer is disposed on portions of a bottom surface of the conductive material of the first conductive pad.

3. The package of claim 2, wherein a first width of the first conductive pad is greater than a second width of the first substrate via.

4. The package of claim 2, wherein a top surface of the conductive material, a top surface of the barrier layer, and a top surface of the dielectric liner are aligned.

5. The package of claim 2, wherein a thickness of the barrier layer is in a range of 10 nanometers to 50 nanometers.

6. The package of claim 1, further comprising a package substrate coupled to a second side of the first semiconductor substrate using a conductive connection, wherein the second side is on an opposite side of the first semiconductor substrate from the first side.

7. The package of claim 1, wherein a material of the dielectric liner and a material of the second dielectric layer are different.

8. The package of claim 1, further comprising a guard ring structure disposed in the plurality of first dielectric layers, wherein the guard ring structure surrounds the first substrate via, and wherein the guard ring structure is electrically coupled to the first conductive pad.

9. The package of claim 8, wherein the guard ring structure is in physical contact with the first conductive pad.

10. The package of claim 8, wherein the guard ring structure extends vertically through the plurality of first dielectric layers.

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