Integrated pressure sensing chip and integrated pressure sensor

Abstract

The utility model provides an integrated pressure sensing chip and an integrated pressure sensor, and the integrated pressure sensing chip comprises a substrate which is provided with a first surface and a second surface which are opposite to each other, and the first surface is provided with a groove and a through hole which are adjacent to each other; the first covering layer and the second covering layer are arranged on the first surface, the first covering layer is arranged on the groove, and the second covering layer is arranged on the through hole; the first resistive layer is arranged in the first covering layer, and the second resistive layer is arranged in the second covering layer; the isolation layer and the compensation layer are sequentially stacked on the first covering layer and the second covering layer respectively; and the conductive connecting piece penetrates through the compensation layer and the isolation layer and is electrically led out of the first resistance layer and the second resistance layer respectively. The integration level and the application range of the integrated pressure sensor can be improved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to an integrated pressure sensing chip and an integrated pressure sensor. Background Technology

[0002] A pressure sensor is a device that converts external pressure loads into electrical signal outputs. MEMS pressure sensors, fabricated using Microelectromechanical Systems (MEMS) technology, offer advantages such as low cost, small size, high accuracy, and high reliability, and are now widely used in industrial control, automotive, consumer electronics, and the Internet of Things (IoT) industries.

[0003] Based on the pressure reference type, pressure sensors can be further subdivided into absolute pressure, gauge pressure, and differential pressure sensors. Absolute pressure sensors measure absolute pressure relative to a vacuum; gauge pressure sensors use external atmospheric pressure as the pressure reference; and differential pressure sensors characterize the difference between two input pressure loads.

[0004] Existing pressure sensors are basically only applicable to their respective measurement environments (measurement scenarios), which not only hinders integration but also makes pressure testing more expensive in scenarios that require multiple pressure measurements. Utility Model Content

[0005] The purpose of this invention is to provide an integrated pressure sensing chip and an integrated pressure sensor to improve the integration level and application range of integrated pressure sensors.

[0006] To solve the above-mentioned technical problems, the integrated pressure sensing chip provided in this application includes:

[0007] The substrate has a first surface and a second surface opposite to each other, and the first surface has adjacent grooves and through holes;

[0008] A first cover layer and a second cover layer are disposed on the first surface, the first cover layer is disposed on the groove, and the second cover layer is disposed on the through hole;

[0009] A first resistive layer is disposed in the first cover layer, and a second resistive layer is disposed in the second cover layer;

[0010] Each of the isolation layer and the compensation layer is sequentially stacked on the first cover layer and the second cover layer;

[0011] The conductive connectors that penetrate the compensation layer and the isolation layer are electrically led out of the first resistive layer and the second resistive layer, respectively.

[0012] Optionally, a bonding connection layer is further provided between the substrate and the first cover layer and the second cover layer for bonding connection.

[0013] Optionally, the bonding layer exposes a first cover layer corresponding to the groove and covers a second cover layer corresponding to the via.

[0014] Optionally, the bonding layer includes silicon oxide, and the first capping layer and the second capping layer are the top silicon layer of the SOI substrate.

[0015] Optionally, the compensation layer may be made of silicon.

[0016] Optionally, both the first resistive layer and the second resistive layer each include a strain gauge and a wire resistance, wherein the strain gauge and the corresponding wire resistance constitute a Wheatstone bridge.

[0017] Optionally, the isolation layer includes a stacked oxide layer and a nitride layer, wherein the oxide layer covers the first resistive layer and the second resistive layer, and the nitride layer covers the oxide layer.

[0018] Optionally, a groove is provided between the first covering layer, isolation layer and compensation layer on the groove and the second covering layer, isolation layer and compensation layer on the through hole for physical isolation.

[0019] Optionally, the cavity formed by the groove and the first covering layer is a vacuum for absolute pressure sensing, or the cavity formed by the groove and the first covering layer is at atmospheric pressure for gauge pressure sensing.

[0020] Based on another aspect of this application, an integrated pressure sensor is also provided, including the integrated pressure sensing chip as described above.

[0021] In summary, this utility model provides an integrated pressure sensing chip, which includes a substrate having a first surface and a second surface opposite to each other. The first surface has adjacent grooves and through-holes; a first cover layer and a second cover layer disposed on the first surface, the first cover layer being disposed on the grooves and the second cover layer being disposed on the through-holes; a first resistive layer disposed in the first cover layer and a second resistive layer disposed in the second cover layer; an isolation layer and a compensation layer sequentially stacked on the first and second cover layers; and conductive connectors penetrating the compensation layer and the isolation layer, each electrically leading out from the first and second resistive layers. The integrated pressure sensing chip provided in this application integrates differential pressure sensing and absolute pressure sensing (or gauge pressure sensing) into one unit, achieving high integration, reducing chip manufacturing costs, device size, and packaging costs. It also enables the chip to adapt to and be applied to more complex environments and can simultaneously measure differential pressure and absolute pressure (or gauge pressure). In a further embodiment, the relatively close temperature drift between the differential pressure sensing and absolute pressure sensing can be used for mutual calibration, improving the device's performance and reliability. Attached Figure Description

[0022] Those skilled in the art will understand that the accompanying drawings are provided to better understand the present invention and do not constitute any limitation on the present invention. Wherein:

[0023] Figure 1 This is a schematic diagram of the integrated pressure sensing chip provided in an embodiment of this application;

[0024] Figure 2 This is a circuit diagram of a Wheatstone bridge;

[0025] Figure 3 A flowchart illustrating a method for manufacturing an integrated pressure sensing chip according to an embodiment of this application;

[0026] Figures 4A-4G The diagram shows the structural schematic corresponding to the steps of the manufacturing method of the integrated pressure sensor chip provided in the embodiments of this application.

[0027] In the attached figures: 10-substrate; 10a-first surface; 10b-second surface; AA-first region; BB-second region; 13-groove; 15-via; 17-bonding interconnect layer; 20-SOI substrate; 20a-top silicon layer; 20b-buried oxide layer; 20c-substrate silicon layer; 21-first capping layer; 22-first resistive layer; 22a-first strain gauge; 22b-first wire resistance; 23-second capping layer; 24-second resistive layer; 24a-second strain gauge; 24b-second wire resistance; 25-isolation layer; 25a-oxide layer; 25b-nitride layer; 26-compensation layer; 27-conductive connector; 27a-plug; 27b-pad; 28-trench. Detailed Implementation

[0028] To make the objectives, advantages, and features of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may emphasize different aspects and sometimes use different scales.

[0029] It should be understood that when an element or layer is referred to as "on" or "connected to" other elements or layers, it may be directly on or connected to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on" or "directly connected to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this utility model, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. Spatial relation terms such as "below," "under," "below," "above," "on top," "above," etc., may be used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relational terms are intended to also include different orientations of the devices in use and operation. For example, if the devices in the figures are flipped, then elements or features described as “below,” “under,” or “below” will be oriented “on” other elements or features. Devices may be oriented additionally (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly. The terminology used herein is intended only to describe particular embodiments and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “comprising” is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the terms “and / or” include any and all combinations of the associated listed items.

[0030] This application provides an integrated pressure sensing chip.

[0031] Figure 1 This is a schematic diagram of the integrated pressure sensing chip provided in the embodiments of this application.

[0032] like Figure 1 As shown, the integrated pressure sensing chip provided in this application embodiment includes a substrate 10, a groove 13, a through hole 15, a first cover layer 21, a second cover layer 23, a first resistive layer 22, a second resistive layer 24, an isolation layer 25, a compensation layer 26, and a conductive connector 27.

[0033] The substrate 10 can be made of a semiconductor material suitable for bonding processes, such as a silicon substrate (i.e., a silicon wafer). The substrate 10 has adjacent first regions AA and second regions BB, each used to set pressure sensing structures for different application scenarios. Additionally, the substrate 10 also has opposing first surfaces 10a and second surfaces 10b. In this application, the first surface 10a can be, for example, the front side of the substrate 10, used to set the pressure sensing structure, and the second surface 10b can be, for example, the back side of the substrate 10. A groove 13 is provided in the first region AA of the first surface 10a of the substrate 10, and a through-hole 15 is provided in the second region BB of the first surface 10a, penetrating both the first surface 10a and the second surface 10b of the substrate 10.

[0034] Please continue to refer to Figure 1 The first cover layer 21 is disposed on the first region AA of the first surface 10a and covers the groove 13, forming a closed cavity with the groove 13. The second cover layer 23 is disposed on the second region BB of the first surface 10a and covers the through hole 15, forming a semi-closed cavity with the through hole 15. The first cover layer 21 and the second cover layer 23 are made of the same material, but the thickness of the first cover layer 21 and the second cover layer 23 can be determined according to their respective measurement ranges. In other words, the second cover layer 23 is disposed in the same layer as the first cover layer 21, but their thicknesses can be the same or different. A bonding connection layer 17 is also provided between the first surface 10a of the substrate 10 and the first cover layer 21 and the second cover layer 23 for bonding the substrate 10 and the first cover layer 21 and the second cover layer 23. The first cover layer 21 and the second cover layer 23 can be made of silicon, such as the top silicon layer of an SOI substrate. The bonding layer 17 is made of silicon oxide. In addition to the area where the substrate 10 contacts the first cover layer 21 and the second cover layer 23, the bonding layer 17 also covers the surface of the second cover layer 23 corresponding to the via 15 (i.e., the second cover layer 23 above the via 15) to protect the second cover layer 23 and the surface of the first cover layer 21 corresponding to the exposed groove 13 (i.e., above). That is, the surface of the first cover layer 21 is exposed in the cavity.

[0035] In some examples of this application, the cavity formed by the groove 13 and the first covering layer 21 can be a vacuum, i.e., used for absolute pressure sensing. In some examples of this application, the cavity formed by the groove 13 and the first covering layer 21 can be at atmospheric pressure, i.e., used for gauge pressure sensing.

[0036] Please continue to refer to Figure 1 A first resistive layer 22 is provided in the first covering layer 21 above the groove 13, and a second resistive layer 24 is provided in the second covering layer 23 above the through hole 15. These layers are used to convert the strain of the first covering layer 21 and the second covering layer 23 under pressure into their respective resistance changes. The first resistive layer 22 includes a first strain gauge resistor 22a and a first wire resistor 22b, and the second resistive layer 24 includes a second strain gauge resistor 24a and a second wire resistor 24b. The strain gauge resistors and their corresponding wire resistors constitute a Wheatstone bridge (see [link to Wheatstone bridge principle]). Figure 2 The aforementioned strain gauges and wire resistors can both be doped regions in the first capping layer 21 and the second capping layer 23 using ion implantation. The doping concentration of the strain gauges is lower than that of the corresponding wire resistors, and the shape, size, and doping concentration of the strain gauges in the first capping layer 21 and the second capping layer 23 can be reasonably set according to actual needs. In some examples of this application, the Wheatstone bridge in the first region AA or the second region BB has a (e.g., Figure 2 R1 in the middle) or both (e.g., R1) Figure 2 The strain gauges R1 and R2 are located above the groove 13 or through hole 15, while the remaining resistors of the Wheatstone bridge are located outside the groove 13 or through hole 15 as fixed resistors, thus forming a single-arm Wheatstone bridge or a half-bridge Wheatstone bridge. In some other examples of this application, the Wheatstone bridge in the first region AA or the second region BB has four (e.g., Figure 2 The strain gauges R1, R2, R3 and R4 are located above the groove 13 or through hole 15, which constitutes a full-bridge Wheatstone bridge.

[0037] Please continue to refer to Figure 1 An isolation layer 25 and a compensation layer 26 are sequentially stacked on the capping layers of the first region AA and the second region BB, that is, an isolation layer 25 and a compensation layer 26 are sequentially stacked on the first capping layer 21 and the second capping layer 23, respectively. The isolation layer 25 may include several insulating dielectric layers for providing electrical isolation and protection. The compensation layer 26 is used to compensate for the stress of the isolation layer 25 relative to the capping layers (including the first capping layer 21 and the second capping layer 23). The material of the compensation layer 26 may be the same as or similar to the material of the capping layers. In this application, the isolation layer 25 may include a stacked oxide layer 25a and a nitride layer 25b. The oxide layer 25a covers the first resistive layer 22 and the second resistive layer 24, the nitride layer 25b covers the oxide layer 25a, and the compensation layer 26 may be a polysilicon layer.

[0038] In this application, Figure 1In the example shown, a groove 28 is provided between the first cover layer 21, the isolation layer 25, and the compensation layer 26 on the groove 13 and the second cover layer 23, the isolation layer 25, and the compensation layer 26 on the through hole 15 for physical isolation. This avoids mutual interference between the film layer above the groove 13 and the film layer above the through hole 15, while maintaining a small gap between the groove 13 and the through hole 15. In other examples, a groove may not be provided between the film layer above the groove 13 and the film layer above the through hole 15, provided a larger gap is maintained between the groove 13 and the through hole 15.

[0039] Please continue to refer to Figure 1 Each of the first region AA and the second region BB is provided with a plurality of conductive connectors 27. The conductive connectors 27 penetrate the compensation layer 26 and the isolation layer 25, and each electrically leads out the first resistance layer 22 and the second resistance layer 24. Each conductive connector 27 may include a plug 27a and a pad 27b. The plug 27a is located in the compensation layer 26 and the isolation layer 25, and is resistively connected to the wires in the first resistance layer 22 and the second resistance layer 24. The pad 27b is located on the surface of the compensation layer 26 and is connected to the plug 27a.

[0040] This application also provides a method for manufacturing an integrated pressure sensing chip, used to manufacture the aforementioned integrated pressure sensing chip.

[0041] Figure 3 This is a flowchart illustrating a method for manufacturing an integrated pressure sensing chip according to an embodiment of this application.

[0042] like Figure 3 As shown in the embodiments of this application, the manufacturing method of the integrated pressure sensing chip includes:

[0043] S01: Provide a substrate, the substrate including adjacent first and second regions;

[0044] S02: A bonding connection layer is formed to cover the front side of the substrate, and a groove is formed in the first region of the substrate;

[0045] S03: Provide an SOI substrate and bond the top silicon layer of the SOI substrate to the bonding connection layer of the substrate;

[0046] S04: Remove the substrate silicon layer and buried oxide layer of the SOI substrate to expose the top silicon layer;

[0047] S05: A first resistive layer is formed in the top silicon layer of the first region, and a second resistive layer is formed in the top silicon layer of the second region;

[0048] S06: An isolation layer, a compensation layer and a conductive connector are sequentially formed on the top silicon layer. The conductive connector penetrates the compensation layer and the isolation layer and is electrically led out of the first resistive layer and the second resistive layer, respectively.

[0049] S07: The substrate of the second region is etched from the back side of the substrate to form a through-hole through the substrate to expose the bonding connection layer of the top silicon layer.

[0050] Figures 4A-4G This is a schematic diagram of the structure corresponding to the steps of the manufacturing method of the integrated pressure sensing chip provided in the embodiments of this application. The following will be combined with Figures 4A-4G This embodiment describes in detail the manufacturing method of the integrated pressure sensing chip.

[0051] First, please refer to Figure 4A Step S01 is executed, providing a substrate 10, which includes adjacent first region AA and second region BB. The substrate 10 may be made of silicon, i.e., a silicon substrate.

[0052] Next, please refer to Figure 4B In step S02, a bonding connection layer 17 is formed to cover the front side (first side 10a) of the substrate 10, and a groove 13 is formed in the first region AA of the substrate 10. The bonding connection layer 17 may be made of silicon oxide and may be formed using furnace tube process or CVD process. After forming a photoresist layer on the front side of the substrate 10, a groove 13 is formed in the first region AA of the front side of the substrate 10 using photolithography and etching processes. The remaining photoresist layer is removed to expose the bonding connection layer 17. The bonding connection layer 17 covers the surface of the first region AA and the second region BB, excluding the groove 13.

[0053] Next, please refer to Figure 4C In step S03, an SOI substrate 20 is provided, and the top silicon layer 20a of the SOI substrate 20 is bonded to the bonding layer 17 of the substrate 10.

[0054] Next, please refer to Figure 4D In step S04, the substrate silicon layer 20c and buried oxide layer 20b of the SOI substrate 20 are removed to expose the top silicon layer 20a. The substrate silicon layer 20c and buried oxide layer 20b of the SOI substrate 20 can be removed sequentially by a polishing process, and the top silicon layer 20a of the first region AA is used as the first capping layer 21, and the top silicon layer 20a of the second region BB is used as the second capping layer 23.

[0055] Next, please refer to Figure 4EIn step S05, a first resistive layer 22 is formed in the top silicon layer 20a (i.e., the first capping layer 21) of the first region AA, and a second resistive layer 24 is formed in the top silicon layer 20a (i.e., the second capping layer 23) of the second region BB. The strain resistance and wire resistance in the first resistive layer 22 and the second resistive layer 24 can be formed using an ion implantation process. Of course, in some examples, the first resistive layer 22 and the second resistive layer 24 may also include a fixed resistor formed using an ion implantation process. The fixed resistor is located outside the groove 13 and the via 15, and its resistance does not change with pressure.

[0056] Next, please refer to Figure 4F In step S06, an isolation layer 25, a compensation layer 26, and a conductive connector 27 are sequentially formed on the top silicon layer 20a. The conductive connector 27 penetrates the compensation layer 26 and the isolation layer 25, and electrically leads out the first resistive layer 22 and the second resistive layer 24, respectively. The structure and material of the isolation layer 25, the compensation layer 26, and the conductive connector 27 can be referred to the foregoing. After forming the isolation layer 25, the compensation layer 26, and the conductive connector 27, a trench 28 can also be formed between the first region AA and the second region BB. This trench 28 can, for example, penetrate the isolation layer 25, the compensation layer 26, and the top silicon layer 20a to prevent mutual interference between the first region AA and the second region BB.

[0057] Next, please refer to Figure 4G In step S07, the second region BB of the substrate 10 is etched from the back side of the substrate 10 to form a through-hole 15 that exposes the bonding connection layer 17 of the top silicon layer 20a.

[0058] As can be seen from the above chip structure and manufacturing method, the integrated pressure sensor chip provided in this application integrates differential pressure sensing and absolute pressure sensing (or gauge pressure sensing) into one unit, achieving a high degree of integration. This reduces chip manufacturing costs, device size, and packaging costs, and also enables it to adapt to and be applied to more complex environments, while simultaneously measuring differential pressure and absolute pressure (or gauge pressure). In a further embodiment, the relatively close temperature drift between the differential pressure sensor and the absolute pressure sensor can be used for mutual calibration, improving the device's performance and reliability.

[0059] This application also provides an integrated pressure sensor, which includes the integrated pressure sensing chip as described above.

[0060] In summary, this utility model provides an integrated pressure sensing chip, which includes a substrate having a first surface and a second surface opposite to each other. The first surface has adjacent grooves and through-holes; a first cover layer and a second cover layer disposed on the first surface, the first cover layer being disposed on the grooves and the second cover layer being disposed on the through-holes; a first resistive layer disposed in the first cover layer and a second resistive layer disposed in the second cover layer; an isolation layer and a compensation layer sequentially stacked on the first and second cover layers; and conductive connectors penetrating the compensation layer and the isolation layer, each electrically leading out from the first and second resistive layers. The integrated pressure sensing chip provided in this application integrates differential pressure sensing and absolute pressure sensing (or gauge pressure sensing) into one unit, achieving high integration, reducing chip manufacturing costs, device size, and packaging costs. It also enables the chip to adapt to and be applied to more complex environments and can simultaneously measure differential pressure and absolute pressure (or gauge pressure). In a further embodiment, the relatively close temperature drift between the differential pressure sensing and absolute pressure sensing can be used for mutual calibration, improving the device's performance and reliability.

[0061] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An integrated pressure sensing chip, characterized by, The integrated pressure sensor chip comprises: a substrate having opposite first and second surfaces, the first surface being provided with adjacent recesses and through holes; first and second cover layers provided on the first surface, the first cover layer being provided on the recesses and the second cover layer being provided on the through holes; a first resistance layer provided in the first cover layer and a second resistance layer provided in the second cover layer; an isolation layer and a compensation layer each being sequentially stacked on the first and second cover layers; conductive connecting members penetrating through the compensation layer and the isolation layer and each electrically leading out the first and second resistance layers.

2. The integrated pressure sensing die of claim 1, wherein, A bonding connection layer is further provided between the substrate and the first and second cover layers for bonding connection.

3. The integrated pressure sensing die of claim 2, wherein, The bonding connection layer exposes the first cover layer corresponding to the recesses and covers the second cover layer corresponding to the through holes.

4. The integrated pressure sensing die of claim 2, wherein, The bonding connection layer comprises silicon oxide, and the first and second cover layers are top silicon layers of an SOI substrate.

5. The integrated pressure sensing die of claim 4, wherein, The compensation layer comprises a silicon layer.

6. The integrated pressure sensing die of claim 1, wherein, The first and second resistance layers each comprise a strain resistance and a wire resistance, and the strain resistance and the corresponding wire resistance form a Wheatstone bridge.

7. The integrated pressure sensing die of claim 1, wherein, The isolation layer comprises stacked oxide and nitride layers, the oxide layer covering the first and second resistance layers, and the nitride layer covering the oxide layer.

8. The integrated pressure sensing die of claim 1, wherein, A groove is provided between the first cover layer, the isolation layer and the compensation layer on the recesses and the second cover layer, the isolation layer and the compensation layer on the through holes for physical isolation.

9. The integrated pressure sensing die of claim 1, wherein, The cavity formed by the recesses and the first cover layer is a vacuum for absolute pressure sensing, or the cavity formed by the recesses and the first cover layer is at atmospheric pressure for gauge pressure sensing.

10. An integrated pressure sensor, characterized by The integrated pressure sensor chip comprises any one of claims 1 to 9.

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