Multi-bit flipping resistant storage architecture for aerospace application SoC (System on Chip) system
By introducing a hierarchical storage structure and encoding/decoding technology into the SoC system, the problem of insufficient resistance to multi-bit flipping in the space radiation environment of the SoC system is solved, thereby improving the reliability and performance of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-04
- Publication Date
- 2026-03-10
AI Technical Summary
Existing SoC systems lack sufficient resistance to multi-bit flip-flops in space radiation environments, and existing ruggedization designs fail to effectively consider the hierarchical structure characteristics of memory cells, resulting in significant performance impact.
It adopts a hierarchical storage structure, including cache units, memory units and flash memory units, and achieves the correction of multi-bit flip errors through data backup and encoding/decoding technology between different levels.
It improves the SoC system's resistance to multiple bit flips, reduces the negative impact on system performance, and enhances the reliability of the storage architecture.
Smart Images
Figure CN223986320U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of memory and SoC, and particularly relates to an anti-multiple-bit-upset memory architecture for a SoC system for spaceflight application. BACKGROUND
[0002] Integrated circuits applied in a space radiation environment need to cope with single event effects caused by high-energy radiation particles, and in order to meet the requirements of complex spaceflight tasks on a satellite-borne processor, a satellite-borne SoC system needs to implement the calculation and storage of a large amount of data, most of the area of the SoC system is occupied by memory units, and the area ratio of the memory is more than 50%, the reliability of the memory directly affects the reliability of the entire SoC system and has an important influence on whether the entire system can correctly implement functions.
[0003] A single particle radiation event can cause a memory unit to flip and produce a soft error, according to the number of memory unit flips, single-bit upset (SBU) and multiple cell upset (MCU) can be divided into single-bit upset (SBU) and multiple cell upset (MCU). With the development of process and the reduction of transistor feature size to nanometer scale, the proportion of multiple-bit upset (MBU) phenomenon of multiple sensitive nodes in the circuit affected by high-energy particles is increasing, which poses new challenges to the hardening design of the satellite-borne SoC memory architecture. At present, the anti-MBU hardening design of the SoC memory is to harden the memory alone, although the anti-MBU capability of a certain memory unit is improved, the hierarchical structure characteristics of the memory units in the SoC are not considered, and the hardening circuit introduced has a certain influence on the performance of the entire SoC memory architecture. CONTENT OF THE UTILITY MODEL
[0004] In order to solve the above-mentioned deficiencies of the related prior art, the application provides an anti-multiple-bit-upset memory architecture for a SoC system for spaceflight application, which realizes hardening by using a hierarchical memory structure and different memory unit characteristics, and corrects MBU errors by mutual backup of data in different levels, improves the anti-MBU capability of the memory architecture of the SoC system and reduces the performance influence.
[0005] In order to achieve the above-mentioned purpose, the utility model adopts the following technology:
[0006] An anti-multiple-bit-upset memory architecture for a SoC system for spaceflight application, comprising:
[0007] A cache unit connected with a CPU of the SoC system and used for caching data;
[0008] The memory unit is connected with the cache unit and the CPU of the SoC system, and is used for backing up the data in the cache unit.
[0009] The flash memory unit is connected with the memory unit, the cache unit and the CPU of the SoC system, and is used for backing up the data in the memory unit.
[0010] Further, the cache unit comprises a cache chip, a register, a first encoder and a first decoder, the cache chip is connected with the memory unit through the register, and is connected with the CPU of the SoC system through the first encoder and the first decoder.
[0011] Further, the cache unit further comprises a counter, the first decoder is connected with the counter, and the counter is connected with the cache chip.
[0012] Further, the memory unit comprises a memory chip, a second encoder and a second decoder, the memory chip is connected with the first encoder through the second decoder and is connected with the first decoder through the second encoder.
[0013] Further, the flash memory unit comprises a flash memory chip, a third encoder and a third decoder, the flash memory chip is connected with the second decoder through the third encoder and is connected with the second encoder through the third decoder.
[0014] The utility model has the advantages that:
[0015] By setting three levels of storage, the anti-multiple bit flipping is realized by mutual backup of data in different levels, the MBU error can be corrected and recovered through the backup mode, the anti-MBU capability of the storage architecture of the SoC system is improved, and the performance influence is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 It is the anti-multiple bit flipping storage architecture structure schematic diagram of the embodiment of the application. DETAILED DESCRIPTION
[0017] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model more clear, the embodiments of the utility model are described in detail below in combination with the drawings, but the embodiments described in the utility model are part of the embodiments of the utility model, not all the embodiments.
[0018] The embodiment of the application provides an anti-multiple bit flipping storage architecture for a SoC system for space application, as shown in the figure, comprising a cache unit, a memory unit, a flash memory unit and the like. Figure 1
[0019] The cache unit is connected with a CPU of the SoC system and is used for caching data; the memory unit is connected with the cache unit and the CPU of the SoC system and is used for backup storage of data in the cache unit; and the flash memory unit is connected with the memory unit, the cache unit and the CPU of the SoC system and is used for backup storage of data in the memory unit.
[0020] Specifically, the cache unit comprises a cache chip, a register, a first encoder and a first decoder, the cache chip is SRAM, the cache chip is connected with the memory unit through the register and is connected with the CPU of the SoC system through the first encoder and the first decoder.
[0021] The memory unit comprises a memory chip, a second encoder and a second decoder, the memory chip is DRAM, the memory chip is connected with the first encoder through the second decoder and is connected with the first decoder through the second encoder.
[0022] The flash memory unit comprises a flash memory chip, a third encoder and a third decoder, the flash memory chip is FLASH, the flash memory chip is connected with the second decoder through the third encoder and is connected with the second encoder through the third decoder.
[0023] The cache unit, the memory unit and the flash memory unit are integrated in the SoC system, the distance between the position of the cache unit and the position of the CPU is less than the distance between the position of the memory unit and the position of the CPU, and the distance between the position of the memory unit and the position of the CPU is less than the distance between the position of the flash memory unit and the position of the CPU.
[0024] The cache unit is the storage unit closest to the CPU, and is used to cache data for fast access by the CPU, solving the problem of delay. In order to solve the problem of MBU, the data cached in the cache chip is backed up to the lower level storage, i.e. to the memory chip of the memory unit, which can be used for recovery when data error occurs. When the data cached in the cache chip of the cache unit is incorrect, the CPU can access the correct data by accessing the memory unit. The first encoder and the first decoder are used to encode and decode the data entering and exiting the cache chip, so as to protect the data. Preferably, the way of interleaved parity check code can be used to detect the flip error. When the flip occurs, the check code changes, and the error can be detected. 32 bits of data use interleaved parity check code, and any continuous error less than 8 bits will be detected. In order to prevent the phenomenon of a large number of access misses when accessing the cache unit due to the occurrence of MBU, the cache unit in the embodiment adopts a non-blocking design, i.e. connecting the memory unit through the register MSHR (Miss State Handle Register), and realizing the temporary storage and unified processing of the missing data request through the register MSHR, so as to reduce the access delay caused by accessing the memory unit Memory due to access miss. In some optional embodiments, the register, the first encoder and the first decoder are integrated in the cache chip or the cache controller, the cache controller is integrated in the SoC system as a part of the cache unit, and is arranged close to the CPU.
[0025] Preferably, the cache unit further comprises a counter, the first decoder is connected to the counter, and the counter is connected to the cache chip. The counter is used to count when the first decoder detects an error during decoding, and when the counting operation reaches a preset number of times, the system background can perform a refresh operation on the cache chip, so as to improve the reliability of the cache unit. As an optional implementation example, the counter is integrated in the cache chip or the cache controller.
[0026] The memory unit is an intermediate level in the storage architecture, and is a backup of the data in the cache unit. The access speed of the memory unit is slower than that of the cache unit, but the data storage capacity of the memory unit is larger than that of the cache unit. In order to improve the error correction capability of the data in the memory unit, the data in the memory unit also exists in the flash memory unit. When the data in the memory unit is incorrect, the correct data can be obtained by accessing the flash memory unit to realize recovery. The second encoder and the second decoder are used to encode and decode the data entering and exiting the memory chip, so as to protect the data. Preferably, the LRRO-BCH code capable of correcting two and detecting three can be used to protect the data in the memory, wherein the LRRO (Low Redundancy and Reduced Overhead encoding) is used as an outer code, which is responsible for providing flexible code rate compatibility and reducing redundancy overhead; the BCH (Bose-Chaudhuri-Hocquenghem encoding) is used as an inner code, which is a classic linear block code with strong error correction capability. In some optional embodiments, the second encoder and the second decoder are integrated in the memory chip or in the memory controller, and the memory controller is integrated in the SoC system as part of the memory unit.
[0027] The flash memory unit is the last level in the storage architecture, and has the lowest access speed requirement and the highest storage capacity. The flash memory unit is also the basic source of data in the cache unit and the memory unit. The floating gate structure of the flash memory itself can reduce the influence of single event effects, that is, only when the stored data is "0" can there be a relatively high probability of flipping. The third encoder and the third decoder are used to encode and decode the data entering and exiting the flash memory chip, so as to protect the data. Preferably, the Hsiao code capable of correcting one and detecting two is used to protect the data in the flash memory unit. In some optional embodiments, the third encoder and the third decoder are integrated in the flash memory chip or in the flash memory controller, and the flash memory controller is integrated in the SoC system as part of the flash memory unit.
[0028] The above only describes the preferred embodiments of the present application, and is not used to limit the present application. Obviously, those skilled in the art can make various modifications and changes to the present application without departing from the spirit and scope of the present application.
Claims
1. A multi-bit flip resistant memory architecture for space application oriented SoC systems, characterized in that, The application relates to a cache unit, a memory unit and a flash memory unit connected with a CPU of an SoC system. The cache unit is connected with the memory unit and the CPU of the SoC system, and is used for caching data. The memory unit is connected with the cache unit and the CPU of the SoC system, and is used for backing up and storing the data in the cache unit. The flash memory unit is connected with the memory unit, the cache unit and the CPU of the SoC system, and is used for backing up and storing the data in the memory unit.
2. The space application oriented SoC system's anti-multi-bit-flip memory architecture of claim 1, wherein, The cache unit comprises a cache chip, a register, a first encoder and a first decoder, the cache chip is connected with the memory unit through the register, and is connected with the CPU of the SoC system through the first encoder and the first decoder.
3. The anti-multi-bit-flip memory architecture for a space application oriented SoC system of claim 2, wherein, The cache chip adopts SRAM.
4. The anti-multi-bit-flip memory architecture for a space application oriented SoC system of claim 2, wherein, The memory unit comprises a memory chip, a second encoder and a second decoder, the memory chip is connected with the first encoder through the second decoder, and is connected with the first decoder through the second encoder.
5. The anti-multi-bit-flip memory architecture for a space application oriented SoC system of claim 4, wherein, The memory chip adopts DRAM.
6. The anti-multi-bit-flip memory architecture for a space application oriented SoC system of claim 4, wherein, The flash memory unit comprises a flash memory chip, a third encoder and a third decoder, the flash memory chip is connected with the second decoder through the third encoder, and is connected with the second encoder through the third decoder.
7. The anti-multi-bit-flip memory architecture for a space application oriented SoC system of claim 6, wherein, The flash memory chip adopts FLASH.
8. The anti-multi-bit-flip memory architecture for a space application oriented SoC system of claim 2, wherein, The cache unit further comprises a counter, the first decoder is connected with the counter, and the counter is connected with the cache chip.