MOS tube series control circuit, electronic load and electronic equipment

Abstract

The utility model discloses an MOS tube series control circuit, an electronic load and electronic equipment, and the circuit comprises an MOS tube unit which comprises a first MOS tube and at least one second MOS tube connected in series with the first MOS tube; a control unit; the at least one voltage-sharing unit corresponds to the second MOS tube, and the voltage-sharing unit comprises a high-potential end, a low-potential end, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor. According to the invention, the source and drain voltages of the MOS transistors connected in series are equal, the loop response speed of the electronic load is improved, and the stability of bearing high voltage input is improved.

Description

Technical Field

[0001] This application relates to the field of power supply testing, and in particular to a MOSFET series control circuit, an electronic load, and an electronic device. Background Technology

[0002] In related technologies, high-voltage input is carried out in electronic loads by connecting MOSFETs in series. For example, two or more MOSFETs with a conventional rated voltage of 1500V are connected in series to carry an input voltage of 2400V or higher.

[0003] However, while connecting MOSFETs in series can achieve higher input voltages, in practical applications, the uneven source-drain voltages of each MOSFET result in slow loop response and oscillations at high voltages.

[0004] In summary, the existing series connection of MOSFETs prevents electronic loads from quickly establishing a closed control loop and results in poor stability when carrying high voltage inputs. Utility Model Content

[0005] This application proposes a MOSFET series control circuit, an electronic load, and an electronic device, which can achieve equal source and drain voltages of the MOSFETs after series connection, improve the loop response speed of the electronic load, and enhance stability when carrying high voltage input.

[0006] A MOSFET series control circuit according to an embodiment of the first aspect of this application includes: a MOSFET unit, the MOSFET unit including a first MOSFET and at least one second MOSFET connected in series with the first MOSFET; a control unit, the control unit being connected to the gate of the first MOSFET to control the conduction state of the first MOSFET; a power supply terminal, the power supply terminal being connected to the input terminal of the second MOSFET, and the output terminal of the first MOSFET being grounded; at least one voltage equalization unit, the voltage equalization unit corresponding to the second MOSFET, the voltage equalization unit including a high potential terminal, a low potential terminal, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, the gate of the second MOSFET being connected to the low potential terminal through the first resistor and the first capacitor connected in parallel, the gate of the second MOSFET being connected to the high potential terminal through the second resistor and the second capacitor connected in parallel, the drain of the second MOSFET being connected to the source of the second MOSFET through the third capacitor, the gate of the second MOSFET being connected to the source of the second MOSFET through the fourth capacitor, and the drain of the second MOSFET being connected to the high potential terminal; and a fifth capacitor, the drain of the first MOSFET being connected to the source of the first MOSFET through the fifth capacitor.

[0007] According to some embodiments of this application, the voltage equalization unit further includes a clamping transistor, and the gate of the second MOS transistor is connected to the source of the second MOS transistor through the clamping transistor.

[0008] According to some embodiments of this application, the clamping transistor includes a first transistor and a second transistor. The gate of the second transistor is connected to the base and collector of the second transistor, the emitter of the second transistor is connected to the emitter of the first transistor, and the source of the second transistor is connected to the base and collector of the first transistor.

[0009] According to some embodiments of this application, the control unit includes an MCU, a DAC module, a single-ended to differential circuit, an error amplifier, and a current sampling resistor. The signal output terminal of the MCU is connected to the input terminal of the DAC module, the output terminal of the DAC module is connected to the input terminal of the single-ended to differential circuit, the output terminal of the single-ended to differential circuit is connected to the non-inverting and inverting inputs of the error amplifier, the output terminal of the error amplifier is connected to the gate of the first MOS transistor, the source of the first MOS transistor is grounded through the current sampling resistor, and the two ends of the current sampling resistor are connected to the non-inverting and inverting inputs of the error amplifier, respectively.

[0010] According to some embodiments of this application, a fuse is connected in series with the drain of the first MOS transistor.

[0011] The electronic load according to the second aspect of this application includes the above-described MOS transistor series control circuit.

[0012] An electronic device according to a third aspect of this application includes the above-described MOS transistor series control circuit.

[0013] The MOSFET series control circuit, electronic load, and electronic device according to the embodiments of this application have at least the following beneficial effects:

[0014] In this embodiment, the conduction state of the first MOSFET is controlled by a control unit. A fifth capacitor is placed between the drain and source of the first MOSFET to suppress high-frequency signals between the drain and source, preventing oscillation. A voltage equalization unit is provided for each second MOSFET, and a third capacitor is placed between the drain and source of the second MOSFET to suppress high-frequency signals between the drain and source, preventing oscillation. A voltage divider network is formed by a first resistor and a second resistor of equal resistance, ensuring that the voltage between the gate and source, and between the gate and drain of the second MOSFET are equal. A first capacitor and a second capacitor are connected in parallel across the first and second resistors respectively to achieve AC voltage division, preventing sudden voltage changes across the first and second resistors during dynamic changes, thus allowing the dynamic voltages across them to quickly become equal. This application uses a voltage equalization unit to synchronize the conduction levels of the second and first MOSFETs during dynamic closing control, thus achieving equal source and drain voltages for the series-connected MOSFETs, improving the loop response speed of the electronic load, and enhancing stability when carrying high-voltage inputs.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0017] Figure 1 This is a circuit diagram of two MOS transistors connected in series in an embodiment of this application;

[0018] Figure 2 This is a circuit diagram of three MOS transistors connected in series in an embodiment of this application. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] In the description of this application, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0021] In the description of this application, "multiple" refers to two or more. The use of "first" and "second" is for the purpose of distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or the order in which the technical features are indicated.

[0022] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0023] Reference Figure 1 As shown, a MOSFET series control circuit includes: a MOSFET unit, a control unit, a power supply terminal VBUS, at least one voltage equalization unit, and a fifth capacitor. The MOSFET unit includes a first MOSFET and at least one second MOSFET connected in series with the first MOSFET. When there are multiple second MOSFETs, they are connected in series sequentially. The control unit is connected to the gate of the first MOSFET to control its conduction state. The power supply terminal VBUS is connected to the input terminal of the second MOSFET, and the output terminal of the first MOSFET is grounded. The voltage equalization unit corresponds to the second MOSFET. The voltage equalization unit includes a high-potential terminal, a low-potential terminal, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The gate of the second MOSFET is connected to the low-potential terminal via the first resistor and the first capacitor connected in parallel. The gate of the second MOSFET is connected to the high-potential terminal via the second resistor and the second capacitor connected in parallel. The drain of the second MOSFET is connected to the source of the second MOSFET via the third capacitor. The gate of the second MOSFET is connected to the source of the second MOSFET via the fourth capacitor. The drain of the second MOSFET is connected to the high-potential terminal. The resistance values ​​of the first resistor and the second resistor are equal. The fifth capacitor connects the drain of the first MOSFET to the source of the first MOSFET.

[0024] In this embodiment, the conduction state of the first MOSFET is controlled by a control unit. A fifth capacitor is placed between the drain and source of the first MOSFET to suppress high-frequency signals between the drain and source, preventing oscillation. A voltage equalization unit is provided for each second MOSFET, and a third capacitor is placed between the drain and source of the second MOSFET to suppress high-frequency signals between the drain and source, preventing oscillation. A voltage divider network is formed by a first resistor and a second resistor of equal resistance, ensuring that the voltage between the gate and source, and between the gate and drain of the second MOSFET are equal. A first capacitor and a second capacitor are connected in parallel across the first and second resistors respectively to achieve AC voltage division, preventing sudden voltage changes across the first and second resistors during dynamic changes, thus allowing the dynamic voltages across them to quickly become equal. This application uses a voltage equalization unit to synchronize the conduction levels of the second and first MOSFETs during dynamic closing control, thus achieving equal source and drain voltages for the series-connected MOSFETs, improving the loop response speed of the electronic load, and enhancing stability when carrying high-voltage inputs.

[0025] In this embodiment, there can be one or more second MOSFETs. When there is only one second MOSFET, i.e., one second MOSFET connected in series with the first MOSFET, the drain of the second MOSFET is connected to the power supply terminal VCC, and the source of the second MOSFET is connected to the drain of the first MOSFET. When there are multiple second MOSFETs, the drain of one second MOSFET is connected to the power supply terminal VCC, and the source of the other second MOSFET is connected to the drain of the first MOSFET.

[0026] In this embodiment, the number of voltage equalization units corresponds one-to-one with the number of second MOSFETs. When there is only one second MOSFET, the high-potential terminal in the voltage equalization unit is the power supply terminal VBUS, and the low-potential terminal is the ground terminal. When there are multiple second MOSFETs, the high-potential terminal in the voltage equalization unit corresponding to the second MOSFET connected to the first MOSFET is the drain of the current second MOSFET, and the low-potential terminal is the ground terminal. In the remaining voltage equalization units, the high-potential terminal in the voltage equalization unit corresponding to the second MOSFET is the drain of the current second MOSFET, and the low-potential terminal is the source of the current second MOSFET. It should be understood that the high-potential terminal and low-potential terminal in this application are only relative concepts within the voltage equalization unit, and the low-potential terminal and high-potential terminal are not the same in different voltage equalization units.

[0027] In some embodiments of this application, the voltage equalization unit further includes a clamping transistor, and the gate of the second MOS transistor is connected to the source of the second MOS transistor through the clamping transistor.

[0028] In this embodiment, a clamping transistor is added between the gate and source of the second MOSFET to provide a clamping voltage to the second MOSFET, thereby reducing the probability of damage to the second MOSFET when the voltage between the gate and source changes drastically.

[0029] In some embodiments of this application, the clamping transistor includes a first transistor and a second transistor. The gate of the second transistor is connected to the base and collector of the second transistor, the emitter of the second transistor is connected to the emitter of the first transistor, and the source of the second transistor is connected to the base and collector of the first transistor.

[0030] In this embodiment, a clamping transistor consisting of back-to-back diodes is added between the gate and source of the second MOSFET. The first transistor and the second transistor provide a clamping voltage to the second MOSFET, resulting in a good clamping effect.

[0031] In some embodiments of this application, the control unit includes an MCU, a DAC module, a single-ended to differential circuit, an error amplifier, and a current sampling resistor. The signal output terminal of the MCU is connected to the input terminal of the DAC module, the output terminal of the DAC module is connected to the input terminal of the single-ended to differential circuit, the output terminal of the single-ended to differential circuit is connected to the non-inverting and inverting inputs of the error amplifier, the output terminal of the error amplifier is connected to the gate of a first MOSFET, the source of the first MOSFET is grounded through the current sampling resistor, and the two ends of the current sampling resistor are connected to the non-inverting and inverting inputs of the error amplifier, respectively.

[0032] In this embodiment, a digital control signal is sent by the MCU, and the DAC module converts the digital control signal into a single-ended analog signal and inputs it to the single-ended to differential circuit. The single-ended to differential circuit converts the single-ended analog signal into a pseudo-differential signal and inputs it to the error amplifier. The sampling signal fed back by the current sampling resistor is also input to the error amplifier and compared with the pseudo-differential signal output by the single-ended to differential circuit to form a corresponding analog signal output to the gate of the first MOS transistor, thereby forming a closed control loop.

[0033] In this embodiment, the control unit can form a closed control loop through the MCU, DAC module, single-ended to differential circuit, error amplifier and current sampling resistor to meet the requirements of closed-loop control of electronic load.

[0034] In some embodiments of this application, a fuse F1 is connected in series with the drain of the first MOSFET.

[0035] In this embodiment, a fuse F1 is connected in series with the drain of the first MOSFET to prevent high voltage from being conducted to the first MOSFET and causing secondary damage when the second MOSFET is damaged, thereby reducing the probability of damage to the first MOSFET.

[0036] The following is a detailed description of the specific circuit, using a second MOSFET as an example. (Refer to...) Figure 1As shown, in this embodiment, the first MOSFET is MOSFET Q1, the second MOSFET is MOSFET Q2, the first resistor and the second resistor are resistors R1 and R2 respectively, the first capacitor, the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor are capacitors C1, C2, C3, C4 and C5 respectively, and the first transistor and the second transistor are transistors Q3 and Q4 respectively; the power supply terminal VBUS is grounded through MOSFETs Q2 and Q1 connected in series, resistor R1 and capacitor C1 are connected in parallel, resistor R2 and capacitor C2 are connected in parallel, one end of resistor R1 and capacitor C1 is grounded, and the other end is connected to the gate of MOSFET Q2 through resistor R4; one end of resistor R2 and capacitor C2 is connected in parallel. One end is connected to the power supply terminal VBUS, and the other end is connected to the gate of MOSFET Q2 through resistor R4. The gate of MOSFET Q2 is connected to the source of MOSFET Q2 through capacitor C4. The drain of MOSFET Q2 is connected to the source of MOSFET Q2 through capacitor C3. The drain of MOSFET Q1 is connected to the source of MOSFET Q2 through capacitor C5. The source of MOSFET Q1 is grounded through current sampling resistor Rs. A fuse F1 is connected in series with the drain of MOSFET Q1. The output of the single-ended to differential circuit is connected to the non-inverting and inverting inputs of error amplifier EA through resistors R7 and R8, respectively. The two ends of the current sampling resistor Rs are connected to the non-inverting and inverting inputs of error amplifier EA through resistors R5 and R6, respectively.

[0037] In this embodiment, transistors Q3 and Q4 form a clamping transistor to provide a clamping voltage to the gate and source of MOSFET Q2. Capacitors C5 and C3 suppress high-frequency signals between the drain and source of MOSFETs Q1 and Q2, respectively, to prevent oscillation. Capacitor C4 suppresses sudden changes in the VGS voltage of Q2, improving the stability of MOSFET Q2 and preventing it from running out of control. In this embodiment, running out of control refers to the MOSFET not conducting or conducting excessively between the drain and source. Before the closed control loop of MOSFET Q2 is established, the source voltage VS2 changes with the conduction degree of MOSFET Q1. For MOSFET Q2, the gate-source voltage VGS2 = VG2 - VS2, resulting in nonlinear conduction between the drain and source of MOSFET Q2, thus causing running out of control. In the dynamic adjustment control configuration, the voltage across capacitor C4 changes with the charge and discharge degree of MOSFET Q1, which plays a delaying role and prevents the gate-source voltage VGS2 of Q2 from changing drastically, thus preventing running out of control. Capacitors C1 and C2 act as an AC voltage divider to prevent sudden voltage changes across resistors R1 and R2 during dynamic fluctuations, thus ensuring that the dynamic voltages across them quickly become equal. Resistors R1 and R2 form a voltage divider network using two resistors of equal resistance, ensuring that the gate voltage of MOSFET Q2 is VG2 = V1 = V2 = VBUS. (1 / 2), where V1 is the voltage across resistor R1 and V2 is the voltage across resistor R2.

[0038] The inverting input of error amplifier EA is initially biased at approximately -0.5V, and MOSFET Q1 is not turned on. After power is applied to the VBUS terminal, capacitors C3 and C5 are charged. The voltage VC5 across capacitor C5 is equal to the voltage VC3 across capacitor C3, and thus VC5 = VC3 = VBUS. (1 / 2), the gate voltage of MOSFET Q2 is VG2 = V1 = V2 = VBUS (1 / 2) Source voltage VS2=VC5. At the same point, the gate-source voltage VGS2 of MOSFET Q2 is 0V, and Q2 is not conducting. At this time, the entire control loop is not established, and there is no current in the entire loop of the MOSFET unit.

[0039] When the DAC module outputs a corresponding analog signal of approximately 0-3.5V, the voltage at the non-inverting input of the error amplifier EA is greater than that at the inverting input. At this time, the error amplifier EA outputs a positive value that is greater than the turn-on voltage Vgs(th) of MOSFET Q1, and MOSFET Q1 turns on. After MOSFET Q1 turns on, current flows through the current sampling resistor Rs. The voltage difference across the current sampling resistor Rs is amplified by the proportional resistors R5 / R6 / R7 / R8 and compared with the signal output by the single-ended to differential circuit. The differential amplifier EA then outputs the corresponding analog signal to the gate of MOSFET Q1, thereby forming a closed control loop 1.

[0040] When MOSFET Q1 is turned on and a feedback loop is established, the current flowing through MOSFET Q1 is denoted as Id1. The drain voltage VD1 of MOSFET Q1 decreases, and the source voltage VS2 of MOSFET Q2 equals VD1. Therefore, the source voltage VS2 of MOSFET Q2 also decreases. According to the characteristics of MOSFETs, the current flowing through the drain D and source S is Id = VGS. Gm, at this time the current of MOSFET Q2 is set to Id2, and Id2 = VGS2. Gm2=(VG2-VS2) Gm2, where VG2=V1=V2=VBUS (1 / 2) remains unchanged. Id2 is inversely proportional to VS2. After MOSFET Q1 is turned on, VD1 changes, and since VS2 = VD1, then Id2 = VGS2. Gm2=(VG2-VS2) Gm2=(VG2-VD1) When Gm2 is established, MOSFET Q2 will turn on, forming closed control loop 2. Ultimately, closed control loop 2 corresponding to MOSFET Q2 changes with the closed control loop 1 corresponding to MOSFET Q1. In the power loop, Id1=Id2, and the source-drain voltage VDS of MOSFETs Q1 and Q2 are equal, that is, VDS1=VDS2.

[0041] The following is a circuit example illustrating the connection of two second MOSFETs, i.e., three MOSFETs connected in series. (Refer to...) Figure 2 As shown, the two second MOSFETs are MOSFET Q2 and MOSFET Q5, that is, in Figure 2 Another MOSFET Q5 is connected in series between MOSFET Q2 and the power supply terminal VBUS. The voltage equalization unit corresponding to MOSFET Q5 includes resistors R10, capacitors C7, C8, and C9, as well as clamping transistors Q6 and Q7. It should be noted that the high-potential terminal in the voltage equalization unit corresponding to MOSFET Q2 is the common terminal of resistors R10 and R11, and the low-potential terminal is ground. Similarly, the high-potential terminal in the voltage equalization unit corresponding to MOSFET Q5 is the power supply terminal VBUS, and the low-potential terminal is the common terminal of resistors R2 and R4. The voltage equalization unit composed of resistors R10, capacitors C7, C8, and C9, and transistors Q6 and Q7 operates similarly to the previous voltage equalization unit and will not be described in detail here.

[0042] This application also relates to an electronic load, including the MOS transistor series control circuit of the above embodiments.

[0043] This application also relates to an electronic device, including the aforementioned MOS transistor series control circuit.

[0044] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, this application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of this application.

Claims

1. A series control circuit for MOSFETs, characterized in that, The MOS tube unit comprises a first MOS tube and at least one second MOS tube connected in series with the first MOS tube. The control unit is connected to the gate of the first MOS tube to control the conduction state of the first MOS tube. The power supply end is connected to the input end of the second MOS tube, and the output end of the first MOS tube is grounded. The at least one voltage equalization unit corresponds to the second MOS tube, and comprises a high potential end, a low potential end, a first resistor, a second resistor, a first capacitor, a second capacitor, a third capacitor and a fourth capacitor. The gate of the second MOS tube is connected to the low potential end through the first resistor and the first capacitor connected in parallel with each other. The gate of the second MOS tube is connected to the high potential end through the second resistor and the second capacitor connected in parallel with each other.

2. The MOS transistor string control circuit according to claim 1, wherein The drain of the second MOS tube is connected to the source of the second MOS tube through the third capacitor.

3. The MOS transistor string control circuit according to claim 2, wherein The gate of the second MOS tube is connected to the source of the second MOS tube through the fourth capacitor.

4. The MOS string control circuit of claim 1, wherein, The fifth capacitor is connected between the drain of the first MOS tube and the source of the first MOS tube.

5. The MOS string control circuit of claim 1, wherein, The voltage equalization unit further comprises a clamping tube, and the gate of the second MOS tube is connected to the source of the second MOS tube through the clamping tube.

6. An electronic load, characterized by The clamping tube comprises a first transistor and a second transistor, and the gate of the second MOS tube is connected to the base and the collector of the second transistor, respectively.

7. An electronic device, comprising: The control unit comprises an MCU, a DAC module, a single-ended to differential circuit, an error amplifier and a current sampling resistor. The gate of the first MOS tube is connected to the output end of the error amplifier. The drain of the first MOS tube is connected in series with a fuse. The MOS tube series control circuit comprises any one of claims 1 to 5. The MOS tube series control circuit comprises any one of claims 1 to 5.

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