PCM equipment

Abstract

The utility model discloses PCM equipment, which belongs to the technical field of telecommunication, comprises an input interface, a signal amplifier, a sampling hold circuit, a signal conditioning circuit, an ADC (analog to digital converter) module, a clock generator, a power module, a digital processor, a memory, an Ethernet controller and a remote communication module, and solves the technical problems of sampling synchronization and high-precision sampling of the PCM equipment. According to the utility model, the tracking sampling holding circuit formed by the AD8250 amplifier and the AD503 is adopted, so that the accuracy and the stability of signals during high-frequency sampling can be ensured. The perfect alignment of time sequences among the modules in the system is ensured, and the problem of long-distance low-power-consumption data transmission is solved.

Description

Technical Field

[0001] This utility model belongs to the field of telecommunications technology, and in particular relates to a PCM device. Background Technology

[0002] Current PCM (Pulse Code Modulation) equipment mainly consists of the following modules:

[0003] Analog signal input and sample-and-hold circuit: Traditional techniques typically use standard low-noise amplifiers and basic filtering circuits. These circuits may introduce signal distortion or noise when processing high-frequency signals, affecting sampling accuracy.

[0004] Analog-to-digital conversion (ADC): Many existing technologies use more common ADCs, such as 12-bit or 16-bit resolution, which may not be sufficient for some high-precision applications.

[0005] Clock synchronization: Traditional PCM devices typically use multiple independent clock modules, which can lead to clock drift and system instability.

[0006] Existing technologies also suffer from low signal accuracy, and are susceptible to signal interference during high-frequency or high-precision signal acquisition, leading to a decrease in sampling accuracy. Utility Model Content

[0007] The purpose of this invention is to provide a PCM device that solves the technical problems of maintaining sampling synchronization and high-precision sampling in PCM devices.

[0008] To achieve the above objectives, the present invention adopts the following technical solution:

[0009] A PCM device includes an input interface, a signal amplifier, a sample-and-hold circuit, a signal conditioning circuit, an ADC module, a clock generator, a power supply module, a digital processor, a memory, an Ethernet controller, and a remote communication module.

[0010] The ADC module, clock generator, memory, Ethernet controller, and remote communication module are all connected to the digital processor;

[0011] The input interface is connected to a signal amplifier, the signal amplifier is connected to a sample-and-hold circuit, the sample-and-hold circuit is connected to a signal conditioning circuit, and the signal conditioning circuit is connected to an ADC module.

[0012] The clock generator is also connected to the ADC module, and is used to provide a crystal clock for the ADC module and the digital processor;

[0013] The input interface connects to an external voice input device;

[0014] The power supply module provides power to the signal amplifier, sample-and-hold circuit, signal conditioning circuit, ADC module, clock generator, digital processor, memory, Ethernet controller, and remote communication module.

[0015] Preferably, the power supply module includes an AD-DC module, a positive 12V regulator, a negative 12V regulator, a 5V regulator, and a 3.3V regulator. The input terminal of the AD-DC module is connected to external AC power, and the output terminal outputs 15V power. The input terminal of the positive 12V regulator is connected to 15V power, and the output terminal outputs +12V power. The input terminal of the 5V regulator is connected to 12V power, and the output terminal outputs 5V power. The input terminal of the 3.3V regulator is connected to 5V power, and the output terminal outputs 3.3V power.

[0016] The input terminal of the -12V voltage regulator is connected to a 15V power supply, and the output terminal outputs a -12V power supply.

[0017] Preferably, the AD-DC module is an HLK-PM15 AC-DC module, the positive 12V regulator is an LM7812, the negative 12V regulator is an LM7912, the 5V regulator is an LM7805, and the 3.3V regulator is an AMS1117.

[0018] Preferably, the signal amplifier includes amplifier IC1, resistors R1, R2, R3, and R4, capacitors C1, C2, C3, C4, and C5, and resistor R10. The input interface is interface J1. The positive input terminal +IN of amplifier IC1 is connected to pin 2 of interface J1 through resistors R1 and R3 connected in series. The negative input terminal -IN of amplifier IC1 is connected to pin 1 of interface J1 through resistors R2 and R4 connected in series. Capacitors C1, C2, and C3 constitute a filter network for the positive input terminal +IN and the negative input terminal -IN of amplifier IC1.

[0019] The output of amplifier IC1 outputs the sampled signal after one stage of amplification through resistor R10;

[0020] Amplifier IC1 has pins 2 and 9 connected to ground, pin 8 connected to +12V power supply, and pin 3 connected to -12V power supply; capacitors C4 and C5 are the filter capacitors for pins 8 and 3 of amplifier IC1, respectively.

[0021] Amplifier IC1's pins 6, 5, and 4 are connected to different I / O ports of the digital processor, respectively.

[0022] The sample-and-hold circuit includes amplifier IC2, amplifier IC4, transistor Q3, transistor Q1, transistor Q2, resistors R9, R6, R8, R7, R5, R11, R6, R12, amplifier IC3, resistors R13, R14, R15, and R16. The positive input terminal of amplifier IC2 is connected to the output terminal of amplifier IC1 through resistor R10, and the negative input terminal is connected to the output terminal of amplifier IC2. The output terminal of amplifier IC2 is connected to pin 2 of transistor Q3. Pin 1 of transistor Q3 is connected to the output terminal of amplifier IC2 through resistor R9, and pin 3 is connected to the positive input terminal of amplifier IC4 through resistor R11. The negative input terminal of amplifier IC4 is connected to the output terminal of amplifier IC4. The output terminal of amplifier IC4 outputs the sample-and-hold signal through resistor R12.

[0023] Capacitor C6 is the grounding capacitor for the positive input terminal of amplifier IC4. The base of transistor Q1 is connected to an I / O port of the digital processor through resistor R5, the emitter is connected to the +12V power supply through resistor R8, and the collector is connected to the -12V power supply through resistor R7.

[0024] The base of transistor Q2 is connected to the collector of transistor Q1, the emitter is connected to the -12V power supply, and the collector is connected to pin 1 of transistor Q3; the emitter of transistor Q1 is also connected to ground through resistor R6.

[0025] The output of amplifier IC4 is connected to the positive input of amplifier IC3 through resistor R12. The negative input of amplifier IC3 is connected to the +12V power supply through resistor R13, and its output is connected to pin 1 of resistor R15. The output of amplifier IC3 is also connected to the negative input of amplifier IC3 through resistor R14. Pin 2 of resistor R15 is connected to ground through resistor R16. Pin 2 of resistor R15 outputs the conditioned signal and is connected to an I / O port of the digital processor.

[0026] Preferably, the ADC module uses an LTC2499 signal, a TXC 7P-20-16.384MHz clock generator, a Zynq-7000 ARM Cortex-A9 digital processor, an AT45DB321E memory, a W5500 Ethernet controller, and an SX1278 remote communication module.

[0027] Preferably, the amplifier IC1 is model AD8250, the amplifier IC2 and amplifier IC4 are both model AD503, and the amplifier IC4 is model TL081; the transistor Q3 is model 2N4393, the transistor Q1 is model 2N4916, and the transistor Q2 is model 2N2222.

[0028] This invention discloses a PCM device that solves the technical problems of maintaining sampling synchronization and high-precision sampling in PCM devices. It employs a tracking sample-and-hold circuit composed of an AD8250 amplifier and an AD503, ensuring signal accuracy and stability during high-frequency sampling. Compared with existing technologies, this high-precision amplification and sample-and-hold combination effectively avoids signal distortion, making it particularly suitable for processing high-frequency and audio signals. Using a TXC 7P-20 high-precision crystal oscillator and a Xilinx Zynq-7000 processor, precise clock synchronization and adaptive control ensure perfect timing alignment between modules within the system. Such synchronization typically requires multiple independent clock modules in existing technologies, which are prone to clock drift and phase errors, affecting data accuracy and stability. The LoRa SX1278 module is used for remote wireless data transmission, solving the problem of long-distance, low-power data transmission. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating the overall principle of this utility model;

[0030] Figure 2 This is a block diagram of the power supply module of this utility model.

[0031] Figure 3 This is a circuit diagram of the input interface, signal amplifier, sample-and-hold circuit, and signal conditioning circuit of this utility model. Detailed Implementation

[0032] Depend on Figures 1-3 The PCM device shown includes an input interface, a signal amplifier, a sample-and-hold circuit, a signal conditioning circuit, an ADC module, a clock generator, a power supply module, a digital processor, a memory, an Ethernet controller, and a remote communication module.

[0033] The ADC module, clock generator, memory, Ethernet controller, and remote communication module are all connected to the digital processor;

[0034] The ADC module uses an LTC2499 signal, a TXC 7P-20-16.384MHz clock generator, a Zynq-7000 ARM Cortex-A9 digital processor, an AT45DB321E memory, a W5500 Ethernet controller, and an SX1278 remote communication module.

[0035] The input interface is connected to a signal amplifier, the signal amplifier is connected to a sample-and-hold circuit, the sample-and-hold circuit is connected to a signal conditioning circuit, and the signal conditioning circuit is connected to an ADC module.

[0036] The signal amplifier includes amplifier IC1, resistors R1, R2, R3, and R4, capacitors C1, C2, C3, C4, and C5, and resistor R10. The input interface is interface J1. The positive input terminal +IN of amplifier IC1 is connected to pin 2 of interface J1 through resistors R1 and R3 connected in series. The negative input terminal -IN of amplifier IC1 is connected to pin 1 of interface J1 through resistors R2 and R4 connected in series. Capacitors C1, C2, and C3 form a filter network for the positive input terminal +IN and the negative input terminal -IN of amplifier IC1.

[0037] The output of amplifier IC1 outputs the sampled signal after one stage of amplification through resistor R10;

[0038] Amplifier IC1 has pins 2 and 9 connected to ground, pin 8 connected to +12V power supply, and pin 3 connected to -12V power supply; capacitors C4 and C5 are the filter capacitors for pins 8 and 3 of amplifier IC1, respectively.

[0039] Amplifier IC1's pins 6, 5, and 4 are connected to different I / O ports of the digital processor, respectively.

[0040] The input terminal of amplifier IC1 receives analog signals from analog signal sources (such as sensors or audio devices) through a filter network consisting of resistors R1, R2, R3, and R4, and capacitors C1, C2, and C3. The signal amplifier constructed using amplifier IC1 has the following advantages:

[0041] Low noise: The input voltage noise density is as low as 8nV / √Hz (at 10kHz), which can effectively detect and amplify weak signals, reduce the impact of noise interference on measurement accuracy, and is suitable for applications with high signal quality requirements.

[0042] High precision: It has excellent DC accuracy, with offset voltage as low as ±100μV (maximum), offset voltage drift as low as ±0.6μV / ℃ (maximum), gain error as low as ±0.02% (maximum), and gain drift as low as ±5ppm / ℃ (maximum), ensuring the accuracy and stability of signal amplification.

[0043] High-speed performance: -3dB bandwidth up to 20MHz, slew rate of 30V / μs, capable of quickly responding to changes in input signal, suitable for processing high-frequency signals and rapidly changing signals.

[0044] High common-mode rejection ratio (CMRR): The CMRR is as high as 120dB (minimum) at DC and still maintains 100dB (minimum) at 1kHz. It can effectively suppress the interference of common-mode signals, extract the required differential-mode signals, and improve the reliability of measurement.

[0045] The sample-and-hold circuit includes amplifier IC2, amplifier IC4, transistor Q3, transistor Q1, transistor Q2, resistors R9, R6, R8, R7, R5, R11, R6, R12, amplifier IC3, resistors R13, R14, R15, and R16. The positive input terminal of amplifier IC2 is connected to the output terminal of amplifier IC1 through resistor R10, and the negative input terminal is connected to the output terminal of amplifier IC2. The output terminal of amplifier IC2 is connected to pin 2 of transistor Q3. Pin 1 of transistor Q3 is connected to the output terminal of amplifier IC2 through resistor R9, and pin 3 is connected to the positive input terminal of amplifier IC4 through resistor R11. The negative input terminal of amplifier IC4 is connected to the output terminal of amplifier IC4. The output terminal of amplifier IC4 outputs the sample-and-hold signal through resistor R12.

[0046] Capacitor C6 is the grounding capacitor for the positive input terminal of amplifier IC4. The base of transistor Q1 is connected to an I / O port of the digital processor through resistor R5, the emitter is connected to the +12V power supply through resistor R8, and the collector is connected to the -12V power supply through resistor R7.

[0047] The base of transistor Q2 is connected to the collector of transistor Q1, the emitter is connected to the -12V power supply, and the collector is connected to pin 1 of transistor Q3; the emitter of transistor Q1 is also connected to ground through resistor R6.

[0048] The output of amplifier IC4 is connected to the positive input of amplifier IC3 through resistor R12. The negative input of amplifier IC3 is connected to the +12V power supply through resistor R13, and its output is connected to pin 1 of resistor R15. The output of amplifier IC3 is also connected to the negative input of amplifier IC3 through resistor R14. Pin 2 of resistor R15 is connected to ground through resistor R16. Pin 2 of resistor R15 outputs the conditioned signal and is connected to an I / O port of the digital processor.

[0049] The sample-and-hold circuit receives the amplified analog signal and precisely maintains the voltage state of that signal. This circuit ensures signal stability at the sampling point and prevents signal drift.

[0050] The base of transistor Q1 is the hold signal control terminal, which is controlled by an I / O port of the digital processor. Amplifier IC3 is a voltage offset circuit that shifts the positive and negative voltage signals output by amplifier IC4 in the positive direction. In this embodiment, resistor R13 is a potentiometer. After modulation, a final output signal from 0V to 20V can be obtained. This signal is then modulated by a voltage divider circuit composed of resistors R15 and R16 to finally divide the voltage output to meet the input requirements of LTC2499.

[0051] The LTC2499 is responsible for converting analog signals to digital signals. This ADC features a high sampling rate of 1 MSPS and 24-bit resolution, enabling it to accurately convert complex analog signals.

[0052] The LTC2499's clock is provided by a TXC 7P-20 crystal oscillator, ensuring precise timing synchronization for each sampling cycle.

[0053] The TXC 7P-20 crystal oscillator keeps the clock of the LTC2499 in sync with the clock of the Zynq-7000 processor by providing the crystal clock for the Zynq-7000 processor.

[0054] The Zynq-7000 processor is responsible for further decoding, encoding, processing, and optimization of analog signals. This process is existing technology and will not be described in detail, such as encoding algorithms like G.711.

[0055] The amplifier IC1 is model AD8250, the amplifier IC2 and amplifier IC4 are both model AD503, and the amplifier IC4 is model TL081; the transistor Q3 is model 2N4393, the transistor Q1 is model 2N4916, and the transistor Q2 is model 2N2222.

[0056] The clock generator is also connected to the ADC module, and is used to provide a crystal clock for the ADC module and the digital processor;

[0057] The input interface connects to an external voice input device;

[0058] The power supply module provides power to the signal amplifier, sample-and-hold circuit, signal conditioning circuit, ADC module, clock generator, digital processor, memory, Ethernet controller, and remote communication module.

[0059] The power supply module includes an AD-DC module, a positive 12V regulator, a negative 12V regulator, a 5V regulator, and a 3.3V regulator. The input terminal of the AD-DC module is connected to external AC power, and the output terminal outputs 15V power. The input terminal of the positive 12V regulator is connected to 15V power, and the output terminal outputs +12V power. The input terminal of the 5V regulator is connected to 12V power, and the output terminal outputs 5V power. The input terminal of the 3.3V regulator is connected to 5V power, and the output terminal outputs 3.3V power.

[0060] The input terminal of the -12V voltage regulator is connected to a 15V power supply, and the output terminal outputs a -12V power supply.

[0061] The AD-DC module is model HLK-PM15 AC-DC module, the positive 12V regulator is model LM7812, the negative 12V regulator is model LM7912, the 5V regulator is model LM7805, and the 3.3V regulator is model AMS1117.

[0062] This invention discloses a PCM device that solves the technical problems of maintaining sampling synchronization and high-precision sampling in PCM devices. It employs a tracking sample-and-hold circuit composed of an AD8250 amplifier and an AD503, ensuring signal accuracy and stability during high-frequency sampling. Compared with existing technologies, this high-precision amplification and sample-and-hold combination effectively avoids signal distortion, making it particularly suitable for processing high-frequency and audio signals. Using a TXC 7P-20 high-precision crystal oscillator and a Xilinx Zynq-7000 processor, precise clock synchronization and adaptive control ensure perfect timing alignment between modules within the system. Such synchronization typically requires multiple independent clock modules in existing technologies, which are prone to clock drift and phase errors, affecting data accuracy and stability. The LoRa SX1278 module is used for remote wireless data transmission, solving the problem of long-distance, low-power data transmission.

Claims

1. A PCM device, characterized by: The input interface, the signal amplifier, the sample and hold circuit, the signal conditioning circuit, the ADC module, the clock generator, the power module, the digital processor, the memory, the Ethernet controller and the remote communication module are connected with the digital processor. The input interface is connected with the signal amplifier, the signal amplifier is connected with the sample and hold circuit, the sample and hold circuit is connected with the signal conditioning circuit, and the signal conditioning circuit is connected with the ADC module. The clock generator is also connected with the ADC module, and is used for providing a crystal clock for the ADC module and the digital processor. The input interface is connected with an external voice input device. The power module provides power supply voltage for the signal amplifier, the sample and hold circuit, the signal conditioning circuit, the ADC module, the clock generator, the digital processor, the memory, the Ethernet controller and the remote communication module. The input end of the AD-DC module is connected with external mains, and the output end outputs 15V power supply; the input end of the positive 12V voltage stabilizer is connected with the 15V power supply, and the output end outputs +12V power supply; the input end of the 5V voltage stabilizer is connected with the 12V power supply, and the output end outputs 5V power supply; the input end of the 3.3V voltage stabilizer is connected with the 5V power supply, and the output end outputs 3.3V power supply.

2. A PCM device as claimed in claim 1, characterized in that: The input end of the negative 12V voltage stabilizer is connected with the 15V power supply, and the output end outputs -12V power supply. The model of the AD-DC module is HLK-PM15 type AC-DC module, the model of the positive 12V voltage stabilizer is LM7812, the model of the negative 12V voltage stabilizer is LM7912, the model of the 5V voltage stabilizer is LM7805, and the model of the 3.3V voltage stabilizer is AMS1117.

3. A PCM device as claimed in claim 2, characterized in that: The signal amplifier comprises an amplifier IC1, resistors R1, R2, R3, R4, capacitors C1, C2, C3, C4, C5 and a resistor R10, the input interface is an interface J1, the positive input end +IN of the amplifier IC1 is connected with the 2-pin of the interface J1 through the series connection of the resistor R1 and the resistor R3, the negative input end -IN of the amplifier IC1 is connected with the 1-pin of the interface J1 through the series connection of the resistor R2 and the resistor R4, and the capacitors C1, C2 and C3 constitute a filter network of the positive input end +IN and the negative input end -IN of the amplifier IC1.

4. A PCM device as claimed in claim 2, characterized in that: The output end of the amplifier IC1 outputs a first-amplified sample signal through the resistor R10. The 2-pin and the 9-pin of the amplifier IC1 are connected with ground, the 8-pin is connected with +12V power supply, and the 3-pin is connected with -12V power supply; the capacitors C4 and C5 are filter capacitors of the 8-pin and the 3-pin of the amplifier IC1 respectively. The 6-pin, the 5-pin and the 4-pin of the amplifier IC1 are connected with different IO ports of the digital processor respectively. ​ The sample and hold circuit comprises an amplifier IC2, an amplifier IC4, a transistor Q3, a triode Q1, a triode Q2, a resistor R9, a resistor R6, a resistor R8, a resistor R7, a resistor R5, a resistor R11, a resistor R12, an amplifier IC3, a resistor R13, a resistor R14, a resistor R15 and a resistor R16, the positive input end of the amplifier IC2 is connected with the output end of the amplifier IC1 through a resistor R10, the negative input end is connected with the output end of the amplifier IC2, the output end of the amplifier IC2 is connected with the 2 pin of the transistor Q3, the 1 pin of the transistor Q3 is connected with the output end of the amplifier IC2 through a resistor R9, the 3 pin is connected with the positive input end of the amplifier IC4 through a resistor R11, the negative input end of the amplifier IC4 is connected with the output end of the amplifier IC4, and the output end of the amplifier IC4 outputs a sample and hold signal through a resistor R12; The capacitor C6 is an input ground capacitor of the positive input end of the amplifier IC4, the base of the triode Q1 is connected with an IO port of a digital processor through a resistor R5, the emitter is connected with a +12V power supply through a resistor R8, and the collector is connected with a -12V power supply through a resistor R7; The base of the triode Q2 is connected with the collector of the triode Q1, the emitter is connected with a -12V power supply, and the collector is connected with the 1 pin of the transistor Q3; the emitter of the triode Q1 is also connected with a ground wire through a resistor R6; The output end of the amplifier IC4 is connected with the positive input end of the amplifier IC3 through a resistor R12, the negative input end of the amplifier IC3 is connected with a +12V power supply through a resistor R13, the output end is connected with the 1 pin of a resistor R15, the output end of the amplifier IC3 is also connected with the negative input end of the amplifier IC3 through a resistor R14, the 2 pin of the resistor R15 is connected with a ground wire through a resistor R16, and the 2 pin of the resistor R15 outputs a processed signal and is connected with an IO port of a digital processor.

5. A PCM device as claimed in claim 1, characterized in that: The signal of the ADC module is LTC2499, the model of the clock generator is TXC 7P-20-16.384MHz, the model of the digital processor is Zynq-7000 ARM Cortex-A9 processor, the model of the memory is AT45DB321E, the model of the Ethernet controller is W5500, and the model of the remote communication module is SX1278.

6. A PCM device as claimed in claim 4, characterized in that: The model of the amplifier IC1 is AD8250, the models of the amplifier IC2 and the amplifier IC4 are both AD503, and the model of the amplifier IC4 is TL081; the model of the transistor Q3 is 2N4393, the model of the triode Q1 is 2N4916, and the model of the triode Q2 is 2N2222.

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