Semiconductor device
By setting staggered virtual metal rings and sealing rings around the semiconductor device, the problem of crack propagation to the chip was solved, the device yield was improved, the manufacturing process was simplified, and the cost was reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2026-03-10
AI Technical Summary
In existing technologies, sealing rings cannot effectively prevent cracks from propagating to the chip, resulting in damage to the electronic circuits and mechanical damage within the chip.
Multiple metal layers are set around the chip area, including sealing rings and staggered virtual metal rings. The virtual metal rings are staggered in the direction close to the chip area, and the size and shape of the metal structure are adjusted in different directions to absorb the energy of crack propagation.
It effectively prevents cracks from propagating to the chip, improves the yield of semiconductor devices, reduces mechanical damage, simplifies the manufacturing process, and lowers manufacturing costs.
Smart Images
Figure CN223987371U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor device. Background Technology
[0002] In semiconductor manufacturing, after the wafer completes its process, it needs to be cut according to pre-defined scribe lines to cut and decompose the large wafer into multiple chips with electrical functions.
[0003] In related technologies, to reduce the damage to the chip caused by cracks generated during the dicing process, a sealing ring is usually introduced between the chip and the dicing track. However, cracks that the sealing ring fails to prevent can still propagate to the chip. This not only affects the electronic circuitry within the chip but also introduces mechanical damage to the bonded interfaces, causing disconnection. Utility Model Content
[0004] In view of this, embodiments of the present disclosure provide a semiconductor device, including: a chip region and a peripheral region surrounding the chip region; the peripheral region includes multiple metal layers stacked along a first direction, each of the metal layers including:
[0005] A sealing ring surrounds the outer side of the chip area;
[0006] Multiple non-continuous virtual metal rings are located sequentially on the inner and / or outer sides of the sealing ring; in the same metal layer, the metal structures in two adjacent virtual metal rings are staggered in the second direction;
[0007] The first direction is perpendicular to the plane where the metal layer is located, and the second direction is the direction on the plane where the metal layer is located, closer to the chip area.
[0008] In some embodiments, in the second direction, the dimensions of the metal structures in the plurality of virtual metal rings decrease sequentially in a third direction; the third direction is the extension direction of the side where the metal structure is located.
[0009] In some embodiments, the shape of the metal structure includes a concave shape, a long strip shape, a polygon shape, an H shape, and an I-shaped shape.
[0010] In some embodiments, the projection of the metal structure in the virtual metal ring onto the third direction overlaps with the projection of the metal structure in the adjacent virtual metal ring onto the third direction.
[0011] In some embodiments, within the same virtual metal ring, the projection of the metal structure in the second direction partially overlaps with the projection of the adjacent metal structure in the second direction.
[0012] In some embodiments, in two adjacent metal layers, the metal structures in the virtual metal ring are arranged alternately with the metal structures in the virtual metal ring adjacent along the first direction.
[0013] In some embodiments, the semiconductor device further includes:
[0014] Multiple metal vias are connected between two adjacent layers of the virtual metal rings; the multiple metal vias are staggered in the second direction.
[0015] In some embodiments, the metal layer further includes:
[0016] Multiple pseudo-metals are located inside the sealing ring and the virtual metal ring, and outside the sealing ring and the virtual metal ring; the dimension of the metal structure in the third direction is larger than the dimension of the pseudo-metals in the third direction.
[0017] In some embodiments, the semiconductor device further includes: a first isolation structure and a second isolation structure;
[0018] The sealing ring, the virtual metal ring, and the pseudo-metal in the metal layer are located in the first isolation structure;
[0019] The metal via is located in the second isolation structure.
[0020] In some embodiments, the chip region includes a chip; the metal layer in the peripheral region is located on the same layer as the metal interconnect layer in the chip;
[0021] The peripheral area includes at least a sealing ring area and a cutting channel area; wherein the sealing ring is disposed on the sealing ring area.
[0022] This disclosure provides a semiconductor device comprising: a chip region and a peripheral region surrounding the chip region; the peripheral region includes multiple metal layers stacked along a first direction, each metal layer including: a sealing ring surrounding the outer side of the chip region; a plurality of non-contiguous virtual metal rings sequentially located inside and / or outside the sealing ring; and metal structures in adjacent virtual metal rings within the same metal layer being staggered in a second direction. Because multiple virtual metal rings are sequentially arranged inside and / or outside the sealing ring, and the metal structures in adjacent virtual metal rings within the same metal layer are staggered in the direction close to the chip region, the path for crack intrusion during wafer dicing can be increased, effectively absorbing energy during crack propagation, thereby preventing crack propagation into the chip and improving the yield of the semiconductor device after dicing. Attached Figure Description
[0023] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.
[0024] Figure 1 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 1 ;
[0025] Figure 2 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 2 ;
[0026] Figure 3 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 3 ;
[0027] Figure 4 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 4 ;
[0028] Figure 5 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 5 ;
[0029] Figure 6 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 6 ;
[0030] Figure 7 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 7 ;
[0031] Figure 8 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 8 ;
[0032] Figure 9 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 9 ;
[0033] Figure 10 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 10 ;
[0034] Figure 11 Schematic diagram of the structure of the semiconductor device provided in the embodiments of this disclosure Figure 10 one. Detailed Implementation
[0035] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0036] In the following description, numerous details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.
[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.
[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0040] The semiconductor devices in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0041] Before introducing the embodiments of this disclosure, let's define three directions that may be used in the following embodiments to describe the three-dimensional structure. These three directions may include a first direction, a second direction, and a third direction. The first direction may be a direction perpendicular to the plane containing the metal layer; the second direction and the third direction are parallel to the plane containing the metal layer, wherein the second direction is the direction closer to the chip region, and the third direction is the extension direction of the edge containing the metal structure. The first direction is defined as the X-axis direction, the second direction as the Y-axis direction, and the third direction as the Z-axis direction.
[0042] This disclosure provides a semiconductor device 100, such as... Figures 1 to 3 As shown, the semiconductor device 100 includes: a chip region 11 and a peripheral region 12 surrounding the chip region 11; the peripheral region 12 includes multiple metal layers 120 stacked along the X-axis direction, each metal layer 120 including: a sealing ring 121 surrounding the outside of the chip region 11; a plurality of non-continuous virtual metal rings 122 located sequentially inside and / or outside the sealing ring 121; in the same metal layer 120, the metal structures 122a in two adjacent virtual metal rings 122 are staggered in the Y-axis direction.
[0043] It should be noted that the Y-axis and Z-axis directions in this embodiment are not two fixed directions on the plane where the metal layer 120 is located, but rather two directions corresponding to each edge of the virtual metal ring 122. For example, please refer to... Figure 1 For the topmost edge of the virtual metal ring 122, the Y-axis direction and the Z-axis direction are vertical and horizontal, respectively; for the leftmost edge of the virtual metal ring 122, the Y-axis direction and the Z-axis direction are horizontal and vertical, respectively.
[0044] In this embodiment, the chip region 11 and the peripheral region 12 are regions with different functional structures. The chip region 11 includes a chip (not shown) with device functionality, while the peripheral region 12 is the area surrounding the chip region 11 that does not have actual circuit connection functionality. The peripheral region 12 includes at least a sealing ring region and a scribe line region; the sealing ring 121 is disposed on the sealing ring region. Additionally, the peripheral region 12 may also include a region located between the chip and the sealing ring 121 that does not have actual circuit connection functionality.
[0045] Furthermore, the semiconductor device 100 in this embodiment may include, but is not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), phase-change memory (PCM), NAND memory, or NorFlash memory.
[0046] In some embodiments, the sealing ring 121 and the virtual metal ring 122 are shaped as closed patterns surrounding the chip region 11, and may include closed patterns formed by multiple straight line segments; for example... Figure 1 and Figure 2 Both the sealing ring 121 and the virtual metal ring 122 shown have an octagonal ring structure; for example, Figure 3 The sealing ring 121 shown has an octagonal ring structure, and the virtual metal ring 122 has a dodecagonal ring structure. In other embodiments, one edge of the virtual metal ring 122 can also be provided, thereby increasing protection in the corresponding direction and preventing crack propagation in that direction.
[0047] In this embodiment of the disclosure, the number of virtual metal rings 122 can be set according to actual needs; for example... Figure 1 The number of virtual metal rings 122 shown can be 4. Figure 2 The number of virtual metal rings 122 shown can be 3. Figure 3 The number of virtual metal rings 122 shown can be two. Furthermore, the positions of multiple virtual metal rings 122 can be set according to actual needs; for example, Figure 1 The four virtual metal rings 122 shown are located sequentially on the inner and outer sides of the sealing ring 121. Figure 2 The three virtual metal rings 122 shown are located sequentially inside the sealing ring 121. Figure 3The two virtual metal rings 122 shown are located sequentially outside the sealing ring 121. It should be noted that the virtual metal rings 122 and the sealing ring 121 can be adjacent to each other (e.g., ...). Figure 1 and Figure 2 As shown), it can also have a larger gap (such as...). Figure 3 (As shown).
[0048] In this embodiment, the metal structures 122a in two adjacent virtual metal rings 122 are staggered in the Y-axis direction. Specifically, the projection of the metal structure 122a in the virtual metal ring 122 in the Y-axis direction covers the gap between two metal structures 122a in adjacent virtual metal rings 122. This prevents cracks from passing through the virtual metal rings 122 along the Y-axis direction, ensuring the reliability of the virtual metal rings 122 in blocking cracks.
[0049] In this embodiment, the metal layer 120 in the peripheral region 12 and the metal interconnect layer (e.g., interconnect layer M0, M1 or M2) in the chip on the chip region 11 are located on the same layer; thus, the metal structure in the metal layer 120 (i.e., sealing ring 121 and virtual metal ring 122) and the metal structure in the chip can be fabricated simultaneously using the same manufacturing process, thereby simplifying the photolithography, etching and other processes in the manufacturing process, which is beneficial for process integration and reducing manufacturing costs.
[0050] In this embodiment, since multiple virtual metal rings are arranged sequentially on the inner and / or outer sides of the sealing ring, and the metal structures in two adjacent virtual metal rings in the same metal layer are staggered in the direction close to the chip area, the path of crack intrusion during wafer dicing can be increased, the energy of crack propagation can be effectively absorbed, thereby preventing cracks from propagating to the chip area and improving the yield of semiconductor devices after dicing.
[0051] Next, please refer to Figures 4 to 10 The semiconductor device 100 in the embodiments of this disclosure will be described in detail.
[0052] In some embodiments, please refer to Figures 4 to 8 In any one of them, the metal layer 120 also includes: a plurality of dummy metals 123 located inside the sealing ring 121 and the virtual metal ring 122, and outside the sealing ring 121 and the virtual metal ring 122; the dimension of the metal structure 122a in the Z-axis direction is larger than the dimension of the dummy metals 123 in the Z-axis direction.
[0053] In this embodiment, the pseudo-metal 123 refers to a metal structure that is inherently present in the semiconductor device but has no actual circuit functional connection. It should be noted that the metal structure 122a can be the pseudo-metal 123; that is, the metal structure 122a is not an additional structure, but a structure obtained by changing the shape and position of the pseudo-metal. In this way, not only can the original process flow in the semiconductor device formation be maintained, but the uniformity of the metal density in the semiconductor structure can also be adjusted through the virtual metal ring 122 (or metal structure 122a), ensuring the consistency and stability of the circuit.
[0054] In addition, since the size of the metal structure 122a in the Z-axis direction is larger than that of the pseudo-metal 123 in the Z-axis direction, the metal structure 122a blocks cracks that extend along the Y-axis direction, preventing further crack propagation and improving the wafer's resistance to crack intrusion during the dicing process, resulting in a higher yield of semiconductor devices.
[0055] In some embodiments, please refer to Figure 5 In the Y-axis direction, the dimensions of the metal structure 122a in the Z-axis direction of the multiple virtual metal rings 122 decrease sequentially.
[0056] In this way, because the metal structure 122a, which is far from the outer side of the chip region 11, is larger, the virtual metal ring 122 (i.e., metal structure 122a) on the outer side can absorb more energy during crack propagation during wafer dicing, thus effectively blocking the intrusion of large cracks; the metal structure 122a, which is closer to the inner side of the chip region 11, is smaller, thus effectively blocking small cracks that propagate to the inner side, thereby improving the yield of semiconductor devices.
[0057] Furthermore, since the size of the metal structure 122a in the multiple virtual metal rings 122 arranged along the Y-axis gradually decreases in the Z-axis direction, that is, the closer the metal structure 122a is to the chip region 11, the closer the size of the metal structure 122a is to the pseudo-metal 123; in this way, the stress concentration can be gradually reduced, making the stress distribution more uniform.
[0058] In some embodiments, the shape of the metal structure 122a includes a concave shape, a strip shape, a polygon shape, an H shape, and an I-shaped shape.
[0059] In this embodiment of the disclosure, please refer to Figure 4 The shape of the metal structure 122a is elongated, which makes the virtual metal ring 122 (i.e., metal structure 122a) more uniformly stressed, easier to absorb and consume the mechanical energy introduced by the cutting process, and reduces the mechanical damage to the chip area 11 caused by cutting.
[0060] In this embodiment of the disclosure, please refer to Figure 6The metal structure 122a is U-shaped, and the metal structures 122a in two adjacent virtual metal rings 122 are riveted together, which can block and extend the path of crack propagation.
[0061] In this embodiment of the disclosure, please refer to Figure 7 The metal structure 122a is I-shaped, and the metal structures 122a in two adjacent virtual metal rings 122 are riveted together, thereby blocking and extending the path of crack propagation.
[0062] It should be noted that, within the same metal layer, the shapes of the metal structures 122a in multiple virtual metal rings 122 can be different; please refer to... Figure 5 In the two innermost virtual metal rings 122, the metal structure 122a is elongated, while in the remaining six virtual metal rings 122, the metal structure 122a is U-shaped. Furthermore, within the same virtual metal ring 122, the structures of multiple metal structures 122a can be different; for example, within the same virtual metal ring 122, the structures of multiple metal structures 122a can be alternating H-shapes and elongated shapes.
[0063] It should also be noted that the virtual metal 122a located at the corner of the virtual metal ring 122 can be located on one of the two adjacent sides of the virtual metal ring, or it can be located on both adjacent sides of the virtual metal ring at the same time (i.e., the bend has a certain angle).
[0064] In other embodiments, the shape of the metal structure 122a may also be other suitable shapes, and this disclosure is not limiting in this regard.
[0065] In some embodiments, the projection of the metal structure 122a in the virtual metal ring 122 in the Z-axis direction overlaps with the projection of the metal structure 122a in the Z-axis direction of the adjacent virtual metal ring 122.
[0066] For example, please refer to Figure 5 and Figure 6 The shape of the metal structure 122a includes a concave shape, and the projection of this concave shape in the Z-axis direction overlaps with the projection portion of the metal structure 122a in the adjacent virtual metal ring 122 in the Z-axis direction. Thus, the metal structures 122a in the two adjacent virtual metal rings 122 are riveted together.
[0067] For example, please refer to Figure 7 The metal structure 122a has an I-shaped shape, and the projection of the I-shape in the Z-axis direction overlaps with the projection of the metal structure 122a in the adjacent virtual metal ring 122 in the Z-axis direction. Thus, the metal structures 122a in the two adjacent virtual metal rings 122 are riveted together.
[0068] In this way, not only can the propagation path of cracks be blocked and extended, but the number of rivet points between two adjacent metal structures 122a can also be increased, making the metal structures 122a closer and stronger, thereby improving the strength and stability of the overall structure. At the same time, the rivet points can serve as stress dispersion points, reducing stress concentration at individual locations and further improving the structure's resistance to damage.
[0069] In some embodiments, please refer to Figure 8 Within the same virtual metal ring 122, the projection of metal structure 122a along the Y-axis partially overlaps with the projection of adjacent metal structure 122a along the Y-axis. This increases the path and complexity of crack propagation, requiring the crack to continuously change direction during propagation. During this process, the crack's energy continuously decreases, thus hindering crack propagation.
[0070] In some embodiments, please refer to Figure 9 and Figure 10 ,in, Figure 9 A perspective view of virtual metal rings in two metal layers is shown. In two adjacent metal layers 120, the metal structures 122a in the virtual metal ring 122 are arranged alternately with the metal structures 122a in the virtual metal ring 122 adjacent to each other along the X-axis.
[0071] Please refer to Figure 9 and Figure 10 The projection of the metal structure 122a in the virtual metal ring 122 onto the adjacent metal layer 120 (i.e., the X-axis direction) covers the gap between two metal structures 122a' in adjacent virtual metal rings 122' along the X-axis direction. This prevents cracks from passing through the virtual metal ring along the X-axis direction, ensuring the reliability of the virtual metal ring 122 in blocking cracks.
[0072] In this embodiment of the disclosure, please refer to Figure 9 In this design, the riveting directions of the metal structures in two adjacent virtual metal rings along the X-axis are opposite; for example, the riveting direction (i.e., the opening) of metal structure 122a in virtual metal ring 120 faces the opposite direction of the Y-axis; the riveting direction (i.e., the opening) of metal structure 122a' in virtual metal ring 120' faces the Y-axis. Thus, when a crack propagates between different metal layers, the crack propagation path becomes more complex due to the opposite riveting directions of the metal structures in adjacent virtual metal rings. This increases the difficulty of crack propagation, thereby slowing down the crack propagation rate and reducing the number of cracks.
[0073] In some embodiments, please refer to Figure 10 and Figure 11The semiconductor device 100 also includes: a plurality of metal vias 130 connected between two adjacent virtual metal rings 122; the plurality of metal vias 130 are staggered in the Y-axis direction.
[0074] In this embodiment, multiple metal vias 130 are staggered in the Y-axis direction, which increases the path when the crack expands in the X-axis and Y-axis directions, helps to consume the energy of crack propagation, thereby reducing the speed of crack propagation and increasing the difficulty of crack propagation.
[0075] In this embodiment of the disclosure, the materials of the metal structure 122a, the pseudo-metal 123, the sealing ring 121, and the metal via 130 include: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polycrystalline silicon, or any combination thereof.
[0076] In some embodiments, please refer to Figure 10 The semiconductor device 100 further includes: a first isolation structure 140 and a second isolation structure 150; a sealing ring 121, a virtual metal ring 122 and a pseudo metal in the metal layer 120 are located in the first isolation structure 140; and a metal via 130 is located in the second isolation structure 150.
[0077] In this embodiment of the disclosure, the materials of the first isolation structure 140 and the second isolation structure 150 may be silicon oxide, silicon nitride, or silicon oxynitride, etc. The materials of the first isolation structure 140 and the second isolation structure 150 may be the same or different. For example, the material of the first isolation structure 140 may be silicon oxide, and the material of the second isolation structure 150 may be silicon nitride.
[0078] In this embodiment, by designing different structures and arrangements of dummy metal to form a virtual metal ring 122, and adjusting the arrangement of metal vias 130, the complexity of the crack propagation path during wafer dicing is increased, effectively increasing the intrusion path of cracks during wafer dicing, thereby preventing cracks from propagating to the chip area and improving the yield of semiconductor devices after dicing.
[0079] In addition, since the virtual metal ring 122 is located inside and / or outside the sealing ring 121, that is, the virtual metal ring 122 is located at the edge of the semiconductor device, it will affect the process window and bonding steps of processes such as chemical mechanical polishing (CMP), resulting in a higher manufacturing yield of the semiconductor device.
[0080] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.
[0081] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.
[0082] The above are merely some embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, The semiconductor device comprises: a chip region and a peripheral region surrounding the chip region; the peripheral region comprises a plurality of metal layers stacked along a first direction, each of the metal layers comprising: a sealing ring surrounding the outside of the chip region; a plurality of discontinuous virtual metal rings located in turn inside and / or outside the sealing ring; in the same metal layer, the metal structures in adjacent two of the virtual metal rings are staggered in a second direction; the first direction is perpendicular to the plane in which the metal layers are located, and the second direction is the direction close to the chip region in the plane in which the metal layers are located.
2. The semiconductor device of claim 1, wherein: in the second direction, the size of the metal structures in the plurality of virtual metal rings in a third direction decreases in turn; the third direction is the extension direction of the side of the metal structure.
3. The semiconductor device of claim 1, wherein The shape of the metal structure includes concave shape, long strip shape, H shape, I shape.
4. The semiconductor device of claim 2, wherein: the projection of the metal structure in the third direction in the virtual metal ring partially overlaps the projection of the metal structure in the third direction in the adjacent virtual metal ring.
5. The semiconductor device of claim 1, wherein: in the same virtual metal ring, the projection of the metal structure in the second direction partially overlaps the projection of the adjacent metal structure in the second direction.
6. The semiconductor device of claim 1, wherein: in adjacent two of the metal layers, the metal structures in the virtual metal rings are staggered with the metal structures in the virtual metal rings adjacent in the first direction.
7. The semiconductor device of claim 2, wherein The semiconductor device further comprises: a plurality of metal vias connected between adjacent two of the virtual metal rings; a plurality of the metal vias are staggered in the second direction.
8. The semiconductor device of claim 7, wherein, The metal layer further comprises: a plurality of dummy metals located inside the sealing ring and the virtual metal ring, and outside the sealing ring and the virtual metal ring; the size of the metal structure in the third direction is greater than the size of the dummy metal in the third direction.
9. The semiconductor device of claim 8, wherein, The semiconductor device further comprises: a first isolation structure and a second isolation structure; the sealing ring, the virtual metal ring and the dummy metal in the metal layer are located in the first isolation structure; the metal via is located in the second isolation structure.
10. The semiconductor device of claim 2, wherein: the chip region comprises a chip; the metal layers in the peripheral region are located in the same layer as the metal interconnection layer in the chip; the peripheral region comprises at least a sealing ring region and a scribe lane region; wherein the sealing ring is arranged on the sealing ring region.