Semiconductor device

Abstract

The utility model provides a semiconductor device. The semiconductor device comprises a semiconductor substrate, an inner connecting line and at least one heat through hole. The semiconductor substrate includes at least one active member. An interconnect is disposed over and electrically coupled to the at least one active member. At least one thermal via passes through the interconnect and is thermally coupled to the at least one active member, wherein a thermal conductivity of the at least one thermal via is different from a thermal conductivity of the dielectric layer in the interconnect.

Description

Technical Field

[0001] This utility model relates to a semiconductor device. Background Technology

[0002] The miniaturization of semiconductor devices and electronic components has made it possible to integrate more devices and components into a given volume, and to achieve high integration density for various semiconductor devices and / or electronic components. Utility Model Content

[0003] This invention provides a semiconductor device, comprising: a semiconductor substrate including at least one active component; an interconnect disposed on the at least one active component and electrically coupled to the at least one active component; and at least one thermal via penetrating the interconnect and thermally coupled to the at least one active component, wherein the thermal conductivity of the at least one thermal via is different from the thermal conductivity of the dielectric layer of the interconnect.

[0004] This invention provides a semiconductor device, comprising: a redistribution circuit structure; a die stack disposed above and electrically coupled to the redistribution circuit structure, and comprising: a first layer comprising: a first substrate including at least one first active component; and a first interconnect disposed above and electrically coupled to the at least one first active component; and a second layer disposed above and electrically coupled to the first layer, and comprising: a second substrate including at least one second active component; and a second interconnect disposed above and electrically coupled to the at least one second active component; wherein the first layer is between the second layer and the redistribution circuit structure; and at least one thermal control component disposed above the redistribution circuit structure and thermally coupled to the die stack, and comprising: at least one thermal via extending vertically inside the die stack, wherein the thermal conductivity of the at least one thermal via is different from the thermal conductivity of the dielectric layer of the first interconnect and the thermal conductivity of the dielectric layer of the second interconnect. Attached Figure Description

[0005] The various aspects of the embodiments of this utility model are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0006] Figures 1 to 21 Schematic cross-sectional views are shown of various stages in a method of manufacturing a semiconductor device according to some embodiments of this disclosure.

[0007] Figures 22 to 27 Semiconductor devices according to alternative embodiments of the present disclosure are shown respectively.

[0008] Figure 28 and Figure 31 A schematic plan view showing the positioning architecture of hot spots and thermal control components included in a semiconductor device according to various embodiments of the present disclosure.

[0009] Figures 32 to 37 Schematic three-dimensional side views of various architectures of thermal vias according to some embodiments of this disclosure are shown respectively.

[0010] Figures 38 to 41 Schematic cross-sectional views are shown of various stages in a method of manufacturing a semiconductor device according to some embodiments of this disclosure.

[0011] Figures 42 to 43 Semiconductor devices according to alternative embodiments of the present disclosure are shown respectively.

[0012] Figure 44 A schematic cross-sectional view illustrating the application of a semiconductor device according to some embodiments of this disclosure.

[0013] [Icon Symbol Explanation]

[0014] 10, 20, 30: Semiconductor dies;

[0015] 40A, 40B, 40C, 1000, 2000: Stacking units;

[0016] 50: Carrier;

[0017] 52, 206, 510, 5101, 5102, 5103, 5104, 510 N-3 510 N-2 510 N-1 510 N 15101, 15102, 1600, 1700, 6001, 6002, 6003: Dielectric layer;

[0018] 54: Supporting substrate;

[0019] 56: Release layer;

[0020] 110, 130, 150: Padding;

[0021] 120, 140, 160: Through holes;

[0022] 200A, 200B: Substrate;

[0023] 202: Semiconductor substrate;

[0024] 204: Isolation structure;

[0025] 208: Contact plug;

[0026] 300: Transistor;

[0027] 310: Gate structure;

[0028] 312: Gate electrode;

[0029] 314: Gate dielectric layer;

[0030] 316: Gate spacer;

[0031] 320: Source / Drain region;

[0032] 330: Well Area

[0033] 400A, 400B, 400C, 400D, 400E, 400F: Thermal conductive components, thermal control components;

[0034] 410, 412, 414, 416, 420, 422, 424: Thermal control unit;

[0035] 500: Internal connection;

[0036] 520, 5201, 5202, 5203, 5204, 520 N-3 520 N-2 520 N-1 520 N 15201, 15202: Seed layers;

[0037] 530, 5301, 5302, 5303, 5304, 530 N-3 530 N-2 530 N-1 530 N 15301, 15302: Conductive layers;

[0038] 710, 720: Thermally conductive adhesive;

[0039] 800: Cover;

[0040] 900: Radiator;

[0041] 1001, 1002, 1003: Perforation;

[0042] 1500: Re-layout circuit structure;

[0043] 1800: Conductive terminal;

[0044] 1800c: Conductive component;

[0045] 1800u: Raised metal pattern, UBM pattern;

[0046] 1900, 1910, 1920: Insulating encapsulation;

[0047] 4010, 4020: Thermal energy storage materials;

[0048] 4010C, 4030C, 4040C: Core section;

[0049] 4010S, 4030S, 4040S: Outer casing;

[0050] 6201, 6202, 6203: Bonding layers;

[0051] 6400, 6401, 6402, 6403: High thermal conductivity layers;

[0052] 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000: Semiconductor devices;

[0053] C1: First component;

[0054] C2: Second component;

[0055] CT: Terminal;

[0056] DL1, DL1', DL2, DL2', DL3, DL4, DL N-3 DL N-2 DL N-1 DL N Dielectric structure;

[0057] IF1, IF2, IF3, IF4, IF5: Joining interfaces;

[0058] L1: Construction layer, first construction layer;

[0059] L2: Construction layer, second construction layer;

[0060] L3: Construction layer, third construction layer;

[0061] L4: Construction layer, fourth construction layer;

[0062] L N-1 : Construction layer, the (N-1)th construction layer;

[0063] L N-2 : Construction layer, the (N-2)th construction layer;

[0064] L N-3 : Construction layer, the (N-3)th construction layer;

[0065] L N: Construction layer, the (N)th construction layer;

[0066] L1', L2': Construction layers;

[0067] ML1, ML1', ML2, ML2', ML3, ML4, ML N-3 ML N-2 ML N-1 ML N Metallization layer;

[0068] OP1, OP2: Openings;

[0069] S50, S50B, S52, S110, S120, S130, S140, S150, S160, S206, S410, S420, S510 N S520 N S530 N S800, S1001, S1900b, S1900t: Surface;

[0070] S202A, S202B, S202: Rear surface;

[0071] S500, S1002, S1003, S6001, S6002, S6003, S6201, S6202, S6203: The top surface shown;

[0072] SC: Component assembly;

[0073] T1: First level;

[0074] T2: Second level;

[0075] T3: Third level;

[0076] UF: Bottom filler adhesive;

[0077] W1, W1', W2, W2', W3, W3': Circuit chips;

[0078] X, Y, Z: Direction. Detailed Implementation

[0079] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components, values, operations, materials, arrangements, or similar elements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or similar elements are contemplated. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0080] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0081] In addition, for ease of explanation, terms such as "first," "second," "third," and "fourth" may be used in this document to describe similar or different components or features illustrated in the figure, and may be used interchangeably depending on the order of their existence or the context of the description.

[0082] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms (e.g., those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant art and this disclosure, and shall not be interpreted as having an idealized or overly formal meaning unless expressly defined herein.

[0083] This disclosure may also include other features and processes. For example, test structures may be included to aid in the verification testing of three-dimensional (3D) packages or three-dimensional integrated circuit (3DIC) devices. These test structures may, for example, include test pads formed in redistribution layers or on a substrate to enable testing of 3D packages or 3DIC devices, use of probes and / or probe cards, and similar operations. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with testing methods including intermediate verification of known good dies to improve yield and reduce costs.

[0084] It should be understood that the following embodiments of this disclosure provide feasible concepts that can be implemented in a wide variety of specific contexts. The specific embodiments described herein relate to semiconductor devices (or semiconductor packages or semiconductor structures) with a multi-level stacked structure, each level including at least one semiconductor die or chip, and are not intended to limit the scope of this disclosure. Due to the use of thermal control components with thermal energy storage materials in the interconnects of one or more levels of the stacked structure, the thermal management of the semiconductor device is well controlled. That is, heat dissipation of hot spots in the semiconductor device is greatly improved, resulting in better reliability of the semiconductor device. In the embodiments of this disclosure, thermal control components with thermal energy storage materials can be disposed within the interconnects of one or more levels in the stacked structure, wherein each thermal control component with thermal energy storage material may include a vertical portion and a horizontal portion connected to the vertical portion, wherein the thermal control component with thermal energy storage material can be formed as one or more dielectric layers through the interconnects of one or more levels of the stacked structure. In a non-limiting example, the vertical portion of the thermal control component with thermal energy storage material can be in the form of a pillar or columnar shape adjacent to or surrounding a hot spot. In a non-limiting example, on the other hand, the horizontal portion of a thermal control assembly with thermal energy storage material can be in the form of a segment, slab, or plate shape adjacent to or overlapping a hot spot. This disclosure is not limited to the embodiments disclosed herein; in particular, this disclosure can take the form of any combination of vertical and horizontal portions of the thermal control assembly with thermal energy storage material mentioned herein.

[0085] In some embodiments, the manufacturing method is part of a wafer-level packaging process. It should be understood that additional processes may be provided before, during, and after the illustrated methods, and only a few other processes may be briefly described herein. In this disclosure, it should be understood that the illustrations of components in all figures are schematic and not drawn to scale. In all the various views and illustrative embodiments of this disclosure, components similar to or substantially identical to those previously illustrated will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated. For clarity of illustration, the figures are illustrated using orthogonal axes (X, Y, and Z) of a Cartesian coordinate system, according to which the views are oriented; however, this disclosure is not specifically limited thereto.

[0086] Figures 1 to 21 These are schematic cross-sectional views of various stages of a method for manufacturing a semiconductor device (e.g., 10000A) according to some embodiments of this disclosure. Figures 22 to 27 Schematic cross-sectional views of semiconductor devices (e.g., 10000B, 10000C, 10000D, 10000E, 10000F, 10000G) according to alternative embodiments of the present disclosure are shown respectively. Figure 28 and Figure 31 The disclosure illustrates schematic diagrams of the positioning architecture of hot spots (e.g., 300, or the like) and thermal control components (e.g., 400A, 400B, 400C, 400D, 400E, or 400F) included in a semiconductor device according to various embodiments of the present disclosure. Figure 28 and Figure 31 This is a schematic plan view showing the positioning architecture of hot spots (e.g., hot spot 300 or the like) and thermal control components (e.g., 400A, 400B, 400C, 400D, 400E or 400F) included in a semiconductor device according to various embodiments, wherein the schematic plan view shows the relative positions of various locations of the hot spots (e.g., hot spot 300 or the like) and thermal control components (e.g., 400A, 400B, 400C, 400D, 400E or 400F). Figures 32 to 37 Schematic three-dimensional side views of various architectures of thermal vias (e.g., 410, 412, 414, 416) according to some embodiments of this disclosure are shown respectively. The embodiments are intended to provide further illustration but are not intended to limit the scope of this disclosure.

[0087] refer to Figure 1In some embodiments, a substrate 200A is provided. For example, substrate 200A includes multiple components of various types (also referred to as semiconductor components) formed in a semiconductor substrate 202, such as... Figure 1 As shown. The plurality of components may include active components, passive components, or combinations thereof. The plurality of components may include integrated circuit (IC) devices. The plurality of components may include transistors, capacitors, resistors, diodes, photodiodes, fuse devices, jumpers, sensors, or other similar devices. The functions of the plurality of components may include memory, processors, sensors, amplifiers, power distribution, input / output circuit systems, etc. The plurality of components may be referred to individually as the semiconductor components disclosed herein.

[0088] In some embodiments, the semiconductor substrate 202 includes a bulk semiconductor substrate, a crystalline silicon substrate, a doped semiconductor substrate (e.g., a p-type semiconductor substrate or an n-type semiconductor substrate), a semiconductor-on-insulator (SOI) substrate, or the like. In some embodiments, the semiconductor substrate 202 includes one or more doped regions or various types of doped regions, depending on requirements and / or product design requirements / layout. In some embodiments, the doped regions are doped with p-type dopants and / or n-type dopants. For example, the p-type dopant is boron or BF2, and the n-type dopant is phosphorus or arsenic. The doped regions can be configured as n-type metal-oxide-semiconductor (NMOS) transistors or p-type metal-oxide-semiconductor (PMOS) transistors. The semiconductor substrate 202 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed over an insulating layer. The insulating layer is, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The semiconductor substrate 202 may also use other substrates, such as multilayer substrates or gradient substrates. In some alternative embodiments, the semiconductor substrate 202 comprises a semiconductor substrate made of other suitable elemental semiconductors, such as diamond or germanium; suitable compound semiconductors, such as gallium arsenide, silicon carbide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; suitable alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; or combinations thereof. For example, the semiconductor substrate 202 is a bulk silicon substrate.

[0089] like Figure 1As shown, the plurality of components (e.g., one or more transistors 300) may be formed in the semiconductor substrate 202. In some embodiments, a plurality of isolation structures 204 are formed in the semiconductor substrate 202 to separate the transistors 300. In some embodiments, the isolation structure 204 is a trench isolation structure. In other embodiments, the isolation structure 204 includes a local oxidation of silicon (LOCOS) structure. In some embodiments, the insulating material of the isolation structure 204 includes silicon oxide, silicon nitride, silicon oxynitride, spin-coated dielectric material, or a low-k dielectric material. For example, a low-k dielectric material typically has a dielectric constant below 3.9. In one embodiment, the insulating material can be formed via chemical vapor deposition (CVD) (such as high-density plasma CVD (HDP-CVD) and sub-atmospheric CVD (SACVD)) or by spin-on coating. In some embodiments, components (e.g., transistor 300) and isolation structures 204 are formed in the substrate 200A during a front-end-of-line (FEOL) process. In one embodiment, transistor 300 is formed following a complementary MOS (CMOS) process. The number and arrangement of components formed in the semiconductor substrate 202 should not be limited to the embodiments or figures disclosed herein. That is, the number of components may be more than two. It should be understood that, depending on the product design, the number and arrangement of components may have different materials or configurations.

[0090] Transistor 300 can be a PMOS transistor independently. For example, each of transistors 300 includes a gate structure 310 and a plurality of source / drain regions 320 located on two opposite sides of the gate structure 310, wherein the gate structure 310 is formed on an n-well region 330, and the source / drain regions 320 are formed within the n-well region 330. In one embodiment, the gate structure 310 includes a gate electrode 312, a gate dielectric layer 314, and a gate spacer 316. The gate dielectric layer 314 may extend between the gate electrode 312 and the semiconductor substrate 202, and may or may not further cover the sidewalls of the gate electrode 312. The gate spacer 316 may laterally surround the gate electrode 312 and the gate dielectric layer 314. In one embodiment, the source / drain region 320 includes a plurality of p-type doped regions formed in the n-well region 330 by ion implantation. In an alternative embodiment, the source / drain region 320 includes a plurality of epitaxial structures formed in and protruding from the surface of the semiconductor substrate 202 by epitaxial growth.

[0091] Alternatively, transistor 300 includes a gate structure 310 and a plurality of source / drain regions 320 located on two opposite sides of the gate structure 310, wherein the gate structure 310 is formed on a p-well region 330, and the source / drain regions 320 are formed within the p-well region 330. In one embodiment, the gate structure 310 includes a gate electrode 312, a gate dielectric layer 314, and a gate spacer 316. The gate dielectric layer 314 may extend between the gate electrode 312 and the semiconductor substrate 202, and may or may not further cover the sidewalls of the gate electrode 312. The gate spacer 316 may laterally surround the gate electrode 312 and the gate dielectric layer 314. In one embodiment, the source / drain regions 320 include a plurality of n-type doped regions formed in the p-well region 330 by ion implantation. In an alternative embodiment, the source / drain region 320 includes a plurality of epitaxial structures formed in and protruding from the surface of the semiconductor substrate 202 by epitaxial growth.

[0092] In a non-limiting example, all transistors 300 may have the same type. For example, all transistors 300 may be NMOS transistors. Or, for another example, all transistors 300 may be PMOS transistors. This disclosure is not limited thereto. In yet another non-limiting example, one or some of the transistors 300 may have a different type than the rest of the transistors 300. For example, one or some of the transistors 300 may be NMOS transistors, while the rest may be PMOS transistors, or vice versa.

[0093] In some embodiments, some or all of the transistors 300 may be logic components or part of a logic component, and may or may not interact with each other. Furthermore, at least some of the transistors 300 may be memory components or part of a memory component, and may or may not interact with each other. The memory component may be, for example, static random-access memory (SRAM), wherein the transistors 300 used as logic components and the transistors 300 used as memory components are electrically coupled and electrically communicated.

[0094] For illustrative purposes, transistor 300 is shown in the form of a planar transistor; however, this disclosure is not limited thereto. Transistor 300 may independently be a field-effect transistor (FET), such as a planar FET, tunnel field-effect transistor (TFET), or fin-type FET (FINFET); a gate-all-around (GAA) transistor; a nanosheet transistor; a nanowire transistor; the like; or a combination thereof, depending on requirements and / or product design requirements / layout. According to some embodiments, transistor 300 may be a planar FET and / or TFET device or part of a planar FET and / or TFET device, which may include a silicon body standing on a substrate and a gate standing on the silicon body (i.e., the channel region) to provide control from the top side of the channel region. According to some embodiments, transistor 300 may be a FinFET device or part of a FinFET device, which may include a thin (vertical) fin having a silicon body above a substrate and a gate wrapped around the fin (i.e., the channel region) to provide control from three sides of the channel region. According to some embodiments, transistor 300 may be a nanostructure transistor device (e.g., a GAA transistor device, a nanosheet transistor, or a nanowire transistor) or part of a nanostructure transistor device, which may include a gate structure surrounding (e.g., bonding) the periphery of one or more nanostructures (i.e., the channel region) to improve channel current control.

[0095] like Figure 1 As shown, for example, substrate 200A further includes a dielectric layer 206 stacked above semiconductor substrate 202 and a plurality of contact plugs 208 penetrating dielectric layer 206 and electrically connected to transistor 300. In some embodiments, dielectric layer 206 and contact plugs 208 are also formed in substrate 200A during FEOL process. Dielectric layer 206 may laterally surround gate structure 310 and cover source / drain region 320 to provide protection for components formed on / in semiconductor substrate 202. Some of contact plugs 208 may penetrate dielectric layer 206 to establish electrical connection with source / drain region 320, while other portions of contact plugs 208 may partially penetrate dielectric layer 206 to establish electrical connection with gate (e.g., gate 312) of gate structure 310, thereby providing a plurality of terminals for electrical connection to components (e.g., interconnects or interconnect structures) or external components formed laterally.

[0096] The dielectric layer 206 may be referred to as an interlayer dielectric (ILD) layer, and the contact plug 208 may be referred to as a metal contact or a metallized contact. For example, the contact plug 208 electrically connected to the source / drain region 320 is referred to as a source / drain contact, and the contact plug 208 electrically connected to the gate 312 is referred to as a gate contact. In some embodiments, the contact plug 208 may comprise copper (Cu), copper alloys, nickel (Ni), aluminum (Al), manganese (Mn), magnesium (Mg), silver (Ag), gold (Au), tungsten (W), combinations thereof, or similar materials. The contact plug 208 can be formed by processes such as plating, such as electroplating or electroless plating; CVD, such as plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD); combinations thereof; or similar processes. Throughout this specification, the term "copper" is intended to include substantially pure elemental copper, copper containing unavoidable impurities, and copper alloys containing small amounts of elements such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium.

[0097] In some embodiments, dielectric layer 206 comprises silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, spin-on glass (SOG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorinated silica glass (FSG), carbon-doped silicon oxide (e.g., SiCOH), polyimide, and / or combinations thereof. In alternative embodiments, dielectric layer 206 comprises a low-dielectric-constant dielectric material. For example, a low-dielectric-constant dielectric material generally has a dielectric constant below 3.9. Examples of low-dielectric-constant dielectric materials may include... (BLACK (Applied Materials of Santa Clara, California), Xerogel, Aerogel, Amorphous fluorinated carbon, Parylene, Benzocyclobutene (BCB), Flare (Dow Chemical, Midland, Michigan), hydrogen silsesquioxane (HSQ), or fluorinated silicon oxide (SiOF) and / or combinations thereof. It should be understood that dielectric layer 206 may comprise one or more dielectric materials. For example, dielectric layer 206 may comprise a monolayer or multilayer structure. In some embodiments, dielectric layer 206 is formed to a suitable thickness by CVD (e.g., flowable CVD (FCVD), HDP-CVD, and SACVD), spin coating, sputtering, or other suitable methods.

[0098] Seed layers (not shown) may be formed between dielectric layer 206 and contact plugs 208 as needed. That is, for example, the seed layer covers the bottom surface and sidewalls of each of the contact plugs 208. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer on top of the titanium layer. The seed layer is formed using, for example, PVD or a similar process. In one embodiment, the seed layer may be omitted.

[0099] Additionally, an additional barrier layer or adhesive layer (not shown) may be formed between the contact plug 208 and the dielectric layer 206, as needed. This additional barrier layer or adhesive layer prevents the seed layer and / or the contact plug 208 from diffusing into the underlying and / or surrounding layers. The additional barrier layer or adhesive layer may comprise Ti, TiN, Ta, TaN, combinations thereof, multilayers thereof, or similar materials, and may be formed using CVD, ALD, PVD, combinations thereof, or similar processes. In an alternative embodiment that includes a seed layer, the additional barrier layer or adhesive layer is sandwiched between the dielectric layer 206 and the seed layer, and the seed layer is sandwiched between the contact plug 208 and the additional barrier layer or adhesive layer. In one embodiment, the additional barrier layer or adhesive layer may be omitted.

[0100] like Figure 1As shown, for example, substrate 200A further includes a plurality of through vias 1001. In some embodiments, through vias 1001 are formed laterally adjacent to transistor 300 and perpendicularly through dielectric layer 206, extending further into the semiconductor substrate 202. In some embodiments, each through via 1001 includes a liner 110 and a conductive via 120, wherein the bottom and sidewalls of the conductive via 120 are lined by the liner 110. That is, the conductive via 120 of through via 1001 is separated from the semiconductor substrate 202 and dielectric layer 206 through the respective liner 110. In some embodiments, through via 1001 may taper gradually from dielectric layer 206 to semiconductor substrate 202. Alternatively, through via 1001 may have substantially vertical sidewalls. In a cross-sectional view along direction Z, the shape of through via 1001 may depend on requirements and / or product design requirements / layouts, and is not limited to this disclosure. Additionally, in the top view (planar view) on the XY plane, the through-hole 1001 is circular. However, depending on requirements and / or product design requirements / layout, the shape of the through-hole 1001 can be elliptical, rectangular, polygonal, or a combination thereof; this disclosure is not limited thereto. In some embodiments, the through-hole 1001 is not exposed in an accessible manner by the back surface S202 of the semiconductor substrate 202, but can be exposed in an accessible manner by the surface S206 of the dielectric layer 206. This disclosure does not limit the number of through-holes 1001, which can be selected and specified according to requirements and / or product design requirements / layout.

[0101] The via 120 may be formed of a conductive material, such as copper, tungsten, aluminum, silver, combinations thereof, or the like. The pad 110 may be formed of a barrier material, such as TiN, Ta, TaN, Ti, or the like. In alternative embodiments, dielectric pads (not shown) (e.g., silicon nitride, oxides, polymers, combinations thereof) may also be selectively formed between the pad 110 and the semiconductor substrate 202, and between the pad 110 and the dielectric layer 206. Alternatively, the pad 110 may be omitted.

[0102] The pad 110, via 120, and optional dielectric pad can be formed, but not limited to, by forming a plurality of recesses in the dielectric layer 206 and the semiconductor substrate 202; depositing optional dielectric, barrier, and conductive materials into the plurality of recesses; and removing excess material above the plane containing the indicated top opening of the plurality of recesses. For example, the plurality of recesses are padded with optional dielectric pads to laterally separate the semiconductor substrate 202 and the dielectric layer 206 from the pad 110 padded with the sidewalls of the via 120 and the indicated bottom surface. In some embodiments, the via 1001 is formed using a via-first method. In such embodiments, the via 1001 is formed before the interconnect (e.g., 500) is formed. Alternatively, the via 1001 can be formed using a via-last method, which can be used after the interconnect (e.g., 500) is formed.

[0103] In some embodiments, the semiconductor substrate 202 is in wafer or panel form when considered as a top view or plan view (e.g., XY plane) along direction Z. The semiconductor substrate 202 may be in the form of a wafer with a size of about 4 inches or greater. The semiconductor substrate 202 may be in the form of a wafer with a size of about 6 inches or greater. The semiconductor substrate 202 may be in the form of a wafer with a size of about 8 inches or greater. Alternatively, the semiconductor substrate 202 may be in the form of a wafer with a size of about 12 inches or greater. Transistors 300 formed in the substrate 200A may be arranged in an array along directions X and Y. Directions X, Y, and Z may be different from each other. For example, direction X is perpendicular to direction Y, and directions X and Y are independently perpendicular to direction Z, such as... Figure 1 As shown. In this disclosure, direction Z can be referred to as the stacking direction, and the XY plane defined by directions X and Y can be referred to as a plan view or top view.

[0104] refer to Figure 2 In some embodiments, interconnects 500 are disposed above the semiconductor substrate 202 and the dielectric layer 206 of the substrate 200A. For example, interconnects 500 include a plurality of stacked build-up layers (e.g., L1, L2, L3, L4…). N-3 L N-2 L N-1 and L N In this disclosure, for illustrative purposes, interconnect 500 includes a first portion having four building layers (e.g., L1, L2, L3, and L4) and a portion having N-4 building layers (e.g., ..., L...).N-3 L N-2 L N-1 With L N The second part is stacked on top of and electrically connected to the first part, where N is greater than four. However, this disclosure is not limited thereto; alternatively, the first part may include one, two, three, four, or more building layers, and the second part may include one, two, three, four, or more building layers. The number of building layers included in the first part of interconnect 500 and the number of building layers included in the second part of interconnect 500 are selected and designed according to requirements and / or product design requirements / layout. In some embodiments, the first part is referred to as a local interconnect formed in a middle-end-of-line (MEOL) process, and the second part is referred to as a global interconnect formed in a back-end-of-line (BEOL) process.

[0105] Interconnect 500 can be electrically coupled to the plurality of components formed in the substrate 200A, such as Figure 2 As shown. That is, the interconnect 500 provides routing functionality for the plurality of components formed in the substrate 200A. In some embodiments, at least some of the plurality of components formed in the substrate 200A are electrically connected to each other through the interconnect 500 (e.g., a first portion of the interconnect 500), and are electrically connected to external electronic devices / components through the interconnect 500 (e.g., a second portion of the interconnect 500). Figure 2 As shown, the interconnect 500 includes one or more dielectric layers 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...). N-3 510 N-2 510 N-1 and 510 N ), or one or more seed layers 520 (e.g., 5201, 5202, 5203, 5204, ..., 520). N-3 520 N-2 520 N-1 And 520 N ) and one or more conductive layers 530 (e.g., 5301, 5302, 5303, 5304, ..., 530) N-3 530 N-2 530 N-1 And 530 NIn some embodiments, each seed layer 520 is padded with a corresponding conductive layer 530 (e.g., its sidewalls and bottom). In some embodiments, each conductive layer 530 (e.g., 5301, 5302, 5303, 5304, ..., 530...) N-3 530 N-2 530 N-1 And 530 N This includes line portions extending along a horizontal direction (e.g., direction X or direction Y), through-hole portions extending along a vertical direction (e.g., direction Z), and / or combinations thereof. Seed layers 520 (e.g., 5201, 5202, 5203, 5204, ..., 520...). N-3 520 N-2 520 N-1 And 520 N ) and the corresponding conductive layers 530 (e.g., 5301, 5302, 5303, 5304, ..., 530) N-3 530 N-2 530 N-1 And 530 N The interconnect 500 can be referred to as the metallization layer ML (e.g., ML1, ML2, ML3, ML4, ..., ML). N-3 ML N-2 ML N-1 and ML N This can be a routing structure, or redistribution layer, used to provide routing functionality, and can be collectively referred to as the routing structure of interconnect 500. Dielectric layers 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...) N-3 510 N-2 510 N-1 and 510 N The dielectric structure of interconnect 500 can be collectively referred to as the interconnect 500, and is used to provide protection for the routing structure, metallization layer or redistribution layer of interconnect 500.

[0106] A dielectric layer and a corresponding metallization layer can be considered together as a building block of interconnect 500 (e.g., 5101, 5201 and 5301; 5102, 5202 and 5302; 5103, 5203 and 5303; 5104, 5204 and 5304; ...; 510...). N-3 520 N-3 With 530 N-3 510 N-2 520 N-2 With 530 N-2 510N-1 520 N-1 With 530 N-1 510 N 520 N With 530 N ).like Figure 2 As shown, for example, the topmost layer of seed layer 520 (e.g., 520) N ) and the topmost layer of conductive layer 530 (e.g., 530) N It can be transmitted through the topmost layer of dielectric layer 510 (e.g., 510). N The interconnect 500 is exposed in a tangible manner for external connectivity. In some embodiments, the metallization layers ML1 to ML2 of the interconnect 500 are... N The line dimensions (e.g., thickness and width) gradually increase along the direction from substrate 200A to interconnect 500.

[0107] However, this disclosure is not limited thereto; as an alternative, the seed layer 520 can be omitted. In such an alternative embodiment, the conductive layer 530 (e.g., 5301, 5302, 5303, 5304, ..., 530...) N-3 530 N-2 530 N-1 And 530 N The metallization layer ML, which can be referred to as interconnect 500 (e.g., ML1, ML2, ML3, ML4, ..., ML), can be referred to as interconnect 500. N-3 ML N-2 ML N-1 and ML N A dielectric layer or redistribution layer is used to provide routing functionality and can be collectively referred to as the routing structure of the interconnect 500. A dielectric layer and a corresponding metallization layer can be considered together as a building block of the interconnect 500 (e.g., 5101 and 5301; 5102 and 5302; 5103 and 5303; 5104 and 5304; ...; 510...). N-3 With 530 N-3 510 N-2 With 530 N-2 510 N-1 With 530 N-1 510 N With 530 N ).

[0108] In some embodiments, the interconnect 500 may be formed by (but is not limited to) forming a blanket of a first dielectric material over dielectric layer 206; patterning the first dielectric material blanket to form dielectric layer 5101 having a plurality of first openings (not shown) therethrough, the plurality of first openings allowing access to portions of vias 1001 and components such as transistors 300; optionally forming a blanket of a first seed layer material over dielectric layer 5101, the first seed layer material blanket extending into the plurality of first openings to pad the plurality of... The first opening contacts the portion of the exposed perforation 1001 and the portion of the component such as transistor 300; a first conductive material blanket is formed on the first seed layer material blanket, the first conductive material blanket filling the plurality of first openings; excess of the first seed layer material blanket and excess of the first conductive material blanket above the indicated top surface of dielectric layer 5101 are removed to form a metallization layer ML1 including seed layer 5201 and conductive layer 5301, thereby forming a building layer L1 (e.g., a first building layer L1 including 5101, 5201 and 5301). A second dielectric material blanket is formed over a first building layer L1; the second dielectric material blanket is patterned to form a dielectric layer 5102, the dielectric layer 5101 having a plurality of second openings (not shown) extending therethrough, the plurality of second openings allowing access to portions of the metallization layer ML1; a second seed layer material blanket is optionally formed over the dielectric layer 5102, the second seed layer material blanket extending into the plurality of second openings to pad the plurality of second openings and contact the exposed portions of the metallization layer ML1; a second conductive material blanket is formed over the second seed layer material blanket, the second conductive material blanket filling the plurality of second dielectric layers L1. Two openings; remove excess second seed layer material blanket and excess second conductive material blanket above the indicated top surface of dielectric layer 5102 to form a metallization layer ML2 including seed layer 5202 and conductive layer 5302, thereby forming a building layer L2 (e.g., a second building layer L2 including 5102, 5202 and 5302); then repeat the formation steps of forming the first and / or second building layers to form the remaining building layers (e.g., third building layer L3 (e.g. including 5103, 5203 and 5303), fourth building layer L4 (e.g. including 5104, 5204 and 5304), ..., the (N-3)th building layer L). N-3 (For example, including 510) N-3 520 N-3 and 530 N-3 ), the (N-2)th building layer L N-2 (For example, including 510) N-2 520N-2 and 530 N-2 ), the (N-1)th building layer L N-1 (For example, including 510) N-1 520 N-1 and 530 N-1 ), and the (N)th building layer L N (For example, including 510) N 520 N and 530 N At this point, the interconnect 500 has been fabricated. The interconnect 500 can be formed on the substrate 200A using a single-damascene or dual-damascene process. This disclosure is not limited thereto.

[0109] In some embodiments, dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510) N-3 510 N-2 510 N-1 and 510 N The material can be polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), nitrides (e.g., silicon nitride), oxides (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), borosilicate glass (BPSG), combinations thereof, or similar materials, which can be patterned using photolithography and / or etching processes. Alternatively, the dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...) N-3 510 N-2 510 N-1 and 510 N The material can be aluminum nitride (AlN), boron nitride (BN), diamond-like carbon, Al2O3, or BeO. The etching process can include dry etching, wet etching, or a combination thereof. After the etching process, a cleaning step can be optionally performed, for example, to clean and remove residues generated by the etching process. In some embodiments, the dielectric material blanket is formed using suitable fabrication techniques such as spin coating, CVD (e.g., PECVD), etc. For example, the material of dielectric layer 5101 is silicon oxide. In one embodiment, dielectric layers 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...) are... N-3 510 N-2 510 N-1 and 510 NThe materials of the dielectric layers 510 and 5102 are the same. Alternatively, the dielectric layers 510 (e.g., 5101, 5102, 5103, 5104, ..., 510) are made of the same material. N-3 510 N-2 51 0N-1 and 510 N The materials may be partially or completely different from each other.

[0110] Formed on dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510). N-3 510 N-2 510 N-1 and 510 N The openings in each of the dielectric layers 510 may include a trenchhole and a viahole located below the trenchhole and spatially connected to it. The lateral dimension of the trenchhole may be larger than the lateral dimension of the viahole. In some embodiments, the sidewalls of each viahole are sloping sidewalls. In alternative embodiments, the sidewalls of each viahole are vertical sidewalls. In some embodiments, the sidewalls of each trenchhole are sloping sidewalls. In alternative embodiments, the sidewalls of each trenchhole are vertical sidewalls. The sidewalls of a viahole and the corresponding sidewalls of a trenchhole may be collectively referred to in dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...). N-3 510 N-2 510 N-1 and 510 N A sidewall of an opening formed in the dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510). In some embodiments, the sidewall of an opening is formed in the dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510). N-3 510 N-2 510 N-1 and 510 N Each of the openings formed in the dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 5105) contains a dual damascene structure. The formation of the openings is not limited by this disclosure. N-3 510 N-2 510 N-1 and 510 N The openings (with a dual damascene structure) formed in the dielectric layer 510 can be formed using any suitable molding process, such as a via-first method or a trench-first method. For illustrative purposes, the openings in the dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...) are shown below. N-3 510 N-2 510N-1 and 510 N The number of openings formed in the metallization layer ML (e.g., ML1, ML2, ML3, ML4, ..., ML) is not limited by this disclosure and can be specified and selected based on requirements and / or layout design requirements / layout. N-3 ML N-2 ML N-1 and ML N The portion formed in the trench or cavity can be referred to as a horizontally extending (e.g., extending along the X and / or Y directions) conductive line portion, wire, conductive trace, conductive metal wire, metallized line, route line, or redistribution line, and the metallization layer ML (e.g., ML1, ML2, ML3, ML4, ..., ML) N-3 ML N-2 ML N-1 and ML N The portion formed in a via hole can be referred to as a vertically extending (e.g., extending in the Z direction) via, metallized via, route via, or redistribution via.

[0111] In other alternative embodiments, the dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510) is used to form the dielectric layer 510. N-3 510 N-2 510 N-1 and 510 NThe dielectric material blanket layer comprises a two-layer structure, wherein the first dielectric layer includes a silicon carbide (SiC) layer, a silicon nitride (Si3N4) layer, an aluminum oxide layer, or the like, and the second dielectric layer (stacked above the first dielectric layer) includes a silicon oxide layer (e.g., a silicon-rich oxide (SRO) layer), a silicon nitride layer, a silicon oxynitride layer, a spin-coated dielectric layer, or a low dielectric constant dielectric layer, etc. It should be noted that the low dielectric constant dielectric layer is generally made of a dielectric material having a dielectric constant less than 3.9. In some alternative embodiments, the first and second dielectric layers have different etching selectivity. In this case, the first dielectric layer may be referred to as an etching stop layer (ESL) to prevent damage to the underlying components (e.g., contact plug 208 and dielectric layer 206) due to over-etching, while the second dielectric layer may be referred to as an inter-metallic layer (IML). In this alternative embodiment, the first and second dielectric layers are patterned using a combination of photolithography and etching processes. The etching processes may include dry etching, wet etching, or a combination thereof. A cleaning step may be selectively performed after the etching process, for example, to clean and remove residues generated from the etching process. However, this disclosure is not limited to this, and the etching process may be performed by any other suitable method. The plurality of first openings formed in the first and second dielectric layers each include trench vias and through-holes located below and spatially connected to the trench vias. For example, trench vias are formed in the second dielectric layer and extend from the indicated top surface of the second dielectric layer to a location inside the second dielectric layer. For example, through-holes are formed in both the second and first dielectric layers and extend from the location inside the second dielectric layer to the indicated bottom surface of the first dielectric layer. The location may be at approximately 1 / 2 to approximately 1 / 3 of the thickness of the second dielectric layer; however, this disclosure is not limited to this.

[0112] Used to form seed layers 520 (e.g., 5201, 5202, 5203, 5204, ..., 520). N-3 520 N-2 520 N-1 And 520 NThe seed layer material blanket coating can be formed by a blanket coating made of metal or metal alloy material, and this disclosure is not limited thereto. The material of each seed layer material blanket coating may include titanium, copper, molybdenum, tungsten, titanium nitride, titanium tungstenide, combinations thereof, or similar materials, and can be formed using processes such as sputtering, PVD, or similar methods. The seed layer material blanket coating can be patterned by etching, such as dry etching, wet etching, or combinations thereof; this disclosure is not limited thereto. Seed layers 520 (e.g., 5201, 5202, 5203, 5204, ..., 520...) N-3 520 N-2 520 N-1 And 520 N Each of these is referred to as a metal layer, which can be a single layer or a composite layer comprising multiple sublayers formed of different materials. For example, seed layers 520 (e.g., 5201, 5202, 5203, 5204, ..., 520...). N-3 520 N-2 520 N-1 And 520 N Each of the seed layers 520 may be or includes a titanium layer and a copper layer situated on top of the titanium layer. In one embodiment, the seed layers 520 (e.g., 5201, 5202, 5203, 5204, ..., 520...) N-3 520 N-2 520 N-1 And 520 N The materials of the seed layers 520 are the same as each other. Alternatively, the seed layers 520 (e.g., 5201, 5202, 5203, 5204, ..., 520...) N-3 520 N-2 520 N-1 And 520 N The materials can be different from each other.

[0113] Used to form conductive layer 530 (e.g., 5301, 5302, 5303, 5304, ..., 530). N-3 530 N-2 530 N-1 And 530 N Each conductive material blanket layer can be made of a conductive material formed by plating (e.g., electroplating or electroless plating) or deposition, such as copper, copper alloys, aluminum, aluminum alloys, combinations thereof (e.g., AlCu), similar materials, or combinations thereof, and can be patterned using photolithography and etching processes to form multiple conductive patterns / conductive segments. In one embodiment, conductive layers 530 (e.g., 5301, 5302, 5303, 5304, ..., 530...) N-3 530 N-2 530 N-1 And 530 NThe materials of the conductive layers 530 are the same as each other. Alternatively, the conductive layers 530 (e.g., 5301, 5302, 5303, 5304, ..., 530...) are all the same. N-3 530 N-2 530 N-1 And 530 N The materials can be different from each other.

[0114] In this case, the metallization layer ML N The top surface shown (e.g., including seed layer 520) N S520 surface N and conductive layer 530 N Surface S530 N Essentially flush with the dielectric structure DL N The top surface shown (e.g., dielectric layer 510) N Surface S510 N That is, the metallization layer ML N The top surface shown is essentially the same as the dielectric structure DL. N The top surfaces shown are coplanar. The top surface S500 of the interconnect 500 (e.g., including dielectric layer 510) is shown. N Surface S510 N Seed layer 520 N Surface S520 N With conductive layer 530 N Surface S530 N ) can be flush and can have a high degree of coplanarity, such as Figure 2 As shown.

[0115] The removal of excess seed layer material and excess conductive material coating can be achieved by planarization processes such as mechanical grinding, chemical mechanical polishing (CMP), and / or etching. After the planarization process, a cleaning step can be optionally performed, for example, to clean and remove residues generated from the planarization process. However, this disclosure is not limited to this, and the planarization process can be performed by any other suitable method.

[0116] In some embodiments, building layer L1 (including 5101, 5201, and 5301) is disposed on (e.g., in physical contact) and electrically coupled to via through via 1001, and is disposed on (e.g., in physical contact) and electrically coupled to via through contact plug 208 on a component (e.g., transistor 300) to provide routing functionality thereto; building layer L2 (including 5102, 5202, and 5302) is disposed on (e.g., in physical contact) and electrically coupled to building layer L1, and is thus electrically coupled to via 1001 and component (e.g., transistor 300) formed in semiconductor substrate 202 through contact plug 208 and building layer L1 to provide routing functionality thereto; building layer L3 (Including 5103, 5203, and 5303) are disposed on and electrically coupled to the building layer L2 (e.g., through physical contact), and thus electrically coupled to the via 1001 and components (e.g., transistor 300) formed in the semiconductor substrate 202 through the contact plug 208 and building layers L1 to L2 to provide routing functionality thereto; and building layer L4 (including 5104, 5204, and 5304) are disposed on and electrically coupled to the building layer L2 (e.g., through physical contact), and thus electrically coupled to the via 1001 and components (e.g., transistor 300) formed in the semiconductor substrate 202 through the contact plug 208 and building layers L1 to L3 to provide routing functionality thereto. Figure 2 As shown, the building layer L N-3 (including dielectric layer 510) N-3 Seed layer 520 N-3 and conductive layer 530 N-3 The contact plug is disposed on and electrically coupled to the building layer L4 (e.g., through an additional building layer formed therebetween, if present), and thus electrically coupled to the via 1001 and components (e.g., transistor 300) formed in the semiconductor substrate 202 through the contact plug 208, the building layers L1 to L4 and the additional building layer formed therebetween (if present) to provide routing functionality thereto; the building layer L N-2 (including dielectric layer 510) N-2 Seed layer 520 N-2 and conductive layer 530 N-2 It is set in the construction layer L N-3 Above (e.g., physical contact) and electrically connected thereto, and thus through contact plug 208, building layers L1 to L N-3 Electrically coupled to vias 1001 and components (e.g., transistors 300) formed in the semiconductor substrate 202, and to additional building layers (if any) formed therebetween, to provide routing functionality; building layer L N-1 (including dielectric layer 510) N-1 Seed layer 520 N- 1 and conductive layer 530N-1 It is set in the construction layer L N-2 Above (e.g., physical contact) and electrically connected thereto, and thus through contact plug 208, building layers L1 to L N-2 Electrically coupled to vias 1001 and components (e.g., transistors 300) formed in the semiconductor substrate 202, and to additional building layers (if any) formed therebetween, to provide routing functionality thereto; and building layer L N (including dielectric layer 510) N Seed layer 520 N and conductive layer 530 N It is set in the construction layer L N-1 Above (e.g., physical contact) and electrically connected thereto, and thus through contact plug 208, building layers L1 to L N-1 Electrically coupled to vias 1001 and components (e.g., transistors 300) formed in the semiconductor substrate 202, and to additional building layers (if any) formed therebetween, to provide routing functionality. This completes the circuit wafer W1'.

[0117] refer to Figure 3 In some embodiments, interconnects 500 are patterned to form lines that penetrate dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...). N-3 510 N-2 510 N-1 and 510 N The opening OP1 exposes the dielectric layer 206 in an accessible manner. In some embodiments, the opening OP1 has substantially vertical sidewalls, such as... Figure 3 As shown. Alternatively, opening OP1 can be made through the dielectric layer 510 of the internal interconnect 500. N The dielectric layer 206 gradually tapers towards the substrate 200A. In the cross-sectional view along direction Z, the shape of the opening OP1 may depend on requirements and / or product design requirements / layout, and is not intended to limit this disclosure. In the top (planar) view on the XY plane, the opening OP1 is square (see [reference]). Figure 28 However, depending on the requirements and / or product design / layout, the shape of the opening OP1 can be elliptical, circular, rectangular, polygonal, or a combination thereof; this disclosure is not limited thereto. For illustrative purposes, Figure 3 Only a single opening OP1 is shown in the diagram; however, this disclosure is not limited to this. The number of openings OP1 can be one, two, or more (see reference). Figure 28 The multiple openings shown (OP1) can be selected and / or specified according to requirements and / or product design requirements / layout.

[0118] In embodiments including multiple openings OP1, the sizes of the openings OP1 can vary. In a non-limiting example, some of the openings OP1 may have substantially the same size, while others may have different sizes, such as... Figure 28 As shown. Alternatively, the dimensions of all openings OP1 can be substantially the same as each other. Or, the dimensions of all openings OP1 can be different from each other. This disclosure is not limited to this.

[0119] Patterning processes can be performed using photolithography and / or etching processes. Etching processes can include dry etching, wet etching, or a combination thereof. After the etching process, a cleaning step can be optionally performed, for example, to clean and remove residues generated from the etching process.

[0120] refer to Figure 4 In some embodiments, thermal energy storage material 4010 is deposited above the interconnect 500, and the thermal energy storage material 4010 further extends into the opening OP1. For example, the opening OP1 is completely filled with the thermal energy storage material 4010. Figure 4As shown, the thermal energy storage material 4010 can (e.g., physically) contact the dielectric layer 206 exposed through the opening OP1. The thermal energy storage material 4010 can be formed by deposition (e.g., PVD or CVD). In a non-limiting example, the thermal energy storage material 4010 includes a thermal (energy) storage solid-solid phase change material (PCM) configured to readily undergo a solid-solid martensitic transformation from one crystalline structure to another different crystalline structure during temperature changes. In some embodiments, the solid-solid martensitic transformation from one crystalline structure to another different crystalline structure is reversible. In this configuration, the thermal energy storage material 4010 can store thermal energy (e.g., heat generated by hot spots such as transistor 300) through mechanical deformation (e.g., from a first crystalline structure to a different second crystalline structure), and then release the thermal energy (e.g., heat) at a slower rate through mechanical deformation (e.g., from a second crystalline structure to a different first crystalline structure). Due to this mechanism, heat spikes in the semiconductor device disclosed herein can be mitigated. In other words, if the thermal energy storage material 4010 is considered to be made of NiTi, the energy (generated from hot spots inside the semiconductor device) would need to undergo a phase transition (e.g., a shape change in the NiTi instance), where instead of an immediate increase in temperature (at and / or near the hot spots inside the semiconductor device), the energy is used for the phase transition; subsequently, the energy can be released at a slower rate, which helps to mitigate the heat spike problem (e.g., at and / or near the hot spots inside the semiconductor device). The thermal energy storage material 4010 may include materials such as germanium (Ge)-antimony (Sb)-tellurium (Te) (GST), vanadium dioxide (VO2), titanium (III), metal alloys, any other suitable metal alloys (e.g., nickel-titanium systems, including NiTi, NiTiHf, NiCuTi, NiCuTiHf, or NiTiV with or without nitrogen doping; or the like). For example, the thermal energy storage material 4010 includes shape memory alloys (SMA) that readily undergo a solid-to-solid martensitic transformation. This disclosure is not limited thereto. In some embodiments, the thermal conductivity of the thermal energy storage material 4010 is different from (e.g., greater than) that of the dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...). N-3 510 N-2 510N-1 and 510 N Thermal conductivity.

[0121] refer to Figure 5 In some embodiments, the thermal energy storage material 4010 is planarized to form a thermal control portion 410 in the opening OP1. For example, the thermal energy storage material 4010 is planarized to remove the dielectric layer 510. N Surface S510 N The excess amount of thermal energy storage material 4010 above is used to form a metallization layer ML1 to ML2 in the opening OP1 and laterally positioned on the inner interconnect 500. N The adjacent thermal control unit 410. In some embodiments, the thermal control unit 410 is connected to the dielectric structure DL1 to DL2 of the interconnect 500. N (For example, DL1, DL2, DL3, DL4, ..., DL) N-3 DL N-2 DL N-1 DL N Lateral coverage (e.g., physical contact). The thermal control unit 410 may be embedded in the building layers L1 to L2 of the interconnect 500. N In some embodiments, the surface S410 of the thermal control unit 410 is substantially flush with the top surface S500 of the connecting line 500. In other words, the surface S410 of the thermal control unit 410 is substantially coplanar with the top surface S500 of the connecting line 500. Figure 5 As shown, the thermal control unit 410 can completely penetrate the internal interconnect 500. For example, the thermal control unit 410 is cylindrical or cylindrical in shape and is adjacent to a hot spot (e.g., transistor 300). In a non-limiting example, the cylindrical or cylindrical shape of the thermal control unit 410 extends along the Z direction. For illustrative purposes, Figure 5 Only a single thermal control unit 410 is shown in the illustration; however, this disclosure is not limited thereto. The number of thermal control units 410 may be one, two, or more (see reference). Figure 28 This can be selected and / or specified based on needs and / or product design requirements / layout.

[0122] Planarization processes may include polishing, chemical mechanical polishing, etching, or combinations thereof. During the planarization process, the dielectric layer 510 may also be... N Seed layer 520 N and / or conductive layer 530 NPlanarization is performed. After planarization, a cleaning step may be optionally performed, for example, to clean and remove residues generated from the planarization process. However, this disclosure is not limited to this, and the planarization process can be performed by any other suitable method.

[0123] refer to Figure 6 In some embodiments, a dielectric layer 6001 is formed over the interconnect 500. For example, the dielectric layer 6001 is disposed on the top surface S500 of the interconnect 500 (e.g., including surface S510). N Surface S520 N and surface S530 N Above (e.g., in physical contact), where interconnects 500 are disposed between dielectric layer 6001 and substrate 200A. Dielectric layer 6001 may be referred to as a bonding layer or a bonded dielectric layer. Dielectric layer 6001 may be a single layer or comprise multiple stacked sub-dielectric layers. Dielectric layer 6001 may be transparent (but not limited to) through... Figure 5 The dielectric layer 6001 is formed by conformally forming a blanket layer of material for forming the dielectric layer 6001 on the structure shown. In a non-limiting example, the material of the dielectric layer 6001 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride; other suitable dielectric layers; or combinations thereof. The dielectric layer 6001 can be formed using suitable manufacturing techniques such as spin coating, CVD, ALD, PVD, etc. The illustrated top surface S6001 in the dielectric layer 6001 can be flat and can have a high degree of coplanarity, such as... Figure 6 As shown.

[0124] refer to Figure 7 In some embodiments, the dielectric layer 6001 is patterned to form an opening OP2 extending through the dielectric layer 6001, wherein the opening OP2 exposes the thermal control portion 410 in an accessible manner. In some embodiments, the opening OP2 has substantially vertical sidewalls, such as... Figure 7 As shown. Alternatively, the opening OP2 may taper gradually from the top surface S6001 of the dielectric layer 6001 to the top surface S500 of the interconnect 500. In the cross-sectional view along direction Z, the shape of the opening OP2 may depend on requirements and / or product design requirements / layout, and is not intended to limit this disclosure. In the top (plan) view on the XY plane, the opening OP2 is rectangular in shape (see reference). Figure 29 However, depending on the requirements and / or product design specifications / layout, the shape of the opening OP2 can be elliptical, circular, square, polygonal, or a combination thereof; this disclosure is not limited thereto. For illustrative purposes, Figure 7Only a single opening OP2 is shown in the diagram; however, this disclosure is not limited thereto. The number of openings OP2 can be one, two, or more (see reference). Figure 29 The multiple openings shown (OP2) can be selected and / or specified according to requirements and / or product design requirements / layout.

[0125] Patterning processes can be performed using photolithography and / or etching processes. Etching processes can include dry etching, wet etching, or a combination thereof. After the etching process, a cleaning step can be optionally performed, for example, to clean and remove residues generated from the etching process.

[0126] refer to Figure 8 In some embodiments, a thermal energy storage material 4020 is deposited over the dielectric layer 6001, and the thermal energy storage material 4020 further extends into the opening OP2. For example, the opening OP2 is completely filled with the thermal energy storage material 4020. Figure 8As shown, the thermal energy storage material 4020 can (e.g., physically) contact the thermal control section 410 exposed through the opening OP2. The thermal energy storage material 4020 can be formed by deposition (e.g., PVD or CVD). In a non-limiting example, the thermal energy storage material 4020 includes a thermal (energy) storage solid-solid phase change material (PCM) configured to readily undergo a solid-solid martensitic transformation from one crystalline structure to another different crystalline structure during temperature changes. In some embodiments, the solid-solid martensitic transformation from one crystalline structure to another different crystalline structure is reversible. In this configuration, the thermal energy storage material 4020 can store thermal energy (e.g., heat generated by hot spots such as transistor 300) through mechanical deformation (e.g., from a first crystalline structure to a different second crystalline structure), and then release the thermal energy (e.g., heat) at a slower rate through mechanical deformation (e.g., from a second crystalline structure to a different first crystalline structure). Due to this mechanism, heat spikes in the semiconductor device disclosed herein can be mitigated. Similarly, if the thermal energy storage material 4020 is considered to be made of NiTi, the energy (generated from hot spots inside the semiconductor device) would need to undergo a phase transition (e.g., a shape change in the NiTi instance), where instead of an immediate increase in temperature (at and / or near the hot spots inside the semiconductor device), the energy is used for the phase transition; subsequently, the energy can be released at a slower rate, which helps to mitigate the heat spike problem (e.g., at and / or near the hot spots inside the semiconductor device). The materials of the thermal energy storage material 4020 may include germanium (Ge)-antimony (Sb)-tellurium (Te) (GST), vanadium dioxide (VO2), titanium (III), metal alloys, any other suitable metal alloys (e.g., nickel-titanium systems, including NiTi, NiTiHf, NiCuTi, NiCuTiHf, or NiTiV with or without nitrogen doping; or the like). For example, the thermal energy storage material 4020 includes shape memory alloys (SMAs) that readily undergo a solid-to-solid martensitic transformation. This disclosure is not limited thereto. In some embodiments, the thermal conductivity of the thermal energy storage material 4020 is different from (e.g., greater than) that of the dielectric layer 510 (e.g., 5101, 5102, 5103, 5104, ..., 510...). N-3 510 N-2 510N-1 and 510 N The thermal conductivity of the thermal energy storage material 4020 is the same as that of the thermal energy storage material 4010. In another non-limiting example, the thermal conductivity of the thermal energy storage material 4020 is different from that of the thermal energy storage material 4010. This disclosure is not limited thereto.

[0127] refer to Figure 9 In some embodiments, the thermal energy storage material 4020 is planarized to form a thermal control portion 420 in the opening OP2. For example, the thermal energy storage material 4020 is planarized to remove excess thermal energy storage material 4020 located above the illustrated top surface S6001 of the dielectric layer 6001 to form the thermal control portion 420 in the opening OP2, wherein the thermal control portion 420 is laterally covered by the dielectric layer 6001. In some embodiments, the thermal control portion 420 is in physical contact with the dielectric layer 6001. The thermal control portion 420 may be embedded in the dielectric layer 6001 and above the interconnect 500. In some embodiments, the surface S420 of the thermal control portion 420 is substantially flush with the illustrated top surface S6001 of the dielectric layer 6001. In other words, the surface S420 of the thermal control portion 420 is substantially coplanar with the illustrated top surface S6001 of the dielectric layer 6001. Figure 9 As shown, the thermal control unit 420 can completely penetrate the dielectric layer 6001. For example, the thermal control unit 420 is in the form of a segment, slab, or plate, and is located adjacent to a hot spot (e.g., transistor 300). For illustrative purposes, Figure 9 Only a single thermal control unit 420 is shown in the diagram; however, this disclosure is not limited thereto. The number of thermal control units 420 may be one, two, or more (see reference). Figure 29 This can be selected and / or specified based on needs and / or product design requirements / layout.

[0128] Planarization processes may include polishing, chemical mechanical polishing, etching, or combinations thereof. The dielectric layer 6001 may also be planarized during the planarization process. After planarization, a cleaning step may be selectively performed, for example, to clean and remove residues generated from the planarization process. However, this disclosure is not limited to this, and the planarization process can be performed by any other suitable method. Figure 9As shown, thermal control unit 410 can be physically connected and thermally coupled to thermal control unit 420, wherein thermal control unit 410 and thermal control unit 420 connected thereto can be collectively referred to as thermal conductive element 400A. In embodiments, thermal control unit 410 is referred to as the vertical portion of thermal conductive element 400A, and thermal control unit 420 is referred to as the horizontal portion of thermal conductive element 400A. In some embodiments, the material of thermal control unit 410 is the same as the material of thermal control unit 420. In alternative embodiments, the material of thermal control unit 410 is different from the material of thermal control unit 420, which will be discussed in detail later. In some embodiments, for each thermal conductive element 400A, thermal control unit 410 and thermal control unit 420 are arranged in a one-to-one architecture.

[0129] In some embodiments, the thermally conductive component 400A is referred to as a thermal capacitor, thermal storage capacitor, thermal control component, thermal control member, thermal control module, thermal management component, thermal management member, thermal management module, or thermal control assembly. Figure 9 Only one thermal control component 400A is shown, but the number of thermal control components 400A can be one, two, or more. This disclosure is not limited thereto. Due to the thermal conductive component 400A, the heat generated by hot spots (e.g., transistor 300) within the semiconductor device of this disclosure can be directed to and stored within the thermal conductive component 400A, which mitigates the thermal spikes of hot spots (e.g., transistor 300) within the semiconductor device of this disclosure, thereby improving the reliability of the semiconductor device of this disclosure. In some embodiments, the thermal conductive component 400A is electrically isolated from and thermally coupled to the components (e.g., transistor 300) of the interconnect 500 and the substrate 200A.

[0130] At this point, circuit chip W1 has been manufactured. For example, as... Figure 9 As shown, the circuit chip W1 includes a substrate 200A (including a semiconductor substrate 202 on which a plurality of transistors 300 are formed, a plurality of isolation structures 204, a dielectric layer 206, a plurality of contact plugs 208 and a plurality of through holes 1001), an interconnect 500 disposed above and electrically coupled to the substrate 200A, a dielectric layer 6001 disposed above the interconnect 500; and one or more thermal control components 400A (including thermal control sections 410 and 420) penetrating the interconnect 500 and the dielectric layer 6001.

[0131] refer to Figure 10In some embodiments, a bonding layer 6201 is formed over the dielectric layer 6001 and the thermal control assembly 400A. For example, the bonding layer 6201 is disposed over the top surface S6001 of the dielectric layer 6001 and the surface S420 of the thermal control unit 420 (e.g., in physical contact), wherein the dielectric layer 6001 is disposed between the bonding layer 6201 and the interconnect 500. The bonding layer 6201 may be referred to as a dielectric layer or a bonded dielectric layer. The bonding layer 6201 may be a single layer or comprise multiple stacked sub-dielectric layers. The bonding layer 6201 may be transparent (but not limited to) through... Figure 9 The structure shown is formed by conformally forming a blanket layer of material for forming the bonding layer 6201. In a non-limiting example, the material of the bonding layer 6201 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or silicon carbonitride; other suitable dielectric layers; or combinations thereof. The bonding layer 6201 may be formed by suitable manufacturing techniques such as spin coating, CVD, ALD, PVD, etc. The illustrated top surface S6201 of the bonding layer 6201 may be flat and may have a high degree of coplanarity, such as... Figure 10 As shown. In some cases, the bonding layer 6201 can be considered part of the circuit wafer W1. Due to the presence of the bonding layer 6201, subsequent bonding processes can be more reliable due to the uniformity at the bonding surface.

[0132] refer to Figure 11 In some embodiments, a circuit chip W2' is provided. For example, the circuit chip W2' includes a substrate 200B (including a semiconductor substrate 202 formed of a plurality of transistors 300, a plurality of isolation structures 204, a dielectric layer 206, and a plurality of contact plugs 208) and interconnects 500 disposed above and electrically coupled to the substrate 200B. The details, formation, and materials of the interconnects 500 and the semiconductor substrate 202, isolation structures 204, dielectric layer 206, contact plugs 208, and transistors 300 included in the substrate 200B are similar to or substantially the same as those of the circuit chip W2'. Figures 1 to 2 The details, formation, and materials of the interconnects 500 of the described circuit chip W1' and the semiconductor substrate 202, isolation structure 204, dielectric layer 206, contact plug 208, and transistor 300 contained in the substrate 200A are therefore not repeated here for the sake of brevity.

[0133] refer to Figure 12In some embodiments, circuit chip W2' is placed above circuit chip W1 and bonded to circuit chip W1 via wafer-on-wafer (WoW) bonding. In some embodiments, circuit chip W2' is placed above circuit chip W1 via a pick-and-place process for bonding. For example, the semiconductor substrate 202 of circuit chip W2' is placed (e.g., in physical contact) above the top surface S6201 of the bonding layer 6201 of circuit chip W1, and the semiconductor substrate 202 of circuit chip W2' is bonded to the top surface S6201 of the bonding layer 6201 of circuit chip W1 via a bonding process including dielectric-to-dielectric bonding (e.g., oxide-to-silicon bonding or nitride-to-silicon bonding). In such an embodiment, a dielectric-to-dielectric bonding interface (e.g., an oxide-to-silicon bonding interface or a nitride-to-silicon bonding interface) IF1 exists between circuit wafer W2' and circuit wafer W1 (e.g., bonding layer 6201), and the bonding interface IF1 is considered to be the bonding interface between circuit wafer W2' and circuit wafer W1 (e.g., bonding layer 6201). In some embodiments, if a natural oxide is formed over the semiconductor substrate 202 (e.g., back surface S202B) of circuit wafer W2', the bonding interface IF1 having a dielectric-to-dielectric bonding interface further includes an oxide-to-oxide bonding interface or a nitride-to-oxide bonding interface; this disclosure is not limited thereto. After the bonding, circuit wafer W1 can be considered as Figure 12 The first tier T1 of the stacked structure shown is illustrated, and the circuit chip W2' can be regarded as the second tier T2 of the stacked structure.

[0134] refer to Figure 13 In some embodiments, a thermal control unit 412, a dielectric layer 6002, and a thermal control unit 420 are successively formed above the circuit chip W2' to form the circuit chip W2 (also considered as the second layer T2). Figure 13As shown, in the second level T2, thermal control unit 412 can be physically connected and thermally coupled to thermal control unit 420, wherein thermal control unit 412 and thermal control unit 420 connected thereto can be collectively referred to as thermal conductive assembly 400B. In embodiments, thermal control unit 412 is referred to as the vertical portion of thermal conductive assembly 400B, and thermal control unit 420 is referred to as the horizontal portion of thermal conductive assembly 400B. In some embodiments, for the second level T2, the material of thermal control unit 412 is the same as the material of thermal control unit 420. Alternatively, for the second level T2, the material of thermal control unit 412 may be different from the material of thermal control unit 420, which will be discussed in detail later. In some embodiments, for each thermal conductive assembly 400B, thermal control unit 412 and thermal control unit 420 are arranged in a one-to-one architecture. Figure 13 As shown, for each thermal control component 400B in the second level T2, the thermal control unit 412 can completely penetrate the interconnect 500, the substrate 200B and the bonding layer 6201, wherein the thermal control unit 412 is cylindrical or cylindrical in shape and is adjacent to the hot spot (e.g., transistor 300).

[0135] In some embodiments, the thermally conductive component 400B is referred to as a thermal capacitor, thermal storage capacitor, thermal control component, thermal control member, thermal control module, thermal management component, thermal management member, thermal management module, or thermal control assembly. Figure 13 Only one thermal control component 400B is shown, but the number of thermal control components 400B can be one, two, or more. This disclosure is not limited thereto. Due to the thermally conductive component 400B, the heat generated by hot spots (e.g., transistor 300) in the second layer T2 of the semiconductor device disclosed herein can be directed to the thermally conductive component 400B in the second layer T2 and stored therein. This mitigates the thermal spikes of hot spots (e.g., transistor 300) inside the semiconductor device disclosed herein, thereby improving the reliability of the semiconductor device disclosed herein. In some embodiments, for the second layer T2, the thermally conductive component 400B is electrically isolated from and thermally coupled to the components (e.g., transistor 300) of the interconnect 500 and the substrate 200B.

[0136] At this point, circuit chip W2 has been manufactured. For example, as... Figure 13As shown, the circuit chip W2 includes a substrate 200B (including a semiconductor substrate 202 on which a plurality of transistors 300 are formed, a plurality of isolation structures 204, a dielectric layer 206, and a plurality of contact plugs 208), an interconnect 500 disposed above and electrically coupled to the substrate 200B, a dielectric layer 6002 disposed above the interconnect 500, and one or more thermal control components 400B (including thermal control units 412 and 420) penetrating a bonding layer 6201, the interconnect 500, and the dielectric layer 6002. Details, formation, and materials of the thermal control unit 412 and the dielectric layer 6002 are respectively related to... Figures 3 to 5 and combined Figure 28 Details, formation, and materials of the thermal control unit 410 described herein, as well as its relationship with Figure 6 The details, formation, and materials of the dielectric layer 6001 described herein are similar to or substantially the same, and the thermal control unit 420 is located on top of it. Figures 7 to 9 and combined Figure 29 Therefore, for the sake of brevity, it will not be described here.

[0137] In some embodiments, the thermal control portion 420 of the thermal control component 400B in the second layer T2 completely penetrates the dielectric layer 6002 of the second layer T2 to be physically connected to the thermal control portion 412 of the thermal control component 400B in the second layer T2, and the thermal control portion 412 of the thermal control component 400B in the second layer T2 completely penetrates the interconnect 500, the substrate 200B, and the bonding layer 6201 to be physically connected and coupled to the thermal control portion 420 of the thermal control component 400A in the first layer T1, such as... Figure 13 As shown. The thermal control unit 412 of the thermal control component 400B in the second level T2 can be thermally coupled to the thermal control unit 420 of the thermal control component 400A in the first level T1, as follows. Figure 13 As shown. In some embodiments, the thermal control unit 412 of the thermal control assembly 400B in the second level T2 may be in physical contact (e.g., direct contact) with the thermal control unit 420 of the thermal control assembly 400A in the first level T1.

[0138] Continue to refer to Figure 13 In some embodiments, after forming the thermal control component 400B, a bonding layer 6202 is formed over the dielectric layer 6002 and the thermal control component 400B. For example, the bonding layer 6202 is disposed over the top surface S6002 of the dielectric layer 6002 and the surface S420 of the thermal control portion 420 (e.g., in physical contact), wherein the dielectric layer 6002 is disposed between the bonding layer 6202 and the interconnect 500 of the circuit wafer W2. The bonding layer 6202 may be referred to as a dielectric layer or a bonding dielectric layer. The details, formation, and materials of the bonding layer 6202 are related to... Figure 10The details, formation, and materials of the bonding layer 6201 described herein are similar or substantially the same, and therefore will not be repeated here. The illustrated top surface S6202 of the bonding layer 6202 may be flat and may have a high degree of coplanarity, such as... Figure 13 As shown. In some cases, the bonding layer 6202 can be considered part of the circuit chip W2. Due to the presence of the bonding layer 6202, subsequent bonding processes can be more reliable due to the uniformity at the bonding surface.

[0139] refer to Figure 14 In some embodiments, a circuit chip W3' is provided. For example, the circuit chip W3' includes a substrate 200B (including a semiconductor substrate 202 formed of a plurality of transistors 300, a plurality of isolation structures 204, a dielectric layer 206, and a plurality of contact plugs 208) and interconnects 500 disposed above and electrically coupled to the substrate 200B. The interconnects 500 of the circuit chip W3' and the details, formation, and materials of the semiconductor substrate 202, isolation structures 204, dielectric layer 206, contact plugs 208, and transistors 300 included in the substrate 200B are similar to or substantially the same as those of the circuit chip W3'. Figures 1 to 2 The details, formation, and materials of the interconnects 500 of the described circuit chip W1' and the semiconductor substrate 202, isolation structure 204, dielectric layer 206, contact plug 208, and transistor 300 contained in the substrate 200A are therefore not repeated here for the sake of brevity.

[0140] In some embodiments, circuit chip W3' is placed above circuit chip W2 and bonded to circuit chip W2 via WoW bonding, such as Figure 14As shown. In some embodiments, a circuit wafer W3' is placed over a circuit wafer W2 via a pick-and-place process for bonding. For example, the semiconductor substrate 202 of the circuit wafer W3' is placed over the top surface S6202 of the bonding layer 6202 of the circuit wafer W2 (e.g., physical contact), and the semiconductor substrate 202 of the circuit wafer W3' is bonded to the top surface S6202 of the bonding layer 6202 of the circuit wafer W2 via a bonding process including dielectric-to-dielectric bonding (e.g., oxide-to-silicon bonding or nitride-to-silicon bonding). In such an embodiment, there is a dielectric-to-dielectric bonding interface (e.g., oxide-to-silicon bonding or nitride-to-silicon bonding) IF2 between the circuit wafer W3' and the circuit wafer W2 (e.g., bonding layer 6202), and this bonding interface IF2 is considered to be the bonding interface between the circuit wafer W3' and the circuit wafer W2 (e.g., bonding layer 6202). In some embodiments, if a natural oxide is formed over the semiconductor substrate 202 (e.g., the back surface S202B) of the circuit wafer W3', the bonding interface IF2 having a dielectric-to-dielectric bonding interface further includes an oxide-to-oxide bonding interface or a nitride-to-oxide bonding interface; this disclosure is not limited thereto. After the bonding, the circuit wafer W3' can be considered as Figure 14 The third tier T3 of the stacked structure shown.

[0141] Continue to refer to Figure 14 In some embodiments, after the circuit chip W3' is bonded to the circuit chip W2, a thermal control section 412 is formed through the interconnect 500, the substrate 200B, and the bonding layer 6202. The details, formation, and materials of the thermal control section 412 are as follows: Figures 3 to 5 and combined Figure 28 The details, formation, and materials of the thermal control unit 410 are similar or substantially the same, so for the sake of brevity, they will not be repeated here.

[0142] refer to Figure 15 In some embodiments, in Figure 14 The stacked structure shown forms at least one through-hole 1002 (including a pad 130 and a through-hole 140) and at least one through-hole 1003 (including a pad 150 and a through-hole 160). For illustrative purposes, as... Figure 15As shown, at least one perforation 1002 may include one perforation 1002 and at least one perforation 1003 may include one perforation 1003; however, this disclosure is not limited thereto. The number of each of the perforations 1002 and 1003 may be more than one, and they may be selected and / or specified based on requirements and / or product design requirements / layout. The details, formation, and materials of the perforations 1002 and 1003 are related to... Figure 1 The details (e.g., architecture, such as shape), formation, and materials of the perforated 1001 described herein are similar or substantially the same, and therefore will not be repeated here. For example, as Figure 15 As shown, gasket 130 exposes the bottom of the through-hole 140 of perforation 1002 in an accessible manner, and gasket 150 exposes the bottom of the through-hole 160 of perforation 1003 in an accessible manner. Alternatively, the bottom and sidewalls of the through-hole 140 of perforation 1002 are physically covered by gasket 130, and the bottom and sidewalls of the through-hole 160 of perforation 1003 are physically covered by gasket 150.

[0143] In some embodiments, such as Figure 15 As shown, the top surface S1002 of the perforation 1002 (e.g., the surface S130 including the pad 130 and the surface S140 of the via 140) and the top surface S1003 of the perforation 1003 (e.g., the surface S150 including the pad 150 and the surface S160 of the via 160) are substantially flush with the top surface S500 of the interconnect 500 in the third level T3 (e.g., the surface S510). N S520 N and S530 N In other words, the top surface S1002 of the perforation 1002 (e.g., including surfaces S130 and S140) and the top surface S1003 of the perforation 1003 (e.g., including surfaces S150 and S160) are substantially coplanar with the top surface S500 of the interconnect 500 (e.g., including surface S510). N S520 N and S530 N ).

[0144] In a non-limiting example, through-hole 1002 passes through the second level T2 and the third level T3 of the stacked structure and extends further into the first level T1, thus electrically connecting the first level T1, the second level T2, and the third level T3 to each other through (e.g., physically) contacting through-hole 1002 with metallic features (e.g., the metallization layer of interconnect 500) in the first level T1, the second level T2, and the third level T3. In such a case, through-hole 1003 passes through the third level T3 of the stacked structure and extends further into the second level T2, thereby electrically connecting the second level T2 and the third level T3 to each other through (e.g., physically) contacting through-hole 1003 with metallic features (e.g., the metallization layer of interconnect 500) in the second level T2 and the third level T3.

[0145] In another non-limiting example, through-hole 1002 passes through the second level T2 and the third level T3 of the stacked structure and extends further into the first level T1 to electrically connect the first level T1 and the third level T3 through (e.g., physically) contact between through-hole 1002 and metal features (e.g., the metallization layer of interconnect 500) in the first level T1 and the third level T3. In this alternative case, through-hole 1003 passes through the third level T3 of the stacked structure and extends further into the second level T2, thereby electrically connecting the second level T2 and the third level T3 to each other through (e.g., physically) contact between through-hole 1003 and metal features (e.g., the metallization layer of interconnect 500) in the second level T2 and the third level T3, and electrically connecting the first level T1 and the second level T2 to each other through (e.g., physically) contact between through-hole 1002 and metal features (e.g., the metallization layer of interconnect 500) in the third level T3.

[0146] In embodiments including multiple through-holes 1002, the through-holes 1002 pass through the second level T2 and the third level T3 of the stacked structure and further extend to the first level T1, wherein one or more of the through-holes 1002 electrically connect the first level T1, the second level T2, and the third level T3 to each other through (e.g., physically) contacting metallic features (e.g., metallization layers in interconnects 500) in the first level T1, the second level T2, and the third level T3, and the remaining portions of the through-holes 1002 physically contact the through-holes. The remainder of 1002 electrically connects the first level T1 and the third level T3 to each other via metallic features (e.g., metallization layers in interconnect 500) in the first level T1 and the third level T3, and wherein one or more of the vias 1003 penetrate the third level T3 of the stacked structure and further extend into the second level T2, so as to electrically connect the second level T2 and the third level T3 to each other via (e.g., physically) contacting one or more of the vias 1003 with metallic features (e.g., metallization layers in interconnect 500) in the second level T2 and the third level T3. In some embodiments where the electrical connection between the first level T1, the second level T2, and the third level T3 is properly established by the vias 1002, the vias 1003 may be omitted.

[0147] refer to Figure 16 In some embodiments, after forming vias 1002 and 1003, a dielectric layer 6003 and a thermal control unit 420 are successively formed on the circuit chip W3' to form the circuit chip W3 (also considered as the third layer T3). Figure 16 As shown, in the third level T3, the thermal control unit 412 can be physically connected to and thermally coupled to the thermal control unit 420, wherein the thermal control unit 412 and the connected thermal control unit 420 can be collectively referred to as the thermally conductive assembly 400B of the third level T3. In an embodiment, for the thermally conductive assembly 400B of the third level T3, the thermal control unit 412 is referred to as the vertical portion of the thermally conductive assembly 400B, and the thermal control unit 420 is referred to as the horizontal portion of the thermally conductive assembly 400B. In some embodiments, for the third level T3, the material of the thermal control unit 412 is the same as the material of the thermal control unit 420. Alternatively, for the third level T3, the material of the thermal control unit 412 may be different from the material of the thermal control unit 420, which will be discussed in detail later. In some embodiments, for each thermally conductive assembly 400B in the third level T3, the thermal control unit 412 and the thermal control unit 420 are arranged in a one-to-one architecture. Figure 16As shown, for each thermal control component 400B in the third level T3, the thermal control unit 412 can completely penetrate the interconnect 500, the substrate 200B and the bonding layer 6202, wherein the thermal control unit 412 is cylindrical or cylindrical in shape and is adjacent to the hot spot (e.g., transistor 300).

[0148] Figure 16 Only one thermal control component 400B is shown; however, the number of thermal control components 400B can be one, two, or more. This disclosure is not limited thereto. Due to the thermally conductive component 400B, the heat generated by hot spots (e.g., transistor 300) in the third layer T3 of the semiconductor device disclosed herein can be directed to and stored within the thermally conductive component 400B in the third layer T3. This mitigates the thermal spikes of hot spots (e.g., transistor 300) within the semiconductor device disclosed herein, thereby improving the reliability of the semiconductor device disclosed herein. In some embodiments, for the third layer T3, the thermally conductive component 400B is electrically isolated from and thermally coupled to the components (e.g., transistor 300) of the interconnect 500 and the substrate 200B.

[0149] At this point, circuit chip W3 has been manufactured. For example, as... Figure 16 As shown, the circuit chip W3 includes a substrate 200B (including a semiconductor substrate 202 on which a plurality of transistors 300 are formed, a plurality of isolation structures 204, a dielectric layer 206, and a plurality of contact plugs 208), an interconnect 500 disposed above and electrically coupled to the substrate 200B, a dielectric layer 6003 disposed above the interconnect 500, and one or more thermal control components 400B (including thermal control units 412 and 420) penetrating the bonding layer 6202, the interconnect 500, and the dielectric layer 6003. Details, formation, and materials of the thermal control unit 412 and the dielectric layer 6003 are respectively related to... Figures 3 to 5 and combined Figure 28 Details, formation, and materials of the thermal control unit 410 described herein, as well as its relationship with Figure 6 The details, formation, and materials of the dielectric layer 6001 described herein are similar to or substantially the same, and the thermal control unit 420 is located on top of it. Figures 7 to 9 and combined Figure 29 The description is omitted here for brevity. In some embodiments, the thermal control section 420 of the thermal control component 400B in the third layer T3 completely penetrates the dielectric layer 6003 of the third layer T3 to be physically connected to the thermal control section 412 of the thermal control component 400B in the third layer T3, and the thermal control section 412 of the thermal control component 400B in the third layer T3 completely penetrates the interconnect 500, the substrate 200B and the bonding layer 6202 to be physically connected and coupled to the thermal control section 420 of the thermal control component 400B in the second layer T2, as shown below. Figure 16 As shown. The thermal control unit 412 of the thermal control component 400B in the third level T3 can be thermally coupled to the thermal control unit 420 of the thermal control component 400B in the second level T2, as follows. Figure 16 As shown. In some embodiments, the thermal control unit 412 of the thermal control component 400B in the third level T3 may be in physical contact (e.g., direct contact) with the thermal control unit 420 of the thermal control component 400B in the second level T2.

[0150] Continue to refer to Figure 16 In some embodiments, a bonding layer 6203 is formed over the dielectric layer 6003 and the thermal control component 400B included in the circuit chip W3. For example, the bonding layer 6203 is disposed over the top surface S6003 of the dielectric layer 6003 and the surface S420 of the thermal control component 420 (e.g., in physical contact), wherein the dielectric layer 6003 is disposed between the bonding layer 6203 and the interconnect 500 of the circuit chip W3. The bonding layer 6203 may be referred to as a dielectric layer or a bonding dielectric layer. The details, formation, and materials of the bonding layer 6203 are related to... Figure 10 The details, formation, and materials of the bonding layer 6201 described herein are similar or substantially the same, and therefore will not be repeated here. The illustrated top surface S6203 of the bonding layer 6203 may be flat and may have a high degree of coplanarity, such as... Figure 16 As shown. In some cases, the bonding layer 6203 can be considered part of the circuit chip W3. Due to the presence of the bonding layer 6203, subsequent bonding processes can be more reliable due to the uniformity at the bonding surface.

[0151] refer to Figure 17 In some embodiments, a carrier 50 is provided above the circuit chip W3 and the carrier 50 is bonded to the circuit chip W3 via a WoW bonding process. In some embodiments, the carrier 50 is placed above the circuit chip W3 via a pick-and-place process for bonding. Details of the carrier 50 may be described in conjunction with... Figure 1The details of the semiconductor substrate 202 described herein are similar or substantially the same, and therefore will not be repeated here for the sake of brevity. For example, the carrier 50 is a silicon substrate without source components. For example, the carrier 50 is placed above (e.g., in physical contact) the top surface S6203 of the bonding layer 6203 of the circuit wafer W3, and the carrier 50 is bonded to the top surface S6203 of the bonding layer 6203 of the circuit wafer W3 by a bonding process including dielectric-to-dielectric bonding (e.g., oxide-to-silicon bonding or nitride-to-silicon bonding). In such an embodiment, there is a bonding interface IF3 (e.g., oxide-to-silicon bonding or nitride-to-silicon bonding) between the carrier 50 and the circuit wafer W3 (e.g., bonding layer 6203), and this is considered the bonding interface between the carrier 50 and the circuit wafer W3 (e.g., bonding layer 6203). In some embodiments, if a natural oxide is formed over the carrier 50 (e.g., surface S50B), the bonding interface IF3 having a dielectric-to-dielectric bonding interface further includes an oxide-to-oxide bonding interface or a nitride-to-oxide bonding interface; this disclosure is not limited thereto. After the bonding, the carrier 50 may be referred to as a support substrate comprising a stacked structure of multiple levels (e.g., T1 to T3). Furthermore, since the carrier 50 is a silicon substrate, the carrier 50 may also be a heat dissipation component of the semiconductor device 10000A (in... Figure 21 middle).

[0152] refer to Figure 17 and Figure 18 In some embodiments, a planarization process is performed on the semiconductor substrate 202 of the circuit wafer W1 (in the first layer T1), thereby thinning the semiconductor substrate 202 of the circuit wafer W1 and exposing the through-hole 1001 in an accessible manner. Figure 18 As shown, portions of the semiconductor substrate 202 and the pad 110 can be removed from the stacked circuit chip W1, thereby exposing the via 120 from the circuit chip W1. In some cases, during the removal of portions of the semiconductor substrate 202 and the pad 110 from the circuit chip W1, portions of the via 120 of the circuit chip W1 may also be slightly removed.

[0153] Then, for example, a patterning process is performed on the semiconductor substrate 202 of the circuit wafer W1, wherein a portion of the semiconductor substrate 202 is further removed to form a semiconductor substrate 202 having a patterned back surface S202A, such that a portion of each through-hole 1001 (including a portion of each pad 110 and a portion of each via 120) protrudes from the patterned back surface S202A of the semiconductor substrate 202. The patterning process may include an etching process (e.g., wet etching or dry etching) or a similar process. This disclosure is not limited thereto.

[0154] like Figure 18 As shown, the pad 110 may cover the entire sidewall of the via 120 and expose the bottom of the via 120; however, this disclosure is not limited thereto. In one embodiment, the pad 110 may only cover the sidewall of the via 120 embedded in a semiconductor substrate 202 having a patterned back surface S202A. For example, the portion of the pad 110 that is disposed on the sidewall of the via 120 and protrudes from the patterned back surface S202A of the semiconductor substrate 202 after the planarization process is removed during the patterning process. In one embodiment, the pad 110 may cover both the sidewall and the bottom of the via 120. That is, the portion of the pad 110 that is disposed on the sidewall of the via 120 and protrudes from the patterned back surface S202A of the semiconductor substrate 202 after the planarization process is retained during the patterning process. The planarization process may include a polishing process, a chemical mechanical polishing process, an etching process, a combination thereof, etc. The etching process may include dry etching, wet etching, or a combination thereof.

[0155] In some embodiments, a dielectric material (not shown) is formed on the patterned back surface S202A of the semiconductor substrate 202 of the circuit wafer W1. In some embodiments, the dielectric material is formed directly and conformally over the semiconductor substrate 202 and the via 1001 of the circuit wafer W1, wherein the semiconductor substrate 202 and the via 1001 of the circuit wafer W1 are covered by and in physical contact with the dielectric material. In some embodiments, the dielectric material may be formed as a dielectric material blanket layer. In some embodiments, the dielectric material may be a polymer layer made of PI, PBO, BCB, or any other suitable polymer-based dielectric material. In some embodiments, the dielectric material may be an Ajinomoto Buildup Film (ABF), a Solder Resist Film (SRF), or a similar film. In some embodiments, the dielectric material may be formed by suitable manufacturing techniques, such as spin coating, stacking, deposition, etc. Subsequently, another planarization process is performed on the dielectric material to form a dielectric layer 52 that laterally covers the through-holes 1001 protruding from the semiconductor substrate 202 of the circuit wafer W1, wherein the dielectric layer 52 exposes the surfaces S1001 of the through-holes 1001 (including the surfaces S110 of the pads 110 and S120 of the vias 120) in an accessible manner. In some embodiments, in the other planarization process, a portion of the dielectric material laterally located next to the through-holes 1001 on the patterned back surface S202A of the protruding semiconductor substrate 202 is retained, while the remaining dielectric material is removed; the remaining dielectric material constitutes the dielectric layer 52.

[0156] In some embodiments, the other planarization process may include a polishing process, a chemical mechanical polishing process, an etching process, or a combination thereof. The etching process may include dry etching, wet etching, or a combination thereof. For example, such as... Figure 18 As shown, the surface S52 of the dielectric layer 52 is substantially flush with the surface S1001 of the via 1001. That is, the surface S52 of the dielectric layer 52 is substantially coplanar with the surface S1001 of the via 1001. In some embodiments, a cleaning step may be optionally performed after each planarization process, for example to clean and remove residues generated from the planarization process. However, this disclosure is not limited thereto, and each planarization process may be performed by any other suitable method.

[0157] refer to Figure 19 In some embodiments, the redistribution circuit structure 1500 is formed on the circuit chip W1, wherein the redistribution circuit structure 1500 is electrically coupled to the via 1001. Figure 19As shown, for illustrative purposes, the redistribution structure 1500 includes only two building layers (e.g., L1' and L2'), however, this disclosure is not limited thereto. The number of building layers included in the redistribution structure 1500 may be one, two, or more, depending on requirements and / or product design requirements / layout. Building layer L1' may include a dielectric layer 15101, a seed layer 15201, and a conductive layer 15301, and building layer L2' may include a dielectric layer 15102, a seed layer 15202, and a conductive layer 15302, as shown below. Figure 19 As shown. The details, formation, and materials of the dielectric layer 15101, seed layer 15201, and conductive layer 15301 included in the building layer L1', and the details, formation, and materials of the dielectric layer 15102, seed layer 15202, and conductive layer 15302 included in the building layer L2', are similar to or substantially the same as those shown. Figure 1 The details, formation, and materials of the dielectric layer 5101, seed layer 5201, and conductive layer 5301 included in the building layer L1 will not be repeated here.

[0158] The dielectric layer 15101 may be referred to as the dielectric structure DL1' of the building layer L1', and the seed layer 15201 and the conductive layer 15301 may be referred to as the metallization layer ML1' (or redistribution layer) of the building layer L1'. On the other hand, the dielectric layer 15102 may be referred to as the dielectric structure DL2' of the building layer L2', and the seed layer 15202 and the conductive layer 15302 may be referred to as the metallization layer ML2' (or redistribution layer) of the building layer L2'. The metallization layers ML1' and ML2' may be collectively referred to as the routing structure of the redistribution circuit structure 1500. In some embodiments, the line dimensions (e.g., thickness and width) of the metallization layers ML1' and ML2' of the redistribution circuit structure 1500 gradually increase along the direction from the circuit wafer W1 to the metallization layer ML2'. In some alternative embodiments, the seed layers 15201 and 15202 may be omitted.

[0159] For example, a building layer L1' is disposed above the surface S52 of the dielectric layer 52 and electrically connected to the via 1001 through direct contact, thereby electrically coupling to components (e.g., transistor 300) included in the circuit wafers W1, W2, and W3 (e.g., further through interconnects 500 and / or through vias 1002, 1003). In such a case, a building layer L2' is disposed above the building layer L1' and electrically connected to the via 1001 through the building layer L1', thereby electrically coupling to components (e.g., transistor 300) included in the circuit wafers W1, W2, and W3 (e.g., further through interconnects 500 and / or through vias 1002, 1003). That is, the redistribution structure 1500 provides routing functionality to components (e.g., transistor 300) included in the circuit wafers W1, W2, and W3.

[0160] continue Figure 19 In some embodiments, after the redistribution structure 1500 is formed, a dielectric layer 1600, a dielectric layer 1700, and a plurality of conductive terminals 1800 are sequentially formed on the redistribution structure 1500, wherein the conductive terminals 1800 are disposed on the redistribution structure 1500 and electrically coupled to the redistribution structure 1500. Figure 19 As shown, a dielectric layer 1600 may be formed over the redistribution structure 1500, and a plurality of openings (not shown) are formed in the dielectric layer 1600, which penetrate the dielectric layer 1600 and expose a portion of the redistribution structure 1500 (e.g., metallization layer ML2') in an accessible manner. The dielectric layer 1600 may be referred to as a passivation layer. In such a case, a dielectric layer 1700 is formed over the dielectric layer 1600, and a plurality of openings (not shown) are formed in the dielectric layer 1700, which penetrate the dielectric layer 1700 and expose a portion of the redistribution structure 1500 (e.g., metallization layer ML2') exposed by the dielectric layer 1600 in an accessible manner. The dielectric layer 1700 may be referred to as a post-passivation layer. Dielectric layer 1600 may be or include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials, and may be formed by deposition, such as CVD (e.g., PECVD). This disclosure is not limited thereto. Dielectric layer 1700 may be or include a PI layer, a PBO layer, or a dielectric layer formed of other suitable polymers, and may be formed by spin coating or deposition.

[0161] In alternative embodiments, dielectric layer 1600 may be omitted. Additionally or alternatively, dielectric layer 1700 may be omitted. This disclosure is not limited thereto.

[0162] In some embodiments, each conductive terminal 1800 may include an under-ball metallurgy (UBM) pattern 1800u and a conductive element 1800c, the conductive element 1800c being disposed on and electrically coupled to the UBM pattern 1800u. For example... Figure 19As shown, for example, the conductive component 1800c of the conductive terminal 1800 is electrically coupled to the redistribution structure 1500 (e.g., the metallization layer ML2' exposed in an accessible manner by dielectric layers 1600 and 1700) through the UBM pattern 1800u of the conductive terminal 1800. In this case, the conductive terminal 1800 is electrically coupled to the redistribution structure 1500 through dielectric layers 1600 and 1700.

[0163] Each of the UBM patterns 1800u is made, for example, of a metal layer comprising a single layer or of a metallized layer comprising a composite layer having multiple sublayers formed of different materials. The materials of the UBM patterns 1800u may include copper, nickel, titanium, molybdenum, tungsten, titanium nitride, tungsten-titanium, alloys thereof, or similar materials, and may be formed, for example, by an electroplating process. For example, each of the UBM patterns 1800u comprises a titanium layer and a copper layer above the titanium layer. In some embodiments, the UBM patterns 1800u may be formed, for example, using sputtering, PVD, or similar processes. This disclosure does not limit the shape or number of the UBM patterns 1800u.

[0164] Each of the conductive components 1800c includes, for example, microbumps, metal pillars, controlled collapse chip connection (C4) bumps (e.g., which may have a size of about 80 μm, but are not limited to), ball grid array (BGA) bumps (e.g., which may have a size of about 400 μm, but are not limited to), bumps formed by electroless nickel-immersion gold technique (ENIG), bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG), etc. This disclosure is not limited thereto. This disclosure does not limit the shape and number of conductive terminals 1800.

[0165] refer to Figure 20 In some embodiments, after forming the conductive terminal 1800, a dicing (monomerization) process is performed to cut through the dielectric layer 1600, dielectric layer 1700, stacked structure (including circuit wafers W1 to W3), and carrier 50 to form multiple stacking units 1000. Figure 20For the sake of illustration and simplicity, only one stacking unit 1000 is shown in the image. Each stack unit 1000 may include a carrier 50, a semiconductor die 30 (e.g., a product of cutting through a circuit wafer W3) disposed on and thermally coupled to the carrier 50 and in a third level T3, a semiconductor die 20 (e.g., a product of cutting through a circuit wafer W2) disposed on and electrically coupled to the semiconductor die 30 and in a second level T2, a semiconductor die 10 (e.g., a product of cutting through a circuit wafer W1) disposed on and electrically coupled to the semiconductor die 20 and in a first level T1, a redistribution circuit structure 1500 disposed on and electrically coupled to the semiconductor die 10 in the first level T1, a dielectric layer 1600 disposed on the redistribution circuit structure 1500, a dielectric layer 1700 disposed on the dielectric layer 1600, and a plurality of conductive terminals 1800 disposed on the redistribution circuit structure 1500 and electrically coupled to the redistribution circuit structure 1500 through the dielectric layers 1600 and 1700. For example, in the stacked cell 1000, the sidewalls of the carrier 50, the semiconductor die 30, the semiconductor die 20, the semiconductor die 10, the redistribution structure 1500, the dielectric layer 1600, and the dielectric layer 1700 are aligned with each other. That is, the sidewalls of the carrier 50, the semiconductor die 30, the semiconductor die 20, the semiconductor die 10, the redistribution structure 1500, the dielectric layer 1600, and the dielectric layer 1700 together constitute the sidewalls of the stacked cell 1000, such as... Figure 20 As shown. In one embodiment, the dicing (monodilation) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. This disclosure is not limited thereto.

[0166] In some embodiments, some of the conductive terminals 1800 are electrically coupled to the semiconductor die 10 through the redistribution wiring structure 1500 and the via 1001; some of the conductive terminals 1800 are electrically coupled to the semiconductor die 20 through the redistribution wiring structure 1500, the internal interconnects 500 of the semiconductor die 10, and the vias 1001 and 1002; and some of the conductive terminals 1800 are electrically coupled to the semiconductor die 30 through the redistribution wiring structure 1500, the internal interconnects 500 of the semiconductor die 10, and the vias 1001 and 1002. This disclosure is not limited thereto. In an alternative embodiment, some of the conductive terminals 1800 are electrically coupled to the semiconductor die 10 through the redistribution wiring structure 1500 and the via 1001; some of the conductive terminals 1800 are electrically coupled to the semiconductor die 30 through the redistribution wiring structure 1500, the internal interconnects 500 of the semiconductor die 10, and the vias 1001, 1002, 500, and 1003 of the semiconductor die 30; and some of the conductive terminals 1800 are electrically coupled to the semiconductor die 20 through the redistribution wiring structure 1500, the internal interconnects 500 of the semiconductor die 10, and the vias 1001, 1002, 500, and 1003 of the semiconductor die 30.

[0167] refer to Figure 21 In some embodiments, a thermal dissipating module is provided and coupled to a stacking cell 1000 to form a semiconductor device 10000A. In a non-limiting example, the thermal dissipating module includes a lid 800 and a heat sink 900. For example, such as Figure 21As shown, the cover 800 is disposed (e.g., adhered to) the carrier 50 (e.g., at its surface S50) via a thermally conductive adhesive 710 between the cover 800 and the carrier 50, and the heat sink 900 is disposed (e.g., adhered to) the cover 800 (e.g., at its surface S800) via a thermally conductive adhesive 720 between the heat sink 900 and the cover 800. That is, the cover 800 is thermally coupled to the stacking unit 1000 via the thermally conductive adhesive 710, and the heat sink 900 is thermally coupled to the stacking unit 1000 via the thermally conductive adhesive 720, the cover 800, and the thermally conductive adhesive 710. Due to the heat dissipation modules (e.g., 800 and / or 900), the thermal dissipation of the semiconductor device 10000A is further improved. However, this disclosure is not limited thereto. In another non-limiting example, the heat dissipation module may consist of only a cover 800 or a heat sink 900. In embodiments where the cover 800 is omitted, the heat sink 900 is thermally coupled to the stack unit 1000 via a thermally conductive adhesive 720 or 710. Alternatively, if the heat dissipation of the semiconductor device 10000A can be well controlled by thermal control components (e.g., 400A, 400B) embedded therein, the heat dissipation module can be completely omitted from the semiconductor device 10000A.

[0168] For example, thermally conductive adhesives 710 and 720 are independently made of thermally conductive materials or any material capable of heat transfer. Thermally conductive adhesives 710 and 720 can independently be any suitable adhesive, glue, epoxy resin, underfill, die attach film (DAF), thermal interface material (TIM), or the like. For example, cover 800 and radiator 900 are independently made of materials with a high thermal conductivity of about 200 W / (m·K) to about 400 W / (m·K) or higher. Cover 800 and radiator 900 can be independently formed of materials with high thermal conductivity, such as steel, stainless steel, copper, the like, combinations thereof, or any material with good thermal conductivity for a heat dissipation mechanism. In some embodiments, cover 800 and radiator 900 are independently coated with another metal. Cover 800 and radiator 900 can be independently a single continuous material, or can comprise multiple components having the same or different materials. Figure 21 The heat dissipation module shown is for illustrative purposes only. The cover 800 can be of any suitable form (e.g., plate form), and the heat sink 900 can be of any suitable form (e.g., fin form, etc.). This disclosure is not limited thereto.

[0169] In some embodiments, the semiconductor device 10000A includes thermal control components (e.g., 400A, 400B) in the local interconnects (formed in MEOL) and global interconnects (formed in BEOL) of the interconnects (e.g., 500) included in each semiconductor die (e.g., 10, 20, and / or 30), such as... Figure 21 As shown. However, this disclosure is not limited thereto. In alternative embodiments, one or more thermal control components (not shown) may be formed only in the global interconnect (formed in BEOL) of the interconnect (e.g., 500) included in each semiconductor die (e.g., 10, 20 and / or 30), wherein the vertical portion of the thermal control component extends only through the global interconnect (formed in BEOL) of the interconnect (e.g., 500).

[0170] In this disclosure, the thermal control unit 410 may be more specifically referred to as a thermal via, see reference. Figures 32 to 37 In a non-limiting example, the thermal control unit 410 includes a heat-perforated hole (see reference) containing a core portion 4010C. Figure 32 The core 4010C is composed of, for example, Figure 4 The thermal energy storage material 4010 described herein is used. This disclosure is not limited thereto. In another non-limiting example, the thermal control unit 410 includes a core portion 4010C and a shell portion 4030S laterally covering the core portion 4010C, which are heat-perforated (see reference). Figure 33 ), wherein the outer casing 4030S is made of a different material than such Figure 4 The thermal energy storage material 4010 is made of a thermal energy storage material. For example, the outer shell 4030S is made of a thermal energy storage material such as AlN, BN, diamond-like carbon, Al2O3, BeO, combinations thereof, or similar materials, which can be formed by appropriate manufacturing techniques such as spin coating, CVD (e.g., PECVD). In some embodiments, the material of the outer shell 4030S can be a dielectric material (or layer) with high thermal conductivity. In another non-limiting example, the thermal control unit 410 includes a core portion 4010C and an outer shell 4040S that laterally covers the core portion 4010C (see reference). Figure 34 The outer casing 4040S is made of metal or a metal alloy (rather than of...). Figure 4The heat storage material 4010 is used. For example, the outer casing 4040S is made of metal, metal alloy (e.g., copper or copper alloy), combinations thereof, or the like, and can be formed by suitable manufacturing techniques such as plating or deposition. In some embodiments, the outer casing 4040S may be a conductive material (or layer) with high thermal conductivity. In another non-limiting example, the thermal control unit 410 includes a core portion 4030C and an outer casing 4010S that laterally covers the core portion 4030C (see reference). Figure 35 The core 4030C is different from that of other core components. Figure 4 The thermal energy storage material 4010 is made of thermal energy storage material, and the outer casing 4010S is made of such material. Figure 4 The thermal energy storage material 4010 is made of a thermal energy storage material. For example, the core portion 4030C is made of a thermal energy storage material such as AlN, BN, diamond-like carbon, Al2O3, BeO, combinations thereof, or the like, which can be formed by appropriate manufacturing techniques such as spin coating, CVD (e.g., PECVD), etc. In some embodiments, the material of the core portion 4030C can be a dielectric material (or layer) with high thermal conductivity. In another non-limiting example, the thermal control unit 410 includes the core portion 4040C and a shell portion 4010S that laterally covers the core portion 4040C (see reference). Figure 36 The core 4040C is made of metal or a metal alloy, rather than a material such as... Figure 4 The thermal energy storage material 4010 is made of a thermal energy storage material. For example, the core portion 4040C is made of metal, metal alloy (e.g., copper or copper alloy), combinations thereof, or the like, and can be formed by suitable manufacturing techniques such as plating or deposition. In some embodiments, the core portion 4040C may be a conductive material (or layer) with high thermal conductivity. In a non-limiting example, the thermal control portion 410 includes a heat-perforated hole (see reference) containing the core portion 4040C. Figure 37 Similarly, in this disclosure, the thermal control unit 412 can be more commonly referred to as a heat through-hole, which employs... Figures 32 to 37 The architecture. This disclosure is not limited to this.

[0171] In embodiments having a heat-permeable opening including a core portion and a housing portion, the heat-permeable opening may be formed, but is not limited to, in the following manner: in the opening (e.g., Figure 3 In OP1, material of the outer shell portion is conformally deposited above the inner interconnect 500 (e.g., surface S500); material of the core portion is formed on the material of the outer shell portion, the material of the core portion further filling the opening OP1; and a planarization process (e.g., similar to...) is performed. Figure 5The process involves removing excess material from the surface S500 of the inner interconnect 500 of the core portion and / or the outer shell portion, such that the remaining material of the core portion and the outer shell portion within the opening OP1 forms a heat-permeable hole including the core portion and the outer shell portion.

[0172] In some embodiments, thermal control components 400A and 400B of the semiconductor device 10000A are connected to each other and perpendicularly aligned (e.g., in direction Z). However, this disclosure is not limited thereto. In some embodiments, Figure 22 Semiconductor device 10000B and Figure 21 Similar to the semiconductor device 10000A, the difference is that semiconductor dies 10, 20, and 30 all employ thermal control components 400A, wherein these thermal control components 400A contained in semiconductor dies 10, 20, and 30 are not connected to each other. For example... Figure 22 As shown, for example, the thermal control components 400A included in semiconductor dies 10, 20, and 30 are not perpendicularly aligned with each other. In other words, in a vertical projection along the Z direction (e.g., the XY plane), the thermal control components 400A included in semiconductor dies 10, 20, and 30 are at least partially offset from each other. Details, formation, and materials of the thermal control components 400A have been described in [the original text]. Figures 3 to 9 and combined Figures 28 to 29 As described in the previous section, it will not be repeated here. Due to the heat-conducting component 400A, the heat generated by hot spots (e.g., transistor 300) in the semiconductor dies 10-30 inside the semiconductor device 10000B can be directed to the heat-conducting component 400A and stored inside it. This reduces the thermal spikes of hot spots (e.g., transistor 300) inside the semiconductor device 10000B, thereby improving the reliability of the semiconductor device 10000B.

[0173] In some embodiments, thermal control components 400A and 400B used in the semiconductor device 10000A are interconnected and formed in individual process steps. However, this disclosure is not limited thereto. In some embodiments, Figure 23 Semiconductor device 10000C and Figure 21 Similar to the semiconductor device 10000A, the difference is that the semiconductor device 10000C uses a thermal control component 400C to replace the interconnected thermal control components 400A and 400B. For example... Figure 23As shown, for example, the thermal control assembly 400C includes a thermal control section 414 and a thermal control section 420 physically connected to and thermally coupled to the thermal control section 414, wherein the thermal control section 414 completely penetrates the interconnects 500 of the semiconductor die 20, semiconductor die 30, and semiconductor die 10, and the thermal control section 420 completely penetrates the dielectric layer 6003. For example, the thermal control section 414 is cylindrical or cylindrical in shape and is adjacent to a hot spot (e.g., transistor 300). The thermal control section 414 may be referred to as the vertical portion of the thermally conductive assembly 400C, and the thermal control section 420 may be referred to as the horizontal portion of the thermally conductive assembly 400C. The thermal control section 414 is integrally formed and is adjacent to a hot spot (e.g., transistor 300 in semiconductor dies 10-30), in some embodiments. The formation and material of the thermal control section 414 are similar to those previously described. Figures 3 to 5 and combined Figure 28 The thermal control unit 410 described herein is similar in formation and material to or substantially the same as that described herein, and the thermal control unit 420 is similar in formation and material to that described herein. Figures 7 to 9 and combined Figure 29 The description has been provided; therefore, for the sake of brevity, it will not be repeated here. In some embodiments, for each thermally conductive component 400C, the thermal control unit 414 and the thermal control unit 420 are arranged in a one-to-one architecture.

[0174] In this disclosure, the thermal control unit 414 can be more specifically referred to as a heat through-hole, which employs... Figures 32 to 37 The architecture. This disclosure is not limited to this.

[0175] In some embodiments, the thermally conductive component 400C is referred to as a thermal capacitor, thermal storage capacitor, thermal control component, thermal control element, thermal control module, thermal management component, thermal management element, or thermal management module. For illustrative purposes, Figure 23 Only one thermal control component 400C is shown in the diagram; however, this disclosure is not limited thereto. The number of thermal control components 400C (including 414 and 420) can be one, two, or more (e.g., as shown in the diagram). Figure 28 and Figure 29As shown, the thermal control components 400C can be selected and specified according to requirements and / or product design requirements / layout. For example, the number of thermal control units 414 and 420 can be adjusted to control the number of thermal control components 400C. Due to the thermal control components 400C, the heat generated by hot spots (e.g., transistors 300) in the semiconductor dies 10-30 inside the semiconductor device 10000C can be directed to the thermal control components 400C and stored therein, which reduces the thermal spikes of hot spots (e.g., transistors 300) inside the semiconductor device 10000C, thereby improving the reliability of the semiconductor device 10000C. For example, the thermal control components 400C are electrically isolated from and thermally coupled to the interconnects 500 and components (e.g., transistors 300) in the semiconductor dies 10-30.

[0176] In some embodiments, in the semiconductor device 10000C, the thermal control section 420 of the thermal control assembly 400C penetrates the dielectric layer 6003 and is laterally covered by the dielectric layer 6003, such as Figure 23 As shown. However, this disclosure is not limited thereto. In some embodiments, Figure 24 Semiconductor device 10000D and Figure 23 Similar to the semiconductor device 10000C, the difference is that the semiconductor device 10000D uses a thermal control component 400D instead of the thermal control component 400C. For example... Figure 24 As shown, for example, a thermal control assembly 400D includes a thermal control section 414 and a thermal control section 422 physically connected to and thermally coupled to the thermal control section 414, wherein the thermal control section 414 completely penetrates the interconnects 500 of the semiconductor die 30, semiconductor die 20, and semiconductor die 10, and the thermal control section 422 is configured to completely replace the dielectric layer 6003. In this case, a bonding layer 6203 is disposed on and connected to the thermal control section 422 of the thermal control assembly 400D, and the semiconductor device 10000D does not have the dielectric layer 6003. The thermal control section 414 may be referred to as the vertical portion of the thermally conductive assembly 400D, and the thermal control section 422 may be referred to as the horizontal portion of the thermally conductive assembly 400D. In some embodiments, the thermal control section 414 is integrally formed and is adjacent to a hot spot (e.g., a transistor 300 in semiconductor dies 10-30). For example, the thermal control section 414 is cylindrical or cylindrical in shape and is located adjacent to the hot spot (e.g., transistor 300). In some embodiments, after the thermal control section 414 is formed, the thermal control section 422 is immediately formed in the form of a continuous plate and overlaps with the hot spot (e.g., transistor 300 in semiconductor dies 10-30) (see reference). Figure 30Then, a bonding layer 6203 is formed. The formation and material of the thermal control section 414 are the same as those previously used. Figures 3 to 5 and combined Figure 28 The thermal control unit 410 described herein is similar in formation and material to or substantially the same as the thermal control unit 422 in formation and material combination. Figure 30 Compared with the previous Figures 7 to 9 The thermal control unit 420 described herein is similar in formation and material to, or substantially the same as, that described herein; therefore, for the sake of brevity, will not be repeated here. For illustrative purposes, Figure 24 The diagram only shows a thermal control assembly 400D with one thermal control unit 414 connected to a thermal control unit 422, but this disclosure is not limited thereto. The number of thermal control units 414 connected to the thermal control unit 422 in the thermal control assembly 400D (including 414 and 422) can be one, two, or more, and can be selected and specified according to requirements and / or product design requirements / layout. For example, in some embodiments, for each thermally conductive assembly 400D, the thermal control unit 414 and the thermal control unit 422 are arranged in a one-to-one architecture. In alternative embodiments, for each thermally conductive assembly 400D, the thermal control unit 414 and the thermal control unit 422 are arranged in a many-to-one architecture.

[0177] For example, the thermally conductive component 400D is electrically isolated from and thermally coupled to the interconnects 500 and components (e.g., transistor 300) in the semiconductor die 10-30. In some embodiments, the thermally conductive component 400D is referred to as a thermal capacitor, thermal storage capacitor, thermal control component, thermal control module, thermal management component, thermal management member, or thermal management module. Due to the thermally conductive component 400D, the heat generated by hot spots (e.g., transistor 300) in the semiconductor die 10-30 inside the semiconductor device 10000D can be directed to the thermally conductive component 400D and stored therein, which mitigates the thermal spikes of hot spots (e.g., transistor 300) inside the semiconductor device 10000D, thereby improving the reliability of the semiconductor device 10000D.

[0178] In some embodiments, in a cross-sectional view of the semiconductor device 10000A, the thermal control components 400A and 400B used in the semiconductor device 10000A independently have a T-shape, such as Figure 21 As shown. However, this disclosure is not limited thereto. In some embodiments, Figure 25 Semiconductor device 10000E and Figure 21Similar to semiconductor device 10000A, except that semiconductor device 10000E uses thermal control component 400E instead of thermal control components 400A and 400B. In some embodiments, in a cross-sectional view of semiconductor device 10000E, the thermal control component 400E included in semiconductor device 10000E is U-shaped (upside down), as shown... Figure 25 As shown.

[0179] For example, the thermal control assembly 400E includes a plurality of thermal control sections 410 and a thermal control section 424 thermally coupled to the plurality of thermal control sections 410. Each thermal control section 410 completely penetrates the interconnect 500 of the semiconductor die 10 and is arranged around a hot spot (e.g., 300) of the semiconductor die 10. The thermal control section 424 completely penetrates the dielectric layer 6001 and is physically connected to the thermal control section 410. In this case, the thermal control section 424 is disposed above the interconnect 500 and the thermal control section 410 and is laterally covered by the dielectric layer 6001. A bonding layer 6201 is disposed above and connected to the thermal control section 424 and the dielectric layer 6001 of the thermal control assembly 400E. The thermal control section 410 may be referred to as the vertical portion of the thermally conductive assembly 400E, and the thermal control section 424 may be referred to as the horizontal portion of the thermally conductive assembly 400E. In some embodiments, the thermal control section 410 is formed in a cylindrical or cylindrical shape and is adjacent to (e.g., surrounding) a hot spot (e.g., the transistor 300 of the semiconductor die 10). The thermal control section 424 is formed as a segment, sheet, or plate overlapping the hot spot (e.g., the transistor 300 of the semiconductor die 10) for thermal connection to the thermal control section 410 adjacent to (e.g., surrounding) the hot spot (e.g., the transistor 300 of the semiconductor die 10). The formation and material formation of the thermal control section 410 are described in detail below. Figures 3 to 9 and combined Figure 28 The description includes the formation and material bonding of the thermal control unit 424. Figure 31 Compared with the previous Figures 7 to 9 The thermal control unit 420 described herein is similar in form and material to or substantially the same as that described herein; therefore, for the sake of brevity, it will not be repeated here.

[0180] For the purpose of explanation, Figure 25 Only a thermal control assembly 400E with two thermal control units 410 connected to a thermal control unit 424 is shown in the illustration; however, this disclosure is not limited thereto. The number of thermal control units 410 connected to the thermal control unit 424 in the thermal control assembly 400E (including 410 and 424) can be two, three, four, or more, and can be selected and specified according to requirements and / or product design requirements / layout. In some embodiments, for each thermally conductive assembly 400E, the thermal control units 410 and 424 are arranged in a many-to-one architecture.

[0181] In some embodiments, the thermally conductive component 400E is referred to as a thermal capacitor, thermal storage capacitor, thermal control component, thermal control member, thermal control module, thermal management component, thermal management member, or thermal management module. Figure 25 The diagram only shows one thermal control component 400E in the first level T1; however, the number of thermal control components 400E can be one, two, or more, and / or can be formed in at least one of the first level T1, the second level T2, and the third level T3, which can be selected and specified according to requirements and / or product design requirements / layout. This disclosure is not limited thereto. Due to the thermally conductive component 400E, the heat generated by hot spots (e.g., transistor 300) in the semiconductor dies 10-30 inside the semiconductor device 10000E can be directed to the thermally conductive component 400E and stored therein, which reduces the thermal spikes of hot spots (e.g., transistor 300) inside the semiconductor device 10000E, thereby improving the reliability of the semiconductor device 10000E. For example, the thermally conductive component 400E is electrically isolated from and thermally coupled to the interconnects 500 and components (e.g., transistor 300) in the semiconductor die 10-30.

[0182] Furthermore, since no thermal control components are present in the dielectric layer 6002 of the second level T2 and the dielectric layer 6003 of the third level T3 included in the semiconductor device 10000E, the uniformity at the bonding surface can be maintained. Therefore, the bonding layer 6202 disposed on the dielectric layer 6002 and the bonding layer 6203 disposed on the dielectric layer 6003 are omitted in some embodiments. For example... Figure 25As shown, a bonding interface IF4, including a dielectric-to-dielectric bonding interface (e.g., an oxide-to-silicon bonding interface or a nitride-to-silicon bonding interface), may exist between a third layer T3 (e.g., the substrate 200B of the semiconductor die 30) and a second layer T2 (e.g., dielectric layer 6002), and the bonding interface IF4 can be considered as the bonding interface between the third layer T3 and the second layer T2. In some embodiments, if a native oxide is formed over the substrate 202 (e.g., the back surface S202B) of the semiconductor die 30, the bonding interface IF4 having a dielectric-to-dielectric bonding interface further includes an oxide-to-oxide bonding interface or a nitride-to-oxide bonding interface. In this configuration, a bonding interface IF5 (e.g., dielectric layer 6003) exists between the carrier 50 and the third layer T3, comprising a dielectric-to-dielectric bonding interface (e.g., an oxide-to-silicon bonding interface or a nitride-to-silicon bonding interface). This bonding interface IF5 can be considered as the bonding interface between the carrier 50 and the third layer T3. In some embodiments, if a native oxide is formed over the carrier 50, the bonding interface IF5 having the dielectric-to-dielectric bonding interface further includes an oxide-to-oxide bonding interface or a nitride-to-oxide bonding interface.

[0183] In some embodiments disclosed herein, a thermal control component 400F is employed in the semiconductor device 10000F, such as Figure 26 As shown. For example, Figure 26 Semiconductor device 10000F and Figure 21 Similar to the semiconductor device 10000A, except that the semiconductor device 10000F employs at least one thermal control component 400F, instead of thermal control components 400A and 400B. In some embodiments, each thermal control component 400F included in the semiconductor device 10000F includes a thermal control section 416 (each referred to as a vertical portion of the corresponding thermal control component 400F) and a high thermal conductive layer 6400 (e.g., 6401, 6402, or 6403) (each referred to as a horizontal portion of the corresponding thermal control component 400F). Figure 26As shown, dielectric layer 6001 is replaced with high thermal conductivity layer 6401, dielectric layer 60021 is replaced with high thermal conductivity layer 6402, and dielectric layer 60031 is replaced with high thermal conductivity layer 6403. A thermal control unit 416 completely penetrates the high thermal conductivity layer 6401 and the interconnect 500 in the first layer T1 to form a thermal control component 400F (including 416 and 6401) in the first layer T1. A thermal control unit 416 completely penetrates the high thermal conductivity layer 6402 and the interconnect 500 in the second layer T2 to form a thermal control component 400F (including 416 and 6402) in the second layer T2. For example, a thermal control unit 416 completely penetrates the high thermal conductivity layer 6403 and the interconnect 500 in the third layer T3 to form a thermal control component 400F (including 416 and 6403) in the third layer T3. In this disclosure, the thermal control unit 414 can also be referred to as a heat through-hole, which employs... Figures 32 to 36 The architecture. This disclosure is not limited to this.

[0184] In some embodiments, for each thermally conductive component 400F (e.g., including 416 and 6301; 416 and 6302; 416 and 6303), the thermal control unit 416 and the high thermal conductivity layer 6400 (e.g., 6401, 6402, or 6403) are arranged in a one-to-one architecture. However, this disclosure is not limited thereto; alternatively, in each thermally conductive component 400F (e.g., including 416 and 6301; 416 and 6302; 416 and 6303), the thermal control unit 416 and the high thermal conductivity layer 6400 (e.g., 6401, 6402, or 6403) are arranged in a many-to-one architecture.

[0185] The high thermal conductivity layer 6400 (e.g., 6401, 6402, and / or 6403) can be made of SiO2, AlN, BN, diamond-like carbon, Al2O3, BeO, combinations thereof, or similar materials. It can be formed using appropriate manufacturing techniques such as spin coating, CVD (e.g., PECVD), and can be patterned using photolithography and / or etching processes. Etching processes can include dry etching, wet etching, or combinations thereof. After etching, a cleaning step can be selectively performed, for example, to clean and remove residues generated from the etching process. The formation and material of the thermal control unit 416 are related to... Figures 3 to 5 and combined Figure 28 The thermal control unit 410 described herein is similar in form and material to or substantially the same as described herein, and therefore will not be repeated here.

[0186] In some embodiments, a high thermal conductivity layer 6401 is formed after the formation of the interconnect 500 in the first layer T1, followed by the formation of a thermal control section 416, wherein the thermal control section 416 penetrates the high thermal conductivity layer 6401 and the interconnect 500 in the first layer T1 to thermally couple (e.g., physically contact) with the high thermal conductivity layer 6401, thereby forming a thermally conductive component 400F in the first layer T1. In some embodiments, a high thermal conductivity layer 6402 is formed after the formation of the interconnect 500 in the second layer T2, followed by the formation of a thermal control section 416, wherein the thermal control section 416 penetrates the high thermal conductivity layer 6402 and the interconnect 500 in the second layer T2 to thermally couple (e.g., physically contact) with the high thermal conductivity layer 6402, thereby forming a thermally conductive component 400F in the second layer T2. In some embodiments, the high thermal conductivity layer 6403 is formed after the formation of the interconnect 500 in the third layer T3, followed by the formation of a thermal control unit 416, wherein the thermal control unit 416 penetrates the high thermal conductivity layer 6403 and the interconnect 500 in the third layer T3 to thermally couple (e.g., physically contact) with the high thermal conductivity layer 6403, thereby forming a thermally conductive component 400F in the third layer T3.

[0187] In some embodiments, the thermally conductive component 400F is referred to as a thermal capacitor, a thermal storage capacitor, a thermal control component, a thermal control member, a thermal control module, a thermal management component, a thermal management member, or a thermal management module. Due to the thermally conductive component 400F, heat generated by hot spots (e.g., transistor 300) in the semiconductor dies 10-30 within the semiconductor device 10000F can be directed to and stored within the thermally conductive component 400F, which mitigates thermal spikes in the hot spots (e.g., transistor 300) within the semiconductor device 10000F, thereby improving the reliability of the semiconductor device 10000F. For example, the thermally conductive component 400F is electrically isolated from and thermally coupled to the interconnects 500 and components (e.g., transistor 300) in the semiconductor dies 10-30.

[0188] In some embodiments, Figure 27 10000G semiconductor device and Figure 21 Similar to the semiconductor device 10000A, except that only the thermal control component 400A is included in the first layer T1 of the semiconductor device 10000G, and the dielectric layer 6001 is replaced by a high thermal conductivity layer (e.g., 6401). Details, formation, and materials of the thermal control component 400A have been described above. Figures 3 to 9 The details, formation, and materials of the high thermal conductivity layer 6401 are described above. Figure 25 As described in the text; therefore, for the sake of brevity, it will not be repeated here. Figure 27As shown, the thermal control component 400A is further thermally coupled to the high thermal conductivity layer 6401. Figure 27 Only one thermal control component 400A is shown in the first level T1. However, the number of thermal control components 400A can be one, two, or more, and / or can be formed in at least one of the first level T1, the second level T2 (with a high thermal conductivity layer 6402 replacing the dielectric layer 6002), and the third level T3 (with a high thermal conductivity layer 6403 replacing the dielectric layer 6003), which can be selected and specified according to requirements and / or product design requirements / layout. This disclosure is not limited thereto. Due to the thermally conductive component 400A and the high thermal conductivity layer 6401 thermally coupled thereto, the heat generated by hot spots (e.g., transistor 300) in the semiconductor dies 10-30 inside the semiconductor device 10000G can be directed to the thermally conductive component 400A and the high thermal conductivity layer 6401 thermally coupled thereto and stored therein. This reduces the thermal spikes of hot spots (e.g., transistor 300) inside the semiconductor device 10000G, thereby improving the reliability of the semiconductor device 10000G. For example, the thermally conductive component 400A and the thermally coupled high thermal conductivity layer 6401 are electrically isolated from and thermally coupled to the interconnects 500 and components (e.g., transistors 300) in the semiconductor die 10-30.

[0189] Furthermore, in some embodiments, since no thermal control components are present in the dielectric layer 6002 of the second level T2 and the dielectric layer 6003 of the third level T3 included in the semiconductor device 10000G, the uniformity at the bonding surface can be maintained. Therefore, the bonding layer 6202 disposed on the dielectric layer 6002 and the bonding layer 6203 disposed on the dielectric layer 6003 are omitted. Figure 27As shown, a bonding interface IF4, including a dielectric-to-dielectric bonding interface (e.g., an oxide-to-silicon bonding interface or a nitride-to-silicon bonding interface), may exist between a third layer T3 (e.g., the substrate 200B of the semiconductor die 30) and a second layer T2 (e.g., dielectric layer 6002), and the bonding interface IF4 can be considered as the bonding interface between the third layer T3 and the second layer T2. In some embodiments, if a native oxide is formed over the substrate 202 (e.g., the back surface S202B) of the semiconductor die 30, the bonding interface IF4 having a dielectric-to-dielectric bonding interface further includes an oxide-to-oxide bonding interface or a nitride-to-oxide bonding interface. In this configuration, a bonding interface IF5 (e.g., dielectric layer 6003) exists between the carrier 50 and the third layer T3, comprising a dielectric-to-dielectric bonding interface (e.g., an oxide-to-silicon bonding interface or a nitride-to-silicon bonding interface). This bonding interface IF5 can be considered as the bonding interface between the carrier 50 and the third layer T3. In some embodiments, if a native oxide is formed over the carrier 50, the bonding interface IF5 having the dielectric-to-dielectric bonding interface further includes an oxide-to-oxide bonding interface or a nitride-to-oxide bonding interface.

[0190] Figures 38 to 41 Schematic cross-sectional views are shown of various stages in a method of manufacturing a semiconductor device (e.g., 20000) according to some embodiments of this disclosure. Figures 42 to 43 Schematic cross-sectional views of semiconductor devices (e.g., 30000 or 40000) according to alternative embodiments of this disclosure are shown respectively. Components similar to or substantially the same as those previously described will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated.

[0191] refer to Figure 38 In some embodiments, in Figure 15 In the third layer T3 of the structure shown, a dielectric layer 6003 and a thermal control component 420 are successively formed on the top surface S500 of the interconnect 500. A dicing (monomerization) process is then performed to form multiple stacking units 40A. Details, formation, and materials of the dielectric layer 6003 and the thermal control component 420 have been described in [the following text is missing from the original extract]. Figure 16 As described in the text, it will not be repeated here. Figure 38For illustrative purposes and simplicity, only one stacking cell 40A is shown. Each of the stacking cells 40A may include a semiconductor die 30 in a third layer T3 (e.g., a product of cutting through a circuit wafer W3), a semiconductor die 20 in a second layer T2 disposed on and electrically coupled to the semiconductor die 30 in the third layer T3 (e.g., a product of cutting through a circuit wafer W2), and a semiconductor die 10 in a first layer T1 disposed on and electrically coupled to the semiconductor die 20 in the second layer T2 (e.g., a product of cutting through a circuit wafer W1). For example, in the stacking cell 40A, the sidewalls of the semiconductor die 30, the semiconductor die 20, and the semiconductor die 10 are aligned with each other. That is, the sidewalls of the semiconductor die 30, the semiconductor die 20, and the semiconductor die 10 together constitute the sidewalls of the stacking cell 40A. In one embodiment, the dicing (monodilation) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. This disclosure is not limited thereto.

[0192] refer to Figure 39 In some embodiments, a carrier substrate 54 is provided, and a release layer 56 is formed over the carrier substrate 54. The carrier substrate 54 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 54 may be a wafer, allowing multiple packages to be formed simultaneously over the carrier substrate 54. The release layer 56 may be formed of a polymeric material that can be removed along with the carrier substrate 54 from the overlay structure to be formed in subsequent steps. In some embodiments, the release layer 56 is an epoxy-based heat-releasing material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 56 may be a UV adhesive that loses its adhesive properties when exposed to ultraviolet (UV) light. The release layer 56 may be dispensed and cured as a liquid, may be laminated onto the carrier substrate 54 as a laminate film, or may be formed on the carrier substrate 54 by any suitable method. The top surface of release layer 56 can be smoothed.

[0193] In some embodiments, at least one stacking unit 40A is picked up and placed above the release layer 56 and on the carrier substrate 54. Figure 39As shown, for illustrative purposes, only one stacking unit 40A is presented as at least one stacking unit 40A, but it is worth noting that the number of at least one stacking unit 40A can be one, two, three, or more, and this disclosure is not limited thereto. For example, the top surface S500 of the interconnect 500 included in the third level T3 is placed above the release layer 56 (e.g., in physical contact). Figure 39 As shown, the rear surface S202 of the semiconductor substrate 202 included in the first layer T1 can be facing upwards.

[0194] refer to Figure 40 In some embodiments, the stacked cells 40A are encapsulated in an insulating material. In some embodiments, an insulating encapsulation material (not shown) is formed over the stacked cells 40A and the release layer 56 on the carrier substrate 54, wherein the stacked cells 40A and the release layer 56 exposed by the stacked cells 40A are completely covered by the insulating encapsulation material. The insulating encapsulation material may be made of a dielectric material (e.g., an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), tetraethyl orthosilicate (TEOS) oxide, or the like) or any insulating material suitable for gap filling, and may be formed by deposition (e.g., a CVD process). Alternatively, the insulating encapsulation material may be a molding compound, a molding underfill adhesive, a resin (e.g., an epoxy-based resin), or the like, which may be formed by a molding process. The molding process may include a compression molding process or a transfer molding process. The insulating encapsulation material may include polymers (e.g., epoxy resins, phenolic resins, silicone resins, or other suitable resins) or other suitable materials. Alternatively, the insulating encapsulation material may comprise an acceptable insulating encapsulation material. In some embodiments, the insulating encapsulation material further comprises inorganic fillers or inorganic compounds (e.g., silica, clay, etc.) that can be added to the insulating encapsulation material to optimize the coefficient of thermal expansion (CTE) of the insulating encapsulation material. This disclosure is not limited thereto.

[0195] After forming the insulating encapsulation material, a planarization process is performed on the insulating encapsulation material to form an insulating encapsulation 1900 that exposes the stacked cell 40A. For example, a portion of the insulating encapsulation material is removed to form an insulating encapsulation 1900 having a surface S1900b, wherein the surface S1900b of the insulating encapsulation 1900 can be tactilely exposed to the first layer T1 (e.g., the rear surface S202A of the semiconductor substrate 202 included in the first layer T1 of the semiconductor die 10 and the surface S1001 of the via 1001 exposed by the rear surface S202A). For example, the surface S1900b of the insulating encapsulation 1900 is substantially flush with the rear surface S202A of the semiconductor substrate 202 included in the first layer T1 of the semiconductor die 10 and the surface S1001 of the via 1001. In other words, the surface S1900b of the insulating encapsulation 1900 is substantially coplanar with the rear surface S202A of the semiconductor substrate 202 included in the first layer T1 of the semiconductor die 10 and the surface S1001 of the through hole 1001.

[0196] In some embodiments, a cleaning step may be optionally performed after the planarization process, for example to clean and remove residues generated from the planarization process. However, this disclosure is not limited to this, and the planarization process can be performed by any other suitable method. Additionally, during the planarization process, a portion of the semiconductor substrate 202 and the via 1001 of the first layer T1 scraped in the stacked cell 40A may be slightly removed. This disclosure is not limited to this. Figure 40 As shown, the stacking unit 40A may be laterally encapsulated in an insulating enclosure 1900.

[0197] Continue to refer to Figure 40 In some embodiments, after forming the insulating enclosure 1900, interconnects 1500, dielectric layers 1600 and 1700, and a plurality of conductive terminals 1800 are formed over the insulating enclosure 1900 and the stacked units 40A laterally encapsulated within the insulating enclosure 1900. Details, formation, and materials of the interconnects 1500, dielectric layers 1600, dielectric layers 1700, and the plurality of conductive terminals 1800 have been described in [details omitted]. Figure 19 This has been discussed before, so for the sake of brevity, it will not be repeated here.

[0198] refer to Figure 41In some embodiments, the carrier substrate 54 is removed. The carrier substrate 54 can be detached (or "peeled off") from the insulating enclosure 1900 and the stacked units 40A laterally encapsulated within the insulating enclosure 1900. In some embodiments, the peeling includes irradiating the release layer 56 with light (e.g., laser light or UV light), causing the release layer 56 to decompose under the heat of the light, and the carrier substrate 54 can be removed. For example, the peeling exposes the insulating enclosure 1900 (e.g., the surface S1900t opposite surface S1900b along direction Z) and the stacked units 40A laterally encapsulated within the insulating enclosure 1900 (e.g., the top surface S6003 of the dielectric layer 6003 included in the third level T3 and the surface S420 of the thermal control portion 420).

[0199] In some embodiments, after removing the carrier substrate 54 and the release layer 56, a bonding layer 6203 and a carrier 50 are sequentially formed on the insulating encapsulation 1900 and on the stacked units 40A laterally encapsulated within the insulating encapsulation 1900. The bonding layer 6203 extends continuously from the stacked units 40A onto the insulating encapsulation 1900, for example, and the carrier 50 completely covers the bonding layer 6203. Figure 41 As shown, the carrier 50 can be bonded to the top surface S6203 of the bonding layer 6203 via the bonding interface IF3. Details, formation, and materials of the bonding layer 6203 have been described in [the diagram / illustration]. Figure 16 The details, formation, and materials of carrier 50 have been discussed in [the document / document / etc.], and have already been [discussed / explained / etc.]. Figure 17 This has been discussed before, so for the sake of brevity, it will not be repeated here.

[0200] Continue to refer to Figure 41 The process involves a cutting (monomeric) process to cut through the carrier 50, bonding layer 6203, insulating encapsulation 1900, rearranged circuit structure 1500, dielectric layer 1600, and dielectric layer 1700 to form multiple stacked units 2000. Figure 41For illustrative purposes and for simplicity, only one stacking cell 2000 is shown in the diagram. Each stacking unit 2000 may include a carrier 50, a stacking unit 40A (a semiconductor die 30 disposed on and thermally coupled to the carrier 50 and in a third level T3, a semiconductor die 20 disposed on and electrically coupled to the semiconductor die 30 and in a second level T2, and a semiconductor die 10 disposed on and electrically coupled to the semiconductor die 20 and in a first level T1), an insulating enclosure 1900 laterally encapsulating the stacking unit 40A, a redistribution structure 1500 disposed on and electrically coupled to the semiconductor die 10 in the first level T1 and extending above the insulating enclosure 1900, a dielectric layer 1600 disposed on the redistribution structure 1500, a dielectric layer 1700 disposed on the dielectric layer 1600, and a plurality of conductive terminals 1800 disposed on the redistribution structure 1500 and electrically coupled to the redistribution structure 1500 through the dielectric layers 1600 and 1700. For example, in stacking cell 2000, the sidewalls of carrier 50, bonding layer 6203, insulating encapsulation 1900, redistribution structure 1500, dielectric layer 1600, and dielectric layer 1700 are aligned with each other. That is, the sidewalls of carrier 50, bonding layer 6203, insulating encapsulation 1900, redistribution structure 1500, dielectric layer 1600, and dielectric layer 1700 together constitute the sidewalls of stacking cell 2000, such as... Figure 41 As shown. In one embodiment, the dicing (monodilation) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. This disclosure is not limited thereto.

[0201] Next, heat dissipation modules can be sequentially formed on the carrier 50. For example, the cover 800 is disposed (e.g., adhered to) the carrier 50 via a thermally conductive adhesive 710 between the cover 800 and the carrier 50, and the heat sink 900 is disposed (e.g., adhered to) the cover 800 via a thermally conductive adhesive 720 between the heat sink 900 and the cover 800. Details, formation, and materials of the thermally conductive adhesive 710, cover 800, thermally conductive adhesive 720, and heat sink 900 have been described in detail. Figure 21The discussion is as follows; therefore, for the sake of brevity, it will not be repeated here. At this point, the semiconductor device 20000 has been manufactured. For example, in the semiconductor device 20000, the sidewalls of the heat sink 900, the sidewalls of the thermally conductive adhesive 720, the sidewalls of the cover 800, the sidewalls of the thermally conductive adhesive 710, and the sidewalls of the stacking unit 2000 are aligned with each other. That is, the sidewalls of the heat sink 900, the sidewalls of the thermally conductive adhesive 720, the sidewalls of the cover 800, the sidewalls of the thermally conductive adhesive 710, and the sidewalls of the stacking unit 2000 together constitute the sidewalls of the semiconductor device 20000. In one embodiment, the dicing (monolithography) process is a wafer dicing process that includes mechanical blade sawing or laser cutting. This disclosure is not limited thereto. However, this disclosure is not limited thereto. In alternative embodiments, the sidewalls of the heat sink 900, the thermally conductive adhesive 720, the cover 800, and / or the thermally conductive adhesive 710 are not aligned with the sidewalls of the stacking unit 2000.

[0202] In some embodiments, Figure 42 Semiconductor devices 30000 and Figure 41 The semiconductor device 20000 is similar, except that stacking cell 40A is replaced with stacking cell 40B. For example... Figure 42 As shown, the stacking unit 40B may include a semiconductor die 30 in a third layer T3, a semiconductor die 20 disposed on and electrically coupled to the semiconductor die 30 in the third layer T3, a semiconductor die 10 disposed on and electrically coupled to the semiconductor die 20 in a first layer T1, and an insulating encapsulation 1910 laterally encapsulating the semiconductor dies 10 and 20. For example, in the stacking unit 40B, the sidewalls of the insulating encapsulation 1910 and the sidewalls of the semiconductor die 30 are aligned with each other. That is, the sidewalls of the insulating encapsulation 1910 and the sidewalls of the semiconductor die 30 together constitute the sidewalls of the stacking unit 40B. In a non-limiting example, at least one through-hole 1002 penetrates the semiconductor dies 20 and 30 and extends further into the semiconductor die 10 to be in (e.g., physical) contact with the semiconductor dies 10, 20, and 30 to provide a suitable electrical connection between the semiconductor dies 10, 20, and 30. At least one through-hole 1003 penetrates the semiconductor die 30 and extends further into the semiconductor die 20 to be in (e.g., physical) contact with the semiconductor dies 20 and 30 to provide a suitable electrical connection between the semiconductor dies 20 and 30, such as Figure 42 As shown in the image.

[0203] Stacked cell 40B can be formed by, but is not limited to, providing circuit chip W1' (similar to) Figures 1 to 2 (process); forming a thermal control component 400A (similar to) in the circuit chip W1'. Figures 3 to 9(process); forming a bonding layer 6201 to form a circuit wafer W1 (similar to the process); Figure 10 (process); provides circuit chip W2' (similar to) Figure 11 (process); bonding circuit wafer W2' to circuit structure W1 (similar to the process); Figure 12 (The process); a thermal control component 400B is formed in the circuit wafer W2', and a bonding layer 6202 is formed above the thermal control component 400B to form the circuit wafer W2 (similar to the process). Figure 13 The process involves dicing the bonded structure containing circuit wafers W1 and W2 to form multiple separate and individual bonded structures containing semiconductor dies 10 and 20 (similar to...). Figure 20 or Figure 37 (process); provides a circuit chip W3 with thermal control component 400B (similar to) Figures 14 to 16 The bonding structure having semiconductor dies 10 and 20 is bonded to the circuit wafer W3 via a chip-on-wafer (CoW) process; the bonding structure having semiconductor dies 10 and 20 is laterally encapsulated in an insulating encapsulation 1910 (similar to the process of the chip-on-wafer (CoW) process). Figure 40 The process involves: (1) a dicing process on the circuit chip W3 and the insulating encapsulation 1910 to form multiple separate and individual stacked units 40B (similar to the process described above); and another dicing process on the circuit chip W3 and the insulating encapsulation 1910 to form multiple separate and individual stacked units 40B (similar to the process described above). Figure 16 or Figure 39 The process of providing the circuit wafer W3 with the thermal control component 400B may include a vertical portion forming the thermal control component 400B (similar to the process of providing the circuit wafer W3 with the thermal control component 400B). Figure 14 (process); forming at least one perforation 1002 and at least one perforation 1003 (similar to) Figure 15 The process); and the horizontal portion forming the thermal control assembly 400B (similar to the process); Figure 16 (The process). The formation and materials of the insulating encapsulation 1910 are similar to or substantially the same as those of the insulating encapsulation 1900 discussed above, and therefore will not be repeated here.

[0204] In some embodiments, Figure 43 Semiconductor devices 40000 and Figure 41 The semiconductor device 20000 is similar, except that stacking cell 40A is replaced with stacking cell 40C. For example... Figure 43As shown, the stacking unit 40C may include a semiconductor die 30 in a third layer T3, a semiconductor die 20 in a second layer T2 disposed above and electrically coupled to the semiconductor die 30 in the third layer T3, a semiconductor die 10 in a first layer T1 disposed above and electrically coupled to the semiconductor die 20, an insulating encapsulator 1910 laterally encapsulating the semiconductor die 10, and an insulating encapsulator 1920 laterally encapsulating the semiconductor die 20 and the insulating encapsulator 1910. For example, in the stacking unit 40C, the sidewalls of the insulating encapsulator 1920 and the sidewalls of the semiconductor die 30 are aligned with each other. That is, the sidewalls of the insulating encapsulator 1920 and the sidewalls of the semiconductor die 30 together constitute the sidewalls of the stacking unit 40C. In one non-limiting example, at least one through-hole 1002 penetrates semiconductor dies 20 and 30 and extends further into semiconductor die 10 to be in (e.g., physical) contact with semiconductor dies 10, 20, and 30 to provide a suitable electrical connection between semiconductor dies 10, 20, and 30. At least one through-hole 1003 penetrates semiconductor die 30 and extends further into semiconductor die 20 to be in (e.g., physical) contact with semiconductor dies 20 and 30 to provide a suitable electrical connection between semiconductor dies 20 and 30, such as... Figure 43 As shown in the image.

[0205] The stacked cell 40C can be formed by, but is not limited to, providing a circuit chip W1' (similar to...) Figures 1 to 2 (process); forming a thermal control component 400A (similar to) in the circuit chip W1'. Figures 3 to 9 (process); forming a bonding layer 6201 to form a circuit wafer W1 (similar to the process); Figure 10 The process involves dicing the circuit wafer W1 to form multiple separate and individual semiconductor dies 10 (similar to the process described above). Figure 20 or Figure 37 (process); provides circuit chip W2' (similar to) Figure 11 (process); at least one semiconductor die 10 is bonded to the circuit wafer W2' via CoW bonding; at least one semiconductor die 10 is laterally encapsulated in an insulating encapsulation 1910 (similar to the process of CoW bonding); Figure 40 (The process); a thermal control component 400B is formed in the circuit wafer W2', and a bonding layer 6202 is formed above the thermal control component 400B to form the circuit wafer W2 (similar to the process). Figure 13 The process involves performing a dicing process on the bonded structure having at least one semiconductor die 10 and a circuit wafer W2 to cut through the insulating encapsulation 1910 and the circuit wafer W2, thereby forming multiple separate and individual bonded structures having semiconductor dies 10 and 20 (similar to the process described above). Figure 20 or Figure 37(process); provides a circuit chip W3 with thermal control component 400B (similar to) Figure 14 (Process 16); through the CoW process, the bonded structure having semiconductor dies 10 and 20 is bonded to the circuit wafer W3; the bonded structure having semiconductor dies 10 and 20 is laterally encapsulated in an insulating encapsulation 1920 (similar to the process of process 16); Figure 40 The process involves: (1) a dicing process on the circuit chip W3 and the insulating encapsulation 1920 to form multiple separate and individual stacked cells 40C (similar to the process described above); and another dicing process on the circuit chip W3 and the insulating encapsulation 1920 to form multiple separate and individual stacked cells 40C (similar to the process described above). Figure 16 or Figure 39 The process of providing the circuit wafer W3 with the thermal control component 400B may include a vertical portion forming the thermal control component 400B (similar to the process of providing the circuit wafer W3 with the thermal control component 400B). Figure 14 (process); forming at least one perforation 1002 and at least one perforation 1003 (similar to) Figure 15 The process); and the horizontal portion forming the thermal control assembly 400B (similar to the process); Figure 16 (The process). The formation and materials of the insulating encapsulation 1920 are similar to or substantially the same as those of the insulating encapsulation 1900 discussed above, and therefore will not be repeated here.

[0206] Semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations thereof can each be die-form or chip-form. Although each semiconductor device disclosed herein includes only three layers in the above embodiments, the number of layers included in each semiconductor device disclosed herein may be two or more, depending on requirements and / or product design requirements / layout. In some embodiments, thermal energy storage materials 4010 and / or thermal energy storage materials 4020 may each be referred to as thermal energy moderating materials.

[0207] In some embodiments, the semiconductor dies (10, 20, and 30) included in the semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations are referred to as semiconductor chips or integrated circuits, which independently include digital chips, analog chips, or mixed-signal chips. In some embodiments, the semiconductor dies (10, 20, and 30) included in the semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations may independently be: logic dies, such as central processing units (CPUs), graphics processing units (GPUs), neural network processing units (NPUs), deep learning processing units (DPUs), tensor processing units (TPUs), system-on-a-chip (SoCs), system-on-integrated circuits (SoICs), application processors (APs), and microcontrollers; power management dies, such as power management integrated circuit (PMIC) dies; and wireless and radio frequency (RF) dies. Frequency (RF) chips; baseband (BB) chips; sensor chips, such as photo / image sensor chips; micro-electro-mechanical system (MEMS) chips; signal processing chips, such as digital signal processing (DSP) chips; front-end chips, such as analog front-end (AFE) chips; application-specific chips, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs); combinations thereof; or similar components.In alternative embodiments, the semiconductor dies (10, 20, and 30) included in semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations may independently be: memory dies with or without controllers, wherein the memory dies include: single-form dies, such as dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), NAND flash memory, wide I / O memory (WIO); pre-stacked memory cubes, such as hybrid memory cubes. Cube (HMC) modules, high-bandwidth memory (HBM) modules; combinations thereof; or similar components. In further alternative embodiments, the semiconductor dies (10, 20, and 30) included in semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations may independently be: artificial intelligence (AI) engines, such as AI accelerators; computing systems, such as AI servers, high-performance computing (HPC) systems, high-power computing devices, cloud computing systems, networking systems, edge computing systems, immersive memory computing systems (ImMC), SoIC systems, etc.; combinations thereof; or similar components.In some other embodiments, the semiconductor dies (10, 20, and 30) included in the semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations may independently be: electrical and / or optical input / output (I / O) interface dies, integrated passive dies (IPDs), voltage regulator dies (VRs), local silicon interconnect dies (LSIs) with or without deep trench capacitor (DTC) features, local silicon interconnect dies with multi-tier functions such as electrical and / or optical network circuit interfaces, IPDs, VRs, DTCs, or similar functions; or similar components.

[0208] The types of semiconductor dies (10, 20, and 30) included in semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations can be selected and specified according to requirements and / or product design requirements / layouts, and therefore are not limited in specificity in this disclosure. In this disclosure, thermal spikes in the semiconductor devices can be mitigated, thereby improving the reliability of the semiconductor devices, provided that hot spots of the semiconductor device are thermally coupled (e.g., physically close) to (e.g., 400A, 400B, 400C, 400D, 400E, and / or 400F). For example, in Figure 25 Semiconductor device 10000E and Figure 27 In semiconductor device 10000G, semiconductor dies 10 and 20 are or include memory dies or low-power logic dies, and semiconductor die 30 is or includes high-power logic dies; therefore, the first level T1 and the second level T2 may not contain thermal control components. In another example, in semiconductor device 10000A ( Figure 21 Semiconductor device 10000B ( Figure 22 Semiconductor device 10000C ( Figure 23 ), Semiconductor device 10000D ( Figure 24 ) and semiconductor device 10000F ( Figure 26In the semiconductor device disclosed herein, semiconductor dies 10, 20, and 30 are or include high-power logic dies, and therefore each level may contain one or more thermal control components. As a non-limiting example, in the semiconductor device disclosed herein, at least one of semiconductor dies 10, 20, and 30 may be or include high-power logic dies, and therefore the corresponding level may include one or more thermal control components, while other levels may not contain thermal control components.

[0209] This disclosure is not limited thereto. In this disclosure, thermal control components (e.g., 400A, 400B, 400C, 400D, 400E and / or 400F) may be employed in any combination or individually (with or without a high thermal conductivity layer (e.g., 6401, 6402 and / or 6403) to mitigate thermal spikes in the semiconductor device of this disclosure, thereby improving the reliability of the semiconductor device of this disclosure.

[0210] Semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000 and / or variations may be individually and further mounted onto another electronic device component or circuit structure, such as a motherboard, packaging substrate, printed circuit board (PCB), printed wiring board and / or other carrier capable of carrying integrated circuits. Alternatively, semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations thereof may be integrated fan-out (InFO) packages, InFO packages with a package-on-package (PoP) structure, chip-on-wafer-on-substrate (CoWoS) packages, flip-chip packages with InFO packages, or the like, or may be part of an InFO package, an InFO package with a PoP structure, a CoWoS package, a flip-chip package with InFO packages, or the like. This disclosure is not limited thereto. The conductive terminal 1800 may be referred to as a connector or terminal of semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000 and / or modified forms.

[0211] Figure 44Schematic cross-sectional views illustrating the application of semiconductor devices (e.g., semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations) according to some embodiments of this disclosure are shown. Components similar to or substantially the same as those previously described will use the same reference numerals, and certain details or descriptions of the same components (e.g., materials, forming processes, positioning configurations, electrical connections, etc.) will not be repeated.

[0212] refer to Figure 44 In some embodiments, a component assembly SC is provided, comprising a first component C1 and a second component C2 disposed above the first component C1. The first component C1 may be or may include a circuit structure, such as a motherboard, a package substrate, another printed circuit board (PCB), a printed wiring board, and / or other carrier capable of carrying an integrated circuit. In some embodiments, the second component C2 mounted on the first component C1 may be similar to one of the connectors or terminals of the semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or modified versions thereof. For example, one or more second components C2 (e.g., semiconductor devices 10000A, 10000B, 10000C, 10000D, 10000E, 10000F, 10000G, 20000, 30000, 40000, and / or variations) may be electrically coupled to the first component C1 via a plurality of terminals CT. The terminals CT may be conductive terminals 1800. In some embodiments, an underfill adhesive UF is formed between the first component C1 and the second component C2 to cover the terminals CT at least laterally. Alternatively, the underfill adhesive UF may be omitted. The underfill adhesive UF may be any acceptable material, such as polymers, epoxy resins, molded underfill, or the like. In one embodiment, the underfill adhesive UF may be formed by underfill dispensing, capillary flow processes, or any other suitable method. The presence of the underfill adhesive UF enhances the bonding strength between the first component C1 and the second component C2.

[0213] According to some embodiments, a semiconductor device includes a semiconductor substrate, interconnects, and at least one thermal via. The semiconductor substrate includes at least one active component. The interconnects are disposed on and electrically coupled to the at least one active component. The at least one thermal via penetrates the interconnects and is thermally coupled to the at least one active component, wherein the thermal conductivity of the at least one thermal via is different from the thermal conductivity of the dielectric layer of the interconnects.

[0214] In one embodiment, in the semiconductor device, the at least one thermal via includes a core portion, and the core portion is made of a solid-to-solid phase change material. In one embodiment, in the semiconductor device, the at least one thermal via further includes a shell portion surrounding the core portion, and the shell portion is made of a dielectric material with high thermal conductivity and is different from the material of the core portion. In one embodiment, in the semiconductor device, the at least one thermal via further includes a shell portion surrounding the core portion, and the shell portion is made of a conductive material with high thermal conductivity and is different from the material of the core portion. In one embodiment, in the semiconductor device, the at least one thermal via includes a core portion and a shell portion surrounding the core portion, wherein the shell portion is made of a solid-to-solid phase change material, and the core portion is made of a dielectric material with high thermal conductivity and is different from the material of the shell portion. In one embodiment, in the semiconductor device, the at least one thermal via includes a core portion and a shell portion surrounding the core portion, wherein the shell portion is made of a solid-to-solid phase change material, and the core portion is made of a conductive material with high thermal conductivity and is different from the material of the shell portion. In one embodiment, in the semiconductor device, the at least one thermal via includes a core portion, and the core portion is made of a metal or a metal alloy. In another embodiment, the semiconductor device further includes: at least one thermal control component disposed adjacent to and thermally coupled to the at least one active member, and including: at least one vertical portion; and a horizontal portion disposed on and connected to the at least one vertical portion, wherein the horizontal portion is made of a solid-solid phase change material, wherein the horizontal portion is disposed on the interconnect, and the at least one vertical portion includes the at least one thermal via. In one embodiment, in the semiconductor device, the at least one vertical portion includes two or more vertical portions connected to the edge of the horizontal portion, and in a cross-section of the semiconductor device along the stacking direction of the semiconductor substrate and the interconnect, the horizontal portion overlaps with the at least one active member.

[0215] According to some embodiments, a semiconductor device includes a redistribution structure, a die stack, and at least one thermal control component. The die stack is located above and electrically coupled to the redistribution structure, and includes a first level and a second level. The first level includes a first substrate having at least one first active component and a first interconnect disposed above and electrically coupled to the at least one first active component. The second level is located above and electrically coupled to the first level, and includes a second substrate having at least one second active component and a second interconnect disposed above and electrically coupled to the at least one second active component. The first level is located between the second level and the redistribution structure. The at least one thermal control component is disposed above the redistribution structure and thermally coupled to the die stack, and includes at least one thermal via extending vertically within the die stack, wherein the thermal conductivity of the at least one thermal via is different from the thermal conductivity of the dielectric layer of the first interconnect and the dielectric layer of the second interconnect.

[0216] In one embodiment, in the semiconductor device, the at least one thermal via extends through the first interconnect, the second substrate, and the second interconnect, and is thermally coupled to the at least one first active component and the at least one second active component. In one embodiment, in the semiconductor device, the at least one thermal via comprises: at least one first thermal via extending through the first interconnect and thermally coupled to the at least one first active component; and at least one second thermal via extending through the second substrate and the second interconnect and thermally coupled to the at least one second active component. In one embodiment, in the semiconductor device, in a cross-section of the semiconductor device along the stacking direction of the die stack and the redistribution circuitry, the at least one first thermal via is offset from the at least one second thermal via. In one embodiment, in the semiconductor device, the at least one thermal via includes at least one of: two or more first thermal vias penetrating the first interconnect and thermally coupled to the at least one first active component, wherein in a cross-section of the semiconductor device along the stacking direction of the die stack and the redistribution structure, the two or more first thermal vias are located on opposite sides of the at least one first active component; and two or more second thermal vias penetrating the second interconnect and thermally coupled to the at least one second active component, wherein in a cross-section of the semiconductor device along the stacking direction of the die stack and the redistribution structure... In a cross-section, the two or more second thermal vias are disposed on opposite sides of the at least one second active component; and two or more first thermal vias penetrate the first interconnect and are thermally coupled to the at least one first active component, and two or more second thermal vias penetrate the second interconnect and are thermally coupled to the at least one second active component, wherein in a cross-section of the semiconductor device along the stacking direction of the die stack and the redistribution structure, the two or more first thermal vias are disposed on opposite sides of the at least one first active component, and the two or more second thermal vias are disposed on opposite sides of the at least one second active component. In one embodiment, the semiconductor device further includes: a first insulating encapsulation that laterally encapsulates the die stack and covers a portion of the redistribution structure exposed by the die stack. In one embodiment, the semiconductor device further includes: a second insulating encapsulation that laterally encapsulates the first and second layers of the die stack and separates the first and second layers of the die stack from the first insulating encapsulation.In one embodiment, in the semiconductor device, the die stack further includes: a third layer disposed above the second layer and electrically coupled to the first layer and the second layer, the second layer being located between the first layer and the third layer, and including: a third substrate including at least one third active member; and a third interconnect disposed above the at least one third active member and electrically coupled to the at least one third active member, wherein the at least one thermal via extends vertically through the third interconnect.

[0217] According to some embodiments, a method of manufacturing a semiconductor device includes the steps of: providing a semiconductor substrate including at least one active component; forming an interconnect over the semiconductor substrate, the interconnect being electrically coupled to the at least one active component; patterning the interconnect to form an opening through the interconnect; and forming a thermal via in the opening, the thermal via being thermally coupled to the at least one active component and extending through the interconnect, wherein the thermal conductivity of the thermal via is different from the thermal conductivity of the dielectric layer of the interconnect.

[0218] In one embodiment, the method, wherein forming the heat via in the opening comprises: depositing a thermal energy storage material on the interconnect and filling the opening; and performing a planarization process to remove excess thermal energy storage material above the opening, thereby forming the heat via in the opening. In another embodiment, the method, wherein forming the heat via in the opening comprises: depositing a first thermal energy storage material on the interconnect, the first thermal energy storage material extending into the opening; depositing a second thermal energy storage material on the first thermal energy storage material and filling the opening; and performing a planarization process to remove excess first and second thermal energy storage material above the opening, thereby forming the heat via in the opening, wherein the heat via includes a core portion having the second thermal energy storage material and a shell portion having the first thermal energy storage material, the shell portion surrounding the core portion, wherein the first thermal energy storage material is different from the second thermal energy storage material.

[0219] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized by comprising: comprising: a semiconductor substrate comprising at least one active component; interconnects disposed over and electrically coupled to the at least one active component; and at least one thermal via penetrating through the interconnects and thermally coupled to the at least one active component, wherein a thermal conductivity of the at least one thermal via is different from a thermal conductivity of a dielectric layer of the interconnects.

2. The semiconductor device according to claim 1, wherein wherein the at least one thermal via comprises a core portion, and a material of the core portion comprises a solid-solid phase change material.

3. The semiconductor device according to claim 2, wherein wherein the at least one thermal via further comprises a shell portion surrounding the core portion, and a material of the shell portion comprises a high thermal conductivity dielectric material and is different from the material of the core portion.

4. The semiconductor device according to claim 2, wherein wherein the at least one thermal via further comprises a shell portion surrounding the core portion, and a material of the shell portion comprises a high thermal conductivity conductive material and is different from the material of the core portion.

5. The semiconductor device according to claim 1, wherein wherein the at least one thermal via comprises a core portion and a shell portion surrounding the core portion, wherein a material of the shell portion comprises a solid-solid phase change material, and a material of the core portion comprises a high thermal conductivity dielectric material and is different from the material of the shell portion.

6. The semiconductor device according to claim 1, wherein wherein the at least one thermal via comprises a core portion and a shell portion surrounding the core portion, wherein a material of the shell portion comprises a solid-solid phase change material, and a material of the core portion comprises a high thermal conductivity conductive material and is different from the material of the shell portion.

7. The semiconductor device according to claim 1, wherein wherein the at least one thermal via comprises a core portion, and a material of the core portion comprises a metal or a metal alloy.

8. The semiconductor device according to claim 1, wherein further comprising: at least one thermal control component disposed proximate to and thermally coupled to the at least one active component, and comprising: at least one vertical portion; and a horizontal portion disposed over and connected to the at least one vertical portion, wherein a material of the horizontal portion comprises a solid-solid phase change material, wherein the horizontal portion is disposed over the interconnects, and the at least one vertical portion comprises the at least one thermal via.

9. The semiconductor device according to claim 8, wherein wherein the at least one vertical portion comprises two or more vertical portions connected to an edge of the horizontal portion, and in a cross-section of the semiconductor device along a stacking direction of the semiconductor substrate and the interconnects, the horizontal portion overlaps the at least one active component.

10. A semiconductor device, characterized by comprising: comprising: a re-distribution line structure; a die stack disposed over and electrically coupled to the re-distribution line structure, and comprising: a first tier comprising: a first substrate comprising at least one first active component; and first interconnects disposed over and electrically coupled to the at least one first active component; and a second tier disposed over and electrically coupled to the first tier, and comprising: a second substrate comprising at least one second active component; and second interconnects disposed over and electrically coupled to the at least one second active component; wherein the first tier is between the second tier and the re-distribution line structure; and at least one thermal control component disposed above the rewiring structure and thermally coupled with the die stack, and comprising: at least one thermal via extending vertically inside the die stack, wherein a thermal conductivity of the at least one thermal via is different from a thermal conductivity of the dielectric layers of the first interconnect and a thermal conductivity of the dielectric layers of the second interconnect.

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