Optical module

Abstract

The optical module provided by the utility model comprises a circuit board and a signal processing chip. A first laser driving chip, a first TIA, a second laser driving chip and a second TIA are arranged on the surface of the circuit board and electrically connected with the signal processing chip. The first side of the signal processing chip faces the first laser driving chip, the first TIA, the second laser driving chip and the second TIA at the same time, the electric connection distance is short, and the high-frequency signal performance is improved. A first bonding pad array and a second bonding pad array are formed on the surface of the signal processing chip, the first bonding pad array is arranged along the edge of the first side of the signal processing chip, and the second bonding pad array deviates towards the center direction of the signal processing chip relative to the first bonding pad array. The first bonding pad array is electrically connected with the wires on the surface layer, the second bonding pad array is electrically connected with the wires on the surface of the second inner layer, and the wires on the surface of the second inner layer are electrically connected with the corresponding wires on the surface layer. Wiring crossing and crosstalk on the surface layer of the circuit board are avoided, and signal transmission performance is optimized.

Description

Technical Field

[0001] This disclosure relates to the field of optical communication technology, and in particular to an optical module. Background Technology

[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, advancements in optical communication technology have become increasingly important. In optical communication technology, the optical module, as one of the key components in optical communication equipment, enables photoelectric signal conversion; and in the development of optical communication technology, the data transmission rate of optical modules is required to continuously improve. Utility Model Content

[0003] In some embodiments of an optical module, by routing traces on the surface and inner layers of a circuit board, the signal processing chip is positioned facing each optical matching chip simultaneously, thereby shortening the electrical connection distance between the signal processing chip and each optical matching chip.

[0004] In some embodiments, an optical module is provided, comprising:

[0005] A circuit board has a surface provided with a first laser driver chip, a first laser input transceiver (TIA), a second laser driver chip, and a second laser input transceiver (TIA). The first laser driver chip and the first TIA are disposed adjacent to each other, and the second laser driver chip and the second TIA are disposed adjacent to each other. The circuit board includes:

[0006] surface layer;

[0007] A first inner layer is connected to the outer layer, and the first inner layer is set as a ground layer;

[0008] The second inner layer is connected to the first inner layer;

[0009] A signal processing chip is disposed on the surface of the circuit board, with a first side of the signal processing chip simultaneously facing the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA; the surface of the signal processing chip has the following:

[0010] A first pad array is disposed along the edge of a first side of the signal processing chip; the first pad array is electrically connected to the traces on the surface layer.

[0011] The second pad array is offset towards the center of the signal processing chip relative to the first pad array; the second pad array is electrically connected to the traces on the second inner layer surface, and the traces on the second inner layer surface are electrically connected to the corresponding traces on the outer layer.

[0012] One of the above technical solutions has the following advantages or beneficial effects: The optical module includes a circuit board and a signal processing chip. The circuit board includes a surface layer, a first inner layer, and a second inner layer, which are connected sequentially, wherein the first inner layer is a ground layer. A first laser driver chip, a first TIA, a second laser driver chip, and a second TIA are disposed on the surface of the circuit board, which are electrically connected to the signal processing chip respectively. The first side of the signal processing chip faces the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA simultaneously. The first laser driver chip, the first TIA, the second laser driver chip, and the second TIA are arranged side by side on the first side of the signal processing chip, so that the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA have shorter electrical connection distances with the signal processing chip, which is beneficial to improving the high-frequency signal performance. A first pad array and a second pad array are formed on the surface of the signal processing chip. The first pad array is disposed along the edge of a first side of the signal processing chip, and the second pad array is offset relative to the first pad array towards the center of the signal processing chip. Thus, the first pad array is located on the edge side of the signal processing chip, and the second pad array is located on the inner side of the signal processing chip. The first pad array faces the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively. The first pad array is electrically connected to the traces on the surface layer, thereby enabling the signal processing chip to be electrically connected to a portion of the channels of the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively. The second pad array is electrically connected to the traces on the second inner layer surface, and the traces on the second inner layer surface are electrically connected to the corresponding traces on the surface layer, thereby enabling the signal processing chip to be electrically connected to another portion of the channels of the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively. Based on the specific first and second pad arrays distributed on the surface of the signal processing chip, and utilizing the inner layer space of the circuit board, electrical connections are established between the signal processing chip and the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively, through traces routed on the surface layer and the second inner layer of the circuit board, thereby achieving multi-channel signal transmission. Simultaneously, the pads of different arrays are electrically connected to traces on different layers of the circuit board, thereby shortening the distances between the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA and the signal processing chip, avoiding crosstalk and wiring intersections on the surface layer of the circuit board, and optimizing signal transmission performance.

[0013] In some embodiments, the first laser driver chip is electrically connected to the signal processing chip;

[0014] The first pad array includes a second emitter pad and a fourth emitter pad;

[0015] The second pad array includes a first emitter pad and a third emitter pad;

[0016] A first surface layer trace and a first inner layer trace are connected between the first laser driver chip and the first emitting pad; the first inner layer trace is located on the surface of the second inner layer.

[0017] A second surface trace connects the first laser driver chip and the second emitting pad;

[0018] A third surface layer trace and a second inner layer trace are connected between the first laser driver chip and the third emission pad; the second inner layer trace is located on the surface of the second inner layer.

[0019] A fourth surface layer trace connects the first laser driver chip to the fourth emission pad.

[0020] One of the above technical solutions has the following advantages or beneficial effects: The first pad array includes a second emitter pad and a fourth emitter pad, and the second pad array includes a first emitter pad and a third emitter pad. A first surface layer trace and a first inner layer trace connect the first laser driver chip and the first emitter pad, with the first inner layer trace located on the surface of the second inner layer. One end of the first surface layer trace is electrically connected to the first laser driver chip, and the other end is electrically connected to the first inner layer trace. The first inner layer trace is electrically connected to the first emitter pad, thus realizing the electrical connection between the first laser driver chip and the first emitter pad, and further realizing the electrical connection between the first laser driver chip and the signal processing chip. A second surface layer trace connects the first laser driver chip and the second emitter pad. One end of the second surface layer trace is electrically connected to the first laser driver chip, and the other end is electrically connected to the second emitter pad, thus realizing the electrical connection between the first laser driver chip and the second emitter pad, and further realizing the electrical connection between the first laser driver chip and the signal processing chip. A third surface layer trace and a second inner layer trace connect the first laser driver chip and the third emission pad, with the second inner layer trace located on the surface of the second inner layer. One end of the third surface layer trace is electrically connected to the first laser driver chip, and the other end is electrically connected to the second inner layer trace. The second inner layer trace is also electrically connected to the third emission pad, thus achieving electrical connection between the first laser driver chip and the third emission pad, and consequently, electrical connection between the first laser driver chip and the signal processing chip. A fourth surface layer trace connects the first laser driver chip and the fourth emission pad. One end of the fourth surface layer trace is electrically connected to the first laser driver chip, and the other end is electrically connected to the fourth emission pad, thus achieving electrical connection between the first laser driver chip and the fourth emission pad, and consequently, electrical connection between the first laser driver chip and the signal processing chip. It can be seen that in the emission signal lines corresponding to adjacent emission channels, one emission signal line includes both surface layer traces and inner layer traces, while the other emission signal line includes only surface layer traces. This staggered arrangement optimizes the wiring space and avoids crosstalk between surface layer traces.

[0021] In some embodiments, the second laser driver chip is electrically connected to the signal processing chip;

[0022] The first pad array includes a sixth emitter pad and an eighth emitter pad;

[0023] The second pad array includes a fifth emitter pad and a seventh emitter pad;

[0024] A fifth surface layer trace and a third inner layer trace are connected between the second laser driver chip and the fifth emission pad; the third inner layer trace is located on the surface of the second inner layer.

[0025] A sixth surface layer trace connects the second laser driver chip to the sixth emission pad;

[0026] A seventh surface layer trace and a fourth inner layer trace are connected between the second laser driver chip and the seventh emission pad; the fourth inner layer trace is located on the surface of the second inner layer.

[0027] An eighth surface layer trace connects the second laser driver chip to the eighth emission pad.

[0028] One of the above technical solutions has the following advantages or beneficial effects: The first pad array includes a sixth emitter pad and an eighth emitter pad, and the second pad array includes a fifth emitter pad and a seventh emitter pad. A fifth surface layer trace and a third inner layer trace connect the second laser driver chip and the fifth emitter pad, with the third inner layer trace located on the surface of the second inner layer. One end of the fifth surface layer trace is electrically connected to the second laser driver chip, and the other end is electrically connected to the third inner layer trace. The third inner layer trace is electrically connected to the fifth emitter pad, thus realizing the electrical connection between the second laser driver chip and the fifth emitter pad, and further realizing the electrical connection between the second laser driver chip and the signal processing chip. A sixth surface layer trace connects the second laser driver chip and the sixth emitter pad. One end of the sixth surface layer trace is electrically connected to the second laser driver chip, and the other end is electrically connected to the sixth emitter pad, thus realizing the electrical connection between the second laser driver chip and the sixth emitter pad, and further realizing the electrical connection between the second laser driver chip and the signal processing chip. A seventh surface layer trace and a fourth inner layer trace connect the second laser driver chip and the seventh emitter pad, with the fourth inner layer trace located on the surface of the second inner layer. One end of the seventh surface layer trace is electrically connected to the second laser driver chip, and the other end is electrically connected to the fourth inner layer trace, which in turn is electrically connected to the seventh emitter pad, thus achieving electrical connection between the second laser driver chip and the seventh emitter pad, and consequently, electrical connection between the second laser driver chip and the signal processing chip. An eighth surface layer trace connects the second laser driver chip and the eighth emitter pad. One end of the eighth surface layer trace is electrically connected to the second laser driver chip, and the other end is electrically connected to the eighth emitter pad, thus achieving electrical connection between the second laser driver chip and the eighth emitter pad, and consequently, electrical connection between the second laser driver chip and the signal processing chip. It can be seen that in the corresponding emitter signal lines of adjacent emitter channels, one emitter signal line includes both surface layer traces and inner layer traces, while the other emitter signal line includes only surface layer traces. This staggered arrangement optimizes routing space and avoids crosstalk between surface layer traces.

[0029] In some embodiments, the first TIA is electrically connected to the signal processing chip;

[0030] The first pad array includes a first receiving pad and a second receiving pad;

[0031] The second pad array includes a third receiving pad and a fourth receiving pad;

[0032] A ninth surface layer trace, a fifth inner layer trace, and a tenth surface layer trace are connected between the first TIA and the first receiving pad. The fifth inner layer trace is used to electrically connect the ninth surface layer trace and the tenth surface layer trace. The fifth inner layer trace is located on the surface of the second inner layer.

[0033] The first TIA and the second receiving pad are connected by an eleventh surface layer trace, a sixth inner layer trace and a twelfth surface layer trace, wherein the sixth inner layer trace is used to electrically connect the eleventh surface layer trace and the twelfth surface layer trace, and the sixth inner layer trace is located on the surface of the second inner layer.

[0034] A thirteenth surface layer trace and a seventh inner layer trace are connected between the first TIA and the third receiving pad, and the seventh inner layer trace is located on the surface of the second inner layer.

[0035] The first TIA and the fourth receiving pad are connected by a fourteenth surface layer trace and an eighth inner layer trace, the eighth inner layer trace being located on the surface of the second inner layer.

[0036] One of the above technical solutions has the following advantages or beneficial effects: The first pad array includes a first receiving pad and a second receiving pad, and the second pad array includes a third receiving pad and a fourth receiving pad. A ninth surface layer trace, a fifth inner layer trace, and a tenth surface layer trace are connected between the first TIA and the first receiving pad. The fifth inner layer trace is used to electrically connect the ninth surface layer trace and the tenth surface layer trace, and is located on the surface of the second inner layer. One end of the ninth surface layer trace is electrically connected to the first TIA, and the other end is electrically connected to the fifth inner layer trace. The fifth inner layer trace is electrically connected to the tenth surface layer trace, and the tenth surface layer trace is electrically connected to the first receiving pad, thereby realizing the electrical connection between the first TIA and the signal processing chip. An eleventh surface layer trace, a sixth inner layer trace, and a twelfth surface layer trace are connected between the first TIA and the second receiving pad. The sixth inner layer trace is used to electrically connect the eleventh surface layer trace and the twelfth surface layer trace, and is located on the surface of the second inner layer. One end of the eleventh surface layer trace is electrically connected to the first TIA, and the other end is electrically connected to the sixth inner layer trace. The sixth inner layer trace is electrically connected to the twelfth surface layer trace, and the twelfth surface layer trace is electrically connected to the second receiving pad, thereby achieving the electrical connection between the first TIA and the signal processing chip. The first TIA and the third receiving pad are connected by a thirteenth surface layer trace and a seventh inner layer trace, with the seventh inner layer trace located on the surface of the second inner layer. One end of the thirteenth surface layer trace is electrically connected to the first TIA, and the other end is electrically connected to the seventh inner layer trace, which is also electrically connected to the third receiving pad, thus achieving the electrical connection between the first TIA and the signal processing chip. The first TIA and the fourth receiving pad are connected by a fourteenth surface layer trace and an eighth inner layer trace, with the eighth inner layer trace located on the surface of the second inner layer. One end of the fourteenth surface layer trace is electrically connected to the first TIA, and the other end is electrically connected to the eighth inner layer trace, which is also electrically connected to the fourth receiving pad, thus achieving the electrical connection between the first TIA and the signal processing chip. As can be seen, the four-channel transmission between the first TIA and the signal processing chip is routed through the second inner layer to avoid crosstalk with the surface traces of the second laser driver chip, optimize the trace distribution, and ensure signal transmission performance.

[0037] In some embodiments, the second TIA is electrically connected to the signal processing chip;

[0038] The first pad array includes a sixth receiving pad and an eighth receiving pad;

[0039] The second pad array includes a fifth receiving pad and a seventh receiving pad;

[0040] A fifteenth surface layer trace and a ninth inner layer trace are connected between the second TIA and the fifth receiving pad, and the ninth inner layer trace is located on the surface of the second inner layer;

[0041] A sixteenth surface layer trace connects the second TIA to the sixth receiving pad;

[0042] A seventeenth surface layer trace and a tenth inner layer trace are connected between the second TIA and the seventh receiving pad, and the tenth inner layer trace is located on the surface of the second inner layer;

[0043] An eighteenth surface layer trace connects the second TIA to the eighth receiving pad.

[0044] One of the above technical solutions has the following advantages or beneficial effects: The first pad array includes a sixth receiving pad and an eighth receiving pad, and the second pad array includes a fifth receiving pad and a seventh receiving pad. A fifteenth surface layer trace and a ninth inner layer trace are connected between the second TIA and the fifth receiving pad, with the ninth inner layer trace located on the surface of the second inner layer. One end of the fifteenth surface layer trace is electrically connected to the second TIA, and the other end is electrically connected to the ninth inner layer trace. The ninth inner layer trace is electrically connected to the fifth receiving pad, thereby achieving electrical connection between the second TIA and the signal processing chip. A sixteenth surface layer trace is connected between the second TIA and the sixth receiving pad. One end of the sixteenth surface layer trace is electrically connected to the second TIA, and the other end is electrically connected to the sixth receiving pad, thereby achieving electrical connection between the second TIA and the signal processing chip. A seventeenth surface layer trace and a tenth inner layer trace are connected between the second TIA and the seventh receiving pad, with the tenth inner layer trace located on the surface of the second inner layer. One end of the seventeenth surface layer trace is electrically connected to the second TIA, and the other end is electrically connected to the tenth inner layer trace. The tenth inner layer trace is electrically connected to the seventh receiving pad, thus achieving the electrical connection between the second TIA and the signal processing chip. An eighteenth surface layer trace connects the second TIA and the eighth receiving pad. One end of the eighteenth surface layer trace is electrically connected to the second TIA, and the other end is electrically connected to the eighth receiving pad, thus achieving the electrical connection between the second TIA and the signal processing chip. It can be seen that in each receiving channel electrically connected between the second TIA and the signal processing chip, among the corresponding receiving signal lines of adjacent receiving channels, one receiving signal line includes both surface layer and inner layer traces, and the other receiving signal line includes only surface layer traces. This staggered arrangement optimizes routing space and avoids crosstalk between surface layer traces.

[0045] In some embodiments, an optical module is provided, comprising:

[0046] Circuit board, including:

[0047] surface layer;

[0048] A first inner layer is connected to the outer layer, and the first inner layer is set as a ground layer;

[0049] The second inner layer is connected to the first inner layer;

[0050] A signal processing chip is disposed on the surface of the circuit board;

[0051] A first laser driver chip is disposed on the surface of the circuit board, facing the first side of the signal processing chip, and electrically connected to the signal processing chip; the first laser driver chip and the signal processing chip are electrically connected to multiple transmission channels, wherein, in adjacent transmission channels, the signal line corresponding to one transmission channel includes a trace on the surface layer and a trace on the second inner layer, and the signal line corresponding to another transmission channel includes another trace on the surface layer;

[0052] A first TIA is disposed on the surface of the circuit board, facing the first side of the signal processing chip, and electrically connected to the signal processing chip. Multiple receiving channels are electrically connected between the first TIA and the signal processing chip. The signal lines corresponding to the first receiving channel include a trace on the surface layer, a trace on the second inner layer, and another trace on the surface layer. The signal lines corresponding to the second receiving channel include a trace on the surface layer, a trace on the second inner layer, and another trace on the surface layer. The signal lines corresponding to the third receiving channel include a trace on the surface layer and a trace on the second inner layer. The signal lines corresponding to the fourth receiving channel include a trace on the surface layer and a trace on the second inner layer.

[0053] One of the above technical solutions has the following advantages or beneficial effects: The optical module includes a circuit board and a signal processing chip. The circuit board includes a surface layer, a first inner layer, and a second inner layer, which are connected sequentially, wherein the first inner layer is a ground layer. A first laser driver chip and a first TIA are disposed on the surface of the circuit board. The first side of the signal processing chip faces both the first laser driver chip and the first TIA. The first laser driver chip and the first TIA are arranged side by side on the first side of the signal processing chip, so that the first laser driver chip, the first TIA, and the signal processing chip have shorter electrical connection distances, which is beneficial to improving high-frequency signal performance. There are multiple transmission channels electrically connected between the first laser driver chip and the signal processing chip, wherein, among adjacent transmission channels, the signal line corresponding to one transmission channel includes a trace on the surface layer and a trace on the second inner layer, and the signal line corresponding to another transmission channel includes another trace on the surface layer. As can be seen, in each transmission channel between the first laser driver chip and the signal processing chip, among the transmission signal lines corresponding to adjacent transmission channels, one transmission signal line includes both surface layer traces and inner layer traces, while the other transmission signal line includes only surface layer traces. This staggered arrangement optimizes wiring space and avoids crosstalk between surface layer traces. The first TIA and the signal processing chip are electrically connected to multiple receiving channels. The signal lines corresponding to the first receiving channel include one trace on the surface layer, one trace on the second inner layer, and another trace on the surface layer; the signal lines corresponding to the second receiving channel include one trace on the surface layer, one trace on the second inner layer, and another trace on the surface layer; the signal lines corresponding to the third receiving channel include one trace on the surface layer and one trace on the second inner layer; and the signal lines corresponding to the fourth receiving channel include one trace on the surface layer and one trace on the second inner layer. Therefore, the four-channel transmission between the first TIA and the signal processing chip uses traces on the second inner layer to avoid crosstalk with the surface traces of the second laser driver chip, optimizes the trace distribution, and ensures signal transmission performance.

[0054] In some embodiments, the optical module includes:

[0055] The second laser driver chip is disposed on the surface of the circuit board, facing the first side of the signal processing chip, and is electrically connected to the signal processing chip; the second laser driver chip and the signal processing chip are electrically connected to multiple transmission channels, wherein, in adjacent transmission channels, the signal line corresponding to one transmission channel includes a trace on the surface layer and a trace on the second inner layer, and the signal line corresponding to another transmission channel includes another trace on the surface layer;

[0056] The second TIA is disposed on the surface of the circuit board, facing the first side of the signal processing chip, and is electrically connected to the signal processing chip; the first TIA and the signal processing chip are electrically connected to multiple receiving channels, wherein, among adjacent receiving channels, the signal line corresponding to one receiving channel includes a trace on the surface layer and a trace on the second inner layer, and the signal line corresponding to another receiving channel includes another trace on the surface layer.

[0057] One of the above technical solutions has the following advantages or beneficial effects: A second laser driver chip and a second TIA are provided on the surface of the circuit board, which are electrically connected to the signal processing chip. The first side of the signal processing chip faces both the second laser driver chip and the second TIA. The second laser driver chip and the second TIA are arranged side-by-side on the first side of the signal processing chip, resulting in a shorter electrical connection distance between them, which is beneficial for improving high-frequency signal performance. Multiple transmission channels are electrically connected between the second laser driver chip and the signal processing chip. Among adjacent transmission channels, the signal line corresponding to one transmission channel includes a trace on the surface layer and a trace on the second inner layer, while the signal line corresponding to another transmission channel includes another trace on the surface layer. Therefore, in each transmission channel electrically connected between the second laser driver chip and the signal processing chip, among the transmission signal lines corresponding to adjacent transmission channels, one transmission signal line includes both a surface layer trace and an inner layer trace, while the other transmission signal line includes only a surface layer trace. This staggered arrangement optimizes wiring space and avoids crosstalk between surface layer traces. The first TIA is electrically connected to the signal processing chip through multiple receiving channels. In adjacent receiving channels, one receiving channel's signal line includes a trace on the surface layer and a trace on the second inner layer, while the other receiving channel's signal line includes another trace on the surface layer. Therefore, in the receiving channels electrically connected between the second TIA and the signal processing chip, in adjacent receiving channels, one receiving signal line includes both a surface layer trace and an inner layer trace, while the other receiving signal line includes only a surface layer trace. This staggered arrangement optimizes wiring space and avoids crosstalk between surface layer traces.

[0058] In some embodiments, the surface of the signal processing chip has the following characteristics:

[0059] A first pad array is disposed along the edge of a first side of the signal processing chip; the first pad array is electrically connected to the traces on the surface layer.

[0060] The second pad array is offset towards the center of the signal processing chip relative to the first pad array; the second pad array is electrically connected to the traces on the second inner layer surface, and the traces on the second inner layer surface are electrically connected to the corresponding traces on the outer layer.

[0061] One of the above technical solutions has the following advantages or beneficial effects: A first pad array and a second pad array are formed on the surface of the signal processing chip. The first pad array is disposed along the edge of a first side of the signal processing chip, and the second pad array is offset relative to the first pad array towards the center of the signal processing chip. Thus, the first pad array is located on the edge side of the signal processing chip, and the second pad array is located on the inner side of the signal processing chip. The first pad array faces the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively. The first pad array is electrically connected to the traces on the surface layer, thereby realizing electrical connections between the signal processing chip and a portion of the channels of the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively. The second pad array is electrically connected to the traces on the second inner layer surface, and the traces on the second inner layer surface are electrically connected to the corresponding traces on the surface layer, thereby realizing electrical connections between the signal processing chip and another portion of the channels of the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively. Based on the specific first and second pad arrays distributed on the surface of the signal processing chip, and utilizing the inner layer space of the circuit board, electrical connections are established between the signal processing chip and the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively, through traces on the surface and inner layers of the circuit board, thereby realizing multi-channel signal transmission. Simultaneously, the pads of different arrays are electrically connected to traces on different layers of the circuit board, avoiding crosstalk and wiring intersections on the surface layer of the circuit board, and optimizing the wiring space.

[0062] In some embodiments, the signal processing chip surface has a transmitter pad group and a receiver pad group, the transmitter pad group being located in a first region of the signal processing chip surface and the receiver pad group being located in a second region of the signal processing chip surface.

[0063] One of the above technical solutions has the following advantages or beneficial effects: A transmit pad group and a receive pad group are formed on the surface of the signal processing chip. The transmit pad group is located in a first region on the surface of the signal processing chip, and the receive pad group is located in a second region on the surface of the signal processing chip. By independently setting up the transmit and receive pad groups in separate regions, crosstalk between the channel transmitting digital signals and the channel receiving electrical signals of the signal processing chip is avoided, thus achieving signal isolation.

[0064] In some embodiments, the four transmission channels electrically connected between the first laser driver chip and the signal processing chip, from top to bottom, are: a first transmission channel, a second transmission channel, a third transmission channel, and a fourth transmission channel;

[0065] The four receiving channels electrically connected between the first TIA and the signal processing chip are, from top to bottom, the fourth receiving channel, the third receiving channel, the second receiving channel, and the first receiving channel.

[0066] One of the above technical solutions has the following advantages or beneficial effects: The four channels between the first laser driver chip and the signal processing chip, from top to bottom, are: the first transmitting channel, the second transmitting channel, the third transmitting channel, and the fourth transmitting channel. The four channels between the first TIA and the signal processing chip, from top to bottom, are: the fourth receiving channel, the third receiving channel, the second receiving channel, and the first receiving channel. Thus, the corresponding transmitting and receiving channels are symmetrically distributed. The common-mode noise cancellation effect formed by the symmetrical distribution can reduce crosstalk between channels, which is beneficial to improving signal integrity. In addition, the reverse electromagnetic fields generated by the symmetrical structure can cancel each other out, improving electromagnetic compatibility. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0068] Figure 1 This is a partial architecture diagram of an optical communication system according to some embodiments;

[0069] Figure 2 This is a partial structural diagram of a host computer according to some embodiments;

[0070] Figure 3 This is a structural diagram of an optical module according to some embodiments;

[0071] Figure 4 An exploded view of an optical module according to some embodiments;

[0072] Figure 5 This is a structural diagram of the internal structure of an optical module according to some embodiments;

[0073] Figure 6 This is an exploded view of the internal structure of an optical module according to some embodiments;

[0074] Figure 7 This is a schematic diagram of the optical path corresponding to an internal layout of an optical module according to some embodiments of the present disclosure. Figure 1 ;

[0075] Figure 8 This is a schematic diagram of the optical path corresponding to an internal layout of an optical module according to some embodiments of the present disclosure. Figure 2 ;

[0076] Figure 9 This is a schematic diagram of a circuit board surface trace according to some embodiments. Figure 1 ;

[0077] Figure 10 This is a schematic diagram of a circuit board surface trace according to some embodiments. Figure 2 ;

[0078] Figure 11 This is a schematic diagram of the pad distribution of a signal processing chip according to some embodiments;

[0079] Figure 12 This is a schematic diagram of an interlayer electrical connection of a circuit board according to some embodiments;

[0080] Figure 13 This is a schematic diagram of the surface layer routing of a circuit board according to some embodiments;

[0081] Figure 14 This is a schematic diagram of the second inner layer routing of a circuit board according to some embodiments;

[0082] Figure 15 This is a schematic diagram of the electrical connection traces between a first laser driver chip, a first TIA, and a signal processing chip according to some embodiments;

[0083] Figure 16 This is a schematic diagram of the electrical connection traces between a second laser driver chip, a second TIA, and a signal processing chip according to some embodiments;

[0084] Figure 17 This is a schematic diagram of the electrical connection traces between a first laser driver chip and a signal processing chip according to some embodiments;

[0085] Figure 18 This is a schematic diagram of the electrical connection traces between a first TIA and a signal processing chip according to some embodiments;

[0086] Figure 19 This is a schematic diagram of the electrical connection traces between a second laser driver chip and a signal processing chip according to some embodiments;

[0087] Figure 20 This is a schematic diagram of the electrical connection traces between a second TIA and a signal processing chip according to some embodiments. Detailed Implementation

[0088] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0089] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0090] In optical communication technology, to establish information transmission between information processing devices, information is loaded onto light, and the speed of light propagation is used to transmit the information. This light carrying information is called an optical signal. When optical signals are transmitted in optical information transmission equipment, optical power loss can be reduced, enabling long-distance transmission of optical signals. At the same time, the cost of optical information transmission equipment such as optical fibers is lower than that of electrical information transmission equipment such as copper wires. Therefore, optical communication technology can achieve high-speed, long-distance, and low-cost information transmission.

[0091] Information processing equipment typically includes optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., while optical information transmission equipment typically includes optical fibers and optical waveguides. Information processing equipment can only recognize and process electrical signals, while optical communication technology uses optical signals for transmission, requiring optical modules to convert between optical and electrical signals.

[0092] An optical module enables the conversion between optical signals and electrical signals between information processing equipment and optical information transmission equipment. In some embodiments, at least one of the optical signal input or output terminals of the optical module is connected to an optical fiber, and at least one of the electrical signal input or output terminals of the optical module is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts the first optical signal into a first electrical signal and transmits the first electrical signal to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber.

[0093] Since multiple information processing devices can transmit information via electrical signals, at least one of these devices needs to be directly connected to the optical module, rather than all of them. Here, the information processing device directly connected to the optical module is also referred to as the host computer of the optical module. Furthermore, the optical signal input or output terminal of the optical module is called the optical port, and the electrical signal input or output terminal is called the electrical port.

[0094] Figure 1 This is a partial structural diagram of an optical communication system according to some embodiments. Figure 1 As shown, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100 for optical modules, an optical module 200, an optical fiber 101, and a network cable 103. Among them, the optical fiber 101 is an optical information transmission device, and the network cable 103 is an electrical information transmission device.

[0095] In some embodiments, one end of the optical fiber 101 extends toward the remote information processing device 1000, and the other end of the optical fiber 101 is connected to the optical module 200 through the optical port of the optical module 200. The optical signal can undergo total internal reflection in the optical fiber 101, and the propagation of the optical signal in the direction of total internal reflection can almost maintain the original optical power. The optical signal undergoes multiple total internal reflections in the optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to the optical module 200, or to transmit the optical signal from the optical module 200 to the remote information processing device 1000, thereby realizing long-distance information transmission based on low power loss.

[0096] The optical communication system includes one or more optical fibers 101. In some embodiments, the optical fiber 101 is detachably connected to the optical module 200; in some embodiments, the optical fiber 101 is non-detachably connected to the optical module 200.

[0097] The host computer 100 is configured to provide data signals to the optical module 200, or receive data signals from the optical module 200, or monitor or control the working status of the optical module 200.

[0098] The host computer 100 includes a housing for accommodating the optical module 200, and an optical module interface 102 disposed on the housing. The optical module 200 is inserted into the housing through the optical module interface 102 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the optical module 200.

[0099] The host computer 100 also includes an external power interface that can connect to an electrical signal network. In some embodiments, the external power interface includes a Universal Serial Bus (USB) interface or a network cable interface 104. The network cable interface 104 is configured to connect a network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103.

[0100] One end of the network cable 103 is connected to the local information processing device 2000, and the other end is connected to the host computer 100, so as to establish an electrical signal connection between the local information processing device 2000 and the host computer 100 through the network cable 103. In some embodiments, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 through the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. The second electrical signal from the host computer 100 is transmitted to the optical module 200. The optical module 200 converts the second electrical signal into a second optical signal and transmits the second optical signal to the optical fiber 101. The second optical signal is transmitted in the optical fiber 101 to the remote information processing device 1000.

[0101] In some embodiments, a first optical signal from a remote information processing device 1000 is transmitted through an optical fiber 101, and the first optical signal from the optical fiber 101 is transmitted to an optical module 200. The optical module 200 converts the first optical signal into a first electrical signal, and transmits the first electrical signal to a host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to a local information processing device 2000.

[0102] In some embodiments, the optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information does not change, but the encoding or decoding method of the information changes.

[0103] In addition to optical network terminals, the host computer 100 also includes optical line terminals (OLTs), optical network equipment (ONTs), or data center servers.

[0104] Figure 2 This is a partial structural diagram of a host computer according to some embodiments. To clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structure of the host computer 100 related to the optical module 200 is shown. For example... Figure 2As shown, in some embodiments, the host computer 100 further includes a PCB circuit board 105 disposed in the receiving cavity, and a cage 106 disposed on the surface of the PCB circuit board 105; the optical module 200 is inserted into the cage 106 and fixed by the cage 106.

[0105] In some embodiments, a heat sink 107 is provided on the cage 106 to dissipate heat for the optical module; in some embodiments, the heat sink 107 has protruding structures such as fins to increase the heat dissipation area.

[0106] In some embodiments, an electrical connector is provided inside the cage 106, which is configured to connect to the electrical port of the optical module 200.

[0107] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the cage 106 fixes the optical module 200. The heat generated by the optical module 200 is conducted to the cage 106 and then diffused through the heat sink 107.

[0108] In some embodiments, the optical module 200 is inserted into the cage 106 of the host computer 100, and the electrical port of the optical module 200 is connected to the electrical connector inside the cage 106, thereby establishing an electrical signal connection between the optical module 200 and the host computer 100.

[0109] In some embodiments, the optical port of the optical module 200 is connected to the optical fiber 101, thereby enabling the optical module 200 to establish an optical signal connection with the optical fiber 101.

[0110] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, in some embodiments, the optical module 200 includes a shell, which comprises an upper shell 201 and a lower shell 202. The upper shell 201 covers the lower shell 202, forming two openings 204 and 205, one of which is an electrical port and the other is an optical port. In some embodiments, the shell forms an opening that serves as both an electrical port and an optical port.

[0111] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0112] The assembly method of combining the upper housing 201 and the lower housing 202 facilitates the installation of circuit boards 300 and other components into the housing. The upper housing 201 and the lower housing 202 can encapsulate and protect the aforementioned devices.

[0113] The direction of the line connecting the two openings 204 and 205 can be consistent with or inconsistent with the length direction of the optical module 200. For example, opening 204 is located at the end of the optical module 200. Figure 3 The opening 205 is also located at the end of the optical module 200 (right end). Figure 3 (The left end). Alternatively, opening 204 is located at the end of optical module 200, while opening 205 is located on the side of optical module 200.

[0114] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0115] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0116] like Figure 3 and Figure 4 As shown, in some embodiments, the optical module includes a circuit board 300 disposed within a housing. The circuit board 300 includes circuit traces, electronic components, and chips, etc. The electronic components and chips are connected according to the circuit design through the circuit traces to realize functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0117] In some embodiments, the circuit board includes a rigid circuit board, which, due to its relatively rigid material, can also serve a load-bearing function, such as being able to stably support the aforementioned electronic components and chips; the rigid circuit board can also be inserted into an electrical connector in the cage 106 of the host computer 100.

[0118] In some embodiments, the circuit board further includes a flexible circuit board, which can be used independently or in conjunction with a rigid circuit board.

[0119] In some embodiments, the circuit board further includes gold fingers formed on its end surface, the gold fingers consisting of a plurality of independent pins.

[0120] In some implementations, the gold fingers 301 are disposed on one side of the surface of the circuit board 300 (e.g., Figure 4 (as shown on the upper surface); In some implementations, the gold fingers 301 are disposed on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thereby adapting to situations where the number of pins is required.

[0121] In some implementations, the gold fingers of the circuit board extend from the opening 204 and are inserted into the electrical connector of the host computer 100; the circuit board is inserted into the cage 106, and the gold fingers 301 are connected to the electrical connector inside the cage 106. The gold fingers 301 are configured to establish an electrical connection with the host computer, enabling electrical connection functions such as power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission.

[0122] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0123] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the host computer, so as to release the fixation between the optical module 200 and the host computer, thereby allowing the optical module 200 to be pulled out of the cage 106.

[0124] In some embodiments, the optical module may include a first lens assembly 400.

[0125] In some embodiments, the optical module may include a second lens assembly 500. The first lens assembly 400 and the second lens assembly 500 are respectively projected onto the surface of the circuit board 300.

[0126] In some embodiments, the first lens assembly 400 and the second lens assembly 500 are arranged sequentially along the length of the circuit board 300.

[0127] In some embodiments, a signal processing chip 302 is provided on the surface of the circuit board 300. The signal processing chip 302 is disposed between the second lens assembly 500 and the gold finger 301.

[0128] Figure 5 This is a diagram illustrating the internal structure of an optical module according to some embodiments. Figure 6 This is an exploded view of the internal structure of an optical module according to some embodiments. For example... Figure 5 and Figure 6 As shown, in some embodiments, the optical module may include a first lens assembly 400 and a second lens assembly 500. The first lens assembly 400 and the second lens assembly 500 are respectively projected onto the surface of the circuit board 300.

[0129] In some embodiments, the first lens assembly 400 and the second lens assembly 500 are arranged side by side along the width direction of the circuit board 300. The signal processing chip 302 faces both the first lens assembly 400 and the second lens assembly 500.

[0130] In some embodiments, the surface of the circuit board 300 is provided with a first photodetector 330, a first TIA 340, a first laser chip 310, and a first laser driver chip 320. The first photodetector 330 is electrically connected to the first TIA 340, and the first laser chip 310 is electrically connected to the first laser driver chip 320.

[0131] In some embodiments, the first lens assembly 400 is projected over the first photodetector 330, the first TIA 340, the first laser chip 310, and the first laser driver chip 320.

[0132] In some embodiments, a receiving cavity is formed between the first lens assembly 400 and the circuit board 300 to accommodate the first photodetector 330, the first TIA 340, the first laser chip 310, and the first laser driver chip 320.

[0133] In some embodiments, the surface of the circuit board 300 is provided with a second photodetector 370, a second TIA 380, a second laser chip 350, and a second laser driver chip 360. The second photodetector 370 is electrically connected to the second TIA 380, and the second laser chip 350 is electrically connected to the second laser driver chip 360.

[0134] In some embodiments, the second lens assembly 500 is projected over the second photodetector 370, the second TIA 380, the second laser chip 350, and the second laser driver chip 360.

[0135] In some embodiments, a receiving cavity is formed between the second lens assembly 500 and the circuit board 300 to accommodate the second photodetector 370, the second TIA 380, the second laser chip 350, and the second laser driver chip 360.

[0136] In some embodiments, the first lens assembly 400 is connected to the first fiber array 400a. In some embodiments, the second lens assembly 500 is connected to the second fiber array 500a. The first fiber array 400a outputs the optical signal emitted by the first laser chip 310 and receives optical signals from outside the optical module to input optical signals to the first photodetector 330.

[0137] In some embodiments, the first lens assembly 400 has a function of adjusting the optical path transmission direction, which can adjust the transmission direction of the optical signal emitted by the first laser chip 310, and can adjust the transmission direction of the optical signal received from the outside to be input to the first photodetector 330.

[0138] In some embodiments, the first laser chip 310 emits light upwards perpendicular to the surface of the circuit board 300. The light emitted by the first laser chip 310 is transmitted and reflected by the first lens assembly 400, changing its transmission direction before entering the first fiber array 400a. The light from the first fiber array 400a is reflected by the first lens assembly 400 and then enters the first photodetector 330.

[0139] In some embodiments, the first photodetector 330 and the first TIA 340 are arranged adjacent to each other. The first photodetector 330 is used to convert the received optical signal into a photocurrent signal, and the first TIA 340 is used to convert the photocurrent signal into a voltage signal and amplify the voltage signal. The processed electrical signal is transmitted to the signal processing chip 302.

[0140] In some embodiments, the first laser chip 310 and the first laser driver chip 320 are disposed adjacent to each other. The first laser driver chip 320 is used to generate a drive signal based on the digital signal output by the signal processing chip 302 and transmit it to the first laser chip 310. Under the action of the drive signal, the first laser chip 310 converts the received electrical signal into an optical signal.

[0141] In some embodiments, the gold finger 301 is electrically connected to one end of the signal processing chip 302, and the other end of the signal processing chip 302 is electrically connected to the first TIA 340, the second TIA 380, the first laser driver chip 320, and the second laser driver chip 360, respectively. One side of the signal processing chip 302 faces the first TIA 340, the second TIA 380, the first laser driver chip 320, and the second laser driver chip 360 simultaneously.

[0142] Figure 7 This is a schematic diagram of the optical path corresponding to an internal layout of an optical module according to some embodiments of the present disclosure. Figure 1 , Figure 8 This is a schematic diagram of the optical path corresponding to an internal layout of an optical module according to some embodiments of the present disclosure. Figure 2 .like Figure 7 and Figure 8 As shown, in some embodiments, the first lens assembly 400 has an optical path deflection function. A reflective surface 401 is formed on the surface of the first lens assembly 400. The reflective surface 401 is configured as an inclined surface. The reflective surface 401 can reflect light signals incident on its surface.

[0143] In some embodiments, the first laser chip 310 and the first photodetector 330 are respectively located below the reflective surface 401. The first fiber array 400a is located on the reflected light path of the reflective surface 401.

[0144] In some embodiments, the first laser chip 310 emits light upward perpendicular to the surface of the circuit board 300, which is incident on the reflective surface 401. The reflective surface 401 reflects the light emitted by the first laser chip 310 parallel to the surface of the circuit board 300, so as to couple it into the first fiber array 400a, thereby realizing the transmission of optical signals.

[0145] In some embodiments, the first laser chip 310 can be a vertical cavity surface emitting laser (VCSEL). The VCSEL laser chip is a semiconductor laser whose light emission direction is perpendicular to the pn junction plane and whose resonant cavity surface is parallel to the pn junction plane.

[0146] In some embodiments, the optical signal generated by the first laser chip 310 is transmitted upward along the surface of the circuit board 300 to the reflective surface 401, and the optical path is deflected by the reflective surface 401 to achieve optical path deflection. For example, the reflective surface 401 reflects the optical signal output by the first laser chip 310 toward the optical port direction, thereby deflecting the optical path transmission direction so that it can be transmitted along the first fiber array 400a, and transmitting the optical signal generated by the first laser chip 310 to the outside of the optical module.

[0147] In some embodiments, the optical signal transmitted along the first fiber array 400a to the inside of the optical module reaches the reflective surface 401, and is reflected downward by the reflective surface 401 to achieve optical path reversal, thereby reversing the optical path to a direction perpendicular to the circuit board 300 so that it can be received by the first photodetector 330.

[0148] Figure 9 This is a schematic diagram of a circuit board surface trace according to some embodiments. Figure 1 , Figure 10 This is a schematic diagram of a circuit board surface trace according to some embodiments. Figure 2 , Figure 11 This is a schematic diagram of the pad distribution of a signal processing chip according to some embodiments. Figures 9-11 As shown, in some embodiments, a signal processing chip 302 is provided on the surface of the circuit board 300. The signal processing chip 302 is electrically connected to the first laser driver chip 320, the first TIA 340, the second laser driver chip 360, and the second TIA 380, respectively. Exemplarily, the first laser driver chip 320 and the second laser driver chip 360 are used to drive the transmission of four optical signals. The first TIA 340 and the second TIA 380 are used to perform gain processing on the four photocurrent signals.

[0149] In some embodiments, the signal processing chip 302 is electrically connected to the first laser driver chip 320, and the signal processing chip 302 sends four digital signals to the first laser driver chip 320 in parallel. The first laser driver chip 320 generates four laser driving signals based on the four digital signals. Similarly, the signal processing chip 302 is electrically connected to the second laser driver chip 360.

[0150] In some embodiments, the signal processing chip 302 is electrically connected to the first TIA340, and the signal processing chip 302 receives the four electrical signals after gain from the first TIA340 in parallel. Similarly, the signal processing chip 302 is electrically connected to the second TIA380.

[0151] In some embodiments, the first lens assembly 400 and the second lens assembly 500 are arranged side by side along the width direction of the circuit board 300, so that the first side of the signal processing chip 302 simultaneously faces the first laser driver chip 320, the first TIA 340, the second laser driver chip 360, and the second TIA 380. The signal processing chip 302 has a shorter electrical connection distance with the first laser driver chip 320, the first TIA 340, the second laser driver chip 360, and the second TIA 380, respectively, which shortens the high-frequency signal trace length, reduces signal transmission loss, and improves high-frequency transmission performance.

[0152] In some embodiments, the signal processing chip 302 has a specific pad distribution on its surface to transmit 8 digital signals in parallel and receive 8 electrical signals in parallel, thereby enabling the first lens assembly 400 and the second lens assembly 500 to be arranged side by side along the width direction of the circuit board 300.

[0153] In some embodiments, the circuit board 300 is a multilayer circuit board. The circuit board 300 includes a top layer, a first inner layer, a second inner layer, and a third inner layer, etc., arranged sequentially from the top layer to the bottom layer. The first inner layer is connected to the top layer and serves as a ground layer. The second inner layer is connected to the first inner layer and serves as a signal layer.

[0154] The third inner layer is connected to the second inner layer, and the third inner layer is a signal layer.

[0155] In some embodiments, by utilizing the inner space of the circuit board 300 and routing traces on the surface and inner layers of the circuit board 300, electrical connections are established between the signal processing chip 302 and the first laser driver chip 320, the first TIA 340, the second laser driver chip 360, and the second TIA 380, respectively, to achieve multi-channel signal transmission, thereby enabling the first lens assembly 400 and the second lens assembly 500 to be arranged side by side along the width direction of the circuit board 300.

[0156] In some embodiments, traces on the surface layer of circuit board 300 and traces on the inner layer of circuit board 300 are interconnected via metal vias, thereby achieving electrical connection between different layers of circuit board 300. The inner layer may be selected as the second inner layer of circuit board 300 to reduce the height of the metal vias, thereby reducing the parasitic inductance introduced by the metal vias. For example, traces on the surface layer of circuit board 300 and traces on the second inner layer of circuit board 300 are interconnected via metal vias.

[0157] In some embodiments, a transmit pad group 320a and a receive pad group 320b are formed on the surface of the signal processing chip 302. The transmit pad group 320a is located in a first region on the surface of the signal processing chip 302, and the receive pad group 320b is located in a second region on the surface of the signal processing chip 302. By independently configuring the transmit pad group 320a and the receive pad group 320b in separate regions, crosstalk between the channel for transmitting digital signals and the channel for receiving electrical signals of the signal processing chip 302 is avoided, thus achieving signal isolation. For example, the transmit pad group 320a is located in the first half-region of the signal processing chip 302, and the receive pad group 320b is located in the second half-region of the signal processing chip 302.

[0158] In some embodiments, taking 8-channel transmission as an example, the transmission pad group 320a includes: a first transmission pad 321a, a second transmission pad 322a, a third transmission pad 323a, a fourth transmission pad 324a, a fifth transmission pad 325a, a sixth transmission pad 326a, a seventh transmission pad 327a, and an eighth transmission pad 328a, respectively corresponding to the transmission of 8 digital signals. The first transmission pad 321a, the second transmission pad 322a, the third transmission pad 323a, and the fourth transmission pad 324a are electrically connected to the first laser driver chip 320. The fifth transmission pad 325a, the sixth transmission pad 326a, the seventh transmission pad 327a, and the eighth transmission pad 328a are electrically connected to the second laser driver chip 360.

[0159] In some embodiments, taking an 8-channel receiver as an example, the receiver pad group 320b includes: a first receiver pad 321b, a second receiver pad 322b, a third receiver pad 323b, a fourth receiver pad 324b, a fifth receiver pad 325b, a sixth receiver pad 326b, a seventh receiver pad 327b, and an eighth receiver pad 328b, respectively, to receive 8 electrical signals. The first receiver pad 321b, the second receiver pad 322b, the third receiver pad 323b, and the fourth receiver pad 324b are electrically connected to the first TIA 340, and the fifth receiver pad 325b, the sixth receiver pad 326b, the seventh receiver pad 327b, and the eighth receiver pad 328b are electrically connected to the second TIA 380.

[0160] In some embodiments, the second emitter pad 322a, the fourth emitter pad 324a, the sixth emitter pad 326a, the eighth emitter pad 328a, the eighth receiver pad 328b, the sixth receiver pad 326b, the first receiver pad 321b, and the second receiver pad 322b form a first pad array 320c. The first pad array 320c is located in the edge region of the signal processing chip 302 and faces the optical matching chip. The optical matching chip includes a first laser driver chip 320, a first TIA 340, a second laser driver chip 360, and a second TIA 380.

[0161] In some embodiments, the first transmitter pad 321a, the third transmitter pad 323a, the fifth transmitter pad 325a, the seventh transmitter pad 327a, the seventh receiver pad 327b, the fifth receiver pad 325b, the fourth receiver pad 324b, and the third receiver pad 323b form a second pad array 320d. The second pad array 320d is located in the inner region of the signal processing chip 302 and faces the gold finger 301.

[0162] In some embodiments, the first transmitting pad 321a and the second transmitting pad 322a are staggered, and the distance between the first transmitting pad 321a and the third transmitting pad 323a is greater than the distance between the second transmitting pad 322a and the fourth transmitting pad 324a. This optimizes wiring space, reduces signal interference, and prevents stress concentration between pads. Similarly, the second receiving pad 322b and the third receiving pad 323b are staggered, and the distance between the second receiving pad 322b and the fourth receiving pad 324b is greater than the distance between the second receiving pad 322b and the first receiving pad 321b.

[0163] In some embodiments, pads in different arrays are electrically connected to traces on different layers of the circuit board 300 to avoid crosstalk and interference of surface traces on the circuit board 300. The first pad array 320c is located at the edge of the signal processing chip 302, and the second pad array 320d is located in the inner region of the signal processing chip 302. Each pad in the first pad array 320c is electrically connected to the surface traces of the circuit board 300; each pad in the second pad array 320d is electrically connected to the inner layer traces of the circuit board 300. The inner layer traces are then electrically connected to the surface traces of the circuit board 300 through metal vias, and the surface traces are then electrically connected to the optical matching chip. Exemplarily, the circuit board 300 includes a surface layer, a first inner layer, and a second inner layer. These three layers are connected sequentially, wherein the first inner layer is a ground layer, and the second inner layer is a signal layer.

[0164] In some embodiments, the first pad array 320c is disposed along the edge of a first side of the signal processing chip 302, and the second pad array 320d is offset relative to the first pad array towards the center of the signal processing chip. Thus, the first pad array 320c is located on the edge side of the signal processing chip 302, and the second pad array 320d is located on the inner side of the signal processing chip 302, with the first pad array 320c facing the first laser driver chip 320, the first TIA 340, the second laser driver chip 360, and the second TIA 380, respectively.

[0165] In some embodiments, the first pad array 320c is electrically connected to the traces on the surface layer 303, thereby enabling the signal processing chip to be electrically connected to a portion of the channels of the first laser driver chip 320, the first TIA340, the second laser driver chip 360, and the second TIA380, respectively.

[0166] In some embodiments, the second pad array 320d is electrically connected to the traces on the second inner layer surface, and the traces on the second inner layer surface are electrically connected to the corresponding traces on the surface layer, thereby enabling the signal processing chip 302 to be electrically connected to another portion of the channels of the first laser driver chip 320, the first TIA 340, the second laser driver chip 360, and the second TIA 380, respectively.

[0167] In some embodiments, based on the specific first pad array 320c and second pad array 320d distributed on the surface of the signal processing chip 302, the signal processing chip 302 is electrically connected to the first laser driver chip 320, the first TIA 340, the second laser driver chip 360 and the second TIA 380 respectively by routing traces on the surface layer and the second inner layer of the circuit board, thereby realizing multi-channel signal transmission.

[0168] In some embodiments, the pads of different arrays are electrically connected to the traces on different layers of the circuit board, while shortening the distance between the first laser driver chip 320, the first TIA340, the second laser driver chip 360 and the second TIA380 and the signal processing chip 302 respectively, avoiding crosstalk and interference of the surface traces of the circuit board, and optimizing the signal transmission performance.

[0169] like Figure 9 As shown, in some embodiments, four signal lines are connected between the first laser driver chip 320 and the signal processing chip 302. Four signal lines are also connected between the first TIA 340 and the signal processing chip 302.

[0170] In some embodiments, the four channels corresponding to the first laser driver chip 320, from top to bottom, are: a first emission channel, a second emission channel, a third emission channel, and a fourth emission channel. Among the emission signal lines corresponding to adjacent emission channels, one emission signal line includes surface traces and inner layer traces, and the other emission signal line includes surface traces, and so on, in an alternating arrangement.

[0171] In some embodiments, the four channels corresponding to the second laser driver chip 360, from top to bottom, are: the fifth transmission channel, the sixth transmission channel, the seventh transmission channel, and the eighth transmission channel. Similarly, among the transmission signal lines corresponding to adjacent transmission channels, one transmission signal line includes surface traces and inner layer traces, and the other transmission signal line includes surface traces, thus arranged in an alternating manner.

[0172] In some embodiments, since the second emitter pad 322a, the fourth emitter pad 324a, the sixth emitter pad 326a, and the eighth emitter pad 328a are located at the edge of the signal processing chip 302, the second emitter channel, the fourth emitter channel, the sixth emitter channel, and the eighth emitter channel are respectively traced on the surface of the circuit board 300 to receive digital signals emitted by the signal processing chip 302. One end of these surface traces is electrically connected to the first laser driver chip 320 or the second laser driver chip 360, and the other end is electrically connected to the corresponding emitter pads.

[0173] In some embodiments, since the first emitter pad 321a, the third emitter pad 323a, the fifth emitter pad 325a, and the seventh emitter pad 327a are located inside the signal processing chip 302, to avoid crosstalk between the surface traces of the circuit board, the signal lines corresponding to the first emitter channel, the third emitter channel, the fifth emitter channel, and the seventh emitter channel include surface traces and inner layer traces of the circuit board 300. One end of the surface trace is electrically connected to the first laser driver chip 320 or the second laser driver chip 360, and the other end is electrically connected vertically to the inner layer traces through a metal via. The inner layer traces are then electrically connected to these pads on the surface of the signal processing chip 302 through metal vias.

[0174] like Figure 10 As shown, in some embodiments, the four channels corresponding to the first TIA340, from bottom to top, are the first receiving channel, the second receiving channel, the third receiving channel, and the fourth receiving channel. To avoid crosstalk between the surface traces of the circuit board, and based on the fact that the first receiving pads 321b and 322b corresponding to the first and second receiving channels are located at the edge of the signal processing chip 302, and the fourth receiving pads 324b and 323b corresponding to the third and fourth receiving channels are located inside the signal processing chip 302, the receiving signal lines corresponding to the first and second receiving channels include one surface trace, one inner layer trace, and another surface trace. The receiving signal lines corresponding to the third and fourth receiving channels include both surface traces and inner layer traces.

[0175] In some embodiments, the four channels corresponding to the second TIA380 are, from bottom to top, the fifth receiving channel, the sixth receiving channel, the seventh receiving channel, and the eighth receiving channel. Among the receiving signal lines corresponding to adjacent receiving channels, one receiving signal line includes surface traces and inner layer traces, and the other receiving signal line includes surface traces, and so on, in an alternating arrangement.

[0176] In some embodiments, the four channels corresponding to the first laser driver chip 320, from top to bottom, are: a first transmitting channel, a second transmitting channel, a third transmitting channel, and a fourth transmitting channel. The four channels corresponding to the first TIA 340, from top to bottom, are: a fourth receiving channel, a third receiving channel, a second receiving channel, and a first receiving channel. Thus, the corresponding transmitting and receiving channels are symmetrically distributed. The common-mode noise cancellation effect formed by the symmetrical distribution can reduce crosstalk between channels, which is beneficial to improving signal integrity. In addition, the reverse electromagnetic fields generated by the symmetrical structure can cancel each other out, improving electromagnetic compatibility. Similarly, the other four transmitting channels are symmetrically distributed with the other four receiving channels.

[0177] In some embodiments, since the first transmission channel is close to the edge of the circuit board 300, the first transmission signal line corresponding to the first transmission channel includes a first surface layer trace 411 located on the surface of the circuit board 300 and a first inner layer trace 413 located on the inner layer of the circuit board 300. The first surface layer trace 411 is located on the surface of the circuit board 300, and the first inner layer trace 413 is located on the inner layer of the circuit board 300. The first surface layer trace 411 and the first inner layer trace 413 are electrically connected between the two layers through metal vias. For example, the first inner layer trace 413 is located on the second inner layer of the circuit board 300, and the first inner layer is a ground layer.

[0178] In some embodiments, the second transmission signal line corresponding to the second transmission channel includes a second surface trace 421 located on the surface of the circuit board 300.

[0179] In some embodiments, the third transmission signal line corresponding to the third transmission channel includes a third surface layer trace 431 located on the surface of the circuit board 300 and a second inner layer trace 433 located on the inner layer of the circuit board 300. The third surface layer trace 431 and the second inner layer trace 433 are electrically connected between layers via metal vias. Exemplarily, the second inner layer trace 433 is located on the second inner layer of the circuit board 300, and the first inner layer is a ground layer. The second inner layer trace 433 and the first inner layer trace 413 are located on the same layer.

[0180] In some embodiments, the fourth transmit signal line corresponding to the fourth transmit channel includes a fourth surface layer trace 441 located on the surface of the circuit board 300.

[0181] In some embodiments, the fifth transmit signal line corresponding to the fifth transmit channel includes a fifth surface layer trace 451 and a third inner layer trace 453 located on the surface of the circuit board 300. The fifth surface layer trace 451 and the third inner layer trace 453 are electrically connected between layers via metal vias. Exemplarily, the third inner layer trace 453 is located on the second inner layer of the circuit board 300, and the first inner layer is a ground layer. The third inner layer trace 453 and the first inner layer trace 413 are located on the same layer.

[0182] In some embodiments, the fifth transmit signal line corresponding to the sixth transmit channel includes a sixth surface layer trace 461 located on the surface of the circuit board 300.

[0183] In some embodiments, the fifth transmit signal line corresponding to the seventh transmit channel includes a seventh surface layer trace 471 and a fourth inner layer trace 473 located on the surface of the circuit board 300. The seventh surface layer trace 471 and the fourth inner layer trace 473 are electrically connected between layers via metal vias. Exemplarily, the fourth inner layer trace 473 is located on the second inner layer of the circuit board 300, and the first inner layer is a ground layer. The fourth inner layer trace 473 and the first inner layer trace 413 are located on the same layer.

[0184] In some embodiments, the eighth transmit signal line corresponding to the eighth transmit channel includes an eighth surface layer trace 481 located on the surface of the circuit board 300.

[0185] In some embodiments, the first receiving signal line corresponding to the first receiving channel includes a ninth surface layer trace 511, a fifth inner layer trace 513, and a tenth surface layer trace 511a. The two ends of the fifth inner layer trace 513 are electrically connected to the ninth surface layer trace 511 and the tenth surface layer trace 511a respectively via metal vias. The fifth inner layer trace 513 is located on the second inner layer of the circuit board 300, and the first inner layer is the ground layer. The fifth inner layer trace 513 and the first inner layer trace 413 are located on the same layer.

[0186] In some embodiments, the second receiving signal line corresponding to the second receiving channel includes an eleventh surface layer trace 521, a sixth inner layer trace 523, and a twelfth surface layer trace 521a.

[0187] In some embodiments, the third receiving signal line corresponding to the third receiving channel includes a thirteenth surface layer trace 531 and a seventh inner layer trace 533.

[0188] In some embodiments, the fourth receiving signal line corresponding to the fourth receiving channel includes a fourteenth surface layer trace 541 and an eighth inner layer trace 543.

[0189] In some embodiments, the fifth receiving signal line corresponding to the fifth receiving channel includes a fifteenth surface layer trace 551 and a ninth inner layer trace 553.

[0190] In some embodiments, the sixth receiving signal line corresponding to the sixth receiving channel includes a sixteenth surface layer trace 561.

[0191] In some embodiments, the seventh receiving signal line corresponding to the seventh receiving channel includes a seventeenth surface layer trace 571 and a tenth inner layer trace 573.

[0192] In some embodiments, the eighth receive signal line corresponding to the eighth receive channel includes the eighteenth surface layer trace 581.

[0193] Figure 12 This is a schematic diagram of an interlayer electrical connection of a circuit board according to some embodiments. For example... Figure 12 As shown, in some embodiments, the circuit board 300 includes a surface layer 303, a first inner layer 304, and a second inner layer 305. The first inner layer 304 is a ground layer, and the second inner layer 305 is a signal layer.

[0194] In some embodiments, the surface of the surface layer 303 is provided with surface layer traces, and the surface of the second inner layer 305 is provided with inner layer traces. A first metal via 306 and a second metal via 307 are provided between the surface of the surface layer 303 and the surface of the second inner layer 305. The surface layer traces are electrically connected to the optical matching chip, and the inner layer traces are electrically connected to the signal processing chip 302.

[0195] In some embodiments, the surface traces on the surface of the surface layer 303 are electrically connected downward through the first metal via 306 to one end of the inner layer traces, and the other end of the inner layer traces are electrically connected upward through the second metal via 307 to the surface of the circuit board 300, so as to guide the electrical signals to the surface of the circuit board 300 for transmission.

[0196] Figure 13 This is a schematic diagram of the surface layer routing of a circuit board according to some embodiments. For example... Figure 13 As shown, in some embodiments, taking an eight-channel circuit as an example, the surface layer of the circuit board 300 has 18 surface traces distributed on it, and these surface traces do not crosstalk each other.

[0197] In some embodiments, one end of the first surface trace 411 is electrically connected to the first laser driver chip, and the other end is electrically connected to the trace on the second inner surface, thereby realizing the connection of the first emission channel between the first laser driver chip 320 and the signal processing chip 302.

[0198] In some embodiments, one end of the second surface trace 421 is electrically connected to the first laser driver chip, and the other end is electrically connected to the second emission pad 322a, thereby realizing the connection of the second emission channel between the first laser driver chip 320 and the signal processing chip 302.

[0199] In some embodiments, one end of the third surface trace 431 is electrically connected to the first laser driver chip, and the other end is electrically connected to the trace on the second inner surface, thereby realizing the connection of the third emission channel between the first laser driver chip 320 and the signal processing chip.

[0200] In some embodiments, one end of the fourth surface trace 441 is electrically connected to the first laser driver chip, and the other end is electrically connected to the fourth emission pad 324a, thereby realizing the connection of the fourth emission channel between the first laser driver chip 320 and the signal processing chip 302.

[0201] In some embodiments, one end of the fifth surface trace 451 is electrically connected to the first laser driver chip, and the other end is electrically connected to the trace on the second inner surface, thereby realizing the connection of the fifth emission channel between the second laser driver chip 360 and the signal processing chip 302.

[0202] In some embodiments, one end of the sixth surface layer trace 461 is electrically connected to the first laser driver chip, and the other end is electrically connected to the second emission pad 322a, thereby realizing the connection of the sixth emission channel between the second laser driver chip 360 and the signal processing chip 302.

[0203] In some embodiments, one end of the seventh surface trace 471 is electrically connected to the first laser driver chip, and the other end is electrically connected to the trace on the second inner surface, thereby realizing the connection of the seventh emission channel between the second laser driver chip 360 and the signal processing chip 302.

[0204] In some embodiments, one end of the eighth surface trace 481 is electrically connected to the first laser driver chip, and the other end is electrically connected to the eighth emission pad 328a, thereby realizing the connection of the eighth emission channel between the second laser driver chip 360 and the signal processing chip 302.

[0205] In some embodiments, the ninth surface layer trace 511 and the tenth surface layer trace 511a are used to electrically connect the first TIA and the signal processing signal. The ninth surface layer trace 511 is electrically connected to the first TIA, and the tenth surface layer trace 511a is electrically connected to the first receiving pad 321b, realizing the first receiving channel connection between the first TIA 340 and the signal processing chip 302. The ninth surface layer trace 511 and the tenth surface layer trace 511a are respectively electrically connected to the traces of the second inner layer.

[0206] In some embodiments, the eleventh surface layer trace 521 and the twelfth surface layer trace 521a are used to electrically connect the first TIA 340 and the signal processing signal. The eleventh surface layer trace 521 is electrically connected to the first TIA 340, and the twelfth surface layer trace 521a is electrically connected to the second receiving pad 322b, realizing the second receiving channel connection between the first TIA 340 and the signal processing chip 302. The eleventh surface layer trace 521 and the twelfth surface layer trace 521a are respectively electrically connected to the traces of the second inner layer.

[0207] In some embodiments, one end of the thirteenth surface layer trace 531 is electrically connected to the first TIA, and the other end is electrically connected to the trace on the second inner layer surface, thereby realizing the connection of the third receiving channel between the first TIA 340 and the signal processing chip 302.

[0208] In some embodiments, one end of the fourteenth surface layer trace 541 is electrically connected to the first TIA, and the other end is electrically connected to the trace on the second inner layer surface, thereby realizing the connection of the fourth receiving channel between the first TIA 340 and the signal processing chip 302.

[0209] In some embodiments, one end of the fifteenth surface layer trace 551 is electrically connected to the second TIA, and the other end is electrically connected to the trace on the second inner layer surface, thereby realizing the connection of the fifth receiving channel between the second TIA 380 and the signal processing chip 302.

[0210] In some embodiments, one end of the sixteenth surface layer trace 561 is electrically connected to the second TIA, and the other end is electrically connected to the sixth receiving pad 326b, thereby realizing the connection of the sixth receiving channel between the second TIA 380 and the signal processing chip 302.

[0211] In some embodiments, one end of the seventeenth surface layer trace 571 is electrically connected to the second TIA, and the other end is electrically connected to the trace on the second inner layer surface, thereby realizing the connection of the seventh receiving channel between the second TIA 380 and the signal processing chip 302.

[0212] In some embodiments, one end of the eighteenth surface layer trace 581 is electrically connected to the second TIA, and the other end is electrically connected to the eighth receiving pad 328b, thereby realizing the connection of the eighth receiving channel between the second TIA 380 and the signal processing chip 302.

[0213] Figure 14 This is a schematic diagram of the second inner layer routing of a circuit board according to some embodiments. For example... Figure 14 As shown, in some embodiments, taking an eight-channel circuit as an example, the second inner layer surface of the circuit board 300 has 10 inner layer traces distributed thereon, and these traces do not crosstalk each other.

[0214] In some embodiments, one end of the first inner layer trace 413 is electrically connected to the first outer layer trace 411, and the other end is electrically connected to the first emission pad 321a, thereby realizing the connection of the first emission channel between the first laser driver chip 320 and the signal processing chip 302.

[0215] In some embodiments, one end of the second inner layer trace 433 is electrically connected to the third outer layer trace 431, and the other end is electrically connected to the third emission pad 323a, thereby realizing the connection of the third emission channel between the first laser driver chip 320 and the signal processing chip 302.

[0216] In some embodiments, one end of the third inner layer trace 453 is electrically connected to the fifth outer layer trace 451, and the other end is electrically connected to the fifth emission pad 325a, thereby realizing the connection of the fifth emission channel between the second laser driver chip 360 and the signal processing chip 302.

[0217] In some embodiments, one end of the fourth inner layer trace 473 is electrically connected to the seventh outer layer trace 471, and the other end is electrically connected to the seventh emission pad 327a, thereby realizing the connection of the seventh emission channel between the second laser driver chip 360 and the signal processing chip 302.

[0218] In some embodiments, the fifth inner layer trace 513 is used to electrically connect the ninth outer layer trace 511 and the tenth outer layer trace 511a, thereby realizing the first receiving channel connection between the first TIA340 and the signal processing chip 302.

[0219] In some embodiments, the sixth inner layer trace 523 is used to electrically connect the eleventh outer layer trace 521 and the twelfth outer layer trace 521a, thereby realizing the connection of the second receiving channel between the first TIA340 and the signal processing chip 302.

[0220] In some embodiments, one end of the seventh inner layer trace 533 is electrically connected to the thirteenth outer layer trace 531, and the other end is electrically connected to the third receiving pad 323b, thereby realizing the connection of the third receiving channel between the first TIA340 and the signal processing chip 302.

[0221] In some embodiments, one end of the eighth inner layer trace 543 is electrically connected to the fourteenth outer layer trace 541, and the other end is electrically connected to the fourth receiving pad 324b, thereby realizing the fourth receiving channel connection between the first TIA340 and the signal processing chip 302.

[0222] In some embodiments, one end of the ninth inner layer trace 553 is connected to the fifteenth outer layer trace 551, and the other end is electrically connected to the fifth receiving pad 325b, thereby realizing the connection of the fifth receiving channel between the second TIA380 and the signal processing chip 302.

[0223] In some embodiments, one end of the tenth inner layer trace 573 is electrically connected to the seventeenth outer layer trace 571, and the other end is electrically connected to the seventh receiving pad 327b, thereby realizing the connection of the seventh receiving channel between the second TIA380 and the signal processing chip 302.

[0224] Figure 15 This is a schematic diagram showing the electrical connection traces between a first laser driver chip, a first TIA, and a signal processing chip according to some embodiments. Figure 15 As shown, in some embodiments, the first laser driver chip 320 is arranged adjacent to the first TIA.

[0225] In some embodiments, the first laser driver chip 320 and the signal processing chip 302 are electrically connected to multiple transmission channels. Among adjacent transmission channels, the signal line corresponding to one transmission channel includes a trace on the surface layer 303 and a trace on the second inner layer 305, and the signal line corresponding to another transmission channel includes another trace on the surface layer.

[0226] In some embodiments, the first TIA340 and the signal processing chip 302 are electrically connected to multiple receiving channels. The signal lines corresponding to the first receiving channel include a trace on the surface layer 303, a trace on the second inner layer 305, and another trace on the surface layer 303. The signal lines corresponding to the second receiving channel include a trace on the surface layer 303, a trace on the second inner layer 305, and another trace on the surface layer 303. The signal lines corresponding to the third receiving channel include a trace on the surface layer 303 and a trace on the second inner layer 305. The signal lines corresponding to the fourth receiving channel include a trace on the surface layer 303 and a trace on the second inner layer 305.

[0227] Figure 16 This is a schematic diagram showing the electrical connection traces between a second laser driver chip, a second TIA, and a signal processing chip according to some embodiments. In some embodiments, the second laser driver chip 360 and the second TIA 380 are arranged adjacent to each other.

[0228] In some embodiments, the second laser driver chip 360 and the signal processing chip 302 are electrically connected to multiple transmission channels. Among adjacent transmission channels, the signal line corresponding to one transmission channel includes a trace on the surface layer 303 and a trace on the second inner layer 305, and the signal line corresponding to another transmission channel includes another trace on the surface layer 303.

[0229] In some embodiments, the first TIA380 is electrically connected to the signal processing chip 302 through multiple receiving channels. Among adjacent receiving channels, the signal line corresponding to one receiving channel includes a trace on the surface layer 303 and a trace on the second inner layer 305, and the signal line corresponding to another receiving channel includes another trace on the surface layer 303.

[0230] Figure 17 This is a schematic diagram of the electrical connection traces between a first laser driver chip and a signal processing chip according to some embodiments. Figure 17 As shown, in some embodiments, the first laser driver chip 320 is electrically connected to the signal processing chip 302.

[0231] In some embodiments, the first laser driver chip 320 and the signal processing chip 302 are electrically connected to multiple transmission channels. Among the transmission signal lines corresponding to adjacent transmission channels, one transmission signal line includes surface traces and inner traces, and the other transmission signal line includes surface traces. This staggered arrangement optimizes the wiring space and avoids crosstalk between surface traces.

[0232] In some embodiments, the first pad array 320c includes a second emitter pad 322a and a fourth emitter pad 324a, and the second pad array 320d includes a first emitter pad 321a and a third emitter pad 323a.

[0233] In some embodiments, a first surface trace 411 and a first inner layer trace 413 are connected between the first laser driver chip 320 and the first emission pad 321a. The first inner layer trace 413 is located on the surface of the second inner layer 305. One end of the first surface trace 411 is electrically connected to the first laser driver chip 320, and the other end is electrically connected to the first inner layer trace 413 through a metal via. The first inner layer trace 413 is electrically connected to the first emission pad 321a through a metal via, thereby realizing the electrical connection between the first laser driver chip 320 and the first emission pad 321a, and further realizing the electrical connection between the first laser driver chip 320 and the signal processing chip 302.

[0234] In some embodiments, a second surface trace 421 connects the first laser driver chip 320 and the second emitting pad 322a. One end of the second surface trace 421 is electrically connected to the first laser driver chip 320, and the other end is electrically connected to the second emitting pad 322a, thereby realizing the electrical connection between the first laser driver chip 320 and the second emitting pad 322a, and further realizing the electrical connection between the first laser driver chip 320 and the signal processing chip 302.

[0235] In some embodiments, a third surface layer trace 431 and a second inner layer trace 433 are connected between the first laser driver chip 320 and the third emission pad 323a, with the second inner layer trace 433 located on the surface of the second inner layer 305. One end of the third surface layer trace 431 is electrically connected to the first laser driver chip 320, and the other end is electrically connected to the second inner layer trace 433 through a metal via. The second inner layer trace 433 is electrically connected to the third emission pad 323a through a metal via, thereby realizing the electrical connection between the first laser driver chip 320 and the third emission pad 323a, and further realizing the electrical connection between the first laser driver chip 320 and the signal processing chip 302.

[0236] In some embodiments, a fourth surface trace 441 is connected between the first laser driver chip 320 and the fourth emitting pad 324a. One end of the fourth surface trace 441 is electrically connected to the first laser driver chip 320, and the other end is electrically connected to the fourth emitting pad 324a, thereby realizing the electrical connection between the first laser driver chip 320 and the fourth emitting pad 324a, and further realizing the electrical connection between the first laser driver chip and the signal processing chip.

[0237] Figure 18 This is a schematic diagram of the electrical connection traces between a first TIA and a signal processing chip according to some embodiments. Figure 18 As shown, in some embodiments, the first TIA340 is electrically connected to the signal processing chip 302.

[0238] In some embodiments, the first TIA340 and the signal processing chip 302 are electrically connected to multiple receiving channels. For example, the first TIA340 and the signal processing chip 302 have four transmission channels, each with a trace on the second inner layer 305, to avoid crosstalk with the surface traces electrically connected to the second laser driver chip 340, optimize the trace distribution, and ensure signal transmission performance.

[0239] In some embodiments, the first pad array 320c includes a first receiving pad 321b and a second receiving pad 322b, and the second pad array 320d includes a third receiving pad 323b and a fourth receiving pad 324b.

[0240] In some embodiments, a ninth surface layer trace 511, a fifth inner layer trace 513, and a tenth surface layer trace 511a are connected between the first TIA340 and the first receiving pad 321b. The two ends of the fifth inner layer trace 513 are electrically connected to the ninth surface layer trace 511 and the tenth surface layer trace 511a via metal vias, respectively. The fifth inner layer trace 513 is located on the surface of the second inner layer 305. One end of the ninth surface layer trace 511 is electrically connected to the first TIA340, and the other end is electrically connected to the fifth inner layer trace 513. The fifth inner layer trace 513 is electrically connected to the tenth surface layer trace 511a, and the tenth surface layer trace 511a is electrically connected to the first receiving pad 321b, thereby achieving an electrical connection between the first TIA340 and the signal processing chip 302.

[0241] In some embodiments, an eleventh surface layer trace 521, a sixth inner layer trace 523, and a twelfth surface layer trace 521a are connected between the first TIA340 and the second receiving pad 322b. The six inner layer trace 523 is electrically connected to the eleventh surface layer trace 521 and the twelfth surface layer trace 521a via metal vias, and is located on the surface of the second inner layer 305. One end of the eleventh surface layer trace 521 is electrically connected to the first TIA340, and the other end is electrically connected to the sixth inner layer trace 523. The sixth inner layer trace 523 is electrically connected to the twelfth surface layer trace 521a, and the twelfth surface layer trace 521a is electrically connected to the second receiving pad 322b, thereby achieving an electrical connection between the first TIA340 and the signal processing chip 302.

[0242] In some embodiments, a thirteenth surface layer trace 531 and a seventh inner layer trace 533 are connected between the first TIA340 and the third receiving pad, with the seventh inner layer trace 533 located on the surface of the second inner layer 305. One end of the thirteenth surface layer trace 531 is electrically connected to the first TIA340, and the other end is electrically connected to the seventh inner layer trace 533 through a metal via. The seventh inner layer trace 533 is electrically connected to the third receiving pad 323b through a metal via, thereby realizing the electrical connection between the first TIA340 and the signal processing chip 302.

[0243] In some embodiments, a fourteenth surface layer trace 541 and an eighth inner layer trace 543 are connected between the first TIA340 and the fourth receiving pad, with the eighth inner layer trace 543 located on the surface of the second inner layer 305. One end of the fourteenth surface layer trace 541 is electrically connected to the first TIA340, and the other end is electrically connected to the eighth inner layer trace 543 through a metal via. The eighth inner layer trace 543 is electrically connected to the fourth receiving pad 324b through a metal via, thereby realizing the electrical connection between the first TIA340 and the signal processing chip 302.

[0244] Figure 19 This is a schematic diagram of the electrical connection traces between a second laser driver chip and a signal processing chip according to some embodiments. Figure 19 As shown, in some embodiments, the second laser driver chip 360 is electrically connected to the signal processing chip 302.

[0245] In some embodiments, the second laser driver chip 360 and the signal processing chip 302 are electrically connected to multiple transmission channels. Among the transmission signal lines corresponding to adjacent transmission channels, one transmission signal line includes surface traces and inner traces, and the other transmission signal line includes surface traces. This staggered arrangement optimizes the wiring space and avoids crosstalk between surface traces.

[0246] In some embodiments, the first pad array 320c includes a sixth emitter pad 326a and an eighth emitter pad 328a, and the second pad array 320d includes a fifth emitter pad 325a and a seventh emitter pad 327a.

[0247] In some embodiments, a fifth surface layer trace 451 and a third inner layer trace 453 are connected between the second laser driver chip 360 and the fifth emission pad 325a. The third inner layer trace 453 is located on the surface of the second inner layer 305. One end of the fifth surface layer trace 451 is electrically connected to the second laser driver chip 360, and the other end is electrically connected to the third inner layer trace 453 through a metal via. The third inner layer trace 453 is electrically connected to the fifth emission pad 325a through a metal via, thereby realizing the electrical connection between the second laser driver chip 360 and the fifth emission pad 325a, and thus realizing the electrical connection between the second laser driver chip 360 and the signal processing chip 302.

[0248] In some embodiments, a sixth surface trace 461 connects the second laser driver chip 360 and the sixth emitting pad 326a. One end of the sixth surface trace 461 is electrically connected to the second laser driver chip 360, and the other end is electrically connected to the sixth emitting pad 326a, thereby realizing the electrical connection between the second laser driver chip 360 and the sixth emitting pad 326a, and further realizing the electrical connection between the second laser driver chip 360 and the signal processing chip 302.

[0249] In some embodiments, a seventh surface layer trace 471 and a fourth inner layer trace 473 are connected between the second laser driver chip 360 and the seventh emission pad 327a. The fourth inner layer trace 473 is located on the surface of the second inner layer 305. One end of the seventh surface layer trace 471 is electrically connected to the second laser driver chip 360, and the other end is electrically connected to the fourth inner layer trace 473 through a metal via. The fourth inner layer trace 473 is electrically connected to the seventh emission pad 327a through a metal via, thereby realizing the electrical connection between the second laser driver chip 360 and the seventh emission pad 327a, and further realizing the electrical connection between the second laser driver chip 360 and the signal processing chip 302.

[0250] In some embodiments, an eighth surface trace 481 connects the second laser driver chip 360 and the eighth emitting pad 328a. One end of the eighth surface trace 481 is electrically connected to the second laser driver chip 360, and the other end is electrically connected to the eighth emitting pad 328a, thereby realizing the electrical connection between the second laser driver chip 360 and the eighth emitting pad 328a, and further realizing the electrical connection between the second laser driver chip 360 and the signal processing chip 302.

[0251] Figure 20 This is a schematic diagram of the electrical connection routing between a second TIA and a signal processing chip according to some embodiments. Figure 20 As shown, in some embodiments, the second TIA380 is electrically connected to the signal processing chip 302.

[0252] In some embodiments, among the receiving channels electrically connected between the second TIA380 and the signal processing chip 302, in the receiving signal lines corresponding to adjacent receiving channels, one receiving signal line includes surface traces and inner traces, and the other receiving signal line includes surface traces. This staggered arrangement optimizes the wiring space and avoids crosstalk between surface traces.

[0253] In some embodiments, the first pad array 320c includes a sixth receiving pad 326b and an eighth receiving pad 328b, and the second pad array 320d includes a fifth receiving pad 325b and a seventh receiving pad 327b.

[0254] In some embodiments, a fifteenth surface layer trace 551 and a ninth inner layer trace 553 are connected between the second TIA 380 and the fifth receiving pad, with the ninth inner layer trace 553 located on the surface of the second inner layer 305. One end of the fifteenth surface layer trace 551 is electrically connected to the second TIA 380, and the other end is electrically connected to the ninth inner layer trace 553 through a metal via. The ninth inner layer trace 553 is electrically connected to the fifth receiving pad 325b through a metal via, thereby realizing the electrical connection between the second TIA and the signal processing chip 302.

[0255] In some embodiments, a sixteenth surface layer trace 561 is connected between the second TIA 380 and the sixth receiving pad 326b. One end of the sixteenth surface layer trace 561 is electrically connected to the second TIA, and the other end is electrically connected to the sixth receiving pad 326b, thereby realizing the electrical connection between the second TIA and the signal processing chip 302.

[0256] In some embodiments, a seventeenth surface layer trace 571 and a tenth inner layer trace 573 are connected between the second TIA380 and the seventh receiving pad 327b, with the tenth inner layer trace 573 located on the surface of the second inner layer 305. One end of the seventeenth surface layer trace 571 is electrically connected to the second TIA380, and the other end is electrically connected to the tenth inner layer trace 573 through a metal via. The tenth inner layer trace 573 is electrically connected to the seventh receiving pad 327b through a metal via, thereby realizing the electrical connection between the second TIA380 and the signal processing chip 302.

[0257] In some embodiments, an eighteenth surface layer trace 581 is connected between the second TIA 380 and the eighth receiving pad 328b. One end of the eighteenth surface layer trace 581 is electrically connected to the second TIA, and the other end is electrically connected to the eighth receiving pad 328b, thereby realizing the electrical connection between the second TIA 380 and the signal processing chip 302.

[0258] In this disclosure, by utilizing the inner layer space of the circuit board and routing traces on the surface and inner layers of the circuit board, electrical connections are established between the signal processing chip and the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA, respectively. The electrical connection distance is short, enabling multi-channel signal transmission. At the same time, the pads of different arrays are electrically connected to the traces on different layers of the circuit board, avoiding crosstalk and wiring intersections on the surface layer of the circuit board, and optimizing the wiring space.

[0259] In this disclosure, the first side of the signal processing chip faces the first laser driver chip, the first TIA, the second laser driver chip, and the second TIA simultaneously, so that the first lens assembly and the second lens assembly are arranged side by side along the width direction of the circuit board.

[0260] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. An optical module characterized by comprising: The application relates to a circuit board, a surface of the circuit board being provided with a first laser drive chip, a first TIA, a second laser drive chip and a second TIA, the first laser drive chip being arranged adjacent to the first TIA, and the second laser drive chip being arranged adjacent to the second TIA; the circuit board comprising: a surface layer; a first inner layer connected with the surface layer, the first inner layer being arranged as a ground layer; a second inner layer connected with the first inner layer; a signal processing chip arranged on the surface of the circuit board, a first side of the signal processing chip facing the first laser drive chip, the first TIA, the second laser drive chip and the second TIA at the same time; the surface of the signal processing chip being formed with: a first pad array arranged along the edge of the first side of the signal processing chip; the first pad array being electrically connected with the wiring on the surface layer; a second pad array offsetting towards the center of the signal processing chip relative to the first pad array; the second pad array being electrically connected with the wiring on the surface of the second inner layer, and the wiring on the surface of the second inner layer being electrically connected with the corresponding wiring on the surface layer. The first laser drive chip is electrically connected with the signal processing chip; The first pad array comprises a second emission pad and a fourth emission pad; The second pad array comprises a first emission pad and a third emission pad; The first laser drive chip is connected with the first emission pad through a first surface layer wiring and a first inner layer wiring; the first inner layer wiring is located on the surface of the second inner layer; The first laser drive chip is connected with the second emission pad through a second surface layer wiring; The first laser drive chip is connected with the third emission pad through a third surface layer wiring and a second inner layer wiring; the second inner layer wiring is located on the surface of the second inner layer; The first laser drive chip is connected with the fourth emission pad through a fourth surface layer wiring.

2. The optical module according to claim 1, characterized by The second laser drive chip is electrically connected with the signal processing chip; The first pad array comprises a sixth emission pad and an eighth emission pad; The second pad array comprises a fifth emission pad and a seventh emission pad; The second laser drive chip is connected with the fifth emission pad through a fifth surface layer wiring and a third inner layer wiring; the third inner layer wiring is located on the surface of the second inner layer; The second laser drive chip is connected with the sixth emission pad through a sixth surface layer wiring; The second laser drive chip is connected with the seventh emission pad through a seventh surface layer wiring and a fourth inner layer wiring; the fourth inner layer wiring is located on the surface of the second inner layer; The second laser drive chip is connected with the eighth emission pad through an eighth surface layer wiring.

3. The optical module according to claim 1, characterized by The first TIA is electrically connected with the signal processing chip; The first pad array comprises a first reception pad and a second reception pad; The second pad array comprises a third reception pad and a fourth reception pad; ​ ​ ​ ​ 4. The optical module according to claim 1, characterized by ​ ​ ​ The first TIA is connected with the first receiving pad through a ninth surface layer trace, a fifth inner layer trace and a tenth surface layer trace, wherein the fifth inner layer trace is used for electrically connecting the ninth surface layer trace and the tenth surface layer trace, and the fifth inner layer trace is located on the second inner layer surface; The first TIA is connected with the second receiving pad through an eleventh surface layer trace, a sixth inner layer trace and a twelfth surface layer trace, wherein the sixth inner layer trace is used for electrically connecting the eleventh surface layer trace and the twelfth surface layer trace, and the sixth inner layer trace is located on the second inner layer surface; The first TIA is connected with the third receiving pad through a thirteenth surface layer trace and a seventh inner layer trace, and the seventh inner layer trace is located on the second inner layer surface; The first TIA is connected with the fourth receiving pad through a fourteenth surface layer trace and an eighth inner layer trace, and the eighth inner layer trace is located on the second inner layer surface.

5. The optical module according to claim 1, characterized by The second TIA is electrically connected with the signal processing chip; The first pad array comprises a sixth receiving pad and an eighth receiving pad; The second pad array comprises a fifth receiving pad and a seventh receiving pad; The second TIA is connected with the fifth receiving pad through a fifteenth surface layer trace and a ninth inner layer trace, and the ninth inner layer trace is located on the second inner layer surface; The second TIA is connected with the sixth receiving pad through a sixteenth surface layer trace; The second TIA is connected with the seventh receiving pad through a seventeenth surface layer trace and a tenth inner layer trace, and the tenth inner layer trace is located on the second inner layer surface; The second TIA is connected with the eighth receiving pad through an eighteenth surface layer trace.

6. An optical module characterized by comprising: Comprise: A circuit board comprising: A surface layer; A first inner layer connected with the surface layer, wherein the first inner layer is set as a ground layer; A second inner layer connected with the first inner layer; A signal processing chip arranged on the surface of the circuit board; A first laser drive chip arranged on the surface of the circuit board, facing a first side of the signal processing chip, and electrically connected with the signal processing chip; the first laser drive chip and the signal processing chip are electrically connected through a plurality of emission channels, wherein in adjacent emission channels, a signal line corresponding to one emission channel comprises a trace on the surface layer and a trace on the second inner layer, and a signal line corresponding to another emission channel comprises another trace on the surface layer; A first TIA is arranged on the surface of the circuit board, faces the first side of the signal processing chip, and is electrically connected with the signal processing chip; a plurality of receiving channels are electrically connected between the first TIA and the signal processing chip, wherein the signal line corresponding to the first receiving channel comprises a trace on the surface layer, a trace on the second inner layer, and another trace on the surface layer; the signal line corresponding to the second receiving channel comprises a trace on the surface layer, a trace on the second inner layer, and another trace on the surface layer; the signal line corresponding to the third receiving channel comprises a trace on the surface layer and a trace on the second inner layer; and the signal line corresponding to the fourth receiving channel comprises a trace on the surface layer and a trace on the second inner layer.

7. The optical module according to claim 6, characterized by Comprise: A second laser drive chip is arranged on the surface of the circuit board, faces the first side of the signal processing chip, and is electrically connected with the signal processing chip; A plurality of transmitting channels are electrically connected between the second laser drive chip and the signal processing chip, wherein in adjacent transmitting channels, the signal line corresponding to one transmitting channel comprises a trace on the surface layer and a trace on the second inner layer, and the signal line corresponding to the other transmitting channel comprises another trace on the surface layer; A second TIA is arranged on the surface of the circuit board, faces the first side of the signal processing chip, and is electrically connected with the signal processing chip; a plurality of receiving channels are electrically connected between the first TIA and the signal processing chip, wherein in adjacent receiving channels, the signal line corresponding to one receiving channel comprises a trace on the surface layer and a trace on the second inner layer, and the signal line corresponding to the other receiving channel comprises another trace on the surface layer.

8. The optical module according to claim 6, characterized by The surface of the signal processing chip is formed with: A first pad array is arranged along the edge of the first side of the signal processing chip; the first pad array is electrically connected with the traces on the surface layer; A second pad array is offset towards the center of the signal processing chip relative to the first pad array; the second pad array is electrically connected with the traces on the surface of the second inner layer.

9. The optical module of claim 6, wherein, The surface of the signal processing chip is formed with a transmitting pad group and a receiving pad group; the transmitting pad group is located in a first region on the surface of the signal processing chip, and the receiving pad group is located in a second region on the surface of the signal processing chip.

10. The optical module of claim 6, wherein, The four transmitting channels electrically connected between the first laser drive chip and the signal processing chip are respectively a first transmitting channel, a second transmitting channel, a third transmitting channel, and a fourth transmitting channel from top to bottom; The four receiving channels electrically connected between the first TIA and the signal processing chip are respectively a fourth receiving channel, a third receiving channel, a second receiving channel, and a first receiving channel from top to bottom.

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