Display device

Abstract

A display device is provided. The display device may include a display panel in which one normal pixel and a plurality of interpolated pixels surrounding the one normal pixel form one pixel group. One normal pixel may include a driving transistor and a normal light emitting element receiving a driving current through a first node connected to a drain electrode of the driving transistor, each of the plurality of interpolated pixels may include a first interpolated light emitting element that receives a portion of the first drive current from the first normal pixel and a second interpolated light emitting element that receives a portion of the second drive current from the second normal pixel, and a first interpolated emission pattern of the first interpolated light emitting element is disposed adjacent to the second normal pixel and a second interpolated emission pattern of the second interpolated light emitting element is disposed adjacent to the first normal pixel.

Description

Technical Field

[0001] This disclosure relates to display devices and mobile electronic devices including display devices. Background Technology

[0002] Wearable devices have been developed in the form of glasses or helmets, in which the focal point is formed at a distance close to the user's eyes. For example, wearable devices may be head-mounted display (HMD) devices or AR glasses. Wearable devices provide users with augmented reality (hereinafter referred to as AR) images or virtual reality (hereinafter referred to as VR) images.

[0003] Wearable devices such as HMDs or AR glasses require display specifications of approximately 3500 PPI (pixels per inch) or higher to allow users to use them for extended periods without experiencing dizziness. For this purpose, silicon-based organic light-emitting diode (OLEDoS) technology is emerging for high-resolution, small-scale organic light-emitting display devices. Silicon-based organic light-emitting diode (OLEDoS) is a technology for fabricating organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) is disposed. Utility Model Content

[0004] This disclosure provides a display device and a mobile electronic device that can achieve up-scaling by arranging multiple interpolated pixels around normal pixels and can improve up-scaling efficiency by optimizing the position of the emission pattern of the interpolated pixels.

[0005] According to embodiments of this disclosure, a display device may include a display panel comprising a normal pixel and a plurality of interpolated pixels surrounding the normal pixel to form a pixel group. A normal pixel may include a driving transistor and a normal light-emitting element that receives driving current through a first node connected to the drain electrode of the driving transistor. Each of the plurality of interpolated pixels may include a first interpolated light-emitting element that receives a first driving current from a first normal pixel and a second interpolated light-emitting element that receives a second driving current from a second normal pixel. A first interpolation emission pattern of the first interpolated light-emitting element is configured to be adjacent to the second normal pixel, and a second interpolation emission pattern of the second interpolated light-emitting element is configured to be adjacent to the first normal pixel.

[0006] The first normal pixel may include a first normal light-emitting element, the second normal pixel may include a second normal light-emitting element, the second interpolated emission pattern is disposed between the first normal emission pattern and the first interpolated emission pattern of the first normal light-emitting element, and the first interpolated emission pattern is disposed between the second normal emission pattern and the second interpolated emission pattern of the second normal light-emitting element.

[0007] A pixel group may include: a normal pixel, located at the center of the pixel group; a first interpolated pixel, located in a first planar direction starting from the normal pixel; a second interpolated pixel, located in a second planar direction opposite to the first planar direction starting from the normal pixel; a third interpolated pixel, located in a third planar direction perpendicular to the first planar direction starting from the normal pixel; a fourth interpolated pixel, located in a fourth planar direction opposite to the third planar direction starting from the normal pixel; a fifth interpolated pixel, located in a first diagonal direction between the first and third planar directions starting from the normal pixel; a sixth interpolated pixel, located in a second diagonal direction between the second and third planar directions starting from the normal pixel; a seventh interpolated pixel, located in a third diagonal direction opposite to the second diagonal direction starting from the normal pixel; and an eighth interpolated pixel, located in a fourth diagonal direction opposite to the first diagonal direction starting from the normal pixel.

[0008] The first interpolated pixel and the second interpolated pixel each receive driving current from a normal pixel in the first plane direction and the second plane direction, respectively, which is disposed in the corresponding one of the first interpolated pixel and the second interpolated pixel.

[0009] For each of the first interpolated pixel and the second interpolated pixel, the first normal pixel is a pixel disposed in a first planar direction starting from the corresponding one of the first interpolated pixel and the second interpolated pixel; and for each of the first interpolated pixel and the second interpolated pixel, the second normal pixel is a pixel disposed in a second planar direction starting from the corresponding one of the first interpolated pixel and the second interpolated pixel.

[0010] The third interpolation pixel and the fourth interpolation pixel each receive driving current from a normal pixel in the third plane direction and the fourth plane direction, respectively, which are set in the corresponding one of the third interpolation pixels and the fourth interpolation pixels.

[0011] For each of the third interpolated pixel and the fourth interpolated pixel, the first normal pixel is a pixel set in a third plane direction starting from the corresponding one of the third interpolated pixel and the fourth interpolated pixel; and for each of the third interpolated pixel and the fourth interpolated pixel, the second normal pixel is a pixel set in a fourth plane direction starting from the corresponding one of the third interpolated pixel and the fourth interpolated pixel.

[0012] The fifth to eighth interpolation pixels each receive driving current from a normal pixel located in the first diagonal direction to the fourth diagonal direction of the corresponding one of the fifth to eighth interpolation pixels.

[0013] Each of the fifth to eighth interpolated pixels may further include a third interpolated light-emitting element that receives a third driving current from the third normal pixel and a fourth interpolated light-emitting element that receives a fourth driving current from the fourth normal pixel.

[0014] The third normal pixel may include a third normal light-emitting element, the fourth normal pixel may include a fourth normal light-emitting element, the third interpolation emission pattern of the third interpolated light-emitting element is configured to be adjacent to the fourth normal pixel, and the fourth interpolation emission pattern of the fourth interpolated light-emitting element is configured to be adjacent to the third normal pixel.

[0015] For each of the fifth to eighth interpolated pixels, the first normal pixel is a pixel set in a first diagonal direction starting from the corresponding one of the fifth to eighth interpolated pixels; for each of the fifth to eighth interpolated pixels, the second normal pixel is a pixel set in a second diagonal direction starting from the corresponding one of the fifth to eighth interpolated pixels; for each of the fifth to eighth interpolated pixels, the third normal pixel is a pixel set in a third diagonal direction starting from the corresponding one of the fifth to eighth interpolated pixels; and for each of the fifth to eighth interpolated pixels, the fourth normal pixel is a pixel set in a fourth diagonal direction starting from the corresponding one of the fifth to eighth interpolated pixels.

[0016] In the fifth to eighth interpolated pixels, the first to fourth interpolated emission patterns are set in a 2×2 matrix.

[0017] In the first interpolated pixel and the second interpolated pixel, the first interpolated emission pattern may include a pair of first sub-interpolated emission patterns that are separate from each other, and the second interpolated emission pattern may include a pair of second sub-interpolated emission patterns that are separate from each other.

[0018] In the first interpolated pixel and the second interpolated pixel, a pair of first sub-interpolated emission patterns and a pair of second sub-interpolated emission patterns are set in a 2×2 matrix.

[0019] In the first interpolated pixel and the second interpolated pixel, a pair of first sub-interpolated emission patterns and a pair of second sub-interpolated emission patterns are set in a 1×4 matrix.

[0020] In the third interpolation pixel and the fourth interpolation pixel, the third interpolation emission pattern may include a pair of third sub-interpolation emission patterns that are separate from each other, and the fourth interpolation emission pattern may include a pair of fourth sub-interpolation emission patterns that are separate from each other.

[0021] In the third and fourth interpolated pixels, a pair of third sub-interpolated emission patterns and a pair of fourth sub-interpolated emission patterns are set in a 2×2 matrix.

[0022] In the third and fourth interpolated pixels, a pair of third sub-interpolated emission patterns and a pair of fourth sub-interpolated emission patterns are set in a 4×1 matrix.

[0023] According to embodiments of this disclosure, a mobile electronic device may include a display panel comprising a normal pixel and a plurality of interpolated pixels surrounding the normal pixel to form a pixel group. A normal pixel may include a driving transistor and a normal light-emitting element that receives driving current through a first node connected to the drain electrode of the driving transistor. Each of the plurality of interpolated pixels may include a first interpolated light-emitting element that receives a first driving current from a first normal pixel and a second interpolated light-emitting element that receives a second driving current from a second normal pixel. A first interpolation emission pattern of the first interpolated light-emitting element is configured to be adjacent to the second normal pixel, and a second interpolation emission pattern of the second interpolated light-emitting element is configured to be adjacent to the first normal pixel.

[0024] The first normal pixel may include a first normal light-emitting element, the second normal pixel may include a second normal light-emitting element, the second interpolated emission pattern is disposed between the first normal emission pattern and the first interpolated emission pattern of the first normal light-emitting element, and the first interpolated emission pattern is disposed between the second normal emission pattern and the second interpolated emission pattern of the second normal light-emitting element.

[0025] In the display device and the mobile electronic device including the display device according to the embodiments, up-scaling is achieved by arranging a plurality of interpolated pixels around normal pixels, and up-scaling efficiency is increased by optimizing the position of the emission pattern of the interpolated pixels. Attached Figure Description

[0026] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0027] Figure 1 This is an exploded perspective view showing a display device according to one embodiment;

[0028] Figure 2 This is a block diagram illustrating a display device according to one embodiment;

[0029] Figure 3 This is an equivalent circuit diagram of the first sub-pixel according to one implementation method;

[0030] Figure 4 This is a layout diagram showing an example of a display panel according to one embodiment;

[0031] Figure 5 and Figure 6 It is shown Figure 4 A layout diagram illustrating the implementation method of the display area;

[0032] Figure 7 It is along Figure 5 A cross-sectional view of an example display panel, taken by line I1-I1';

[0033] Figure 8 This is a perspective view showing a head-mounted display according to one embodiment;

[0034] Figure 9 It is shown Figure 8 An exploded perspective view of an example of a head-mounted display;

[0035] Figure 10 This is a perspective view showing a head-mounted display according to one embodiment;

[0036] Figure 11 This is a schematic diagram illustrating the arrangement of pixels in a display panel according to one embodiment;

[0037] Figure 12 This is a layout diagram showing the emission pattern of pixels according to a comparative example;

[0038] Figures 13 to 17 It is a layout diagram showing the emission pattern of pixels according to one embodiment; and

[0039] Figure 18 This is an equivalent circuit diagram of a normal pixel according to one implementation method. Detailed Implementation

[0040] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are illustrated. However, the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0041] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or an intervening layer may also be present. Throughout the specification, the same reference numerals indicate the same components.

[0042] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below can be referred to as the second element. Similarly, the second element can also be referred to as the first element.

[0043] Features of each of the various embodiments of this disclosure may be combined with each other in part or in whole, and may interact with each other technically in various ways, and the corresponding embodiments may be implemented independently of each other or may be implemented together in association with each other.

[0044] In the following description, specific embodiments will be described with reference to the accompanying drawings.

[0045] Figure 1 This is an exploded perspective view showing a display device according to one embodiment. Figure 2 This is a block diagram illustrating a display device according to one embodiment.

[0046] Reference Figure 1 and Figure 2 According to one embodiment, the display device 10 is a device for displaying moving or still images. The display device 10 according to one embodiment can be applied to portable electronic devices, such as mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, or ultra-mobile PCs (UMPCs). For example, the display device 10 according to one embodiment can be applied as a display unit in a television, laptop computer, monitor, billboard, or Internet of Things (IoT) terminal. Alternatively, the display device 10 according to one embodiment can be applied to smartwatches, smartwatch phones, and head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0047] According to one embodiment, the display device 10 includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (also referred to herein as a timing controller) 400, and a power supply circuit (also referred to herein as a power supply unit) 500.

[0048] The display panel 100 may have a planar shape similar to a quadrilateral in a planar view. For example, the display panel 100 may have a planar shape similar to a quadrilateral, having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or rounded with a predetermined curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but the embodiments described in this specification are not limited thereto.

[0049] like Figure 2 As shown, the display panel 100 includes a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0050] The display area DAA includes multiple pixels (PX), multiple scan lines (SL), multiple emission control lines (EL), and multiple data lines (DL).

[0051] Multiple pixels (PX) can be arranged in a matrix in the first direction DR1 and the second direction DR2. Multiple scan lines (SL) and multiple emission control lines (EL) can extend in the first direction DR1 and are simultaneously arranged in the second direction DR2. Multiple data lines (DL) can extend in the second direction DR2 and are simultaneously arranged in the first direction DR1.

[0052] The multiple scan lines SL include multiple write scan lines GWL, multiple control scan lines GCL (which may also be referred to as write control lines GCL in this document), and multiple bias scan lines EBL. The multiple emit control lines EL include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0053] The multiple pixels PX include multiple sub-pixels SP1, SP2, and SP3. The multiple sub-pixels SP1, SP2, and SP3 may include, for example... Figure 3 The multiple pixel transistors shown are formed by semiconductor processes and disposed on a semiconductor substrate SSUB (see [reference]). Figure 7 For example, multiple pixel transistors for multiple sub-pixels SP1, SP2, and SP3 can be formed using complementary metal-oxide-semiconductor (CMOS).

[0054] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to any one of the plurality of write scan lines GWL (e.g., one of the plurality of write scan lines GWL), any one of the plurality of control scan lines GCL (e.g., one of the plurality of control scan lines GCL), any one of the plurality of bias scan lines EBL (e.g., one of the plurality of bias scan lines EBL), any one of the plurality of first emission control lines EL1 (e.g., one of the plurality of first emission control lines EL1), any one of the plurality of second emission control lines EL2 (e.g., one of the plurality of second emission control lines EL2), and any one of the plurality of data lines DL (e.g., one of the plurality of data lines DL). Each of the multiple sub-pixels SP1, SP2 and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0055] The non-display area NDA includes a scan driver 610, a transmit driver 620, and a data driver 700.

[0056] The scan driver 610 includes multiple scan transistors, and the emitter driver 620 includes multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor diagram]). Figure 7 For example, multiple scanning transistors and multiple light-emitting transistors can be formed using CMOS. Although Figure 2 The diagram shows a scan driver 610 positioned on the left side of the display area DAA and a transmit driver 620 positioned on the right side of the display area DAA, but embodiments described herein are not limited to this. For example, the scan driver 610 and the transmit driver 620 may be positioned on either the left or right side of the display area DAA.

[0057] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit 400 and output them sequentially to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals (also referred to hereinafter as write control signals) in response to the scan timing control signal SCS and output them sequentially to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS and output them sequentially to the bias scan line EBL.

[0058] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive a transmit timing control signal ECS from the timing control circuit 400. The first transmit control driver 621 can generate a first transmit control signal according to the transmit timing control signal ECS and output them sequentially to a first transmit control line EL1. The second transmit control driver 622 can generate a second transmit control signal according to the transmit timing control signal ECS and output them sequentially to a second transmit control line EL2.

[0059] The data driver 700 may include multiple data transistors, and the multiple data transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [reference]). Figure 7 For example, multiple data transistors can be formed using CMOS.

[0060] The data driver 700 receives digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0061] The heat dissipation layer 200 may overlap the display panel 100 on a third direction DR3 in the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on its rear surface. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer with high thermal conductivity, including metals such as silver (Ag), copper (Cu), or aluminum (Al), and / or a layer including graphite.

[0062] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 (see [reference]) using conductive adhesive components such as anisotropic conductive film. Figure 4 Multiple first pads PD1 (see) Figure 4 Circuit board 300 may be a flexible printed circuit board or a flexible film with a flexible material. Although Figure 1 The circuit board 300 shown is unfolded, but it is flexible. In this case, one end of the circuit board 300 may be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be the first pad portion of the circuit board 300 connected to the display panel 100 by means of conductive adhesive members (see PDA1). Figure 4 Multiple first pads PD1 (see) Figure 4 The opposite end of the other end.

[0063] The timing control circuit 400 can receive digital video data DATA and timing signals input from an external source. In response to the timing signals, the timing control circuit 400 generates a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit 400 can also output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0064] The power supply circuit 500 can generate multiple panel driving voltages based on the external power voltage. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0065] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0066] Alternatively, similar to the scan driver 610, transmit driver 620, and data driver 700, each of the timing control circuit 400 and power supply circuit 500 may be located in the non-display area NDA of the display panel 100. In this case, the timing control circuit 400 may include multiple timing transistors, and the power supply circuit 500 may include multiple power transistors. The multiple timing transistors and multiple power transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to semiconductor panel SSUB]). Figure 7 On the ), for example, multiple sequential transistors and multiple power transistors can be formed by CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be disposed between the data driver 700 and the first pad portion of PDA1 (see Figure 4 ).

[0067] Figure 3 This is an equivalent circuit diagram of the first sub-pixel according to one implementation method.

[0068] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can be connected to a first drive voltage VSS applied corresponding to a low-potential voltage (e.g., see reference...). Figure 2 The first driving voltage line VSL and the second driving voltage VDD corresponding to the high potential voltage are applied (for example, refer to...). Figure 2 The second drive voltage line VDL and the third drive voltage VINT corresponding to the initialization voltage are applied (for example, refer to...). Figure 2The third driving voltage line VIL. That is, the first driving voltage line VSL can be a low-potential voltage line, the second driving voltage line VDL can be a high-potential voltage line, and the third driving voltage line VIL can be the initialization voltage line. In this case, the first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0069] The first sub-pixel SP1 includes multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0070] The light-emitting element LE emits light in response to a drive current Ids flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE is proportional to the drive current Ids. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode. The light-emitting element LE can be an organic light-emitting diode including a first electrode, a second electrode, and an organic light-emitting layer disposed between the first electrode and the second electrode, but the embodiments described herein are not limited to this. For example, the light-emitting element LE can be an inorganic light-emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode; in such a case, the light-emitting element LE can be a micro light-emitting diode.

[0071] The first transistor T1 may be a driving transistor that controls the source-drain current Ids (also referred to herein as drive current Ids) flowing between the source and drain electrodes of the first transistor T1 according to the voltage applied to the gate electrode of the first transistor T1. The first transistor T1 includes a gate electrode connected to a first node N1', a source electrode connected to the drain electrode of a sixth transistor T6, and a drain electrode connected to a second node N2.

[0072] A second transistor T2 may be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor CP1.

[0073] A third transistor T3 may be disposed between the first node N1' and the second node N2. The third transistor T3 is turned on by a write control signal on the write control line GCL to connect the first node N1' to the second node N2. Therefore, since the gate and source electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 includes a gate electrode connected to the write control line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1'.

[0074] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current Ids of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0075] A fifth transistor T5 may be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line EBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0076] A sixth transistor T6 may be disposed between the source electrode of the first transistor T1 and the second drive voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal of the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second drive voltage line VDL. Therefore, a second drive voltage VDD of the second drive voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second drive voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0077] A first capacitor CP1 is formed between the first node N1' and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1'.

[0078] A second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second drive voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second drive voltage line VDL.

[0079] The first node N1' is the node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0080] Each of the first transistors T1 to the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 to the sixth transistor T6 may be a P-type MOSFET, but the embodiments described herein are not limited thereto. Each of the first transistors T1 to the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistors T1 to the sixth transistor T6 may be P-type MOSFETs, and each of the remaining transistors may be an N-type MOSFET.

[0081] although Figure 3 The diagram shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to... Figure 3 As shown in the diagram. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 As shown in the image.

[0082] Furthermore, the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 can be combined with... Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 is omitted in this specification.

[0083] Figure 4 This is a layout diagram showing an example of a display panel according to one embodiment.

[0084] Reference Figure 4 According to one embodiment, the display area DAA of the display panel 100 includes a plurality of pixels PX arranged in a matrix. According to one embodiment, the non-display area NDA of the display panel 100 includes a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0085] The scan driver 610 may be disposed on a first side of the display area DAA, and the transmit driver 620 may be disposed on a second side of the display area DAA. For example, the scan driver 610 may be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 may be disposed on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be disposed on the left side of the display area DAA, and the transmit driver 620 may be disposed on the right side of the display area DAA. However, the embodiments described herein are not limited to this, and the scan driver 610 and the transmit driver 620 may be disposed on either the first side or the second side of the display area DAA.

[0086] The first pad portion PDA1 may include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 via conductive adhesive members. The first pad portion PDA1 may be disposed on the third side of the display area DAA. For example, the first pad portion PDA1 may be disposed on one side of the display area DAA in the second direction DR2.

[0087] The first pad portion of PDA1 can be disposed outside the data driver 700 on the second direction DR2. That is, the first pad portion of PDA1 can be closer to the edge of the display panel 100 than the data driver 700.

[0088] The second pad portion PDA2 may include multiple second pads PD2 corresponding to the inspection pads used to test whether the display panel 100 is operating correctly. The multiple second pads PD2 may be connected to a fixture or probe pins during the inspection process, or may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0089] The first distribution circuit 710 distributes the data voltage applied through the first pad portion of PDA1 to multiple data lines DL (e.g., refer to...). Figure 2 For example, the first distribution circuit 710 can distribute the data voltage applied through a first pad PD1 of the first pad portion PDA1 to P data lines DL (P is a positive integer of 2 or greater), and as a result, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0090] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610, the transmit driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0091] Figure 5 and Figure 6 It is shown Figure 4 A layout diagram illustrating the implementation of the display area.

[0092] Reference Figure 5 and Figure 6 Pixel PX (e.g., refer to Figure 4 Each of the following includes a first emission region EA1 for the emission region of the first sub-pixel SP1, a second emission region EA2 for the emission region of the second sub-pixel SP2, and a third emission region EA3 for the emission region of the third sub-pixel SP3.

[0093] Each of the first launch area EA1, the second launch area EA2, and the third launch area EA3 may have a polygonal, circular, elliptical, or atypical shape in a plan view.

[0094] The maximum length of the first launch region EA1 in the first direction DR1 may be less than each of the maximum lengths of the second launch region EA2 and the third launch region EA3 in the first direction DR1. The maximum lengths of the second launch region EA2 and the third launch region EA3 in the first direction DR1 may be substantially the same.

[0095] The maximum length of the first transmission region EA1 in the second direction DR2 may be greater than each of the maximum lengths of the second transmission region EA2 and the third transmission region EA3 in the second direction DR2. The maximum length of the second transmission region EA2 in the second direction DR2 may be greater than (or less than) the maximum length of the third transmission region EA3 in the second direction DR2. The maximum length of the first transmission region EA1 in the second direction DR2 may be less than the maximum length of the second transmission region EA2 in the second direction DR2.

[0096] like Figure 5 and Figure 6As shown, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape formed by six straight lines in a plan view, but the embodiments described herein are not limited to this. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have polygonal shapes, circular shapes, elliptical shapes, or atypical shapes other than hexagons in a plan view.

[0097] like Figure 5 As shown, in each of the plurality of pixels PX, a first emission region EA1 and a second emission region EA2 may be adjacent to each other in a first direction DR1. Furthermore, the first emission region EA1 and a third emission region EA3 may be adjacent to each other in the first direction DR1. Additionally, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in a second direction DR2. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different.

[0098] Alternatively, such as Figure 6 As shown, the first transmission region EA1 and the second transmission region EA2 may be adjacent to each other in the first direction DR1, but the second transmission region EA2 and the third transmission region EA3 may be adjacent to each other in the first oblique direction DD1, and the first transmission region EA1 and the third transmission region EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be the direction between the first direction DR1 and the second direction DR2, and may refer to the direction inclined at 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be the direction perpendicular to the first oblique direction DD1.

[0099] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. Here, the first color light can be light in the blue wavelength band, the second color light can be light in the green wavelength band, and the third color light can be light in the red wavelength band. For example, the blue wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 370 nm to about 460 nm, the green wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 480 nm to about 560 nm, and the red wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 600 nm to about 750 nm.

[0100] exist Figure 5 and Figure 6 The illustration shows that each of a plurality of pixels PX includes three emission regions EA1, EA2, and EA3, but the embodiments described herein are not limited thereto. That is, each of the plurality of pixels PX may include four emission regions.

[0101] Furthermore, the layout of the emission regions of multiple pixel PXs is not limited to Figure 5 and Figure 6 As shown in the diagram. For example, the emission regions of multiple pixels PX can be configured as a stripe structure in which the emission regions are arranged in a first direction DR1, or in which the emission regions are arranged in a diamond shape. Structure, or such as Figure 6 The diagram shows a hexagonal structure with hexagonal emission regions arranged side by side in a plan view.

[0102] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I1-I1'.

[0103] Reference Figure 7 Display panel 100 (for example, refer to Figure 4 It includes a semiconductor backplane (SBP), an emissive backplane (EBP), an emissive layer (EML), an encapsulation layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizer (POL).

[0104] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating layers covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs), each electrically connected to a corresponding one of the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be referenced. Figure 4 The first transistor T1 to the sixth transistor T6 are described.

[0105] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, when the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0106] Each of the multiple well regions WA includes a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0107] The lower insulating layer (BINS) can be disposed between the gate electrode (GE) and the well region (WA). The side insulating layer (SINS) can be disposed on the side surface of the gate electrode (GE). The side insulating layer (SINS) can be disposed on the lower insulating layer (BINS).

[0108] Each of the source region SA and the drain region DA can be a region doped with a type 1 impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be disposed on one side of the gate electrode GE, and the drain region DA can be disposed on the other side of the gate electrode GE.

[0109] Each of the multiple well regions WA also includes a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region with a lower impurity concentration than the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region with a lower impurity concentration than the drain region DA due to the lower insulating layer BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased. Therefore, the length of the channel region CH in each of the pixel transistors PTR can be increased to prevent punch-through and hot carrier phenomena that may be caused by short channels.

[0110] The first semiconductor insulating layer SINS1 can be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 can be made of silicon carbonitride (SiCN) or silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments described in this specification are not limited to this.

[0111] The second semiconductor insulating layer SINS2 can be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments described in this specification are not limited to this.

[0112] Multiple contact terminals (CTEs) may be disposed on the second semiconductor insulating layer (SINS2). Each of the multiple contact terminals (CTEs) can be connected to any one of the gate electrode (GE), source region (SA), and drain region (DA) of a corresponding pixel transistor (PTR) through a hole penetrating the first semiconductor insulating layer (SINS1) and the second semiconductor insulating layer (SINS2). The multiple contact terminals (CTEs) may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them.

[0113] A third semiconductor insulating layer, SINS3, may be disposed on the side surface of each of the plurality of contact terminals, CTEs. The top surface of each of the plurality of contact terminals, CTEs, may be exposed and not covered by the third semiconductor insulating layer, SINS3. The third semiconductor insulating layer, SINS3, may be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments described in this specification are not limited to this.

[0114] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0115] The backplane (EBP) for the light-emitting element includes multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating layers INS1 to INS9. Furthermore, the first conductive layer ML1 to the eighth conductive layer ML8 in the backplane (EBP) are disposed between the multiple insulating layers INS1 to INS9.

[0116] The first conductive layers ML1 to the eighth conductive layers ML8 are used to connect multiple contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuitry for the first sub-pixel SP1 is shown. For example, first transistors T1 to sixth transistors T6 are formed only in the semiconductor backplane SBP, and first transistors T1 to sixth transistors T6 are connected to the first capacitor CP1 (e.g., see reference). Figure 3 ) and the second capacitor CP2 (for example, refer to Figure 3 The connection is achieved through the first conductive layer ML1 to the eighth conductive layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE is also achieved through the first conductive layer ML1 to the eighth conductive layer ML8.

[0117] A first insulating layer INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating layer INS1 to connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating layer INS1 and may be connected to the first via VA1.

[0118] A second insulating layer INS2 may be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of the second through-hole portions VA2 may penetrate the second insulating layer INS2 and be connected to the exposed first conductive layer ML1. Each of the second conductive layers ML2 may be disposed on the second insulating layer INS2 and may be connected to the second through-hole portion VA2.

[0119] A third insulating layer INS3 may be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of the third through-hole portions VA3 may penetrate the third insulating layer INS3 and be connected to the exposed second conductive layer ML2. Each of the third conductive layers ML3 may be disposed on the third insulating layer INS3 and may be connected to the third through-hole portion VA3.

[0120] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of the fourth through-hole portions VA4 may penetrate the fourth insulating layer INS4 and connect to the exposed third conductive layer ML3. Each of the fourth conductive layers ML4 may be disposed on the fourth insulating layer INS4 and may connect to the fourth through-hole portion VA4.

[0121] A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of the fifth through-hole portions VA5 may penetrate the fifth insulating layer INS5 and connect to the exposed fourth conductive layer ML4. Each of the fifth conductive layers ML5 may be disposed on the fifth insulating layer INS5 and may connect to the fifth through-hole portion VA5.

[0122] A sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of the sixth through-hole portions VA6 may penetrate the sixth insulating layer INS6 and connect to the exposed fifth conductive layer ML5. Each of the sixth conductive layers ML6 may be disposed on the sixth insulating layer INS6 and may connect to the sixth through-hole portion VA6.

[0123] A seventh insulating layer INS7 may be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of the seventh through-hole portions VA7 may penetrate the seventh insulating layer INS7 and connect to the exposed sixth conductive layer ML6. Each of the seventh conductive layers ML7 may be disposed on the seventh insulating layer INS7 and may connect to the seventh through-hole portion VA7.

[0124] An eighth insulating layer INS8 may be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of the eighth through-hole portions VA8 may penetrate the eighth insulating layer INS8 and connect to the exposed seventh conductive layer ML7. Each of the eighth conductive layers ML8 may be disposed on the eighth insulating layer INS8 and may connect to the eighth through-hole portion VA8.

[0125] The first conductive layers ML1 to ML8 and the first through-hole portions VA1 to VA8 may be formed of substantially the same material. The first conductive layers ML1 to ML8 and the first through-hole portions VA1 to VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first through-hole portions VA1 to VA8 may be made of substantially the same material. The first insulating layers INS1 to INS8 may be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments described in this specification are not limited to this.

[0126] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thicknesses of the first through-hole portion VA1, the second through-hole portion VA2, the third through-hole portion VA3, the fourth through-hole portion VA4, the fifth through-hole portion VA5, and the sixth through-hole portion VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be greater than the thickness of the first conductive layer ML1. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 may be substantially the same. For example, the thickness of the first conductive layer ML1 may be approximately... The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately [missing information]. The thickness of each of the first through-hole portion VA1, the second through-hole portion VA2, the third through-hole portion VA3, the fourth through-hole portion VA4, the fifth through-hole portion VA5, and the sixth through-hole portion VA6 can be approximately [missing information].

[0127] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be greater than the thickness of the seventh through-hole portion VA7 and the eighth through-hole portion VA8, respectively. The thickness of each of the seventh through-hole portion VA7 and the eighth through-hole portion VA8 may be greater than the thickness of each of the first through-hole portion VA1, the second through-hole portion VA2, the third through-hole portion VA3, the fourth through-hole portion VA4, the fifth through-hole portion VA5, and the sixth through-hole portion VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 may be approximately... The thickness of each of the seventh through-hole section VA7 and the eighth through-hole section VA8 can be approximately

[0128] The ninth insulating layer INS9 can be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments described in this specification are not limited to this.

[0129] Each of the ninth vias VA9 penetrates the ninth insulating layer INS9 and connects to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. The thickness of the ninth via VA9 can be approximately...

[0130]

[0131] The display element layer (EML) may be disposed on the light-emitting element backplane (EBP). The display element layer (EML) may include light-emitting elements (LEs), each comprising a first electrode AND, a light-emitting stack IL, and a second electrode CAT (e.g., see reference 1). Figure 3 ), reflective electrode layer RL, tenth insulating layer INS10 and eleventh insulating layer INS11, tenth via portion VA10, pixel limiting layer PDL and multiple trenches TRC.

[0132] A reflective electrode layer RL may be disposed on the ninth insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode (e.g., reflective electrodes RL1, RL2, RL3, and RL4). For example, as... Figure 7As shown, the reflective electrode layer RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0133] Each of the first reflective electrodes RL1 may be disposed on the ninth insulating layer INS9 and may be connected to the ninth through-hole VA9. The first reflective electrodes RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or metallic compound comprising any one of them. For example, the first reflective electrode RL1 may comprise titanium nitride (TiN).

[0134] Each of the second reflective electrodes RL2 may be disposed on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy comprising any one of them. For example, the second reflective electrode RL2 may comprise aluminum (Al).

[0135] Each of the third reflective electrodes RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or metallic compound comprising any one of them. For example, the third reflective electrode RL3 may comprise titanium nitride (TiN).

[0136] The fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0137] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the second reflective electrode RL2 can be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately [missing information]. Furthermore, the thickness of the second reflective electrode RL2 can be...

[0138] The tenth insulating layer INS10 can be disposed on the ninth insulating layer INS9. The tenth insulating layer INS10 can be disposed between horizontally adjacent reflective electrode layers RL. The tenth insulating layer INS10 can be disposed on the reflective electrode layer RL in the third sub-pixel SP3. The tenth insulating layer INS10 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments described in this specification are not limited to this.

[0139] The eleventh insulating layer INS11 can be disposed on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 can be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments described in this specification are not limited to this. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be optical auxiliary layers through which light reflected by the reflective electrode layer RL passes in the light emitted from the light-emitting element LE.

[0140] To match the resonant distance of the light emitted by the light-emitting element LE from at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating layer INS10 and the eleventh insulating layer INS11 may not be disposed below the first electrode AND of the first sub-pixel SP1. The first electrode AND of the first sub-pixel SP1 may be disposed directly on the reflective electrode layer RL. The eleventh insulating layer INS11 may be disposed below the first electrode AND of the second sub-pixel SP2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 may be disposed below the first electrode AND of the third sub-pixel SP3.

[0141] In summary, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. That is, in order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the dominant wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 can be set in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in... Figure 7 The specification shows that the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 is greater than each of the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 is greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, but the embodiments described herein are not limited thereto.

[0142] Furthermore, although a tenth insulating layer INS10 and an eleventh insulating layer INS11 are shown in the embodiments described in this specification, a twelfth insulating layer may be added, disposed below the first electrode AND of the first sub-pixel SP1. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer may be disposed below the first electrode AND of the second sub-pixel SP2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer may be disposed below the first electrode AND of the third sub-pixel SP3.

[0143] Each of the tenth vias VA10 can penetrate the tenth insulating layer INS10 and / or the eleventh insulating layer INS11 in the second sub-pixel SP2 or the third sub-pixel SP3, and can be connected to the exposed ninth conductive layer (e.g., the reflective electrode layer RL or the first electrode AND). The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0144] The first electrode AND of each of the light-emitting elements LE may be disposed on the tenth insulating layer INS10 (or the eleventh insulating layer INS11) and connected to the tenth via VA10. The first electrode AND of each of the light-emitting elements LE may be connected to the drain region DA or source region SA of the pixel transistor PTR via the tenth via VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first via VA1 to the ninth via VA9, the first conductive layers ML1 to the eighth conductive layers ML8, and the contact terminal CTE. The first electrode AND of each of the light-emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy or metallic compound comprising any one of them. For example, the first electrode AND of each of the light-emitting elements LE may be titanium nitride (TiN).

[0145] A pixel defining layer (PDL) may be disposed on a portion of the first electrode AND of each of the light-emitting elements (LE). The PDL may cover the edge of the first electrode AND of each of the light-emitting elements (LE). The PDL may be used to separate a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3.

[0146] The first emitting region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emitting region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emitting region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0147] The pixel defining layer (PDL) may include a first pixel defining layer (PDL1), a second pixel defining layer (PDL2), and a third pixel defining layer (PDL3). The first pixel defining layer (PDL1) may be disposed on the edge of the first electrode AND of each of the light-emitting elements (LEs), the second pixel defining layer (PDL2) may be disposed on the first pixel defining layer (PDL1), and the third pixel defining layer (PDL3) may be disposed on the second pixel defining layer (PDL2). The first pixel defining layer (PDL1), the second pixel defining layer (PDL2), and the third pixel defining layer (PDL3) may be made of silicon oxide (SiO2). x The inorganic layer is formed, but the embodiments described in this specification are not limited to this. The first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 may each have approximately [missing information]. The thickness.

[0148] When the first pixel-defining layer PDL1, the second pixel-defining layer PDL2, and the third pixel-defining layer PDL3 form a single pixel-defining layer, the height of this single pixel-defining layer increases so that the first encapsulation inorganic layer TFE1 may be cut due to step coverage. Step coverage refers to the ratio of the degree to which the film is coated on the inclined portion to the degree to which it is coated on the flat portion. The lower the step coverage, the greater the likelihood that the film will be cut at the inclined portion.

[0149] Therefore, to prevent the first encapsulated inorganic layer TFE1 from being cut off due to step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have a cross-sectional structure with stepped portions. For example, the width of the first pixel defining layer PDL1 may be greater than the width of each of the second pixel defining layer PDL2 and the third pixel defining layer PDL3, and the width of the second pixel defining layer PDL2 may be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 refers to the horizontal length of the first pixel defining layer PDL1 defined in the first direction DR1 or the second direction DR2.

[0150] Each of the plurality of trench TRCs is permeable to the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. Furthermore, each of the plurality of trench TRCs is permeable to the eleventh insulating layer INS11. The tenth insulating layer INS10 may be partially recessed at each of the plurality of trench TRCs.

[0151] At least one trench TRC can be provided between adjacent sub-pixels in sub-pixels SP1, SP2, and SP3. Although Figure 7 The illustration shows two trench TRCs positioned between adjacent subpixels in subpixels SP1, SP2, and SP3, but the embodiments described herein are not limited to this.

[0152] The light-emitting stack (IL) may include multiple intermediate layers. Figure 7 The illustration shows a light-emitting stack IL having a three-tiered structure including a first stacked layer IL1, a second stacked layer IL2, and a third stacked layer IL3, but embodiments described in this specification are not limited to this. For example, the light-emitting stack IL may have a two-tiered structure including two intermediate layers.

[0153] In a three-stage cascade structure, the light-emitting stack IL may have a cascade structure comprising multiple stacked layers IL1, IL2, and IL3 that emit different colors of light. For example, the light-emitting stack IL may include a first stacked layer IL1 that emits light of a first color, a second stacked layer IL2 that emits light of a third color, and a third stacked layer IL3 that emits light of a second color. The first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 may be stacked sequentially.

[0154] The first stacked layer IL1 may have a structure in which a first hole transport layer, a first organic light-emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second stacked layer IL2 may have a structure in which a second hole transport layer, a second organic light-emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third stacked layer IL3 may have a structure in which a third hole transport layer, a third organic light-emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0155] A first charge generation layer for supplying charge to the second stacked layer IL2 and electrons to the first stacked layer IL1 may be disposed between the first stacked layer IL1 and the second stacked layer IL2. The first charge generation layer may include an N-type charge generation layer that supplies electrons to the first stacked layer IL1 and a P-type charge generation layer that supplies holes to the second stacked layer IL2. The N-type charge generation layer may include a dopant of a metallic material.

[0156] A second charge generation layer for supplying charge to the third stacked layer IL3 and electrons to the second stacked layer IL2 may be disposed between the second stacked layer IL2 and the third stacked layer IL3. The second charge generation layer may include an N-type charge generation layer that supplies electrons to the second stacked layer IL2 and a P-type charge generation layer that supplies holes to the third stacked layer IL3.

[0157] A first stacked layer IL1 may be disposed on the first electrode AND and the pixel defining layer PDL, and may be disposed on the bottom surface of each trench TRC. Due to the trench TRC, the first stacked layer IL1 may be cut between adjacent sub-pixels among sub-pixels SP1, SP2, and SP3. A second stacked layer IL2 may be disposed on the first stacked layer IL1. Due to the trench TRC, the second stacked layer IL2 may be cut between adjacent sub-pixels among sub-pixels SP1, SP2, and SP3. A cavity ESS or empty space may be provided between the first stacked layer IL1 and the second stacked layer IL2. A third stacked layer IL3 may be disposed on the second stacked layer IL2. The third stacked layer IL3 is not cut by the trench TRC and may be configured to cover the second stacked layer IL2 in each of the trench TRCs. That is, in the three-in-series structure, each of the plurality of trench TRCs may be a structure for cutting the first stacked layer IL1 and the second stacked layer IL2, the first charge generation layer, and the second charge generation layer between adjacent sub-pixels among sub-pixels SP1, SP2, and SP3 of the display element layer EML. Furthermore, in the dual-series structure, each of the trench TRCs can be a structure for cutting off the charge generation layer disposed between the lower intermediate layer and the upper intermediate layer, as well as the lower intermediate layer.

[0158] To stably cut the first stacked layer IL1 and the second stacked layer IL2 between adjacent sub-pixels in sub-pixels SP1, SP2, and SP3 of the display element layer EML, the height of each of the plurality of trench TRCs may be greater than the height of the pixel defining layer PDL. The height of each of the plurality of trench TRCs refers to the length of each of the trench TRCs in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. To cut the first stacked layer IL1, the second stacked layer IL2, and / or the third stacked layer IL3 between adjacent sub-pixels in sub-pixels SP1, SP2, and SP3 of the display element layer EML, an alternative structure may exist to replace the trench TRCs. For example, an inverted conical partition wall may be provided on the pixel defining layer PDL to replace the trench TRCs.

[0159] The number of stacked layers emitting different light is not limited to Figure 7The quantities shown are as described. For example, the light-emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first stack layer IL1, and the other may include a second hole transport layer, a second organic light-emitting layer, a third organic light-emitting layer, and a second electron transport layer. In this case, a charge-generating layer for supplying electrons to one intermediate layer and charging the other intermediate layer may be provided between the two intermediate layers.

[0160] also, Figure 7 The diagram shows that the first stacked layer IL1, the second stacked layer IL2, and the third stacked layer IL3 are all disposed in the first emission region EA1, the second emission region EA2, and the third emission region EA3, but the embodiments described herein are not limited to this. For example, the first stacked layer IL1 may be disposed in the first emission region EA1, and may not be disposed in the second emission region EA2 and the third emission region EA3. Furthermore, the second stacked layer IL2 may be disposed in the second emission region EA2, and may not be disposed in the first emission region EA1 and the third emission region EA3. Furthermore, the third stacked layer IL3 may be disposed in the third emission region EA3, and may not be disposed in the first emission region EA1 and the second emission region EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL can be omitted.

[0161] The second electrode CAT can be disposed on the third stacked layer IL3. The second electrode CAT can be disposed on the third stacked layer IL3 in each of the multiple trench TRCs. The second electrode CAT can be formed of a transparent conductive material (TCO) capable of transmitting light, such as ITO or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be improved due to the microcavity effect.

[0162] A TFE (Transmission overlay) layer may be disposed on the display element layer (EML). The TFE layer may include at least one inorganic layer (e.g., encapsulated inorganic layers TFE1 and TFE2) to prevent oxygen or moisture from penetrating into the EML layer. For example, the TFE layer may include a first encapsulated inorganic layer TFE1 and a second encapsulated inorganic layer TFE2.

[0163] The first encapsulation inorganic layer TFE1 can be disposed on the second electrode CAT. The first encapsulation inorganic layer TFE1 can be formed in which silicon nitride (SiN) is selected. x ), silicon oxynitride (SiON) and silicon oxide (SiO) xA multilayer structure consisting of one or more inorganic layers stacked alternately. The first encapsulation inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0164] The second encapsulation inorganic layer TFE2 can be disposed on the first encapsulation inorganic layer TFE1. The second encapsulation inorganic layer TFE2 can be made of titanium oxide (TiO2). x ) or aluminum oxide (AlO) x The second encapsulation inorganic layer TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic layer TFE2 can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0165] The organic layer APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the optical layer OPL. The organic layer APL can be an organic layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0166] The optical layer OPL includes multiple color filters CF1, CF2, and CF3, multiple lenses LNS, and a filler layer FIL. The multiple color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be disposed on an adhesive layer (e.g., an organic layer APL).

[0167] The first color filter CF1 may overlap with the first emission region EA1 of the first sub-pixel SP1. The first color filter CF1 can transmit light of a first color, namely light in the blue wavelength band. The blue wavelength band may be approximately 370nm to 460nm. Therefore, the first color filter CF1 can transmit light of the first color emitted from the first emission region EA1.

[0168] The second color filter CF2 may overlap with the second emission region EA2 of the second sub-pixel SP2. The second color filter CF2 can transmit light of a second color, namely light in the green wavelength band. The green wavelength band may be approximately 480nm to 560nm. Therefore, the second color filter CF2 can transmit light of the second color emitted from the second emission region EA2.

[0169] The third color filter CF3 can overlap with the third emission region EA3 of the third sub-pixel SP3. The third color filter CF3 can transmit light of the third color, namely light in the red wavelength band. The red wavelength band can be approximately 600nm to 750nm. Therefore, the third color filter CF3 can transmit light of the third color emitted from the third emission region EA3.

[0170] Multiple lenses LNS can be respectively disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the multiple lenses LNS can be used to increase the guiding display device 10 (e.g., see reference). Figure 1 The structure of the ratio of light at the front of the lens. Each of the multiple lenses LNS may have a profile shape that is convex in the upward direction.

[0171] A filler layer (FIL) can be disposed on multiple lens lenses (LNS). The filler layer (FIL) can have a predetermined refractive index such that light travels in the third direction (DR3) at the interface between the filler layer (FIL) and the multiple lens lenses (LNS). Furthermore, the filler layer (FIL) can be a planarization layer. The filler layer (FIL) can be an organic layer including acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0172] A cover layer CVL can be disposed on a filler layer FIL. The cover layer CVL can be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, it can be attached to the filler layer FIL. In this case, the filler layer FIL can be used to bond the cover layer CVL. When the cover layer CVL is a glass substrate, it can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin, it can be directly applied to the filler layer FIL.

[0173] A polarizing plate (POL) may be disposed on one surface of the CVL (container layer). The polarizing plate (POL) may be a structure used to prevent visibility degradation caused by reflection of external light. The polarizing plate (POL) may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a λ / 4 plate (quarter-wave plate), but embodiments described herein are not limited to this. However, the polarizing plate (POL) may be omitted when the visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3.

[0174] Figure 8 This is a perspective view showing a head-mounted display according to one embodiment. Figure 9 It is shown Figure 8 An exploded perspective view of an example of a head-mounted display.

[0175] Reference Figure 8 and Figure 9 According to one embodiment, a head-mounted display 1000 includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0176] The first display device 10_1 provides an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 and Figure 2 The display devices 10 described are substantially the same, so the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0177] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210 (e.g., in the Z-axis direction). The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220 (e.g., in the Z-axis direction). Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0178] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600, and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0179] A control circuit board 1600 may be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data (DATA, e.g., see reference). Figure 2 ), and transmits digital video data DATA to the first display device 10_1 and the second display device 10_2 via a connector.

[0180] The control circuit board 1600 can send digital video data DATA corresponding to a left-eye image optimized for the user's left eye to a first display device 10_1, and can send digital video data DATA corresponding to a right-eye image optimized for the user's right eye to a second display device 10_2. Alternatively, the control circuit board 1600 can send the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0181] The display device housing 1100 is used to house a first display device 10_1, a second display device 10_2, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600. A housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are shown to be separately configured (e.g., in the X-axis direction perpendicular to the Z-axis and Y-axis directions), but the embodiments described herein are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one.

[0182] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and

[0183] The second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0184] The headband 1300 is used to secure the display device housing 1100 to the user's head, so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively positioned on the user's left and right eyes. When the display device housing 1100 is made lightweight and compact, such as... Figure 10 As shown, the head-mounted display 1000 may be provided with an eyeglass frame instead of a head-mounted strap 1300.

[0185] In addition, the head-mounted display 1000 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0186] Figure 10 This is a perspective view showing a head-mounted display according to one embodiment.

[0187] Reference Figure 10 According to one embodiment, the head-mounted display 1000_1 may be an eyeglass-type display device in which the display device housing 1200_1 is implemented in a lightweight and compact manner. According to one embodiment, the head-mounted display 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path changing component 1070, and a display device housing 1200_1.

[0188] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the optical path changing component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after its optical path is changed by the optical path changing component 1070, can be provided to the user's right eye through the right eye lens 1020. As a result, the user can view an augmented reality image, which is a combination of the virtual image displayed on the display device 10_3 and the real image seen through the right eye lens 1020, through their right eye.

[0189] Figure 10 The display device housing 1200_1 is shown positioned at the right end of the support frame 1030, but the embodiments described herein are not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, and in this case, the image displayed on the display device 10_3 may be provided to the user's left eye. Alternatively, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, and in this case, the user may view the image displayed on the display device 10_3 through both the left and right eyes.

[0190] Figure 11 This schematically illustrates a display panel according to one embodiment (e.g., see reference 1). Figure 4 A diagram showing the arrangement of pixels in the display panel 100.

[0191] Table 1 schematically illustrates the pixel arrangement of a display panel 100 according to one embodiment. For example, Table 1 shows the arrangement of normal pixels (NP) and interpolated pixels included in a single pixel group.

[0192] Table 1

[0193]

[0194] Refer to Table 1 and Figure 11 In a display panel 100 according to one embodiment, a normal pixel NP and a plurality of interpolated pixels surrounding the normal pixel NP form a pixel group PG. A normal pixel NP includes a driving transistor DR and a normal light-emitting element (e.g., a light source) that receives a driving current (e.g., current I1) through a first node N1 connected to the drain electrode of the driving transistor DR. Figure 11 Normal light-emitting elements LE1, LE3, LE7, and LE9). Normal light-emitting elements (e.g., Figure 11 The normal light-emitting elements LE1, LE3, LE7, and LE9 may include normal emission patterns (e.g., Figure 13 (The normal emission patterns EP1, EP3, EP7 and EP9). In this disclosure, a normal emission pattern refers to the area in which a normal light-emitting element emits light, and may be referred to as a "normal emission region".

[0195] Each of the plurality of interpolated pixels IP1 to IP8 includes a first interpolated light-emitting element (e.g., a portion that receives a first drive current from a first normal pixel). Figure 11 The interpolated light-emitting element LE21 in the middle and the second interpolated light-emitting element (e.g., the portion that receives the second driving current from the second normal pixel) are interpolated light-emitting elements. Figure 11 (The interpolated light-emitting element LE22 in the plurality of interpolated pixels IP1 to IP8). For each of the plurality of interpolated pixels IP1 to IP8, the first normal pixel may mean a normal pixel NP located in one direction. For each of the plurality of interpolated pixels IP1 to IP8, the second normal pixel may mean a normal pixel NP located in another direction.

[0196] The first interpolated emission pattern of the first interpolated light-emitting element is configured to be adjacent to the second normal pixel, and the second interpolated emission pattern of the second interpolated light-emitting element is configured to be adjacent to the first normal pixel. In this disclosure, the interpolated emission pattern refers to the area in which the interpolated light-emitting element emits light, and may be referred to as the "interpolated emission region".

[0197] Referring to Table 1, a pixel group includes a normal pixel NP located at the center of the pixel group, and a pixel PD1 located in a first planar direction starting from the normal pixel NP (e.g., referring to Table 1). Figure 11 The first interpolated pixel IP1 on the plane (e.g., the left side in Table 1), and the second plane direction PD2 set from the normal pixel NP in the opposite direction to the first plane direction PD1 (e.g., refer to...) Figure 11 The second interpolated pixel IP2 on the normal pixel NP (e.g., the right side in Table 1), and the third plane direction PD3 set from the normal pixel NP perpendicular to the first plane direction PD1 (e.g., refer to...) Figure 11 The third interpolated pixel IP3 on the plane (e.g., the top in Table 1), and the fourth plane direction PD4 set from the normal pixel NP in the opposite direction to the third plane direction PD3 (e.g., refer to...). Figure 11 The fourth interpolated pixel IP4 on the surface (e.g., at the bottom of Table 1), and the first diagonal direction PD5 set between the first planar direction PD1 and the third planar direction PD3 starting from the normal pixel NP (e.g., refer to...). Figure 11 The fifth interpolated pixel IP5 on the upper left (e.g., the upper left diagonal in Table 1), and the second diagonal direction PD6 set between the second plane direction PD2 and the third plane direction PD3 starting from the normal pixel NP (e.g., refer to...). Figure 11 The sixth interpolated pixel IP6 on the upper right (e.g., the upper right diagonal in Table 1), and the third diagonal direction PD7 set from the normal pixel NP in the opposite direction to the second diagonal direction PD6 (e.g., refer to...). Figure 11The seventh interpolated pixel IP7 on the upper (e.g., the lower left diagonal in Table 1) and the fourth diagonal direction PD8 set from the normal pixel NP in the opposite direction to the first diagonal direction PD5 (e.g., refer to...) Figure 11 The eighth interpolated pixel IP8 on the upper right (e.g., the lower right corner in Table 1).

[0198] Figure 11 The diagram shows normal pixels 1711, 1713, 1717, and 1719, and interpolated pixels 1712, 1714, 1716, and 1718, surrounding the sixth interpolated pixel IP6 (i.e., INT(M+1,N+1)) in row N+1 and column M+1.

[0199] exist Figure 11 In the above, 1711 is a normal pixel NP (i.e., NOR(M,N)) located on the first diagonal direction PD5 starting from the sixth interpolated pixel IP6 and provided with a normal light-emitting element LE1 in the Nth row and Mth column.

[0200] exist Figure 11 In the middle, 1712 is the first interpolated pixel IP1 (i.e., INT(M+1,N)) located on the third plane direction PD3 starting from the sixth interpolated pixel IP6 and provided with interpolated light-emitting elements LE21 and LE22 in the Nth row and M+1th column.

[0201] exist Figure 11 In the middle, 1713 is the normal pixel NP (i.e., NOR(M+2,N)) located on the second diagonal direction PD6 starting from the sixth interpolated pixel IP6 and provided with normal light-emitting element LE3 in the Nth row and M+2th column.

[0202] exist Figure 11 In the middle, 1714 is the third interpolated pixel IP3 (i.e., INT(M,N+1)) located on the first planar direction PD1 starting from the sixth interpolated pixel IP6 and provided with interpolated light-emitting elements LE41 and LE42 in the N+1th row and Mth column.

[0203] exist Figure 11 In the middle, 1716 is the third interpolated pixel IP3 (i.e., INT(M+2,N+1)) located on the second planar direction PD2 starting from the sixth interpolated pixel IP6 and provided with interpolated light-emitting elements LE61 and LE62 in the N+1th row and M+2th column.

[0204] exist Figure 11 In the middle, 1717 is the normal pixel NP (i.e., NOR(M,N+2)) located on the third diagonal direction PD7 starting from the sixth interpolated pixel IP6 and provided with a normal light-emitting element LE7 in the N+2th row and Mth column.

[0205] exist Figure 11 In the middle, 1718 is the second interpolated pixel IP2 (i.e., INT(M+1,N+2)) located in the N+2th row and M+1th column of the fourth plane direction PD4 starting from the sixth interpolated pixel IP6 and provided with interpolated light-emitting elements LE81 and LE82.

[0206] exist Figure 11 In the diagram, 1719 is a normal pixel NP (i.e., NOR(M+2,N+2)) located on the fourth diagonal direction PD8 starting from the sixth interpolated pixel IP6 and equipped with a normal light-emitting element LE9 in the N+2th row and M+2th column. Figure 11 In the diagram, row N, row N+1, and row N+2 correspond to rows R1, R2, and R3, respectively. Furthermore, columns M, M+1, and M+2 correspond to columns C1, C2, and C3, respectively.

[0207] Refer to Table 1 and Figure 11 A normal pixel NP can supply drive current to eight interpolated pixels IP1 to IP8 located around it. For example, normal pixel 1711 can supply drive current (e.g., currents I2, I3, and I4, etc.) to the interpolated pixels (i.e., INS) 1722, 1723, 1714, 1715, 1712, 1721, 1720, and 1719 located around it. Similarly, normal pixel 1713 can supply drive current to the interpolated pixels 1712, 1715, and 1716, etc. located around it.

[0208] According to one implementation, the first interpolated pixel IP1 to the eighth interpolated pixel IP8 belonging to a pixel group can be divided into two groups as follows.

[0209] First, the first group includes interpolated pixels IP1 to IP4 positioned around the normal pixel NP (e.g., normal pixel 1711) to the left, right, above, and below the normal pixel NP, respectively. For example, the first group includes the first interpolated pixels IP1 to the fourth interpolated pixels IP4 positioned in a first planar direction PD1 to a fourth planar direction PD4 starting from the normal pixel NP. Furthermore, the second group includes interpolated pixels IP5 to IP8 positioned around the normal pixel NP in four diagonal directions. For example, the second group includes the fifth interpolated pixels IP5 to the eighth interpolated pixels IP8 positioned in a first diagonal direction PD5 to a fourth diagonal direction PD8 starting from the normal pixel NP.

[0210] Each of the first interpolated pixels IP1 to the fourth interpolated pixels IP4 belonging to the first group includes a pair of interpolated light-emitting elements (e.g., interpolated light-emitting elements LE21 and LE22) that receive a first driving current from a first normal pixel (e.g., normal pixel 1711) and a second driving current from a second normal pixel (e.g., normal pixel 1713). For example, an interpolated pixel 1712 located between normal pixel 1711 and normal pixel 1713 may include interpolated light-emitting elements LE21 and LE22 that receive driving current from both normal pixel 1711 and normal pixel 1713 and emit light according to the received driving current.

[0211] Each of the fifth through eighth interpolated pixels in the second group includes two pairs of interpolated light-emitting elements (e.g., interpolated light-emitting elements LE51, LE52, LE53, and LE54) that receive a first driving current from a first normal pixel (e.g., normal pixel 1711), a second driving current from a second normal pixel (e.g., normal pixel 1713), a third driving current from a third normal pixel (e.g., normal pixel 1717), and a fourth driving current from a fourth normal pixel (e.g., normal pixel 1719). For example, Figure 11 The sixth interpolated pixel IP6 shown may include interpolated light-emitting elements LE51, LE52, LE53 and LE54 that receive drive current from each of the normal pixels 1711, 1713, 1717 and 1719 and emit light according to the received drive current.

[0212] Figure 12 This is a layout diagram showing the emission pattern of pixels according to a comparative example.

[0213] Reference Figure 12 The pixels in the comparative example may include the following light-emitting elements and emission patterns.

[0214] Normal pixel 1711 includes a normal light-emitting element LE1 containing a normal emission pattern EP1. The normal emission pattern EP1 is connected to the interpolation emission patterns of interpolated pixels 1712, 1714, and 1715, etc.

[0215] Interpolated pixel 1712 includes interpolated light-emitting elements LE21 and LE22, which respectively include interpolated emission patterns EP21 and EP22. Interpolated emission pattern EP21 is connected to normal emission pattern EP1, and interpolated emission pattern EP22 is connected to normal emission pattern EP3 of normal pixel 1713.

[0216] Normal pixel 1713 includes a normal light-emitting element LE3 containing a normal emission pattern EP3. The normal emission pattern EP3 is connected to the interpolation emission patterns of interpolated pixels 1712, 1715, and 1716, etc.

[0217] Interpolated pixel 1714 includes interpolated light-emitting elements LE41 and LE42, and they respectively include interpolated emission patterns EP41 and EP42. Interpolated emission pattern EP41 is connected to normal emission pattern EP1, and interpolated emission pattern EP42 is connected to normal emission pattern EP7 of normal pixel 1717.

[0218] Interpolated pixel 1715 includes interpolated light-emitting elements LE51, LE52, LE53, and LE54, and they respectively include interpolated emission patterns EP51, EP52, EP53, and EP54. Interpolated emission pattern EP51 is connected to normal emission pattern EP1, interpolated emission pattern EP52 is connected to normal emission pattern EP3 of normal pixel 1713, interpolated emission pattern EP53 is connected to normal emission pattern EP7 of normal pixel 1717, and interpolated emission pattern EP54 is connected to normal emission pattern EP9 of normal pixel 1719.

[0219] Interpolated pixel 1716 includes interpolated light-emitting elements LE61 and LE62, and they respectively include interpolated emission patterns EP61 and EP62. Interpolated emission pattern EP61 is connected to normal emission pattern EP3, and interpolated emission pattern EP62 is connected to normal emission pattern EP9 of normal pixel 1719.

[0220] Normal pixel 1717 includes a normal light-emitting element LE7 containing a normal emission pattern EP7. The normal emission pattern EP7 is connected to the interpolation emission patterns of interpolated pixels 1714, 1715, and 1718, etc.

[0221] Interpolated pixel 1718 includes interpolated light-emitting elements LE81 and LE82, and they each include interpolated emission patterns EP81 and EP82. Interpolated emission pattern EP81 is connected to normal emission pattern EP7, and interpolated emission pattern EP82 is connected to normal emission pattern EP9 of normal pixel 1719.

[0222] Normal pixel 1719 includes a normal light-emitting element LE9 containing a normal emission pattern EP9. The normal emission pattern EP9 is connected to the interpolation emission patterns of interpolated pixels 1715, 1716, and 1718, etc.

[0223] In the emission patterns of the pixels according to the comparative example, the first normal emission pattern (e.g., normal emission pattern EP1) of the normal pixel NP that provides the first drive current and the first interpolated emission pattern (e.g., interpolated emission pattern EP21) that receives the first drive current are positioned adjacent to each other. For example, the normal light-emitting element LE1 of the normal pixel 1711 supplies drive current to the interpolated light-emitting element LE21 of the interpolated pixel 1712. The interpolated emission pattern EP21 of the interpolated light-emitting element LE21 is arranged adjacent to the normal emission pattern EP1 of the normal light-emitting element LE1. Since the interpolated emission pattern EP21 and the normal emission pattern EP1 have the same brightness of light emitted per unit area, the interpolated emission pattern EP21 and the normal emission pattern EP1 are substantially indistinguishable from each other to the user. In this way, since the normal emission pattern EP1 and the interpolated emission patterns EP41, EP51 and EP21 around it are arranged adjacent to each other, the user may regard the corresponding emission patterns as essentially a region 1801, which means that the up-scaling efficiency is low.

[0224] In the comparative example, similar to the above description, although normal pixel 1713 provides drive current to interpolated pixels 1712, 1715, and 1716 located around it, the user may perceive the corresponding emission pattern essentially as a region 1802. Furthermore, although normal pixel 1717 provides drive current to interpolated pixels 1714, 1715, and 1718 located around it, the user may perceive the corresponding emission pattern essentially as a region 1803. Moreover, although normal pixel 1719 provides drive current to interpolated pixels 1715, 1716, and 1718 located around it, the user may perceive the corresponding emission pattern essentially as a region 1804.

[0225] According to one embodiment of this disclosure, up-scaling efficiency can be improved by optimizing the position of the interpolated emission pattern.

[0226] Figure 13 This is a layout diagram showing the emission pattern of pixels according to one embodiment.

[0227] and Figure 12 The differences in the comparative examples shown are in Figure 13In one embodiment shown, the first normal emission pattern of the normal pixel NP (e.g., refer to Table 1) that provides the first drive current and the first interpolation emission pattern that receives the first drive current are not arranged adjacent to each other. For example, the normal light-emitting element LE1 of normal pixel 1711 supplies drive current to the interpolation light-emitting element LE22 of interpolation pixel 1712. The interpolation emission pattern EP22 of interpolation light-emitting element LE22 is not arranged adjacent to the normal emission pattern EP1 of normal light-emitting element LE1, but is arranged adjacent to the normal emission pattern EP3 of normal light-emitting element LE3. Instead, in interpolation pixel 1712, the interpolation emission pattern EP21 connected to normal light-emitting element LE3 is arranged adjacent to the normal emission pattern EP1 of normal light-emitting element LE1. According to embodiments of this disclosure, during up-scaling operation, the boundary between normal pixels and interpolated pixels becomes clear, thereby enabling the user to view an up-scaled high-resolution image.

[0228] The rules for arranging the emission pattern according to one embodiment will be described in more detail below.

[0229] Each of the plurality of interpolated pixels IP1 to IP8 (e.g., refer to Table 1) includes a first interpolated light-emitting element (e.g., interpolated light-emitting element LE22) that receives a first driving current from a first normal pixel (e.g., normal pixel 1711) and a second interpolated light-emitting element (e.g., interpolated light-emitting element LE21) that receives a second driving current from a second normal pixel (e.g., normal pixel 1713). A first interpolated emission pattern (e.g., interpolated emission pattern EP22) of the first interpolated light-emitting element (e.g., interpolated light-emitting element LE22) is configured to be adjacent to the second normal pixel (e.g., normal pixel 1713), and a second interpolated emission pattern (e.g., interpolated emission pattern EP21) of the second interpolated light-emitting element (e.g., interpolated light-emitting element LE21) is configured to be adjacent to the first normal pixel (e.g., normal pixel 1711).

[0230] The first normal pixel (e.g., normal pixel 1711) includes a first normal light-emitting element (e.g., normal light-emitting element LE1), and the second normal pixel (e.g., normal pixel 1713) includes a second normal light-emitting element (e.g., normal light-emitting element LE3). A second interpolated emission pattern (e.g., interpolated emission pattern EP21) is disposed between the first normal emission pattern (e.g., normal emission pattern EP1) and the first interpolated emission pattern (e.g., interpolated emission pattern EP22) of the first normal light-emitting element (e.g., normal light-emitting element LE1), and the first interpolated emission pattern (e.g., interpolated emission pattern EP22) is disposed between the second normal emission pattern (e.g., normal emission pattern EP3) and the second interpolated emission pattern (e.g., interpolated emission pattern EP21) of the second normal light-emitting element (e.g., normal light-emitting element LE3). For example, as... Figure 13 As shown, the interpolated emission pattern EP21 is disposed between the normal emission pattern EP1 and the interpolated emission pattern EP22 connected to the normal emission pattern EP1. Furthermore, the interpolated emission pattern EP22 is disposed between the normal emission pattern EP3 and the interpolated emission pattern EP21 connected to the normal emission pattern EP3.

[0231] The first interpolated pixel IP1 and the second interpolated pixel IP2 respectively receive driving current from normal pixels NP disposed on the first planar direction PD1 and the second planar direction PD2 of the first interpolated pixel IP1 and the second interpolated pixel IP2 (for example, the first interpolated pixel IP1 and the second interpolated pixel IP2 each receive driving current from normal pixels NP disposed on the first planar direction PD1 and the second planar direction PD2 of a corresponding one of the first interpolated pixel IP1 and the second interpolated pixel IP2). For each of the first interpolated pixel IP1 and the second interpolated pixel IP2, the first normal pixel is a pixel disposed on the first planar direction PD1 starting from the corresponding one of the first interpolated pixel IP1 and the second interpolated pixel IP2, and the second normal pixel is a pixel disposed on the second planar direction PD2 starting from the corresponding one of the first interpolated pixel IP1 and the second interpolated pixel IP2.

[0232] The third interpolation pixel IP3 and the fourth interpolation pixel IP4 receive driving current from normal pixels NP disposed on the third plane direction PD3 and the fourth plane direction PD4 of the third interpolation pixel IP3 and the fourth interpolation pixel IP4, respectively (e.g., the third interpolation pixel IP3 and the fourth interpolation pixel IP4 each receive driving current from normal pixels NP disposed on the third plane direction PD3 and the fourth plane direction PD4 of a corresponding one of the third interpolation pixels IP3 and the fourth interpolation pixel IP4). For each of the third interpolation pixel IP3 and the fourth interpolation pixel IP4, the first normal pixel is a pixel disposed on the third plane direction PD3 starting from the corresponding one of the third interpolation pixel IP3 and the fourth interpolation pixel IP4, and the second normal pixel is a pixel disposed on the fourth plane direction PD4 starting from the corresponding one of the third interpolation pixel IP3 and the fourth interpolation pixel IP4. For example, as... Figure 13 As shown, the interpolated emission pattern EP41 is disposed between the normal emission pattern EP1 and the interpolated emission pattern EP42 connected to the normal emission pattern EP1. Furthermore, the interpolated emission pattern EP42 is disposed between the normal emission pattern EP7 and the interpolated emission pattern EP41 connected to the normal emission pattern EP7.

[0233] The fifth interpolation pixel IP5 to the eighth interpolation pixel IP8 respectively receive driving current from the normal pixel NP disposed on the first diagonal direction PD5 to the fourth diagonal direction PD8 of the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8 (for example, the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8 each receive driving current from the normal pixel NP disposed on the first diagonal direction PD5 to the fourth diagonal direction PD8 of the corresponding one of the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8).

[0234] The fifth interpolated pixel IP5 to the eighth interpolated pixel IP8 also include a third interpolated light-emitting element that receives a third driving current from the third normal pixel and a fourth interpolated light-emitting element that receives a fourth driving current from the fourth normal pixel.

[0235] The third normal pixel includes a third normal light-emitting element, the fourth normal pixel includes a fourth normal light-emitting element, the third interpolation emission pattern of the third interpolated light-emitting element is set to be adjacent to the third normal pixel, and the fourth interpolation emission pattern of the fourth interpolated light-emitting element is set to be adjacent to the fourth normal pixel.

[0236] However, the settings of the third and fourth interpolation emission patterns can be as follows: Figure 16 and Figure 17 Changes in the middle. For example, as will be discussed later. Figure 16 and Figure 17As described above, the third interpolation emission pattern of the third interpolated light-emitting element can be set to be adjacent to the fourth normal pixel, and the fourth interpolation emission pattern of the fourth interpolated light-emitting element can be set to be adjacent to the third normal pixel.

[0237] For each of the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8, the first normal pixel is a pixel set on the first diagonal direction PD5, which is the corresponding starting point of the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8.

[0238] For each of the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8, the second normal pixel is a pixel set on the second diagonal direction PD6 starting from the corresponding one of the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8.

[0239] For each of the fifth interpolation pixels IP5 to the eighth interpolation pixels IP8, the third normal pixel is a pixel set on the third diagonal direction PD7 starting from the corresponding first one of the fifth interpolation pixels IP5 to the eighth interpolation pixels IP8.

[0240] For each of the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8, the fourth normal pixel is a pixel set on the fourth diagonal direction PD8 starting from the corresponding first one of the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8.

[0241] In the fifth interpolated pixels IP5 to the eighth interpolated pixels IP8, the first to fourth interpolated emission patterns provided therein are arranged in a 2×2 matrix. For example, as Figure 13 As shown, interpolated pixel 1715 may include interpolated emission pattern EP51 adjacent to normal emission pattern EP1, interpolated emission pattern EP52 adjacent to normal emission pattern EP3, interpolated emission pattern EP53 adjacent to normal emission pattern EP7, and interpolated emission pattern EP54 adjacent to normal emission pattern EP9. In the fifth to eighth interpolated pixels IP5 to IP8, the arrangement of the first to fourth interpolated emission patterns is not limited to the example shown and can be changed or modified in various ways to improve up-scaling efficiency as explained in this disclosure.

[0242] Figure 14 This is a layout diagram showing the emission pattern of pixels according to one embodiment.

[0243] Figure 14 Implementation methods and Figure 13The difference in the implementation is that each normal pixel NP (e.g., refer to Table 1) includes four normal emission patterns (e.g., normal emission patterns EP11, EP12, EP13 and EP14), and each interpolated pixel includes four interpolated emission patterns (e.g., interpolated emission patterns EP21, EP22, EP23 and EP24).

[0244] According to one embodiment, in the third interpolated pixel IP3 (e.g., refer to Table 1) and the fourth interpolated pixel IP4 (e.g., refer to Table 1), a pair of third sub-interpolated emission patterns (e.g., interpolated emission patterns EP43 and EP44) and a pair of fourth sub-interpolated emission patterns (e.g., interpolated emission patterns EP41 and EP42) are arranged in a 2×2 matrix.

[0245] According to one embodiment, in the first interpolated pixel IP1 (e.g., refer to Table 1) and the second interpolated pixel IP2 (e.g., refer to Table 1), the first interpolated emission pattern includes a pair of first sub-interpolated emission patterns (e.g., interpolated emission patterns EP22 and EP24) separated from each other, and the second interpolated emission pattern includes a pair of second sub-interpolated emission patterns (e.g., interpolated emission patterns EP21 and EP23) separated from each other. In the first interpolated pixel IP1 and the second interpolated pixel IP2, the pair of first sub-interpolated emission patterns (e.g., interpolated emission patterns EP22 and EP24) and the pair of second sub-interpolated emission patterns (e.g., interpolated emission patterns EP21 and EP23) are arranged in a 2×2 matrix. For example, normal pixel 1711 includes four normal light-emitting elements LE11, LE12, LE13 and LE14, and they include normal emission patterns EP11, EP12, EP13 and EP14 that are separated from each other. Furthermore, the first interpolated pixels IP1 to the fourth interpolated pixels IP4, located in the first planar direction PD1 to the fourth planar direction PD4 starting from the normal pixel NP, have four interpolated light-emitting elements and four interpolated emission patterns. For example, interpolated pixel 1712 includes interpolated light-emitting elements LE21, LE22, LE23 and LE24, and they include interpolated emission patterns EP21, EP22, EP23 and EP24 that are distinct from each other.

[0246] Figure 15 This is a layout diagram showing the emission pattern of pixels according to one embodiment.

[0247] Figure 15 Implementation methods and Figure 13 The difference in the implementation method lies in the change in the arrangement of the interpolation emission patterns provided in the first interpolation pixel IP1 to the fourth interpolation pixel IP4.

[0248] exist Figure 13In one implementation, the first interpolation emission pattern and the second interpolation emission pattern provided in the first interpolation pixel IP1 and the second interpolation pixel IP2 are arranged in the form of a 1×2 matrix. For example, in Figure 13 In the interpolated pixels 1712, the interpolated emission patterns EP21 and EP22 are set in a 1×2 matrix. Figure 15 In one implementation, the arrangement of the first interpolation emission pattern and the second interpolation emission pattern provided in the first interpolation pixel IP1 and the second interpolation pixel IP2 can be in the form of a 2×1 matrix. For example, in Figure 15 In the interpolated pixel 1712, the interpolated emission pattern is set in a 2×1 matrix.

[0249] also, Figure 13 The embodiment shows that the third interpolation emission pattern and the fourth interpolation emission pattern provided in the third interpolation pixel IP3 and the fourth interpolation pixel IP4 are arranged in the form of a 2×1 matrix. For example, in Figure 13 In the interpolated pixel 1714, the interpolated emission patterns EP41 and EP42 are arranged in a 2×1 matrix. Figure 15 In some embodiments, the third interpolation emission pattern and the fourth interpolation emission pattern provided in the third interpolation pixel IP3 and the fourth interpolation pixel IP4 can be arranged in the form of a 1×2 matrix. For example, in Figure 15 In the interpolated pixel 1714, the interpolated emission patterns EP41 and EP42 are set in a 1×2 matrix.

[0250] Figure 16 This is a layout diagram showing the emission pattern of pixels according to one embodiment.

[0251] Figure 16 Implementation methods and Figure 15 The difference in the implementation method lies in the change in the arrangement of the interpolation emission patterns provided in the fifth interpolation pixel IP5 to the eighth interpolation pixel IP8.

[0252] exist Figure 15 In this implementation, each of the fifth interpolated pixel IP5 to the eighth interpolated pixel IP8 includes a first interpolated emission pattern to a fourth interpolated emission pattern, and the first interpolated emission pattern to the fourth interpolated emission pattern are configured to be adjacent to the normal pixel NP that supplies the drive current. For example, as Figure 15 As shown, interpolated pixel 1715 includes interpolated emission patterns EP51, EP52, EP53, and EP54. Figure 15In this embodiment, interpolated emission pattern EP51 is connected to normal emission pattern EP1 and is positioned adjacent to normal emission pattern EP1. Furthermore, interpolated emission pattern EP52 is connected to normal emission pattern EP3 and is positioned adjacent to normal emission pattern EP3. Additionally, interpolated emission pattern EP53 is connected to normal emission pattern EP7 and is positioned adjacent to normal emission pattern EP7. Furthermore, interpolated emission pattern EP54 is connected to normal emission pattern EP9 and is positioned adjacent to normal emission pattern EP9.

[0253] On the other hand, according to Figure 16 In this implementation, interpolated transmission pattern EP51 is connected to normal transmission pattern EP7 and is positioned adjacent to normal transmission pattern EP1. Furthermore, interpolated transmission pattern EP52 is connected to normal transmission pattern EP9 and is positioned adjacent to normal transmission pattern EP3. Additionally, interpolated transmission pattern EP53 is connected to normal transmission pattern EP1 and is positioned adjacent to normal transmission pattern EP7. Furthermore, interpolated transmission pattern EP54 is connected to normal transmission pattern EP3 and is positioned adjacent to normal transmission pattern EP9.

[0254] Figure 17 This is a layout diagram showing the emission pattern of pixels according to one embodiment.

[0255] Figure 17 Implementation methods and Figure 16 The difference in the implementation method lies in the change in the arrangement of the interpolation emission patterns provided in the first interpolation pixel IP1 to the fourth interpolation pixel IP4.

[0256] Reference Figure 17 In the first interpolated pixel IP1 and the second interpolated pixel IP2, a pair of first sub-interpolated emission patterns and a pair of second sub-interpolated emission patterns are arranged in a 1×4 matrix. For example, in interpolated pixel 1712, interpolated emission patterns EP21, EP22, EP23, and EP24 are arranged in a 1×4 matrix. Here, interpolated emission patterns EP21 and EP23 can be connected to the normal emission pattern EP3 of normal pixel 1713, and interpolated emission patterns EP22 and EP24 can be connected to the normal emission pattern EP1 of normal pixel 1711.

[0257] According to one embodiment, in the third interpolated pixel IP3 and the fourth interpolated pixel IP4, the third interpolation emission pattern includes a pair of third sub-interpolated emission patterns (e.g., interpolated emission patterns EP42 and EP44) that are separate from each other, and the fourth interpolated emission pattern includes a pair of fourth sub-interpolated emission patterns (e.g., interpolated emission patterns EP41 and EP43) that are separate from each other. In the third interpolated pixel IP3 and the fourth interpolated pixel IP4, the pair of third sub-interpolated emission patterns (e.g., interpolated emission patterns EP42 and EP44) and the pair of fourth sub-interpolated emission patterns (e.g., interpolated emission patterns EP41 and EP43) are arranged in a 4×1 matrix. For example, interpolated pixel 1714 includes interpolated emission patterns EP41, EP42, EP43, and EP44 arranged in a 4×1 matrix. Here, interpolated emission patterns EP41 and EP43 may be connected to the normal emission pattern EP7 of normal pixel 1717, and interpolated emission patterns EP42 and EP44 may be connected to the normal emission pattern EP1 of normal pixel 1711.

[0258] Figure 18 This is an equivalent circuit diagram of a normal pixel (e.g., referring to the normal pixel NP in Table 1) according to one implementation. For example, Figure 18 Can be used as a reference Figures 11 to 17 The equivalent circuit diagram of a normal pixel NP is described.

[0259] Reference Figure 18 The normal pixel NP may also include a scan transistor SWT connected to the data line DL and controlled by the scan signal SCAN, a drive transistor DR that generates a drive current based on the data voltage provided from the scan transistor SWT, a light-emitting element LE that emits light according to the drive current of the drive transistor DR, and a gate electrode connected to the drive transistor DR and subjected to a light source. Figure 2 The capacitor CT is located between the second driving voltage line VDL and the second driving voltage line VDD.

[0260] In concluding this detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of this disclosure. Therefore, the preferred embodiments of this disclosure are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. A display device, characterized by comprising: Comprising: a display panel in which one normal pixel and a plurality of interpolation pixels surrounding the one normal pixel form one pixel group, wherein the one normal pixel includes a driving transistor and a normal light emitting element that receives a driving current through a first node connected to a drain electrode of the driving transistor, each of the plurality of interpolation pixels includes a first interpolation light emitting element that receives a portion of a first driving current from a first normal pixel and a second interpolation light emitting element that receives a portion of a second driving current from a second normal pixel, and a first interpolation emission pattern of the first interpolation light emitting element is disposed adjacent to the second normal pixel, and a second interpolation emission pattern of the second interpolation light emitting element is disposed adjacent to the first normal pixel.

2. The display device according to claim 1, wherein the first normal pixel includes a first normal light emitting element, the second normal pixel includes a second normal light emitting element, the second interpolation emission pattern is disposed between a first normal emission pattern of the first normal light emitting element and the first interpolation emission pattern, and the first interpolation emission pattern is disposed between a second normal emission pattern of the second normal light emitting element and the second interpolation emission pattern.

3. The display device according to claim 2, wherein The one pixel group includes: the one normal pixel disposed at a center of the one pixel group; a first interpolation pixel disposed in a first planar direction from the one normal pixel; a second interpolation pixel disposed in a second planar direction opposite to the first planar direction from the one normal pixel; a third interpolation pixel disposed in a third planar direction perpendicular to the first planar direction from the one normal pixel; a fourth interpolation pixel disposed in a fourth planar direction opposite to the third planar direction from the one normal pixel; a fifth interpolation pixel disposed in a first diagonal direction between the first planar direction and the third planar direction from the one normal pixel; a sixth interpolation pixel disposed in a second diagonal direction between the second planar direction and the third planar direction from the one normal pixel; a seventh interpolation pixel disposed in a third diagonal direction opposite to the second diagonal direction from the one normal pixel; and an eighth interpolation pixel disposed in a fourth diagonal direction opposite to the first diagonal direction from the one normal pixel.

4. The display device according to claim 3, wherein The first interpolation pixel and the second interpolation pixel each receive a driving current from the normal pixel disposed in the first planar direction and the second planar direction of the corresponding one of the first interpolation pixel and the second interpolation pixel.

5. The display device according to claim 4, wherein As for each of the first interpolation pixel and the second interpolation pixel, the first normal pixel is a pixel disposed in the first planar direction from the corresponding one of the first interpolation pixel and the second interpolation pixel, and As for each of the first interpolation pixel and the second interpolation pixel, the second normal pixel is a pixel disposed in the second planar direction from the corresponding one of the first interpolation pixel and the second interpolation pixel.

6. The display device according to claim 5, wherein The third and fourth interpolation pixels each receive drive current from the normal pixels disposed in the third and fourth planar directions of the corresponding one of the third and fourth interpolation pixels.

7. The display device according to claim 6, wherein With respect to each of the third and fourth interpolation pixels, the first normal pixel is a pixel disposed in the third planar direction from the corresponding one of the third and fourth interpolation pixels, and With respect to each of the third and fourth interpolation pixels, the second normal pixel is a pixel disposed in the fourth planar direction from the corresponding one of the third and fourth interpolation pixels.

8. The display device according to claim 7, wherein The fifth through eighth interpolation pixels each receive drive current from the normal pixels disposed in the first through fourth diagonal directions of the corresponding one of the fifth through eighth interpolation pixels.

9. The display device according to claim 8, wherein Each of the fifth through eighth interpolation pixels further includes a third interpolation light emitting element that receives a third drive current from a portion of a third normal pixel and a fourth interpolation light emitting element that receives a fourth drive current from a portion of a fourth normal pixel.

10. The display device according to claim 9, wherein The third normal pixel includes a third normal light emitting element, The fourth normal pixel includes a fourth normal light emitting element, The third interpolation emission pattern of the third interpolation light emitting element is disposed adjacent to the fourth normal pixel, and The fourth interpolation emission pattern of the fourth interpolation light emitting element is disposed adjacent to the third normal pixel.

Images