Semiconductor element

Abstract

A semiconductor device includes a first transistor having an n-type conductivity over a substrate and a second transistor having a p-type conductivity vertically over the first transistor. The first transistor includes a first semiconductor layer including a first channel region and a first source / drain region, and a first gate structure over the first channel region of the first semiconductor layer. The second transistor includes a second semiconductor layer including a second channel region and a second source / drain region, and a second gate structure on the second channel region of the second semiconductor. The first dielectric layer covers the first transistor and the second transistor. The second dielectric layer is over the first dielectric layer. The third dielectric layer contacts the first dielectric layer and the second dielectric layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in generation after generation of ICs. Each generation features smaller and more complex circuits than the previous one. However, these advancements have increased the complexity of handling and manufacturing ICs. In the course of IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest component (or wiring) that can be created using manufacturing processes) decreases. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to shrink, manufacturing processes continue to become more difficult to execute. Therefore, forming reliable semiconductor devices in increasingly smaller dimensions remains a challenge. Utility Model Content

[0003] In some embodiments disclosed herein, a semiconductor device includes a first transistor having n-type conductivity located above a substrate and a second transistor having p-type conductivity vertically located above the first transistor. The first transistor includes a first semiconductor layer and a first gate structure. The first semiconductor layer includes a first channel region and a first source / drain region, and the first gate structure is located above the first channel region of the first semiconductor layer. The second transistor includes a second semiconductor layer with a second channel region and a second source / drain region, and a second gate structure on the second channel region of the second semiconductor layer. A first dielectric layer covers the first transistor and the second transistor. A second dielectric layer is located above the first dielectric layer. A third dielectric layer contacts the first and second dielectric layers.

[0004] In some embodiments disclosed herein, a semiconductor device includes a first transistor having n-type conductivity located above a substrate and a second transistor having p-type conductivity vertically located above the first transistor. The first transistor includes a first semiconductor layer and a first gate structure. The first semiconductor layer includes a first channel region and a first source / drain region, and the first gate structure is located above the first channel region of the first semiconductor layer. The second transistor includes a second semiconductor layer with a second channel region and a second source / drain region, and a second gate structure on the second channel region of the second semiconductor layer. A first dielectric layer covers the first transistor and the second transistor. A second dielectric layer is located above the first dielectric layer. A third dielectric layer contacts the first and second dielectric layers. The first gate structure contacts three sides of the first channel region, and the second gate structure contacts four sides of the second channel region.

[0005] In some embodiments disclosed herein, a semiconductor device includes a first transistor having n-type conductivity located above a substrate and a second transistor having p-type conductivity vertically located above the first transistor. The first transistor includes a first semiconductor layer and a first gate structure. The first semiconductor layer includes a first channel region and a first source / drain region, and the first gate structure is located above the first channel region of the first semiconductor layer. The second transistor includes a second semiconductor layer with a second channel region and a second source / drain region, and a second gate structure on the second channel region of the second semiconductor layer. A first dielectric layer covers the first transistor and the second transistor. A second dielectric layer is located above the first dielectric layer. A third dielectric layer contacts the first and second dielectric layers. An output terminal is electrically connected to a first of the source / drain regions of the first semiconductor layer and a first of the source / drain regions of the second semiconductor layer. An input terminal is electrically connected to the first gate structure and the second gate structure. A first power supply terminal is electrically connected to a second of the source / drain regions of the first semiconductor layer. A second power supply terminal is electrically connected to a second of the plurality of source / drain regions of the second semiconductor layer. Attached Figure Description

[0006] When with attachment Figure 1 The best understanding of the various features disclosed herein can be obtained from the following detailed description. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased arbitrarily for clarity of discussion.

[0007] Figures 1 to 16D This describes methods in the respective stages of forming a semiconductor device according to some embodiments of this disclosure;

[0008] Figure 17 This is a cross-sectional view of a semiconductor element according to some embodiments of this disclosure;

[0009] Figures 18 to 24D This describes methods in the respective stages of forming a semiconductor device according to some embodiments of this disclosure;

[0010] Figure 25A and Figure 25B These are simulation results of semiconductor elements according to some embodiments of this disclosure.

[0011] [Symbol Explanation]

[0012] 100:Substrate

[0013] 102: Semiconductor layer

[0014] 105: Dielectric layer

[0015] 106: Isolation Structure

[0016] 110: Semiconductor layer

[0017] 110CH: Channel Area

[0018] 110SD: Source / Drain Region

[0019] 110P: Highlighted Part

[0020] 110PA: Pad Area

[0021] 120: Semiconductor layer

[0022] 120B: Bottom

[0023] 120CH: Channel Area

[0024] 120SD: Source / Drain Region

[0025] 120PA: Pad Area

[0026] 120T: Top

[0027] 130: Oxide layer

[0028] 131: Oxide layer

[0029] 132: Oxide layer

[0030] 140: Gate Stack

[0031] 140A: Gate structure

[0032] 140B: Gate structure

[0033] 142A: Interface Layer

[0034] 144A: High-k dielectric layer

[0035] 146A: Work function metal layer

[0036] 148A: Filler metal

[0037] 142B: Interface Layer

[0038] 144B: High-k dielectric layer

[0039] 146B: Work function metal layer

[0040] 148B: Filler metal

[0041] 150: Dielectric layer

[0042] 155: Dielectric layer

[0043] 160: Dielectric layer

[0044] 171: Conductive via

[0045] 172: Conductive via

[0046] 173: Conductive via

[0047] 174: Conductive via

[0048] 175: Conductive via

[0049] 181: Conductive pad

[0050] 182: Conductive pad

[0051] 183: Conductive pad

[0052] 184: Conductive pad

[0053] IMP1: First Implantation Process

[0054] IMP2: Second Implantation Process

[0055] IMP3: Third Implantation Technology

[0056] MA1: Mask

[0057] MA2: Mask

[0058] MA3: Mask

[0059] MA4: Mask

[0060] E1: First Etching Process

[0061] E2: Second Etching Process

[0062] E3: Third Etching Process

[0063] E4: Fourth Etching Process

[0064] O1: Opening

[0065] R1: Groove

[0066] AA, BB, CC: lines Detailed Implementation

[0067] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and not limiting. For example, in the following description, forming a first feature on or on a second feature may include embodiments where the first feature and the second feature are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first feature and the second feature are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0068] Furthermore, for ease of description, spatial relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms may be used herein to describe the relationship of one element or feature to another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to encompass different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein shall be interpreted accordingly. As used herein, “around,” “about,” or “substantially” generally refers to within 20%, 10%, or 5% of a given value or range. The numerical values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “around,” “about,” or “substantially” can be inferred. However, those skilled in this art should realize that the values ​​or ranges described throughout the specification are merely examples and may decrease or change as integrated circuits shrink.

[0069] Gate-all-around (GAA) transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more lithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0070] This disclosure provides a complementary FET (CFET), the method of which will be disclosed in the following discussion. In the CFET, a first transistor is disposed above a substrate (not shown), and a second transistor is disposed vertically above the first transistor. In some embodiments, the first and second transistors may be field-effect transistors (FETs). The first transistor may include a fin configuration, and therefore the first transistor may also be referred to as a FinFET. On the other hand, the second transistor may include a gate-all-around (GAA) configuration, and therefore the second transistor may also be referred to as a GAA FET.

[0071] Figures 1 to 16D This describes methods in various stages of forming a semiconductor device according to some embodiments of this disclosure. Although Figures 1 to 16D The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some of the actions described and / or illustrated may be omitted in whole or in part.

[0072] refer to Figure 1 The substrate 100 is shown. In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate. For example, the substrate 100 is an SOI substrate, which includes a bulk semiconductor layer 102, a dielectric layer 105 on the bulk semiconductor layer 102, and a semiconductor layer 110 on the dielectric layer 105. In some embodiments, the dielectric layer 105 may be a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) and / or other suitable processes. In some embodiments, the BOX layer is a silicon dioxide (SiO2) layer. The semiconductor layer 110 may contain silicon.

[0073] Semiconductor layer 120 is formed on substrate 100 and contacts the top surface of semiconductor layer 110 of substrate 100. Semiconductor layer 120 may contain a different semiconductor material than semiconductor layer 110. More specifically, semiconductor layer 110 may contain a semiconductor material suitable for n-type devices, and semiconductor layer 120 may contain a semiconductor material suitable for p-type devices, but this disclosure is not limited thereto. In some embodiments, semiconductor layer 110 may be made of silicon (Si), and semiconductor layer 120 may be made of germanium (Ge). In some embodiments, semiconductor layer 110 may be made of a substantially pure silicon layer, for example, with a silicon percentage greater than about 98%. Similarly, semiconductor layer 120 may be made of a substantially pure germanium layer, for example, with a germanium percentage greater than about 98%.

[0074] refer to Figure 2A and Figure 2B ,in Figure 2A This is a schematic diagram of a semiconductor device. Figure 2B It is along Figure 2A A cross-sectional view of line AA is shown. A mask MA1 is formed on semiconductor layer 120, and a mask MA2 is formed on mask MA1. Mask MA2 can be patterned using a suitable lithography process, and then mask MA1 can be patterned using the patterned mask MA2. Patterned masks MA1 and MA2 can be used to define active regions on substrate 100. In some embodiments, mask MA1 can be a hard mask and can be made of a suitable material, such as oxide or nitride. For example, mask MA1 can be made of silicon oxide using PECVD. The silicon oxide hard mask can prevent the underlying germanium layer (e.g., semiconductor layer 120) from being oxidized. On the other hand, mask MA2 can be a photoresist layer.

[0075] Figures 3 to 6 This describes the process of defining active regions on substrate 100 using patterned masks MA1 and MA2. More specifically, Figures 3 to 6 The method describes the use of patterned masks MA1 and MA2 as etching masks to perform several etching processes to remove portions of semiconductor layers 110 and 120, thereby defining an active region on substrate 100.

[0076] refer to Figure 3 ,in Figure 3 Follow Figure 2B A cross-sectional view. A first etching process E1 is performed to remove portions of the semiconductor layer 120 exposed by masks MA1 and MA2, thereby forming a recess R1 in the semiconductor layer 120. As a result of the first etching process E1, the etched semiconductor layer 120 may include a top 120T and a bottom 120B below the top 120T, wherein... Figure 3 In the cross-sectional view, the bottom 120B is wider than the top 120T. From different angles, the top 120T can be described as a protrusion extending upward from the bottom 120B.

[0077] The first etching process E1 can be an anisotropic etching process. In some embodiments, the first etching process E1 can be a dry etching process, such as reactive ion etching (RIE), or other suitable etching processes may be used. In some embodiments, the reaction gas of the first etching process E1 may include chlorine (Cl2) and oxygen (O2). Chlorine (Cl2) can be used as an etchant for etching the semiconductor layer 120. In some embodiments, the first etching process E1 can be performed at a pressure of about 5 mTorr to about 30 mTorr, a power of about 200 W to about 900 W, a bias voltage of about 250 V to about 500 V, and a temperature of about 45°C to about 60°C.

[0078] On the other hand, during the first etching process E1, oxygen (O2) can react with a portion of the surface of the semiconductor layer 120 to form an oxide layer 130 on the exposed surface of the semiconductor layer 120 as a byproduct of the first etching process E1. That is, the oxide layer 130 can be arranged on the surface of the recess R1. More specifically, the oxide layer 130 can be arranged on the sidewalls of the top 120T of the semiconductor layer 120 and the top surface of the bottom 120B of the semiconductor layer 120. The oxide layer 130 can be an oxide of the material of the semiconductor layer 120. For example, when the semiconductor layer 120 is made of germanium (Ge), the oxide layer 130 can be germanium oxide (GeO2). In some embodiments, the oxide layer 130 can also be referred to as a dielectric layer.

[0079] refer to Figure 4 , Figure 4 Follow Figure 3 A cross-sectional view is shown. After completing the first etching process E1, a second etching process E2 is performed to remove the horizontal portion of the oxide layer 130, thereby exposing the bottom 120B of the semiconductor layer 120. Once the horizontal portion of the oxide layer 130 is removed, the second etching process E2 removes the exposed bottom 120B of the semiconductor layer 120, thereby narrowing the bottom 120B of the semiconductor layer 120. In some embodiments, the second etching process E2 is performed until the underlying semiconductor layer 110 is exposed.

[0080] The second etching process E2 can be an anisotropic etching process. In some embodiments, the second etching process E2 can be a dry etching process, such as reactive ion etching (RIE), or other suitable etching processes. In some embodiments, the reaction gas of the second etching process E2 may include chlorine (Cl2). Chlorine (Cl2) can be used as an etchant for etching the semiconductor layer 120. The difference between the second etching process E2 and the first etching process E1 is that the reaction gas of the second etching process E2 does not contain oxygen (O2). In some embodiments, the second etching process E2 can be performed at a pressure of about 5 mTorr to about 30 mTorr, a power of about 200 W to about 900 W, a bias voltage of about 250 V to about 500 V, and a temperature of about 45°C to about 60°C.

[0081] As described above, because the second etching process E2 is an anisotropic etching process, it removes the horizontal portion of the oxide layer 130. Since chlorine (Cl2) has a low etching rate on oxide materials, the vertical portion of the oxide layer 130 can be retained on the sidewalls of the top 120T of the semiconductor layer 120. The remaining oxide layer 130 can be used as a protective layer in subsequent etching processes to protect the top 120T of the semiconductor layer 120.

[0082] Furthermore, because the reaction gas in the second etching process E2 does not contain oxygen (O2), once the second etching process E2 is completed, no oxide layer is formed on the semiconductor surface (e.g., semiconductor layers 110 and 120) except for the existing oxide layer 130. In other words, after the second etching process E2 is completed, the sidewalls of the bottom 120B of semiconductor layer 120 and the top surface of semiconductor layer 110 remain exposed through the groove R1.

[0083] refer to Figure 5 ,in Figure 5 Follow Figure 4 A cross-sectional view is shown. After completing the second etching process E2, a third etching process E3 is performed to remove the bottom 120B of the semiconductor layer 120. On the other hand, the oxide layer 130 protects the top 120T of the semiconductor layer 120 from damage during the third etching process E3. As a result of the third etching process E3, the semiconductor layer 120 is vertically separated from the semiconductor layer 110. In other words, the third etching process E3 is performed such that a gap is vertically formed between the semiconductor layer 120 and the semiconductor layer 110.

[0084] The third etching process E3 can be an isotropic etching process. In some embodiments, the third etching process E3 can be an isotropic dry etching process, such as reactive ion etching (RIE), or other suitable etching processes may be used. In some embodiments, the reaction gas of the third etching process E3 may include chlorine (Cl2) and hydrogen bromide (HBr). Both chlorine (Cl2) and hydrogen bromide (HBr) can be used as etchants for etching the semiconductor layer 120. In some embodiments, the third etching process E3 differs from the first etching process E1 and the second etching process E2 in that the third etching process E3 includes hydrogen bromide (HBr). The use of hydrogen bromide (HBr) can provide isotropic properties to the etching process because the etching rate of hydrogen bromide (HBr) on the material of semiconductor layer 120 (e.g., Ge) can be higher than the etching rate on the material of semiconductor layer 110 (e.g., Si). In some embodiments, semiconductor layer 110 can remain substantially intact or negligibly etched during the third etching process E3. In some embodiments, the third etching process E3 can be performed at a pressure of about 5 to about 30 millitors, a power of about 200 W to about 900 W, a bias of about 0 V to about 500 V (e.g., 0 V means no bias is applied), and a temperature of about 45°C to about 60°C.

[0085] refer to Figure 6 ,in Figure 6 Follow Figure 5 A cross-sectional view. After completing the third etching process E3, a fourth etching process E4 is performed to remove a portion of the semiconductor layer 110 exposed through the top 120T (or masks MA1 and MA2) of the semiconductor layer 120, thereby narrowing the semiconductor layer 110. After the fourth etching process E4 is completed, the remaining portion of the semiconductor layer 110 lies vertically below the semiconductor layer 120.

[0086] The fourth etching process E4 can be an anisotropic etching process. In some embodiments, the fourth etching process E4 can be a dry etching process, such as reactive ion etching (RIE), or other suitable etching processes may be used. In some embodiments, the reaction gas of the fourth etching process E4 may include chlorine (Cl2) and oxygen (O2). Chlorine (Cl2) can be used as an etchant for etching the semiconductor layer 120. In some embodiments, the fourth etching process E4 can be performed at a pressure of about 5 mTorr to about 30 mTorr, a power of about 200 W to about 900 W, a bias voltage of about 250 V to about 500 V, and a temperature of about 45°C to about 60°C.

[0087] On the other hand, during the fourth etching process E4, oxygen (O2) can react with the surface portions of semiconductor layers 120 and 110 to form oxide layers 131 and 132, respectively, on the exposed surfaces of semiconductor layers 110 and 120, as byproducts of the fourth etching process E4. More specifically, oxide layer 131 can be arranged on the sidewalls and top surface of semiconductor layer 110, and oxide layer 132 can be arranged on the bottom surface of semiconductor layer 120. No additional oxide layer is formed on the sidewalls of semiconductor layer 120 because they are already covered by oxide layer 130. Oxide layer 131 can be an oxide of the material of semiconductor layer 110, and oxide layer 132 can be an oxide of the material of semiconductor layer 120. For example, when semiconductor layer 110 is made of silicon (Si), oxide layer 131 can be silicon oxide (SiO2). When semiconductor layer 120 is made of germanium (Ge), oxide layer 132 can be germanium oxide (GeO2). Oxide layers 130 and 132 may be made of the same material as oxide layer 131. In some embodiments, oxide layers 131 and 132 may also be referred to as dielectric layers.

[0088] Based on the above discussion, the first etching process E1, the second etching process E2, the third etching process E3, and the fourth etching process E4 include the use of chlorine gas (Cl2) as the etching gas. The first etching process E1 and the fourth etching process E4 also include the use of oxygen (O2) to form oxide layers 130, 131, and 132, while the second etching process E2 and the third etching process E3 may not use oxygen (O2). The third etching process E3 also includes the use of hydrogen bromide (HBr) to provide isotropic etching characteristics, while the first etching process E1, the second etching process E2, and the fourth etching process E4 may not use hydrogen bromide gas (HBr), and therefore the first etching process E1, the second etching process E2, and the fourth etching process E4 may include anisotropic etching characteristics.

[0089] refer to Figure 7 , Figure 7 This is a schematic diagram of a semiconductor device. As mentioned above, Figure 2A The structure can undergo such Figures 3 to 6 The etching process described above. After the etching process is completed, masks MA1 and MA2 are removed from the top surface of semiconductor layer 120. Furthermore, a pre-cleaning process is performed to remove oxide layers 130, 131, and 132, thereby exposing the surfaces of semiconductor layers 110 and 120, resulting in the structure shown below. Figure 7 As shown. As discussed, semiconductor layers 110 and 120 are patterned to form active regions. In some embodiments, patterned semiconductor layer 110 may be referred to as a fin structure above dielectric layer 105, and patterned semiconductor layer 120 may be referred to as nanowires vertically stacked above patterned semiconductor layer 110.

[0090] Regarding the patterned semiconductor layer 110, the patterned semiconductor layer 110 includes a channel region 110CH, source / drain regions 110SD on opposite sides of the channel region 110CH, and pad regions 110PA connected to their respective source / drain regions 110SD. Therefore, the source / drain regions 110SD and pad regions 110PA can together serve as the source / drain structure of a semiconductor device. In some embodiments, each of the pad regions 110PA may have a larger area than the source / drain regions 110SD. Similarly, regarding the patterned semiconductor layer 120, the patterned semiconductor layer 120 includes a channel region 120CH, source / drain regions 120SD on opposite sides of the channel region 120CH, and pad regions 120PA connected to their respective source / drain regions 120SD. In some embodiments, each of the pad regions 120PA may have a larger area than the source / drain regions 120SD. In some embodiments, pad region 120PA may contact pad region 110PA because pad region 120PA contains a larger area, and Figures 4 to 6 The etching process described herein may not etch through the pad region. In some embodiments, the pad region 120PA of the patterned semiconductor layer 120 may be removed in the following processes.

[0091] refer to Figure 8A and Figure 8B ,in Figure 8A This is a schematic diagram of a semiconductor device. Figure 8B It is along Figure 8A The cross-sectional view of line AA. Note that, for the sake of simplicity, Figure 8A Not explained in the text Figure 8B Certain components in the semiconductor layer 120. A gate stack 140 is formed on the substrate 100, intersecting with the channel region 110CH of the semiconductor layer 110 and winding around the channel region 120CH of the semiconductor layer 120. In some embodiments, a mask MA3 may be used to define the outline and position of the gate stack 140.

[0092] like Figure 8B As shown, the gate stack 140 includes a first gate structure 140A and a second gate structure 140B. More specifically, the first gate structure 140A may be referred to as the portion of the gate stack 140 that intersects with the channel region 110CH of the semiconductor layer 110, and the second gate structure 140B may be referred to as the portion of the gate stack 140 that surrounds the channel region 120CH of the semiconductor layer 120. In some embodiments, the gate structure 140A may contact three sides of the semiconductor layer 110 (e.g., the top surface and the opposite sidewall). The gate structure 140B may contact four sides of the semiconductor layer 120 (e.g., the top surface, the bottom surface, and the opposite sidewall).

[0093] Regarding the first gate structure 140A, the first gate structure 140A includes an interface layer 142A, a high-k dielectric layer 144A on the interface layer 142A, a work function metal layer 146A on the high-k dielectric layer 144A, and a fill metal 148A on the work function metal layer 146A. Regarding the second gate structure 140B, the second gate structure 140B includes an interface layer 142B, a high-k dielectric layer 144B on the interface layer 142B, a work function metal layer 146B on the high-k dielectric layer 144B, and a fill metal 148B on the work function metal layer 146B. In some embodiments, the fill metal 148A and the fill metal 148B may be different portions of a single material.

[0094] The gate stack 140 can be formed, for example, by performing an oxidation process to selectively form interface layer 142A on the exposed surface of semiconductor layer 110 and selectively form interface layer 142B on the exposed surface of semiconductor layer 120. For example, the oxidation process may include forming interface layers 142A and 142B using ozone (O3) plasma in an ALD chamber. Therefore, interface layer 142A may be an oxide of the material of semiconductor layer 110, and interface layer 142B may be an oxide of the material of semiconductor layer 120. In some embodiments where semiconductor layers 110 and 120 are made of silicon (Si) and germanium (Ge), respectively, interface layers 142A and 142B may be made of silicon oxide (SiO2) and germanium oxide (GeO2), respectively. That is, when semiconductor layers 110 and 120 are made of different materials, interface layers 142A and 142B may contain different materials.

[0095] After forming interface layers 142A and 142B, a deposition process is performed to form high-k dielectric layers 144A and 144B on interface layers 142A and 142B, respectively. The high-k dielectric layer 144A may extend to the top surface of dielectric layer 105. In some embodiments, the deposition process may be a conformal deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes. Examples of high-k dielectric materials include aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), titanium oxide (TiO), hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0096] After forming high-k dielectric layers 144A and 144B, a deposition process is performed to form work function metal layers 146A and 146B on the high-k dielectric layers 144A and 144B, respectively. In some embodiments, the deposition process may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In some embodiments, work function metal layers 146A and 146B may comprise tantalum nitride (TaN). In other embodiments, work function metal layers 146A and 146B may also comprise titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum (TiAl), tantalum aluminum (TaAl), other suitable work function materials, or combinations thereof. In some embodiments, the work function metal layers 146A and 146B may be made of the same material, which facilitates achieving substantially the same critical voltage for different transistors and further reduces manufacturing complexity. In other embodiments, the work function metal layers 146A and 146B may be made of different work function materials.

[0097] After forming the work function metal layers 146A and 146B, a deposition process is performed to form filler metals 148A and 148B. For example, a filler conductive material is formed on the substrate 100 to fill the space outside the work function metal layers 146A and 146B. In some embodiments, the deposition process may include physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In some embodiments, filler metals 148A and 148B may comprise titanium nitride (TiN). In other embodiments, filler metals 148A and 148B may comprise tungsten (W), aluminum (Al), copper (Cu), or other suitable conductive materials. In some embodiments, the thickness of the work function metal layers 146A and 146B is in the range of about 20 nm to about 40 nm (e.g., 30 nm), and the thickness of the filler metals 148A and 148B is in the range of about 50 nm to about 70 nm (e.g., 60 nm).

[0098] Then, a patterned mask MA3 is formed on the work function metal layers 146A and 146B. Next, an etching process is performed to remove portions of the interface layers 142A and 142B, high-k dielectric layers 144A and 144B, work function metal layers 146A and 146B, and filler metals 148A and 148B exposed through the patterned mask MA3, resulting in a gate stack 140 as shown. Figure 8A and Figure 8B As shown. In some embodiments, the patterned mask MA3 may be a photoresist.

[0099] refer to Figure 9A and Figure 9B ,in Figure 9A This is a schematic diagram of a semiconductor device. Figure 9B For along Figure 9A A cross-sectional view of line BB. After forming the gate stack 140, a first implantation process IMP1 is performed to dope the source / drain regions 110SD of semiconductor layer 110 and the source / drain regions 120SD of semiconductor layer 120. It should be noted that during the first implantation process IMP1, the pad regions 110PA of semiconductor layer 110 and 120PA of semiconductor layer 120 may also be doped; therefore, for simplicity, the relevant details are not repeated. During the first implantation process IMP1, the mask MA3 can be used as a protective layer to prevent damage to the gate stack 140.

[0100] In some embodiments, the implant in the first implantation process IMP1 may be an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb) and the like. That is, after the first implantation process IMP1 is completed, both the source / drain region 110SD of semiconductor layer 110 and the source / drain region 120SD of semiconductor layer 120 are n-type doped regions. In some embodiments, the first implantation process IMP1 is performed at approximately 9 keV to about 12 keV (e.g., 10 keV) and at approximately 1 x 10 15 cm -2 To approximately 2 x 10 15 cm -2 (e.g., 1x10) 15 cm -2 Dosage administration.

[0101] In some embodiments, the first implantation process IMP1 is performed by generating an implant facing the substrate 100 with a non-zero tilt angle θ. Herein, "tilt angle θ" can be the angle between the incident direction of the implant and the normal to the top surface of the substrate 100 (or the normal to the top surface of the semiconductor layers 110 and 120). In practice, during the first implantation process IMP1, the incident direction of the implant can be fixed, and the substrate 100 can be rotated by an angle θ such that the incident direction of the implant is tilted relative to the substrate 100. Performing the first implantation process IMP1 with a tilt angle θ may be advantageous for forming lower-level doped regions in the source / drain regions 110SD of the semiconductor layer 110. If the first implantation process IMP1 is performed without tilting the incident direction (e.g., the tilt angle θ is 0°), the incident direction can be perpendicular to the top surface of the substrate 100 (or the top surface of the semiconductor layers 110 and 120). In this scenario, semiconductor layer 120 may block the implant, and the implant may not be able to reach the source / drain region 110SD of semiconductor layer 110. In some embodiments, the tilt angle θ is in the range of approximately 5° to approximately 30°, for example, 12°. If the tilt angle θ is too small (e.g., much less than 5°), most of the implant may be blocked by semiconductor layer 120. If the tilt angle θ is too large (e.g., much greater than 30°), the incident direction may be too flat, and the implant may be blocked by other structures (not shown) on substrate 100.

[0102] More specifically, the first implantation process IMP1 may include a first step and a second step. The first step includes generating an implant facing one side of the source / drain region 110SD of semiconductor layer 110 and one side of the source / drain region 120SD of semiconductor layer 120. After the first step is completed, substrate 100 (including the structure formed on substrate 100) is twisted by approximately 180° relative to the incident direction of the implant. Alternatively, the second step is then performed by generating the implant facing the other side of the source / drain region 110SD of semiconductor layer 110 and the other side of the source / drain region 120SD of semiconductor layer 120. Therefore, the source / drain regions 110SD of semiconductor layer 110 and 120SD of semiconductor layer 120 can be doped from opposite sides to obtain a more uniform dopant concentration.

[0103] refer to Figure 10A , Figure 10B and Figure 10C ,in Figure 10A This is a schematic diagram of a semiconductor device. Figure 10B For along Figure 10A A cross-sectional view of line BB. Figure 10C For along Figure 10AA cross-sectional view of line CC. After completing the first implantation process IMP1, the mask MA3 is removed from the top surface of the gate stack 140. Then, a dielectric layer 150 is formed on the substrate 100, covering the gate stack 140 and semiconductor layers 110 and 120. The dielectric layer 150 has a portion that vertically fills the space between semiconductor layers 110 and 120. This portion serves as a support structure for semiconductor layer 120 to prevent semiconductor layer 120 from collapsing during subsequent processes.

[0104] In some embodiments, dielectric layer 150 may comprise an oxide, such as aluminum oxide (Al2O3). In other embodiments, dielectric layer 150 may comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass, low-k dielectric materials, and / or other suitable dielectric materials. In some embodiments, the deposition process may be a conformal deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In some embodiments, the thickness of dielectric layer 150 is in the range of about 18 nm to 22 nm, for example, 20 nm.

[0105] refer to Figure 11A and Figure 11B ,in Figure 11A This is a schematic diagram of a semiconductor device. Figure 11B For along Figure 11A A cross-sectional view of line BB. After forming dielectric layer 150, a second implantation process IMP2 is performed to dope the source / drain regions 120SD of semiconductor layer 120. During the second implantation process IMP2, the pad regions 120PA of semiconductor layer 120 may also be doped, so related details will not be omitted for brevity. During the second implantation process IMP2, dielectric layer 150 can act as a protective layer to prevent surface damage on the source / drain regions 120SD of semiconductor layer 120.

[0106] In some embodiments, the implant of the second implantation process IMP2 may be a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), and the like. In some embodiments, the second implantation process IMP2 operates at approximately 9 keV to about 12 keV (e.g., 10 keV) and at approximately 1 x 10⁻⁶ keV. 15 cm -2 To approximately 2 x 10 15 cm -2 (For example, 1 x 10) 15cm -2 Dosage administration.

[0107] In some embodiments, the second implantation process IMP2 is performed by generating an implant perpendicular to the substrate 100. That is, the second implantation process IMP2 is performed without any tilt angle (e.g., tilt angle θ is 0°). In other words, the incident direction of the implant may be perpendicular to the top surface of the substrate 100 (or the top surface of the semiconductor layer 120). Therefore, the second semiconductor layer 120 may undergo the second implantation process IMP2, and the implant of the second implantation process IMP2 may also prevent it from reaching the source / drain region 110SD of the semiconductor layer 110. As a result, the source / drain region 110SD of the semiconductor layer 110 may not undergo the second implantation process IMP2, and therefore the source / drain region 110SD in the semiconductor layer 110 may not contain the p-type dopant used in the second implantation process IMP2.

[0108] Based on the above discussion, it can be seen that the source / drain region 120SD of semiconductor layer 120 can undergo a first implantation process IMP1 (with an n-type implant) and a second implantation process IMP2 (with a p-type implant). As a result, both n-type and p-type implants can be detected in the source / drain region 120SD of semiconductor layer 120. For example, when phosphorus (P) is used in the first implantation process IMP1 and boron (B) is used in the second implantation process IMP2, both phosphorus (P) and boron (B) can be detected in the source / drain region 120SD of semiconductor layer 120, while only phosphorus (P) can be detected in the source / drain region 110SD of semiconductor layer 110. Although the source / drain region 120SD of semiconductor layer 120 contains both n-type and p-type dopants, the source / drain region 120SD in semiconductor layer 120 can exhibit the p-type conductivity type measured by Hall effect measurement, which will be discussed later.

[0109] refer to Figure 12A and Figure 12B ,in Figure 12A This is a schematic diagram of a semiconductor device. Figure 12B For along Figure 12AA cross-sectional view of line CC. After completing the second implantation process IMP2, a dielectric layer 155 is formed on dielectric layer 150. In some embodiments, dielectric layer 155 may comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass, low-k dielectric materials, and / or other suitable dielectric materials. In some embodiments, the deposition process may be a conformal deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In some embodiments, the thickness of dielectric layer 155 is in the range of about 18 nm to 22 nm, for example, 20 nm. Dielectric layers 150 and 155 may be made of different dielectric materials, and this disclosure is not limited thereto. In some embodiments, dielectric layer 150 may comprise aluminum oxide (Al2O3), and dielectric layer 155 may comprise silicon oxide (SiO2).

[0110] refer to Figure 13A and Figure 13B ,in Figure 13A This is a schematic diagram of a semiconductor device. Figure 13B For along Figure 13A A cross-sectional view of line CC is shown. A mask MA4 is formed on dielectric layer 155, and the mask MA4 can be patterned to form an opening O1. In some embodiments, the opening O1 can be perpendicularly overlapped with the pad region 120PA of semiconductor layer 120, respectively. An etching process is then performed through the opening O1 of the mask MA4 to remove portions of dielectric layer 155, portions of dielectric layer 150, and pad region 120PA of semiconductor layer 120. Once the pad region 120PA of semiconductor layer 120 has been removed, the etching process can be stopped. Therefore, the pad region 110PA of semiconductor layer 110 can be exposed through the opening O1.

[0111] In some embodiments, dielectric layer 155 may serve as an adhesive layer between dielectric layer 150 and mask MA4. If dielectric layer 155 is absent, mask MA4 may contact dielectric layer 150. However, experimental results show that mask MA4 may easily peel off from dielectric layer 150, leading to a deterioration in device quality. Therefore, dielectric layer 155 can be beneficial for improving process quality.

[0112] refer to Figure 14A and Figure 14B ,in Figure 14A This is a schematic diagram of a semiconductor device. Figure 14B For along Figure 14AA cross-sectional view of line CC. A third implantation process IMP3 is performed to dope the pad region 110PA of semiconductor layer 110 through openings O1 in dielectric layers 150 and 155. In some embodiments, the implant in the third implantation process IMP3 may be an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb) and the like. That is, after the third implantation process IMP3 is completed, the pad region 110PA of semiconductor layer 110 is an n-type doped region. In some embodiments, the third implantation process IMP3 is performed at a power of 9 keV to approximately 12 keV (e.g., 10 keV) and at approximately 1 x 10⁻⁶ Ω. 15 cm -2 To approximately 2 x 10 15 cm -2 (e.g., 1x10) 15 cm -2 Dosage administration.

[0113] In some embodiments, the third implantation process IMP3 is performed by generating an implant perpendicular to the substrate 100. That is, the third implantation process IMP3 is performed without any tilt angle (e.g., tilt angle θ is 0°). In other words, the incident direction of the implant may be perpendicular to the top surface of the substrate 100 (or the top surface of the semiconductor layer 110).

[0114] As mentioned above, in such Figure 9A and Figure 9B During the first implantation process IMP1, the pad region 110PA of the semiconductor layer 110 can also be doped with an n-type dopant. However, because the area of ​​the pad region 110PA of the semiconductor layer 110 is too large, only the edge regions of the pad region 110PA in the semiconductor layer 110 can be doped. Therefore, a third implantation process IMP3 can be further performed to dope the pad region 110PA of the semiconductor layer 110 from the top surface of the pad region 110PA, so that the entire pad region 110PA of the semiconductor layer 110 can be doped with the desired implant.

[0115] After the third implantation process IMP3 is completed, an annealing process is performed to activate the implant in the source / drain regions 110SD of semiconductor layer 110 and the source / drain regions 120SD of semiconductor layer 120. In some embodiments, the annealing process may be a low-temperature microwave annealing (MWA) process. The annealing process may be performed at a temperature of about 400°C to about 550°C (e.g., 450°C), a power of about 1600W to about 1700W (e.g., 1650W), and a duration of about 80s to about 120s (e.g., 100s). In some embodiments, if the temperature is too high (e.g., much higher than 550°C), semiconductor layer 120 (e.g., Ge) may be damaged. If the temperature is too low (e.g., much lower than 400°C), the temperature may not be able to activate the source / drain regions. The low-temperature MWA process may be beneficial for improving the SS ratio, increasing the Ion / Ioff ratio, and suppressing implant over-diffusion.

[0116] After the activation process (or annealing process) is completed, the channel region 110CH, the source / drain region 110SD, and the gate structure 140A of the semiconductor layer 110 can be used together as a first transistor. On the other hand, the channel region 120CH, the source / drain region 120SD, and the gate structure 140B of the semiconductor layer 120 can be used together as a second transistor stacked on top of the first transistor.

[0117] As described above, the source / drain region 120SD of semiconductor layer 120 contains both n-type and p-type dopants. Consequently, after the activation process (or annealing process) is completed, Hall effect measurements are performed on the source / drain region 120SD of semiconductor layer 120 to determine the conductivity type of the source / drain region 120SD. Hall effect measurements can also be performed on samples of a larger scale, wherein the samples may also undergo the implantation and activation processes described above. The Hall effect is the phenomenon of an electromotive force generated transverse to both the current and the magnetic field when a magnetic field perpendicular to the current is applied, and it is primarily used to identify the carrier density, mobility, and conductivity type of a semiconductor. In some embodiments, phosphorus (P) is used at approximately 1 x 10⁻⁶. 15 cm -2 The dosage and power of approximately 10 keV were used in the first implantation process IMP1, with boron (B) at approximately 1 x 15 cm⁻¹. 2 The dosage and approximately 10 keV of energy were used in the second implantation process, IMP2. Measurements showed that the source / drain region at 120 SD exhibited P-type conductivity, with a carrier concentration (e.g., holes) of approximately 1 x 10⁻⁶. 19 cm -3On the other hand, the source / drain region 110SD of semiconductor layer 110 will exhibit n-type conductivity because the source / drain region 110SD contains only n-type dopants. As a result, the source / drain region 120SD of semiconductor layer 120 can be referred to as a p-type doped region, and the source / drain region 110SD of semiconductor layer 110 can be referred to as an n-type doped region. Here, "p-type doped region" can be referred to as a region using holes as charge carriers, and "n-type doped region" can be referred to as a region using electrons as charge carriers. Therefore, the first transistor at a lower energy level can be an n-type device, while the second transistor at a higher energy level can be a p-type device. In other embodiments, if the annealing process is omitted, the source / drain region 120SD can also exhibit p-type conductivity.

[0118] refer to Figure 15A and Figure 15B ,in Figure 15A This is a schematic diagram of a semiconductor device. Figure 15B For along Figure 15A A cross-sectional view of line CC. Mask MA4 is removed after the third implantation process IMP3 is completed. Dielectric layer 160 is formed on dielectric layer 155 and fills the openings O1 of dielectric layers 150 and 155. In some embodiments, dielectric layer 160 may comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borosilicate glass, low-k dielectric materials, and / or other suitable dielectric materials. In some embodiments, the deposition process may be a conformal deposition process, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like.

[0119] refer to Figure 16A , Figure 16B , Figure 16C and Figure 16D ,in Figure 16A This is a schematic diagram of a semiconductor device. Figure 16B For along Figure 16A The cross-sectional view of line AA. Figure 16C For along Figure 16A A cross-sectional view of line BB. Figure 16D For along Figure 16AA cross-sectional view of line CC. Conductive vias 171, 172, 173, 174, and 175 are formed in dielectric layers 150, 155, and 160. More specifically, conductive via 171 contacts a pad region 110PA of semiconductor layer 110. Conductive via 172 contacts a source / drain region 120SD of semiconductor layer 120. Conductive via 173 contacts the gate stack 140. Conductive via 174 contacts another source / drain region 120SD of semiconductor layer 120. Conductive via 175 contacts another pad region 110PA of semiconductor layer 110. In some embodiments, the source / drain region 110SD of semiconductor layer 110 can be electrically connected to the respective conductive vias 171 and 175 through the pad region 110PA in semiconductor layer 110.

[0120] Conductive vias 171, 172, 173, 174, and 175 can be formed, for example, by forming a patterned mask (not shown) on dielectric layer 160, wherein the patterned mask may include multiple openings corresponding to the locations of conductive vias 171, 172, 173, 174, and 175. An etching process is performed to remove portions of dielectric layers 150, 155, and 160 through the openings of the patterned mask, thereby forming openings in dielectric layers 150, 155, and 160 that expose pad regions 110PA of semiconductor layer 110, source / drain regions 120SD of semiconductor layer 120, and gate stack 140. The patterned mask is then removed, and conductive material is deposited in the openings of dielectric layers 150, 155, and 160. A planarization process such as CMP can be performed to remove excess conductive material outside the openings of dielectric layers 150, 155, and 160, and the portion of the conductive material remaining in the openings can be used as conductive vias 171, 172, 173, 174, and 175. Conductive vias 171, 172, 173, 174, and 175 may contain conductive materials such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive materials.

[0121] Conductive pads 181, 182, 183, and 184 are formed on dielectric layer 160. More specifically, conductive pad 181 may contact conductive vias 171 and 172. Conductive pad 182 may contact conductive via 173. Conductive pad 183 may contact conductive via 174. Conductive pad 184 may contact conductive via 175. Conductive pads 181, 182, 183, and 184 can be formed, for example, by depositing a conductive layer on dielectric layer 160 and then patterning the conductive layer according to a predetermined pattern. Conductive pads 181, 182, 183, and 184 may contain conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive materials.

[0122] In some embodiments, the first and second transistors, conductive vias 171, 172, 173, 174, and 175, and conductive pads 181, 182, 183, and 184 can collectively function as an inverter. For example, conductive pad 182 can be used as the input terminal V of the inverter. IN The conductive pad 183 can be used as the power supply terminal V of the second transistor. DD Conductive pad 184 can be used as the power supply terminal Vss of the first transistor, and conductive pad 181 can be used as the output terminal V of the inverter. DDT In some embodiments, the power supply terminal VDD is connected to a positive voltage, and the power supply terminal Vss is grounded.

[0123] Figure 17 This is a cross-sectional view of a semiconductor element according to some embodiments of the present disclosure. Figure 17 and Figure 16B The cross-sectional views are similar. Figure 17 Structure and Figure 16B The structural difference lies in, for example Figures 3 to 6 Following the etching process, semiconductor layers 110 and 120 may include a tapered cross-sectional profile. For example, with respect to semiconductor layer 110, the lateral width of semiconductor layer 110 may increase from the top to the bottom of semiconductor layer 110. In some embodiments, the bottom surface of semiconductor layer 110 is approximately 42 nm, the top surface of semiconductor layer 110 is approximately 33 nm, and the height of semiconductor layer 110 is approximately 33 nm. Similarly, the lateral width of semiconductor layer 120 may increase from the top to the bottom of semiconductor layer 120. In some embodiments, the bottom surface of semiconductor layer 120 is approximately 32 nm, the top surface of semiconductor layer 120 is approximately 19 nm, and the height of semiconductor layer 120 is approximately 42 nm.

[0124] Regarding the work function metal layers 146A and 146B, directional deposition processes (e.g., physical vapor deposition, PVD) can be used to deposit the work function metal layers 146A and 146B. Directional deposition can result in different deposition rates of the material in the work function metal layer 146B at different surfaces of the semiconductor layer 120. For example, regarding the work function metal layer 146B, the work function metal layer 146B may comprise a first portion on the top surface of the semiconductor layer 120, a second portion on opposite sidewalls of the semiconductor layer 120, and a third portion on the bottom surface of the semiconductor layer 120, wherein the first portion is thicker than the second portion, and the second portion is thicker than the third portion. In some embodiments, the thickness of the second portion is approximately 17 nm. On the other hand, the work function metal layer 146A may comprise a substantially uniform thickness.

[0125] Regarding filler metals 148A and 148B: Filler metals 148A and 148B may be different portions of a single material. However, during the deposition of filler metals 148A and 148B, an observable interface (reference dashed line) may exist within the single material of filler metals 148A and 148B.

[0126] Figures 18 to 24D This section describes methods in various stages of forming a semiconductor device according to some embodiments of this disclosure. It should be noted that... Figures 18 to 24D Some of the components are already referenced above. Figures 1 to 16D The discussion took place, and the components were labeled. For the sake of brevity, the relevant details will not be repeated.

[0127] refer to Figure 18 . Figure 18 Similar to Figure 2B , Figure 18 and Figure 2B The difference is Figure 18 The structure does not include a dielectric layer 105 and a semiconductor layer 102. That is, the semiconductor layer 110 can be used as a substrate.

[0128] refer to Figure 19 A first etching process E1 is performed to remove portions of the semiconductor layer 120 exposed by masks MA1 and MA2, thereby forming a recess R1 in the semiconductor layer 120. As a result of the first etching process E1, the etched semiconductor layer 120 may include a top 120T and a bottom 120B below the top 120T. (As mentioned above...) Figure 3 As mentioned above, oxygen (O2) is used in the first etching process E1, so the oxide layer 130 can be formed on the exposed surface of the semiconductor layer 120 as a byproduct of the first etching process E1.

[0129] refer to Figure 20 After the first etching process E1 is completed, a second etching process E2 is performed to remove the horizontal portion of the oxide layer 130, thereby exposing the bottom 120B of the semiconductor layer 120. Once the horizontal portion of the oxide layer 130 is removed, the second etching process E2 removes the exposed bottom 120B of the semiconductor layer 120 until the underlying semiconductor layer 110 is exposed.

[0130] refer to Figure 21 After completing the second etching process E2, a third etching process E3 is performed to remove the bottom 120B of the semiconductor layer 120. As a result of the third etching process E3, the semiconductor layer 120 is vertically separated from the semiconductor layer 110.

[0131] refer to Figure 22After completing the third etching process E3, a fourth etching process E4 is performed to remove the portion of the semiconductor layer 110 exposed through the top 120T (or masks MA1 and MA2) of the semiconductor layer 120, thereby forming a protrusion 110P protruding from the top surface of the semiconductor layer 110. In some embodiments, the protrusion 110P may also be referred to as a fin structure on the semiconductor layer 110.

[0132] As mentioned above Figure 6 As oxygen (O2) is used in the fourth etching process E4, oxide layers 131 and 132 can be formed on the exposed surfaces of semiconductor layer 110 and semiconductor layer 120, respectively, as byproducts of the fourth etching process E4. More specifically, oxide layer 131 can be arranged on the top surface of semiconductor layer 110 and also on the top surface and sidewalls of protrusion 110P.

[0133] refer to Figure 23 After the etching process is completed, masks MA1 and MA2 are removed from the top surface of semiconductor layer 120. Furthermore, a pre-cleaning process is performed to remove oxide layers 130, 131, and 132, thereby exposing the surfaces of semiconductor layers 110 and 120, resulting in the structure shown below. Figure 23 As shown.

[0134] Subsequently, an isolation structure 106 is formed on the semiconductor layer 110 and laterally surrounds the protrusion 110P. The isolation structure 106 can be formed, for example, by depositing a dielectric material on the semiconductor layer 110 and then etching back the dielectric material to lower the top surface of the dielectric material to a desired position. In some embodiments, the top surface of the isolation structure 106 is lower than the top surface of the protrusion 110P. That is, the isolation structure 106 laterally surrounds the bottom of the protrusion 110P, while the upper part of the protrusion 110P may protrude from the top surface of the isolation structure 106. The isolation structure 106 may also be referred to as a shallow trench isolation (STI) structure.

[0135] refer to Figure 24A , Figure 24B , Figure 24C and Figure 24D ,in Figure 24A This is a schematic diagram of a semiconductor device. Figure 24B For along Figure 24A The cross-sectional view of line AA. Figure 24C For along Figure 24A The cross-sectional view of line BB. Figure 24D For along Figure 16A Cross-sectional view of line CC. Figure 23 The structure can undergo such Figures 8A to 16D The process described above results in a structure as follows: Figure 24A , Figure 24B , Figure 24C and Figure 24D As shown. Figures 24A to 24D Structure and Figures 16A to 16D The difference in structure is that, Figures 16A to 16D In the structure, the dielectric layer 105 is disposed below the bottom surface of the semiconductor layer 110. On the other hand, in Figures 24A to 24D In the structure, the isolation structure 106 is disposed above the semiconductor layer 110 and laterally surrounds the protruding portion 110P of the semiconductor layer 110.

[0136] Figure 25A and Figure 25B Simulation results are shown for semiconductor devices according to some embodiments of this disclosure. More specifically, Figure 25A and Figure 25B for Figures 16A to 16D The simulation results of the semiconductor components discussed in the paper.

[0137] Figure 25A Explanation as follows Figures 16A to 16D The drain current (I) of the semiconductor device under different drain voltages (VD) D ) and gate voltage (V G The relationship between the work function metal layers 146A and 146B and the drain current (I) can be observed. It can be seen that if the work function metal layers 146A and 146B are made of the same material, then the drain current (I) will be... D ) for gate voltage (V G This demonstrates the current symmetry between Si-nFinFETs (e.g., the first transistor) and Ge-NW-pGAAFETs (e.g., the second transistor). Furthermore, the threshold voltages of these devices are substantially the same.

[0138] Figure 25B Explanation as follows Figures 16A to 16D The semiconductor element at different power supply voltages (V GG Output voltage (V) under ) ouT ) and input voltage (V IN The relationship between the work function metal layers 146A and 146B and the output voltage (V) can be observed. It can be seen that if the work function metal layers 146A and 146B are made of the same material, then the output voltage (V) will be... ouT ) and input voltage (V IN It exhibits symmetry. For example, at the supply voltage (V) GG Under the condition that the input voltage (V) is 0.5V, when the input voltage (V) IN When the voltage is 0V, the output voltage (V) ouT ) is Vow-i, while when the output voltage (V ouT When ) is 0, the input voltage (V) IN ) is V IN1 In some embodiments, VOUT1 is substantially equal to V INIFor example, approximately 0.5V. At the supply voltage (V... GG When the input voltage (V) is 0.75V, IN When the voltage is 0V, the output voltage (V) ouT ) is V OUT2 When the output voltage (V) ouT When ) is 0, the input voltage (V) IN ) is V IN2 In some embodiments, V ouT2 Essentially equal to V IN2 For example, approximately 0.75V. At the power supply voltage (V... GG When the input voltage (V) is 1V, IN When the voltage is 0V, the output voltage (V) ouT ) is Voun, and when the output voltage (V ouT When ) is 0, the input voltage (V) IN ) is V IN3 In some implementations, \Toon is essentially equal to V. IN3 For example, approximately 1V.

[0139] Based on the above embodiments, it can be seen that this disclosure provides advantages for manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, and specific advantages are not required for all embodiments. Embodiments of this disclosure provide a method for forming a CFET device. The method includes forming a second semiconductor layer directly on a first semiconductor layer and using a four-step etching process to separate the second semiconductor layer and the first semiconductor layer. The method further includes performing a first implantation process with a tilt angle to successfully dope the first semiconductor layer at a lower level, followed by performing a second implantation process without a tilt angle to dope the second semiconductor layer at a higher level. The method further includes forming a work function metal layer of the first semiconductor layer and the second semiconductor layer with the same material, and can achieve substantially the same critical voltage for different transistors, further reducing manufacturing complexity.

[0140] In some embodiments disclosed herein, a method includes forming a second semiconductor layer on a first semiconductor layer; performing a first etching process to form a groove in the second semiconductor layer such that the second semiconductor layer includes a bottom and a top above the bottom, wherein the first etching process causes a first dielectric layer to be formed on opposite sidewalls of the top; performing a second etching process to narrow the bottom of the second semiconductor layer; performing a third etching process to remove the bottom of the second semiconductor layer; performing a fourth etching process to narrow the first semiconductor layer; and forming a first gate structure on the first semiconductor layer and a second gate structure on the second semiconductor layer, respectively.

[0141] In some embodiments, during a first etching process, a first dielectric layer is further formed on the top surface of the bottom of the second semiconductor layer, and a second etching process is performed such that a portion of the first dielectric layer on the top surface of the bottom of the second semiconductor is removed, while after the second etching process is completed, a portion of the first dielectric layer on the opposite sidewall of the top of the second semiconductor is retained.

[0142] In some embodiments, the method further includes removing the first dielectric layer before forming the first gate structure and the second gate structure.

[0143] In some embodiments, the fourth etching process results in the formation of a second dielectric layer on the exposed surface of the first semiconductor layer and a third dielectric layer on the bottom surface above the second semiconductor layer. Removing the first dielectric layer also includes removing the second and third dielectric layers.

[0144] In some embodiments, the second semiconductor layer is formed in contact with the first semiconductor layer, and the first semiconductor layer and the second semiconductor layer are made of different semiconductor materials.

[0145] In some embodiments, the method further includes forming a mask on the second semiconductor layer before performing the first etching process; and removing the mask after the fourth etching process is completed.

[0146] In some embodiments, the first dielectric layer is an oxide of the material of the second semiconductor layer.

[0147] In some implementations, the first etching process includes the use of chlorine and oxygen. The second etching process includes the use of chlorine. The third etching process includes the use of chlorine and hydrogen bromide. The fourth etching process includes the use of chlorine and oxygen.

[0148] In some embodiments disclosed herein, a method includes forming a second semiconductor layer perpendicularly above a first semiconductor layer on a substrate; forming a first gate structure on the first semiconductor layer and a second gate structure above the second semiconductor layer; performing a first implantation process to dope a first source / drain region of the first semiconductor layer and a second source / drain region of the second semiconductor layer with an n-type dopant, wherein the incident direction of the n-type dopant is tilted at a non-zero angle relative to the normal of the top surface of the substrate; and performing a second implantation process to dope the second source / drain region of the second semiconductor layer with a p-type dopant, wherein the incident direction of the p-type dopant is substantially perpendicular to the top surface of the substrate.

[0149] In some embodiments, the method further includes performing an annealing process to activate a first source / drain region of a first semiconductor layer and a second source / drain region of a second semiconductor layer, wherein after the annealing process is completed, the first source / drain region in the first semiconductor layer exhibits n-type conductivity, while the second source / drain region of the second semiconductor layer exhibits p-type conductivity.

[0150] In some embodiments, during the second implantation process, the second semiconductor layer blocks p-type dopants from reaching the first semiconductor layer.

[0151] In some embodiments, prior to performing the second implantation process, a dielectric layer is formed to fill the space between the first semiconductor layer and the second semiconductor layer.

[0152] In some embodiments, the dielectric layer covers the top surface of the second semiconductor layer.

[0153] In some embodiments, forming a second semiconductor layer vertically over a first semiconductor layer on a substrate includes: forming a second semiconductor material over a first semiconductor material; etching the second semiconductor material such that the second semiconductor layer includes a bottom and a top above the bottom, the bottom being wider than the top, wherein etching the second semiconductor material causes an oxide layer to be formed on the opposite sidewall of the top; removing the bottom of the second semiconductor material; and etching the first semiconductor material.

[0154] In some embodiments, the first semiconductor layer is made of silicon and the second semiconductor layer is made of germanium.

[0155] In some embodiments disclosed herein, a semiconductor device includes a first transistor located above a substrate and a second transistor vertically located above the first transistor. The first transistor includes a first semiconductor layer and a first gate structure. The first semiconductor layer includes a first channel region and a first source / drain region, and the first gate structure is located above the first channel region of the first semiconductor layer. The first semiconductor layer exhibits n-type conductivity. The second transistor includes a second semiconductor layer with a second channel region and a second source / drain region, and a second gate structure on the second channel region of the second semiconductor layer. The second semiconductor layer exhibits p-type conductivity, and some n-type dopants from the first source / drain regions of the first semiconductor layer can be detected in the second source / drain region of the second semiconductor layer.

[0156] In some embodiments, the first gate structure contacts three sides of the first channel region, and the second gate structure contacts four sides of the second channel region.

[0157] In some embodiments, the first semiconductor layer and the second semiconductor layer are made of different semiconductor materials.

[0158] In some embodiments, the first gate structure includes a first interface layer in contact with the first channel region, a first high-k dielectric layer on the first interface layer, a work function metal layer on the first high-k dielectric layer, and a first fill metal on the first work function metal layer. The second gate structure includes a second interface layer in contact with the second channel region, a second high-k dielectric layer on the second interface, a second work function metal layer on the second high-k dielectric layer, and a second fill metal on the second work function metal layer. The first interface layer and the second interface layer are made of different materials.

[0159] In some embodiments, the first work function metal layer and the second work function metal layer are made of the same material.

[0160] In some embodiments disclosed herein, a semiconductor device includes a first transistor having n-type conductivity located above a substrate and a second transistor having p-type conductivity vertically located above the first transistor. The first transistor includes a first semiconductor layer and a first gate structure. The first semiconductor layer includes a first channel region and a first source / drain region, and the first gate structure is located above the first channel region of the first semiconductor layer. The second transistor includes a second semiconductor layer with a second channel region and a second source / drain region, and a second gate structure on the second channel region of the second semiconductor layer. A first dielectric layer covers the first transistor and the second transistor. A second dielectric layer is located above the first dielectric layer. A third dielectric layer contacts the first and second dielectric layers.

[0161] In some embodiments, the first gate structure contacts three sides of the first channel region, and the second gate structure contacts four sides of the second channel region.

[0162] In some embodiments, the first gate structure includes a first interface layer in contact with the first channel region, a first high-k dielectric layer on the first interface layer, a work function metal layer on the first high-k dielectric layer, and a first fill metal on the first work function metal layer. The second gate structure includes a second interface layer in contact with the second channel region, a second high-k dielectric layer on the second interface, a second work function metal layer on the second high-k dielectric layer, and a second fill metal on the second work function metal layer.

[0163] In some embodiments, the first gate structure contacts the second gate structure.

[0164] In some embodiments, the semiconductor element further includes an output terminal electrically connected to a first source / drain region of a first semiconductor layer and a first source / drain region of a second semiconductor layer. An input terminal is electrically connected to a first gate structure and a second gate structure. A first power supply terminal is electrically connected to a second source / drain region of the first semiconductor layer. A second power supply terminal is electrically connected to a second of the plurality of source / drain regions of the second semiconductor layer.

[0165] In some embodiments disclosed herein, a semiconductor device includes a first transistor having n-type conductivity located above a substrate and a second transistor having p-type conductivity vertically located above the first transistor. The first transistor includes a first semiconductor layer and a first gate structure. The first semiconductor layer includes a first channel region and a first source / drain region, and the first gate structure is located above the first channel region of the first semiconductor layer. The second transistor includes a second semiconductor layer with a second channel region and a second source / drain region, and a second gate structure on the second channel region of the second semiconductor layer. A first dielectric layer covers the first transistor and the second transistor. A second dielectric layer is located above the first dielectric layer. A third dielectric layer contacts the first and second dielectric layers. The first gate structure contacts three sides of the first channel region, and the second gate structure contacts four sides of the second channel region.

[0166] In some embodiments, the first gate structure includes a first interface layer in contact with the first channel region, a first high-k dielectric layer on the first interface layer, a work function metal layer on the first high-k dielectric layer, and a first fill metal on the first work function metal layer. The second gate structure includes a second interface layer in contact with the second channel region, a second high-k dielectric layer on the second interface, a second work function metal layer on the second high-k dielectric layer, and a second fill metal on the second work function metal layer.

[0167] In some embodiments, the first gate structure contacts the second gate structure.

[0168] In some embodiments, the semiconductor element further includes an output terminal electrically connected to a first source / drain region of a first semiconductor layer and a first source / drain region of a second semiconductor layer. An input terminal is electrically connected to a first gate structure and a second gate structure. A first power supply terminal is electrically connected to a second source / drain region of the first semiconductor layer. A second power supply terminal is electrically connected to a second of the plurality of source / drain regions of the second semiconductor layer.

[0169] In some embodiments disclosed herein, a semiconductor device includes a first transistor having n-type conductivity located above a substrate and a second transistor having p-type conductivity vertically located above the first transistor. The first transistor includes a first semiconductor layer and a first gate structure. The first semiconductor layer includes a first channel region and a first source / drain region, and the first gate structure is located above the first channel region of the first semiconductor layer. The second transistor includes a second semiconductor layer with a second channel region and a second source / drain region, and a second gate structure on the second channel region of the second semiconductor layer. A first dielectric layer covers the first transistor and the second transistor. A second dielectric layer is located above the first dielectric layer. A third dielectric layer contacts the first and second dielectric layers. An output terminal is electrically connected to a first of the source / drain regions of the first semiconductor layer and a first of the source / drain regions of the second semiconductor layer. An input terminal is electrically connected to the first gate structure and the second gate structure. A first power supply terminal is electrically connected to a second of the source / drain regions of the first semiconductor layer. A second power supply terminal is electrically connected to a second of the plurality of source / drain regions of the second semiconductor layer.

[0170] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor element characterized by comprising: Comprising: a first transistor having n-type conductivity over a substrate and comprising: a first semiconductor layer including a first channel region and a plurality of first source / drain regions; and a first gate structure over the first channel region of the first semiconductor layer; a second transistor having p-type conductivity vertically over the first transistor and comprising: a second semiconductor layer including a second channel region and a plurality of second source / drain regions; and a second gate structure over the second channel region of the second semiconductor layer; a first dielectric layer covering the first transistor and the second transistor; a second dielectric layer over the first dielectric layer; and a third dielectric layer contacting the first dielectric layer and the second dielectric layer. wherein the first gate structure contacts three sides of the first channel region, and the second gate structure contacts four sides of the second channel region.

2. The semiconductor device according to claim 1, wherein wherein:

3. The semiconductor device according to claim 1, wherein the first gate structure comprises: a first interface layer contacting the first channel region; a first high-k dielectric layer over the first interface layer; a first work function metal layer over the first high-k dielectric layer; and a first fill metal over the first work function metal layer; and the second gate structure comprises: a second interface layer contacting the second channel region; a second high-k dielectric layer over the second interface layer; a second work function metal layer over the second high-k dielectric layer; and a second fill metal over the second work function metal layer. wherein the first gate structure contacts the second gate structure. further comprising: an output terminal electrically connected to a first one of the plurality of first source / drain regions of the first semiconductor layer and a first one of the plurality of second source / drain regions of the second semiconductor layer; 4. The semiconductor device according to claim 1, wherein an input terminal electrically connected to the first gate structure and the second gate structure; 5. The semiconductor device according to claim 1, wherein a first power supply terminal electrically connected to a second one of the plurality of first source / drain regions of the first semiconductor layer; and a second power supply terminal electrically connected to a second one of the plurality of second source / drain regions of the second semiconductor layer. Comprising: a first transistor having n-type conductivity over a substrate and comprising: a first semiconductor layer including a first channel region and a plurality of first source / drain regions; and a first gate structure over the first channel region of the first semiconductor layer, wherein the first gate structure contacts three sides of the first channel region; 6. A semiconductor element characterized by comprising: a second transistor having p-type conductivity vertically over the first transistor and comprising: a second semiconductor layer including a second channel region and a plurality of second source / drain regions; and a second gate structure over the second channel region of the second semiconductor layer, wherein the second gate structure contacts four sides of the second channel region; a first dielectric layer covering the first transistor and the second transistor; a second dielectric layer over the first dielectric layer; and a third dielectric layer contacting the first dielectric layer and the second dielectric layer. wherein: the first gate structure comprises: a first interface layer contacting the first channel region; a first high-k dielectric layer over the first interface layer; a first work function metal layer over the first high-k dielectric layer; and 7. The semiconductor device according to claim 6, wherein a first fill metal over the first work function metal layer; and the second gate structure comprises: a second interface layer contacting the second channel region; a second high-k dielectric layer over the second interface layer; a second work function metal layer over the second high-k dielectric layer; and a second fill metal over the second work function metal layer. wherein the first gate structure contacts the second gate structure. a first interface layer in contact with the first channel region; a first high-k dielectric layer over the first interface layer; a first work function metal layer over the first high-k dielectric layer; and a first fill metal over the first work function metal layer; and the second gate structure comprises: a second interface layer in contact with the second channel region; a second high-k dielectric layer over the second interface layer; a second work function metal layer over the second high-k dielectric layer; and a second fill metal over the second work function metal layer.

8. The semiconductor device according to claim 6, wherein wherein the first gate structure contacts the second gate structure.

9. The semiconductor device according to claim 6, wherein further comprising: an output terminal electrically connected to a first one of the plurality of first source / drain regions of the first semiconductor layer and a first one of the plurality of second source / drain regions of the second semiconductor layer; an input terminal electrically connected to the first gate structure and the second gate structure; a first power terminal electrically connected to a second one of the plurality of first source / drain regions of the first semiconductor layer; and a second power terminal electrically connected to a second one of the plurality of second source / drain regions of the second semiconductor layer.

10. A semiconductor element characterized by comprising: comprising: a first transistor having n-type conductivity on a substrate and comprising: a first semiconductor layer comprising a first channel region and a plurality of first source / drain regions; and a first gate structure over the first channel region of the first semiconductor layer; a second transistor having p-type conductivity vertically over the first transistor and comprising: a second semiconductor layer comprising a second channel region and a plurality of second source / drain regions; and a second gate structure over the second channel region of the second semiconductor layer; a first dielectric layer covering the first transistor and the second transistor; a second dielectric layer over the first dielectric layer; a third dielectric layer contacting the first dielectric layer and the second dielectric layer; an output terminal electrically connected to a first one of the plurality of first source / drain regions of the first semiconductor layer and a first one of the plurality of second source / drain regions of the second semiconductor layer; an input terminal electrically connected to the first gate structure and the second gate structure; a first power terminal electrically connected to a second one of the plurality of first source / drain regions of the first semiconductor layer; and a second power terminal electrically connected to a second one of the plurality of second source / drain regions of the second semiconductor layer.

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