Semiconductor device with contact field plate

Abstract

The semiconductor device includes a body region and a drift region on a substrate, a source structure, a drain structure, a gate structure, an interlayer dielectric layer, a plurality of contact field plate contacts, and a subsequent process structure. A source structure is disposed within the body region and a drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plate contacts having at least a first row and a second row are within the interlayer dielectric layer on the dielectric layer, wherein each of the contact field plate contacts is configured to manipulate an electric field generated by the gate structure. The back-end structure is disposed on the interlayer dielectric layer and includes at least one conductive metal layer coupling the first and second rows of contact field plate contacts to the source structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device having a contact field plate. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid and sustained growth in recent years. Advances in IC materials and design technologies have led to continuous improvements in ICs. With each new generation of circuits, they become smaller and more complex, achieving higher functional density (i.e., the number of interconnect devices per wafer region) and smaller geometric dimensions (i.e., the smallest components or lines that can be formed using manufacturing processes). This miniaturization process improves production efficiency and reduces associated costs. However, as feature sizes continue to shrink, manufacturing processes become increasingly challenging, and ensuring the reliability of semiconductor devices becomes increasingly difficult. Therefore, the industry continues to face the challenge of developing processes to manufacture smaller, more reliable integrated circuits. Utility Model Content

[0003] This disclosure provides a semiconductor device. The semiconductor device includes a body region, a drift region, a source structure, a drain structure, a gate structure, an interlayer dielectric layer, a plurality of contact field plates, and a back-end processing structure. The body region and the drift region are on a substrate. The source structure is disposed within the body region and the drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region, and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plates having at least a first row and a second row are disposed within the interlayer dielectric layer on the dielectric layer, wherein each of the contact field plates is configured to manipulate an electric field generated by the gate structure. The back-end processing structure is disposed on the interlayer dielectric layer and includes at least one conductive metal layer coupling the first row and the second row of contact field plates to the source structure.

[0004] This disclosure also provides a semiconductor device. The semiconductor device includes a body region, a drift region, a source structure, a gate structure, an interlayer dielectric layer, and a plurality of contact field plate contacts. The body region and the drift region are on a substrate. The source structure is disposed within the body region and the drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region, and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plate contacts having at least a first row are located within the interlayer dielectric layer on the dielectric layer, wherein each of the contact field plate contacts is configured to manipulate an electric field generated by the gate structure, and wherein at least a portion of the contact field plate contacts is electrically isolated from the source structure.

[0005] This disclosure further provides a semiconductor device. The semiconductor device includes a body region, a drift region, a source structure, a gate structure, an interlayer dielectric layer, a plurality of contact field plate contacts, and a back-end processing structure. The body region and the drift region are on a substrate. The source structure is disposed within the body region and the drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region, and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plate contacts having at least a first row are disposed within the interlayer dielectric layer on the dielectric layer, wherein each of the contact field plate contacts is configured to manipulate an electric field generated by the gate structure. The back-end processing structure is disposed on the interlayer dielectric layer, and the back-end processing structure includes interconnect structures extending through the back-end processing structure, the interconnect structures being associated with the first row of contact field plate contacts, wherein at least one disconnection in the interconnect structure causes the contact field plate contacts to float. Attached Figure Description

[0006] When with attachment Figure 1 To best understand the various aspects of this disclosure, please refer to the following detailed description. It should be noted that, in accordance with industry standard practice, the various features may not be drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 A cross-sectional view schematically showing a portion of a first semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0008] Figure 2 The illustration schematically shows, according to some embodiments, Figure 1 Top cross-sectional view of the first semiconductor device;

[0009] Figure 3 A cross-sectional view schematically showing a portion of a second semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0010] Figure 4 A cross-sectional view schematically showing a portion of a third semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0011] Figure 5 A cross-sectional view schematically showing a portion of a fourth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0012] Figure 6 A cross-sectional view schematically showing a portion of a fifth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0013] Figure 7A cross-sectional view schematically showing a portion of a sixth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0014] Figure 8 A cross-sectional view schematically showing a portion of a seventh semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0015] Figure 9 A cross-sectional view schematically showing a portion of an eighth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0016] Figure 10 A cross-sectional view schematically showing a portion of a ninth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0017] Figure 11 A top cross-sectional view schematically shown of a portion of a tenth semiconductor device in a stage of an integrated circuit manufacturing process, according to some embodiments.

[0018] Figure 12 A top cross-sectional view schematically showing a portion of an eleventh semiconductor device in a stage of an integrated circuit manufacturing process, according to some embodiments.

[0019] Figure 13 A top cross-sectional view schematically showing a portion of a twelfth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0020] Figure 14 A top cross-sectional view schematically showing a portion of a thirteenth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0021] Figure 15 A top cross-sectional view schematically showing a portion of a fourteenth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0022] Figure 16 , Figure 17 , Figure 18 and Figure 19 A cross-sectional view of a fifteenth semiconductor device is schematically shown in a plurality of stages of a first exemplary method according to some embodiments;

[0023] Figure 20 , Figure 21 , Figure 22 and Figure 23A cross-sectional view of a sixteenth semiconductor device is schematically shown in a plurality of stages of a second exemplary method according to some embodiments;

[0024] Figure 24 A flowchart illustrating a third exemplary method for forming a semiconductor device according to some embodiments;

[0025] Figure 25 A top cross-sectional view schematically showing a portion of a seventeenth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments;

[0026] Figure 26 A top cross-sectional view schematically illustrating a portion of an eighteenth semiconductor device in a stage of an integrated circuit manufacturing process according to some embodiments; and

[0027] Figure 27 A top cross-sectional view schematically illustrates a portion of a nineteenth semiconductor device in a stage of an integrated circuit manufacturing process, according to some embodiments.

[0028] [Symbol Explanation]

[0029] 100: Laterally diffused metal-oxide-semiconductor transistor device

[0030] 102: Substrate

[0031] 104: Source Structure

[0032] 105: Gate structure

[0033] 106: Drain structure

[0034] 108: Gate electrode

[0035] 110: Gate dielectric layer

[0036] 112: Sidewall gap material

[0037] 114: Main Area

[0038] 116: Drift Area

[0039] 118: Interlayer dielectric layer

[0040] 120: Shallow trench isolation features

[0041] 122: Source Contact

[0042] 124: Dielectric layer

[0043] 126: Contact field plate contact

[0044] 128: Drain contact

[0045] 129: Metal layer

[0046] 130: Gate contact

[0047] 131: Metal layer

[0048] 132: First intermetallic dielectric layer

[0049] 133: Through hole

[0050] 134: Metal layer

[0051] 135: Metal layer

[0052] 300: Laterally diffused metal-oxide-semiconductor transistor device

[0053] 310: Metal layer

[0054] 312: Metal layer

[0055] 400: Laterally diffused metal-oxide-semiconductor transistor device

[0056] 400A: Laterally diffused metal-oxide-semiconductor transistor device

[0057] 400B: Laterally diffused metal-oxide-semiconductor transistor device

[0058] 400C: Laterally diffused metal-oxide-semiconductor transistor device

[0059] 400D: Laterally diffused metal-oxide-semiconductor transistor device

[0060] 400E: Laterally diffused metal-oxide-semiconductor transistor device

[0061] 400F: Laterally diffused metal-oxide-semiconductor transistor device

[0062] 410: Metal layer

[0063] 411: First through hole

[0064] 412: Second through hole

[0065] 414: Third through hole

[0066] 416: Second metal layer

[0067] 418: Third metal layer

[0068] 420: Fourth metal layer

[0069] 422: First metal layer

[0070] 424: First intermetallic dielectric layer

[0071] 426: Second intermetallic dielectric layer

[0072] 428: Third intermetallic dielectric layer

[0073] 1100: Laterally diffused metal-oxide-semiconductor transistor device

[0074] 1110: Third metal layer

[0075] 1112: Fourth metal layer

[0076] 1114: Second metal layer

[0077] 1118: First metal layer

[0078] 1200: Laterally diffused metal-oxide-semiconductor transistor device

[0079] 1210: First metal layer

[0080] 1212: Second metal layer

[0081] 1214: Third metal layer

[0082] 1216: Through hole

[0083] 1218: Through hole

[0084] 1220: Through hole

[0085] 1300: Laterally diffused metal-oxide-semiconductor transistor device

[0086] 1310: First metal layer

[0087] 1312: Second metal layer

[0088] 1314: Third metal layer

[0089] 1316: Through hole

[0090] 1318: Through hole

[0091] 1320: Through hole

[0092] 1400: Laterally diffused metal-oxide-semiconductor transistor device

[0093] 1410: First metal layer

[0094] 1412: Second metal layer

[0095] 1414: Third metal layer

[0096] 1416: Through hole

[0097] 1418: Through hole

[0098] 1420: Through hole

[0099] 1500: Laterally diffused metal-oxide-semiconductor transistor device

[0100] 1510: First metal layer

[0101] 1512: Second metal layer

[0102] 1514: Third metal layer

[0103] 1516: Through hole

[0104] 1518: Through hole

[0105] 1520: Through hole

[0106] 1600: Structure

[0107] 1610: First masking layer

[0108] 1612: Opening

[0109] 1614: Opening

[0110] 1616: Open

[0111] 1618: Opening

[0112] 1620: Opening

[0113] 1622: Opening

[0114] 1700: Structure

[0115] 1712: Opening

[0116] 1714: Opening

[0117] 1716: Opening

[0118] 1800: Structure

[0119] 1900: Structure

[0120] 2000: Structure

[0121] 2010: First masking layer

[0122] 2012: Opening

[0123] 2018: Opening

[0124] 2020: Opening

[0125] 2022: Opening

[0126] 2100: Structure

[0127] 2112: Opening

[0128] 2200: Structure

[0129] 2300: Structure

[0130] 2400: Method

[0131] 2410: Square

[0132] 2412: Square

[0133] 2414: Square

[0134] 2416: Square

[0135] 2418: Square

[0136] 2420: Square

[0137] 2422: Square

[0138] 2424: Square Detailed Implementation

[0139] The following disclosure provides many different implementations or examples for achieving different features of the provided object. Specific examples of elements and compositions are described below to simplify this disclosure. Of course, these are merely examples and are not intended to limit this disclosure. For example, in the following description, forming a first feature on or over a second feature can include implementations where the first and second features are formed through direct contact, or implementations where an additional feature can be formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not in itself specify a relationship between the various implementations and / or configurations discussed.

[0140] The terms “first,” “second,” and “third,” as used herein, may describe various elements, components, regions, layers, and / or parts, but these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another. The use of the terms “first,” “second,” and “third,” etc., in this document does not imply their order or sequence unless explicitly stated in the text.

[0141] For the sake of brevity, this document may not describe in detail the conventional techniques associated with the manufacture of traditional semiconductor devices. Furthermore, the various operations and processes described herein may be incorporated into a more comprehensive process or workflow, which may have additional functionalities not described in detail herein. In particular, various processes in semiconductor device manufacturing are well-known; therefore, for the sake of brevity, many conventional processes are briefly mentioned or omitted entirely without providing well-known process details. As will be apparent to those skilled in the art upon a full reading of this disclosure, the structure of this disclosure may be used with various techniques and may be incorporated into various semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of elements, and a single element shown in a figure may represent multiple elements.

[0142] In addition, for ease of description, this document may use spatial relative terms such as “above,” “overlapping,” “up,” “above,” “top,” “top,” “below,” “submerged,” “under,” “below,” and “bottom,” to describe the relationship between one element or feature and another element or feature shown in the figures. Besides the orientations described in the figures, spatial relative terms are also intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatial relative terms used herein will be interpreted accordingly. When spatial relative terms (such as those listed above) are used to describe the first element relative to the second element, the first element may be directly on top of the other element, or there may be an intermediate element or layer. When an element or layer is said to be located on top of another element or layer, it may be directly on top of and in contact with the other element or layer.

[0143] It should be noted that terms such as "an embodiment," "an implementation," "an exemplary embodiment," "example," and "concept" mentioned in the specification indicate that the embodiment may include specific features, structures, or properties, but not every embodiment necessarily includes specific features, structures, or properties. Furthermore, these terms do not necessarily refer to the same embodiment. In addition, when specific features, structures, or properties related to an embodiment are described, those generally skilled in the art may influence those features, structures, or properties in other embodiments, whether explicitly described or not.

[0144] Some embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein similar reference numerals are generally used to refer to similar elements. In the following description, numerous specific details are set forth for ease of explanation in order to provide a thorough understanding of the claimed subject matter. However, it will be apparent that the claimed subject matter may be implemented without these specific details. In other instances, structures and apparatus may be shown graphically in block diagrams to facilitate the description of the claimed subject matter.

[0145] Additional operations may be provided before, between, and / or after the stages described in the implementation. Some of the described stages may be replaced or eliminated in different implementations. Additional functionality may be added to the semiconductor device structure. Some features described below may be replaced or eliminated in different implementations. Although some implementations are described with operations performed in a specific order, these operations may be performed in another logical order.

[0146] As used in this article, a “layer” is a region, such as a region with arbitrary boundaries, and not necessarily with uniform thickness. For example, a layer may be a region that includes at least some variation in thickness.

[0147] High-voltage transistor devices are typically constructed with a field plate. The field plate is a conductive element disposed on the channel region to enhance the performance of the high-voltage transistor device by manipulating the electric field generated by the gate electrode (e.g., reducing the peak electric field). By manipulating the electric field generated by the gate electrode, the high-voltage transistor device may therefore exhibit higher breakdown voltages. For example, laterally diffused metal-oxide-semiconductor (LDMOS) transistor devices typically include a field plate that extends from the channel region to an adjacent drift region disposed between the channel region and the drain structure.

[0148] Field plates can be formed using various methods. For example, multiple aligned contact fieldplate electrodes can be electrically coupled to a common source electrode via a conductive material. However, this arrangement can lead to a linear drain current (Id). dlin The attenuation of the linear drain current (Id) reduces the efficiency of contact field plate devices in various applications, such as when used in buck converters. dlin ) is the drain current in the linear region measured when the device is biased.

[0149] This document describes a semiconductor structure and a method for forming the semiconductor structure, wherein the semiconductor structure has a structure related to the field plate structure to reduce the linear drain current (I0). dlin The attenuation of the semiconductor structure is as follows: In various embodiments, the semiconductor structure includes additional contact field plate electrodes and / or contact field plate electrodes that are not electrically coupled to the source electrode.

[0150] Figure 1Cross-sectional views of some embodiments of a semiconductor device are shown, wherein the semiconductor device includes a laterally diffused metal-oxide-semiconductor transistor device 100 having multiple rows of contact field plate (CFP) contacts 126. The semiconductor device shown may be a stage in an integrated circuit manufacturing process. The figure shows a portion of a semiconductor device having circuitry formed in and / or on a substrate 102. The substrate 102 may be one of many types of semiconductor substrates commonly used in semiconductor integrated circuit manufacturing, and integrated circuits may be formed therein and / or on it. The semiconductor substrate may be any structure comprising semiconductor materials, such as, but not limited to, bulk silicon, semiconductor wafers, silicon-on-insulator (SOI) substrates, or silicon-germanium substrates. Other semiconductor materials may also be used, such as materials comprising group III, group IV, and / or group V semiconductors.

[0151] The laterally diffused metal-oxide-semiconductor transistor device 100 includes a source region, or source structure 104, and a drain region, or drain structure 106, disposed within a semiconductor substrate 102. The semiconductor substrate 102 may have a first doping type, while the source structure 104 and drain structure 106 may include highly doped regions having a second doping type different from the first doping type. In some embodiments, the first doping type may be p-type, and the second doping type may be n-type. In other embodiments, the first doping type may be n-type, and the second doping type may be p-type.

[0152] Various electrical components may be formed on substrate 102. Examples of electrical components may include active devices, such as transistors and diodes, and passive devices, such as capacitors, inductors, and resistors. Substrate 102 may include functional regions separated by isolation features, such as shallow trench isolation (STI) features (e.g., shallow trench isolation feature 120), and the functional regions may include microelectronic components formed in and / or on substrate 102. Examples of types of microelectronic components formed in substrate 102 may include, but are not limited to, transistors, such as metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel field effect transistors (PFETs) and / or n-channel field effect transistors (NFETs), resistors, diodes, capacitors, inductors, fuses, and / or other suitable components. Various processes may be performed to form various microelectronic components, such as processes including but not limited to deposition, etching, placement, lithography, annealing, and one or more other suitable processes. Microelectronic components are interconnected to form integrated circuit devices, including one or more logic devices, memory devices (e.g., static random-access memory (SRAM)), radio frequency (RF) devices, input / output (I / O) devices, system-on-chip (SoC) devices, and other suitable types of devices.

[0153] The source structure 104 is disposed within the body region 114. The body region 114 has a first doping type and a doping concentration higher than that of the semiconductor substrate 102. For example, the doping concentration of the semiconductor substrate 102 may be approximately 10. 14 cm -3 Up to approximately 10 16 cm -3 The range, while the doping concentration of the main region 114 may be around 10. 16 cm -3 Up to approximately 10 18cm -3 The range.

[0154] A drain structure 106 is disposed within a drift region 116 (e.g., an n-well or a p-well), and the drift region 116 is disposed within the semiconductor substrate 102 and located laterally adjacent to the body region 114. The drift region 116 has a second doping type and includes a relatively low doping concentration, which may allow the laterally diffused metal-oxide-semiconductor transistor device 100 to provide higher resistance when operating at high voltages. In some embodiments, the doping concentration of the drift region 116 may be approximately 10. 15 cm -3 To about 10 17 cm -3 The range.

[0155] A gate structure 105 is disposed on a semiconductor substrate 102 and laterally disposed between a source structure 104 and a drain structure 106. In some embodiments, the gate structure 105 may extend laterally from above a body region 114 to cover a portion of a drift region 116. The gate structure 105 includes a gate electrode 108, which is separated from the semiconductor substrate 102 by a gate dielectric layer 110. In some embodiments, the gate dielectric layer 110 may comprise silicon dioxide (SiO2) or a high-k gate dielectric material, and the gate electrode 108 may comprise polysilicon or a metal gate material (e.g., aluminum). In some embodiments, the gate structure 105 may also include sidewall spacers 112 disposed on opposite sides of the gate electrode 108. In various embodiments, the sidewall spacers 112 may comprise nitride-based sidewall spacers (e.g., SiN) or oxide-based sidewall spacers (e.g., SiO2, SiOC, etc.).

[0156] One or more dielectric layers 124 may be disposed on the gate electrode 108 and the drift region 116 to define a reduced pinch-off. In some embodiments, one or more dielectric layers 124 extend continuously from a portion of the gate electrode 108 to a portion of the drift region 116. In some embodiments, one or more dielectric layers 124 may be conformally disposed on the drift region 116, the gate electrode 108, and the sidewall spacers 112.

[0157] An inter-level dielectric (ILD) layer 118 may be disposed on the semiconductor substrate 102 and / or various electrical components, and contacts (e.g., plugs) may be formed in the ILD layer 118 to provide electrical connections between other circuits / components. The formation of contacts may include forming openings in the ILD layer, filling the openings with a conductive material, and performing a planarization process, such as chemical mechanical planarization (CMP). In some embodiments, the contacts may include tungsten (W), but other suitable conductive materials may be used, such as silver (Ag), aluminum (Al), copper (Cu), AlCu, etc. One or more conductive metal structures may be disposed within the ILD layer 118. In some embodiments, one or more conductive metal structures may include a plurality of contacts configured between the source structure 104, the drain structure 106, or the gate electrode 108 and one or more metal layers to provide a vertical connection, the one or more metal layers being, for example, a first inter-metal dielectric (IMD) layer 132 covering the inter-metal dielectric layer 118.

[0158] The multiple contacts may include source contacts 122 coupled to source structure 104, drain contacts 128 coupled to drain structure 106, gate contacts 130 coupled to gate electrode 108, and multiple contact field plate contacts 126 coupled to one or more dielectric layers 124, including multiple rows of contact field plates. In some embodiments, the multiple contacts may include the same metallic material. For example, the multiple contacts may include one or more of tungsten (W), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), aluminum copper (AlCu), copper (Cu), and / or other similar conductive materials. In some embodiments, the interlayer dielectric layer 118 may include a dielectric material having a relatively low dielectric constant (e.g., less than or equal to about 3.9) to provide electrical isolation between the multiple contacts and / or contact field plate contacts 126. In some embodiments, the interlayer dielectric layer 118 may include an ultra-low k dielectric material or a low k dielectric material (e.g., SiCO). The contacts 126 of the contact field plate have a row that can be electrically coupled to the source contacts 122 through the metal layer 134. In some embodiments, the metal layer 134 can be coupled to an additional metal layer 135 through a via 133 in the first intermetallic dielectric layer 132.

[0159] Upon receiving a bias voltage, the gate electrode 108 is configured to generate an electric field, and this electric field controls the movement of charge carriers in a channel region (e.g., within the body region 114) laterally disposed between the source structure 104 and the drain structure 106. For example, during operation, the gate-source voltage (V0) relative to the source structure 104...GS V can be selectively applied to the gate electrode 108 to form a conductive channel in the channel region. When V is applied... GS When forming a conductive channel, the drain-source voltage (V) relative to the source structure 104 is... DS A charge carrier can be applied to the drain structure 106 to move charge carriers between the source structure 104 and the drain structure 106.

[0160] During operation, the contact field plate contact 126 is configured to act on the electric field generated by the gate electrode 108. The contact field plate contact 126 can be configured to change the distribution of the electric field generated by the gate electrode 108 in the drift region 116 to enhance the internal electric field of the drift region 116 and increase the drift doping concentration of the drift region 116, thereby increasing the breakdown voltage of the laterally diffused metal-oxide-semiconductor transistor device 100.

[0161] exist Figure 1 In one example, the laterally diffused metal-oxide-semiconductor transistor device 100 includes a plurality of contact field plate contacts 126 having three rows. Figure 2 A top cross-sectional view of a laterally diffused metal-oxide-semiconductor transistor device 100 is shown to illustrate a plurality of contact field plate contacts 126 arranged in three rows between the drain contact 128 and the gate contact 130. Optionally, the laterally diffused metal-oxide-semiconductor transistor device 100 may include a plurality of contact field plate contacts 126 arranged in two or more rows. For example, Figure 25 , Figure 26 and Figure 27 Examples of laterally diffused metal-oxide-semiconductor transistor devices including multiple contact field plate contacts 126 having one, two, and three rows are presented respectively. In this example, the three rows are aligned parallel to the source structure 104, and the contact field plate contacts 126 in each row are laterally aligned with the contact field plate contacts 126 in other rows. Alternatively, the semiconductor device may include contact field plate contacts 126 having misaligned rows and / or contact field plate contacts 126 laterally offset from the contact field plate contacts 126 in other rows. By providing multiple contact field plate contacts 126 having more than one row, the linear drain current (Id) can be reduced. dlin This reduces the attenuation of ) and can improve the efficiency of the laterally diffused metal-oxide-semiconductor transistor device 100.

[0162] Figure 3Cross-sectional views of some embodiments of a semiconductor device are shown, wherein the semiconductor device includes a laterally diffused metal-oxide-semiconductor transistor device 300 having a single row of a plurality of contact field plate contacts 126. In some embodiments, the laterally diffused metal-oxide-semiconductor transistor device 300 may include a plurality of contact field plate contacts 126 having multiple rows, for example, two, three, or more rows. In this embodiment, the contact field plate contacts 126 are electrically isolated from the source contacts 122. That is, the contact field plate contacts 126 and the source contacts 122 are not like... Figure 1 and Figure 2 In the implementation where the source contact 122 and contact field plate contact 126 are coupled to separate metal layers 310 and 312, respectively. Isolating the contact field plate contact 126 in this way reduces the linear drain current (I0). dlin The attenuation of ).

[0163] Figure 4 Cross-sectional views of some embodiments of a semiconductor device are shown, wherein the semiconductor device includes a laterally diffused metal-oxide-semiconductor transistor device 400 having a single row of a plurality of contact field plate contacts 126. In some embodiments, the laterally diffused metal-oxide-semiconductor transistor device 400 may include a plurality of contact field plate contacts 126 having more than one row, such as two, three or more rows. In this embodiment, the contact field plate contacts 126 are floating, that is, the contact field plate contacts 126 are not connected to or otherwise electrically connected to the metal layer in the first intermetallic dielectric layer 132, such as to a fixed voltage or ground. In other words, the contact field plate contacts 126 are electrically isolated. The source contacts 122 are coupled to the metal layer 410. Isolating the contact field plate contacts 126 in this way reduces the attenuation of the linear drain current (Idlin).

[0164] Figure 4 The concept shown, namely the concept of providing floating contact field plate contacts 126, can be achieved by providing disconnect at other locations within the laterally diffused metal-oxide-semiconductor transistor device 400, that is, providing features that cause the contact field plate contacts 126 to be electrically isolated. Figures 5 to 10 A separate cross-sectional view is shown to illustrate the optional location of the break in the back end of the line (BEOL) structure of the semiconductor device. For clarity, details are omitted. Figures 5 to 10The semiconductor device comprises various elements. In these embodiments, the laterally diffused metal-oxide-semiconductor transistor device 400 may include any number of inter-metal dielectric layers (e.g., a first inter-metal dielectric layer, a second inter-metal dielectric layer, a third inter-metal dielectric layer, ... an Xth inter-metal dielectric layer) covering the interlayer dielectric layer 118. The inter-metal dielectric layer can provide electrical insulation and structural support for various features in many manufacturing operations. The inter-metal dielectric layer may include one or more low-k dielectric materials, fluorine-doped silica, organosilicones, carbon-doped oxides, porous silica, organic polymer dielectrics (e.g., polyimide, polynorbornene, benzocyclobutene, and polytetrafluoroethylene (PTFE)), silicon-based polymer dielectrics (e.g., hydrogen silsesquioxane, methylsilsesquioxane) and / or other commonly used materials. The dielectric constant (k value) of the low-k dielectric material may be less than about 3.9.

[0165] Each of the intermetallic dielectric layers may include a corresponding metal layer (e.g., a first metal layer, a second metal layer, a third metal layer, ... a Xth metal layer) and vias (e.g., a first via, a second via, a third via, ... a Xth via) coupling the metal layer to the overlying intermetallic dielectric layer. The metal layers and vias may define interconnect structures extending through subsequent process structures. Disconnection can provide electrical isolation to the contact field plate contacts 126 by omitting any of these metal layers or vias. In some embodiments, each of the metal layers and / or vias may include a single layer, two layers, or multiple layers. In some embodiments, each of the metal layers and / or vias may include a filler material and a liner between the filler material and the dielectric material of the corresponding intermetallic dielectric layer. In some embodiments, these layers may include a liner formed of a noble metal or its alloy, such as, but not limited to, rhenium (Re), rhodium (Rh), ruthenium (Ru), or alloys thereof. In some embodiments, these layers may include a filler material formed of copper (Cu), aluminum (Al), tungsten (W), silver (Ag), or alloys thereof.

[0166] For example, Figure 5The illustrated laterally diffused metal-oxide-semiconductor transistor device 400A has a first inter-metal dielectric layer 424 covering an inter-metal dielectric layer 118, a second inter-metal dielectric layer 426 covering the first inter-metal dielectric layer 424, and a third inter-metal dielectric layer 428 covering the second inter-metal dielectric layer 426. Interconnect structures are disposed in the first inter-metal dielectric layer 424, the second inter-metal dielectric layer 426, and the third inter-metal dielectric layer 428, and the interconnect structures include a first via 411, a second via 412, and a third via 414, a second metal layer 416, a third metal layer 418, and a fourth metal layer 420 covering the third inter-metal dielectric layer 428, which are sequentially contacted. A disconnect is provided in the first inter-metal dielectric layer 424, i.e., a gap is provided between the contact field plate contact 126 and the first via 411 (the gap is defined by a portion of the first inter-metal dielectric layer 424), for example, by omitting... Figures 6 to 10 The first metal layer 422 shown makes the contact field plate contacts 126 electrically isolated from the interconnect structure.

[0167] As another example, Figure 6 The illustrated laterally diffused metal-oxide-semiconductor transistor device 400B has a second intermetallic dielectric layer 426 that is disconnected (e.g., by omitting the second metal layer 416) between the first via 411 and the second via 412. As another example, Figure 7 The illustrated laterally diffused metal-oxide-semiconductor transistor device 400C has a disconnect (e.g., by omitting the fourth metal layer 420) located on the third intermetallic dielectric layer 428. As another example, Figure 8 The illustrated laterally diffused metal-oxide-semiconductor transistor device 400D has a first intermetallic dielectric layer 424 that is disconnected (e.g., by omitting the first via 411) between the first metal layer 422 and the second metal layer 416. As another example, Figure 9 The illustrated laterally diffused metal-oxide-semiconductor transistor device 400E has a second intermetallic dielectric layer 426 that is disconnected (e.g., by omitting the second via 412) between the second metal layer 416 and the third metal layer 418. As another example, Figure 10 The illustrated laterally diffused metal-oxide-semiconductor transistor device 400F has a third intermetallic dielectric layer 428 that is disconnected (e.g., by omitting the third via 414) between the third metal layer 418 and the fourth metal layer 420.

[0168] Figure 11A top cross-sectional view is shown for some embodiments of a semiconductor device, wherein the semiconductor device includes a laterally diffused metal-oxide-semiconductor transistor device 1100 having a single row of a plurality of contact field plate contacts 126. In some embodiments, the laterally diffused metal-oxide-semiconductor transistor device 1100 may include a plurality of contact field plate contacts 126 having more than one row, such as two, three, or more rows. In some embodiments, one or more of the contact field plate contacts 126 may be isolated from the source contacts 122, for example, similar to Figure 3 The implementation method. In some implementations, one or more of the contact field plate contacts 126 may be floating, for example, similar to Figure 4 The implementation method is as follows. In this implementation, multiple source contacts 122 are interconnected in the subsequent process structure via a first metal layer 1118, a portion of multiple contact field plate contacts 126 are coupled to each other via a second metal layer 1114, and the first metal layer 1118 and the second metal layer 1114 are connected via a plurality of spaced-apart third metal layers 1110. Other portions of the multiple contact field plate contacts 126 are coupled to each other via a fourth metal layer 1112. Because of this arrangement, other portions of the contact field plate contacts 126 coupled via the fourth metal layer 1112 can be independently biased during off-state stress (i.e., no current conduction). In this way, the linear drain current (Id) can be reduced. dlin The attenuation of ) . In this example, another portion of the contact field plate contacts 126 coupled through the fourth metal layer 1112 is located near the end of the first row of contact field plate contacts 126, but this may not be necessary in other applications.

[0169] Figure 12A top cross-sectional view of some embodiments of a semiconductor device is shown, wherein the semiconductor device includes a laterally diffused metal-oxide-semiconductor transistor device 1200 having a plurality of contact field plate contacts 126 in three rows. In some embodiments, the laterally diffused metal-oxide-semiconductor transistor device 1200 may include a plurality of contact field plate contacts 126 having two or more rows. In this embodiment, the contact field plate contacts 126 in each row are coupled to each other in a subsequent process structure, but not coupled to contact field plate contacts 126 in other rows. That is, the contact field plate contacts 126 in the first row are all coupled by a first metal layer 1210, the contact field plate contacts 126 in the second row are all coupled by a second metal layer 1212, and the contact field plate contacts 126 in the third row are all coupled by a third metal layer 1214. Each row of contact field plate contacts 126 may be independently coupled to separate vias 1216, 1218, and 1220. With this configuration, each row of contacts 126 in the contact field plate can be selectively supplied with voltage or grounded. In this way, the electric field of the drift region 116 can be adjusted to improve performance.

[0170] Figure 13 A top cross-sectional view of some embodiments of a semiconductor device is shown, wherein the semiconductor device includes a laterally diffused metal-oxide-semiconductor transistor device 1300 having a plurality of contact field plate contacts 126 in three rows. In some embodiments, the laterally diffused metal-oxide-semiconductor transistor device 1300 may include a plurality of contact field plate contacts 126 having two or more rows. In this embodiment, each row of the contact field plate contacts 126 is organized into multiple groups, and each group includes a portion of each row of contact field plate contacts 126. The contact field plate contacts 126 in each group are coupled to each other in a downstream process structure but are not coupled to contact field plate contacts 126 in other groups. For example, the contact field plate contacts 126 may be organized into multiple groups, each group including a 3x3 array of contact field plate contacts 126, and the contact field plate contacts 126 in each group may be coupled via a first metal layer 1310, a second metal layer 1312, or a third metal layer 1314. Each group of contact field plate contacts 126 can be independently coupled to one of the separated vias 1316, 1318, and 1320. With this arrangement, each group of contact field plate contacts 126 can be selectively supplied with voltage or grounded. In this way, the electric field of the drift region 116 can be adjusted to improve performance.

[0171] The rows of contacts 126 in the contact field plate can be organized into groups with other quantities, shapes, etc., depending on the specific application. For example, in Figure 14In a top cross-sectional view of some embodiments of the semiconductor device shown, the semiconductor device includes a laterally diffused metal-oxide-semiconductor transistor device 1400 having a plurality of contact field plate contacts 126 in three rows. In this embodiment, the contact field plate contacts 126 may be organized into a plurality of groups, each group including, for example, six contact field plate contacts 126, and the contact field plate contacts 126 in each group may be coupled via a first metal layer 1410, a second metal layer 1412, or a third metal layer 1414, and from... Figure 14 From this perspective, each of the first metal layer 1410, the second metal layer 1412, or the third metal layer 1414 is triangular. Each set of contact field plate contacts 126 can be independently coupled to one of the separated through holes 1416, 1418, and 1420.

[0172] As another example, Figure 15 A top cross-sectional view of some embodiments of a semiconductor device is shown, wherein the semiconductor device includes a laterally diffused metal-oxide-semiconductor transistor device 1500 having a plurality of contact field plate contacts 126 in three rows. The laterally diffused metal-oxide-semiconductor transistor device 1500 is substantially the same as the previously described laterally diffused metal-oxide-semiconductor transistor device 1400, but each group of contact field plate contacts 126 has different contact field plate contacts 126. In this embodiment, the contact field plate contacts 126 in each group are coupled through a first metal layer 1510, a second metal layer 1512, or a third metal layer 1514, and each group of contact field plate contacts 126 is independently coupled to one of separated vias 1516, 1518, and 1520.

[0173] Now refer to Figure 24 And continue to refer to Figures 1 to 15 The flowchart provides a method 2400 for forming a semiconductor device (e.g., a high-voltage transistor device) with a field plate according to various examples. As can be understood from this disclosure, the order of operations of method 2400 is not limited to... Figure 24 The order shown is as described, and may be performed in one or more variable orders as disclosed herein.

[0174] Figures 16 to 23 A cross-sectional view of an exemplary structure formed by method 2400 is shown. Although Figures 16 to 23 The cross-sectional view shown is described with reference to method 2400, but it is understood that... Figures 16 to 23 The structure shown may be formed by other methods. It is also understood that method 2400 is not limited to the structure shown, and that method 2400 may be applicable to other structures. In other embodiments, some operations illustrated and / or described may be omitted in whole or in part.

[0175] Method 2400 may begin at block 2410. At block 2412, method 2400 may include forming a source structure and a drain structure within a substrate. In some embodiments, the source structure and drain structure may be separated by a body region and a drift region. A gate structure may be formed on the body region and the drift region. In some embodiments, forming the gate structure may include forming a gate dielectric layer on the substrate, and then forming a gate electrode on the gate dielectric layer. After forming the gate electrode, the source structure and drain structure may be formed in the substrate by a placement process. In some embodiments, other doped regions (e.g., drift regions and body regions) may be formed by one or more other placement processes prior to forming the gate dielectric layer. In further embodiments, a portion of the doped regions may be formed prior to forming the gate dielectric layer, and / or a remaining portion of other doped regions may be formed after forming the gate dielectric layer. One or more dielectric layers may be formed on the substrate and on at least a portion of the gate structure.

[0176] At block 2414, method 2400 may include forming an interlayer dielectric (ILD) layer on a substrate and a gate structure. The interlayer dielectric layer may be formed on one or more dielectric layers and on the gate structure. In some embodiments, the interlayer dielectric layer may be formed using deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition processes, or any combination thereof.

[0177] At block 2416, method 2400 may include forming a source contact coupled to a source structure, forming a drain contact coupled to a drain structure, and forming a gate contact coupled to a gate structure. At block 2418, method 2400 may include forming a plurality of contact field plate (CFP) contacts having at least a first row in an interlayer dielectric layer between the gate structure and the drain structure and on one or more dielectric layers. In some embodiments, the source contact, drain contact, gate contact, and the first row of contact field plate contacts may be formed by various processes, such as etching and lithography processes.

[0178] For example, in Figure 16 In the illustrated structure 1600, this structure includes a first masking layer 1610 deposited on an interlayer dielectric layer 118, and the first masking layer 1610 having three openings 1612, 1614, and 1616 covering the drift region 116. As another example, Figure 20In the illustrated structure 2000, this structure includes a first masking layer 2010 deposited on an interlayer dielectric layer 118, and the first masking layer 2010 having an opening 2012 covering the drift region 116. In some embodiments, the first masking layer 1610 and the first masking layer 2010 may be, for example, a hard mask, a photoresist, etc.

[0179] In some implementations, it is possible to Figure 16 Structure 1600 and Figure 20 The structure 2000 is etched to define openings in the interlayer dielectric layer 118, and these openings correspond to openings 1612, 1614, 1616, and 2012. In some embodiments, the structure 2000 is etched to define openings in the interlayer dielectric layer 118, and these openings correspond to openings 1612, 1614, 1616, and 2012. Figure 16 Structure 1600 and Figure 20 The etching process performed on structure 2000 can be a dry etching process, wherein the interlayer dielectric layer 118 is exposed to one or more etchants. In some embodiments, the one or more etchants may include dry etchants (e.g., having an etching chemical composition including fluorine, chlorine, etc.). In some embodiments, the power of the etching process can be in the range of about 100 watts to 1,000 watts (W). In some embodiments, a cleaning process may be performed after the etching process to remove [the etchant]. Figure 16 and Figure 20 The first masking layer 1610 and the first masking layer 2010 in the middle.

[0180] In these examples, source openings 1618 and 2018 are on source structure 104, drain openings 1620 and 2020 are on drain structure 106, and gate openings 1622 and 2022 are on gate electrode 108. These openings 1618, 2018, 1620, 2020, 1622, and 2022 may be formed before or after the formation of openings 1612, 1614, 1616, and 2012. In some embodiments, openings 1612, 1614, 1616, and 2012 may be formed by a second etching process, such as a dry etching process by exposing the interlayer dielectric layer 118 to one or more etchants.

[0181] As an example, Figure 17 It is shown that according to the first masking layer ( Figure 16 The first mask layer 1610) is for Figure 16 Structure 1600 is followed by a first etching process to structure 1700. The first etching process forms the sidewalls and top surface of the interlayer dielectric layer 118 and defines at least three contact field plates with openings 1712, 1714, and 1716. Similarly, Figure 21 It is shown that according to the first masking layer ( Figure 20 The first mask layer (2010) for Figure 20 Structure 2000 is followed by a first etching process to form structure 2100. The first etching process forms the sidewalls and upper surface of the interlayer dielectric layer 118 and defines at least one opening 2112 of the contact field plate.

[0182] In some implementations... Figure 17 The source opening 1618 and Figure 21 The source opening 2018 can be filled with one or more conductive materials to define the source contact 122. Figure 17 The opening of the drain electrode is 1620 and Figure 21 The drain opening 2018 can be filled with one or more conductive materials to define the drain contact 128. Figure 17 The gate opening 1622 and Figure 21 The gate opening 2022 may be filled with one or more conductive materials to define the gate contact 130, and Figure 17 The contact field plate has openings 1712, 1714 and 1716 and Figure 21 The opening 2112 of the contact field plate can be filled with one or more conductive materials to define the contact field plate contact 126. In some embodiments, the source contact 122, drain contact 128, gate contact 130, and contact field plate contact 126 can be formed by depositing a conductive material (e.g., aluminum, titanium, tantalum, tungsten, titanium nitride, tantalum nitride, etc.) on the interlayer dielectric layer 118, thereby filling... Figure 17 Openings 1618, 1620, 1622, 1712, 1714, and 1716, and Figure 21 The openings 2018, 2020, 2022, and 2112 are then used to planarize the conductive material (e.g., chemical mechanical planarization (CMP) process) until the top surface of the interlayer dielectric layer 118 is reached. As an example, Figure 18 The diagram shows the formation of source contact 122, drain contact 128, gate contact 130, and contact field plate contact 126. Figure 16 Structure 1600 followed by structure 1800, and Figure 22 The diagram shows the formation of source contact 122, drain contact 128, gate contact 130, and contact field plate contact 126. Figure 21 The structure after structure 2100 is structure 2200.

[0183] At block 2420, method 2400 may include forming an inter-metal dielectric (IMD) layer on the inter-layer dielectric layer. At block 2422, method 2400 may include forming a conductive metal layer in the inter-metal dielectric layer to couple to one or more contact field plate contacts, source contacts, drain contacts, and gate contacts. In some embodiments, the metal layer may be formed by a damascene process (e.g., a single damascene process) and / or may include a material different from that of the source contacts, drain contacts, gate contacts, and / or contact field plate contacts. As an example, Figure 19 The structure 1900 is shown after the formation of the first intermetallic dielectric layer 132, metal layer 129, metal layer 131, and metal layer 134, and... Figure 23 The structure 2300 is shown after the formation of the first intermetallic dielectric layer 132, metal layer 129, metal layer 131, metal layer 310, and metal layer 312. Method 2400 may end at block 2424.

[0184] Therefore, this disclosure provides a semiconductor device and a method for forming a semiconductor device, which can significantly reduce I in a laterally diffused metal-oxide-semiconductor structure with a contact field plate after stress in the off state. dlin The degradation of these substances improves the efficiency of such devices.

[0185] This disclosure provides a semiconductor device. The semiconductor device includes a body region, a drift region, a source structure, a drain structure, a gate structure, an interlayer dielectric layer, a plurality of contact field plates, and a back-end processing structure. The body region and the drift region are on a substrate. The source structure is disposed within the body region and the drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region, and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plates having at least a first row and a second row are disposed within the interlayer dielectric layer on the dielectric layer, wherein each of the contact field plates is configured to manipulate an electric field generated by the gate structure. The back-end processing structure is disposed on the interlayer dielectric layer and includes at least one conductive metal layer coupling the first row and the second row of contact field plates to the source structure. In some embodiments, the first row and the second row of contact field plates are both parallel and aligned with the source structure. In some embodiments, the downstream process structure is configured to independently provide a bias voltage to at least a first group of contact field plate contacts relative to a second group of contact field plate contacts during off-state stress. In some embodiments, the first group of contact field plate contacts includes portions of a first row and a second row of contact field plate contacts. In some embodiments, the first group of contact field plate contacts is located at the end of the first row of contact field plate contacts. In some embodiments, the downstream process structure includes at least a first conductive metal layer coupling the first row of contact field plate contacts to each other and at least a second conductive metal layer coupling the second row of contact field plate contacts to each other, wherein the downstream process structure is configured to selectively and independently provide voltage or ground to the first and second conductive metal layers.

[0186] This disclosure also provides a semiconductor device. The semiconductor device includes a body region, a drift region, a source structure, a gate structure, an interlayer dielectric layer, and a plurality of contact field plate contacts. The body region and the drift region are on a substrate. The source structure is disposed within the body region and the drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region, and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plate contacts having at least a first row are located within the interlayer dielectric layer, wherein each of the contact field plate contacts is configured to manipulate an electric field generated by the gate structure, and wherein at least a portion of the contact field plate contacts is electrically isolated from the source structure. In some embodiments, the semiconductor device further includes at least a second row of contact field plate contacts within the interlayer dielectric layer and a subsequent processing structure. A back-end process structure is disposed on an interlayer dielectric layer and includes at least a first conductive metal layer coupling a first row of contact field plate contacts to each other and at least a second conductive metal layer coupling a second row of contact field plate contacts to each other. The back-end process structure is configured to selectively and independently provide voltage to the first and second conductive metal layers or to ground. In some embodiments, the semiconductor device further includes at least a second row of contact field plate contacts within the interlayer dielectric layer and the back-end process structure. The back-end process structure is disposed on an interlayer dielectric layer and includes at least a first conductive metal layer coupling a first group of contact field plate contacts in the first and second rows to each other and at least a second conductive metal layer coupling a second group of contact field plate contacts in the first and second rows to each other. The back-end process structure is configured to selectively and independently provide voltage to the first and second groups or to ground. In some embodiments, the semiconductor device further includes a back-end process structure. A back-end process structure is disposed on an interlayer dielectric layer and includes at least a first conductive metal layer coupling a first group of contact field plate contacts to each other and at least a second conductive metal layer coupling to a second group of contact field plate contacts. The back-end process structure is configured to selectively and independently provide voltage to the first and second groups or to ground. The first group of contact field plate contacts is located at the end of a first row of contact field plate contacts and is electrically isolated from the source structure. In some embodiments, the semiconductor device further includes a back-end process structure disposed on the interlayer dielectric layer, wherein the back-end process structure is configured to independently provide a bias voltage to at least the first group of contact field plate contacts relative to the second group of contact field plate contacts when the semiconductor device is in a powered-off state. In some embodiments, the semiconductor device further includes a back-end process structure. The back-end process structure is disposed on an interlayer dielectric layer and includes at least one conductive metal layer coupling the first row of contact field plate contacts to each other. In some embodiments, the downstream process structure includes an interconnect structure extending through the downstream process structure, and the interconnect structure is associated with a first row of contact field plate contacts, wherein the interconnect structure includes at least one disconnection that causes the contact field plate contacts to float.

[0187] This disclosure also provides a method for manufacturing a semiconductor device. The method includes the following operations: providing a substrate having a source structure and a drain structure separated by a body region and a drift region, having a gate structure disposed between the source structure and the drain structure, having an interlayer dielectric layer disposed on the substrate, the source structure, the drain structure, and the gate structure, and having source contacts coupled to the source structure. Forming a plurality of contact field plate contacts having at least a first row in the interlayer dielectric layer between the gate structure and the drain structure. Forming a back-end process structure on the interlayer dielectric layer, the back-end process structure including at least one conductive metal layer coupled to the first row of contact field plate contacts and / or the source structure, wherein the method includes forming at least a second row of contact field plate contacts in the interlayer dielectric layer between the gate structure and the drain structure and / or electrically isolating the contact field plate contacts from the source structure. In some embodiments, the method further includes forming at least a first conductive metal layer in the subsequent process structure to couple a first row of contact field plate contacts to each other through the first conductive metal layer, and forming at least a second conductive metal layer in the subsequent process structure to couple a second row of contact field plate contacts to each other through the second conductive metal layer, wherein forming the subsequent process structure includes configuring the subsequent process structure to selectively and independently provide voltages or grounding to the first conductive metal layer and the second conductive metal layer. In some embodiments, the method further includes forming at least a first conductive metal layer in the subsequent process structure to couple a first group of contact field plate contacts in the first and second rows to each other through the first conductive metal layer, and forming at least a second conductive metal layer in the subsequent process structure to couple a second group of contact field plate contacts in the first and second rows to each other through the second conductive metal layer, wherein forming the subsequent process structure includes configuring the subsequent process structure to selectively and independently provide voltages or grounding to the first and second groups. In some embodiments, the method further includes forming at least a first conductive metal layer in the back-end process structure to couple a first group of contact field plate contacts to each other through the first conductive metal layer and forming at least a second conductive metal layer to couple to a second group of contact field plate contacts, wherein the back-end process structure is configured to selectively and independently provide voltages or ground to the first and second groups, wherein the first group of contact field plate contacts is located at the end of a first row of contact field plate contacts and is electrically isolated from the source structure. In some embodiments, forming the back-end process structure includes configuring the back-end process structure to independently provide a bias voltage to at least the first group of contact field plate contacts relative to the second group of contact field plate contacts when the semiconductor device is in an off state. In some embodiments, forming the back-end process structure includes forming an interconnect structure extending through the back-end process structure, the interconnect structure being associated with the first row of contact field plate contacts, wherein the interconnect structure includes at least one disconnection that causes the contact field plate contacts to float.In some implementations, the method does not include forming a second row of contact field plate contacts in the interlayer dielectric layer between the gate structure and the drain structure.

[0188] This disclosure provides a semiconductor device. The semiconductor device includes a body region, a drift region, a source structure, a drain structure, a gate structure, an interlayer dielectric layer, a plurality of contact field plates, and a back-end processing structure. The body region and the drift region are on a substrate. The source structure is disposed within the body region and the drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region, and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plates having at least a first row and a second row are disposed within the interlayer dielectric layer on the dielectric layer, wherein each of the contact field plates is configured to manipulate an electric field generated by the gate structure. The back-end processing structure is disposed on the interlayer dielectric layer and includes at least one conductive metal layer coupling the first row and the second row of contact field plates to the source structure. In some embodiments, the first row and the second row of contact field plates are both parallel and aligned with the source structure. In some embodiments, the downstream process structure includes at least a first conductive metal layer coupling a first row of contacts in the contact field plate to each other and at least a second conductive metal layer coupling a second row of contacts in the contact field plate to each other, wherein the downstream process structure is configured to selectively and independently provide voltage or ground to the first conductive metal layer and the second conductive metal layer.

[0189] This disclosure also provides a semiconductor device. The semiconductor device includes a body region, a drift region, a source structure, a gate structure, an interlayer dielectric layer, and a plurality of contact field plate contacts. The body region and the drift region are on a substrate. The source structure is disposed within the body region and the drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region, and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plate contacts having at least a first row are located within the interlayer dielectric layer on the dielectric layer, wherein each of the contact field plate contacts is configured to manipulate an electric field generated by the gate structure, and wherein at least a portion of the contact field plate contacts is electrically isolated from the source structure. In some embodiments, the semiconductor device further includes at least a second row of contact field plate contacts within the interlayer dielectric layer and a subsequent processing structure. A back-end process structure is disposed on an interlayer dielectric layer and includes at least a first conductive metal layer coupling a first row of contact field plate contacts to each other and at least a second conductive metal layer coupling a second row of contact field plate contacts to each other. The back-end process structure is configured to selectively and independently provide voltage to the first and second conductive metal layers or to ground. In some embodiments, the semiconductor device further includes at least a second row of contact field plate contacts within the interlayer dielectric layer and the back-end process structure. The back-end process structure is disposed on an interlayer dielectric layer and includes at least a first conductive metal layer coupling a first group of contact field plate contacts in the first and second rows to each other and at least a second conductive metal layer coupling a second group of contact field plate contacts in the first and second rows to each other. The back-end process structure is configured to selectively and independently provide voltage to the first and second groups or to ground. In some embodiments, the semiconductor device further includes a back-end process structure. The downstream process structure is disposed on the interlayer dielectric layer and includes at least a first conductive metal layer that couples a first group of contact field plate contacts to each other and at least a second conductive metal layer that couples to a second group of contact field plate contacts. The downstream process structure is configured to selectively and independently provide the first group and the second group of voltages or ground. The first group of contact field plate contacts is disposed at the end of the first row of contact field plate contacts and is electrically isolated from the source structure.

[0190] This disclosure further provides a semiconductor device. The semiconductor device includes a body region, a drift region, a source structure, a gate structure, an interlayer dielectric layer, a plurality of contact field plate contacts, and a back-end processing structure. The body region and the drift region are on a substrate. The source structure is disposed within the body region and the drain structure is disposed within the drift region. The gate structure includes a gate electrode disposed on the body region and the drift region, and a dielectric layer disposed on the gate electrode and the drift region. The interlayer dielectric layer is disposed on the substrate. Contact field plate contacts having at least a first row are disposed within the interlayer dielectric layer on the dielectric layer, wherein each of the contact field plate contacts is configured to manipulate an electric field generated by the gate structure. The back-end processing structure is disposed on the interlayer dielectric layer and includes interconnect structures extending through the back-end processing structure, the interconnect structures being associated with the first row of contact field plate contacts, wherein at least one disconnection in the interconnect structure causes the contact field plate contacts to float. In some embodiments, the back-end processing structure includes at least one conductive metal layer coupling the first row of contact field plate contacts to each other. In some implementations, at least a portion of the contact field plate contacts are electrically isolated from the source structure.

[0191] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from its spirit and scope.

Claims

1. A semiconductor device, characterized by comprising: Comprising: a body region and a drift region on a substrate; a source structure disposed within the body region and a drain structure disposed within the drift region; a gate structure including a gate electrode disposed on the body region and the drift region and a dielectric layer disposed on the gate electrode and the drift region; an interlayer dielectric layer disposed on the substrate; a plurality of contact field plate contacts having at least a first row and a second row within the interlayer dielectric layer on the dielectric layer, wherein each of the plurality of contact field plate contacts is configured to steer an electric field generated by the gate structure; and a back end of line structure disposed on the interlayer dielectric layer and including at least a first conductive metal layer coupling the first row and the second row of the plurality of contact field plate contacts to the source structure.

2. The semiconductor device according to claim 1, wherein wherein the first row and the second row of the plurality of contact field plate contacts are both aligned in parallel to the source structure.

3. The semiconductor device according to claim 1, wherein wherein the back end of line structure includes at least a first conductive metal layer coupling the first row of the plurality of contact field plate contacts to one another and at least a second conductive metal layer coupling the second row of the plurality of contact field plate contacts to one another, wherein the back end of line structure is configured to selectively and independently provide the first conductive metal layer and the second conductive metal layer with a voltage or ground.

4. A semiconductor device, characterized by comprising: Comprising: a body region and a drift region on a substrate; a source structure disposed within the body region and a drain structure disposed within the drift region; a gate structure including a gate electrode disposed on the body region and the drift region and a dielectric layer disposed on the gate electrode and the drift region; an interlayer dielectric layer disposed on the substrate; and a plurality of contact field plate contacts having at least a first row within the interlayer dielectric layer on the dielectric layer, wherein each of the plurality of contact field plate contacts is configured to steer an electric field generated by the gate structure, wherein at least a portion of the plurality of contact field plate contacts are electrically isolated from the source structure.

5. The semiconductor device according to claim 4, wherein Further comprising: at least a second row of the plurality of contact field plate contacts within the interlayer dielectric layer; and a back end of line structure disposed on the interlayer dielectric layer and including at least a first conductive metal layer coupling the first row of the plurality of contact field plate contacts to one another and at least a second conductive metal layer coupling the second row of the plurality of contact field plate contacts to one another, wherein the back end of line structure is configured to selectively and independently provide the first conductive metal layer and the second conductive metal layer with a voltage or ground.

6. The semiconductor device according to claim 4, wherein Further comprising: at least a second row of the plurality of contact field plate contacts within the interlayer dielectric layer; and a back end of line structure disposed on the interlayer dielectric layer and including at least a first conductive metal layer coupling a first group of the plurality of contact field plate contacts in the first row and the second row to one another and at least a second conductive metal layer coupling a second group of the plurality of contact field plate contacts in the first row and the second row to one another, wherein the back end of line structure is configured to selectively and independently provide the first group and the second group with a voltage or ground.

7. The semiconductor device according to claim 4, wherein Further comprising: A post-process structure disposed on the ILD layer and comprising at least a first conductive metal layer coupling a first set of the plurality of contact field plate contacts to each other and at least a second conductive metal layer coupling to a second set of the plurality of contact field plate contacts, wherein the post-process structure is configured to selectively and independently of each other provide the first set and the second set with a voltage or ground, wherein the first set of the plurality of contact field plate contacts is disposed at an end of the first row of the plurality of contact field plate contacts and is electrically isolated from the source structure.

8. A semiconductor device, characterized by comprising: Comprises: a body region and a drift region on a substrate; a source structure disposed within the body region and a drain structure disposed within the drift region; a gate structure comprising a gate electrode disposed on the body region and the drift region and a dielectric layer disposed on the gate electrode and the drift region; an ILD layer disposed on the substrate; a plurality of contact field plate contacts having at least a first row within the ILD layer on the dielectric layer, wherein each of the plurality of contact field plate contacts is configured to steer an electric field generated by the gate structure; and a post-process structure disposed on the ILD layer, the post-process structure comprising an interconnect structure extending through the post-process structure, the interconnect structure associated with the first row of the plurality of contact field plate contacts, wherein at least a break in the interconnect structure results in the plurality of contact field plate contacts being floating. wherein the post-process structure comprises at least a conductive metal layer coupling the first row of the plurality of contact field plate contacts to each other.

9. The semiconductor device according to claim 8, wherein wherein at least a portion of the plurality of contact field plate contacts is electrically isolated from the source structure.

10. The semiconductor device according to any one of Claims 8 to 9, wherein ​

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