Display device

Abstract

A display device is provided. The display device includes a substrate, a circuit layer, an element layer, and a sealing layer. The display device includes a display area, a non-display area, a hole area, and a hole peripheral area. The circuit layer includes an interlayer insulating layer, a first planarization layer, protection portions surrounding the hole region, a second planarization layer covering the protection portions, and one or more sealing auxiliary grooves positioned between adjacent ones of the protection portions. Each of the one or more sealing auxiliary grooves includes a first auxiliary groove penetrating the second planarization layer and a second auxiliary groove concavely formed in the first planarization layer. A slope of a side surface of the second auxiliary groove with respect to the substrate is steeper than a slope of a side surface of the first auxiliary groove with respect to the substrate. The display device improves lifetime by delaying penetration of oxygen or moisture through the second common layer in the hole peripheral area.

Description

Technical Field

[0001] The disclosure generally relates to a display device and a method for manufacturing the display device. More specifically, the disclosure relates to a display device having a light-transmitting hole disposed in a hole region surrounded by a display area and a method for manufacturing the display device. Background Technology

[0002] With the development of the information society, the demand for display devices that can display images in various formats is growing. For example, display devices are used in many different electronic products, including smart TVs, digital cameras, laptops, cellular phones, and navigation devices.

[0003] The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, or a light-emitting display device. Here, the light-emitting display device can include organic light-emitting display devices, inorganic light-emitting display devices, and micron or nanon light-emitting display devices. Organic light-emitting display devices include organic light-emitting elements, inorganic light-emitting display devices include inorganic light-emitting elements such as inorganic semiconductors, and micron or nanon light-emitting display devices include micron or nanon light-emitting elements.

[0004] Organic light-emitting display devices use light-emitting elements, each comprising a light-emitting layer made of organic light-emitting materials, to display images. Thus, because organic light-emitting display devices use self-emissive elements to display images, they offer superior performance in terms of power consumption, response speed, emission efficiency, brightness, and wide viewing angle compared to other display devices.

[0005] One surface of the display device can be a display surface that includes a display area for displaying images. A light-emitting area that emits light with corresponding brightness and color can be arranged in the display area. Utility Model Content

[0006] The purpose of this utility model is to provide a display device that may include a light-transmitting hole disposed in a hole area surrounding a display area.

[0007] The element layer may include light-emitting elements disposed in the light-emitting region, and each light-emitting element may include a first common layer between the anode electrode and the light-emitting layer and a second common layer between the light-emitting layer and the cathode electrode.

[0008] Since the cathode electrode and the second common layer are completely disposed in the display area, the cathode electrode and the second common layer can also be disposed in the hole area surrounded by the display area and the hole periphery area between the hole area and the display area.

[0009] Therefore, oxygen or moisture can relatively easily penetrate through a second common layer positioned adjacent to the light-transmitting hole, thereby drastically shortening the lifespan of the display device.

[0010] The disclosed aspect provides a display device and a method for manufacturing the display device, wherein the display device can improve its lifespan by delaying the permeation of oxygen or moisture through a second common layer in the periphery region of the hole.

[0011] However, the disclosure is not limited to those described herein. The above and other aspects of the disclosure will become clearer to those skilled in the art by referring to the detailed description of the disclosure given below.

[0012] According to the disclosed aspects, a display device includes: a substrate; a circuit layer disposed on the substrate; a component layer disposed on the circuit layer; and a sealing layer disposed on the component layer. The display device includes: a display area, a light-emitting area disposed in the display area; a non-display area configured to be adjacent to the display area; an aperture area surrounded by the display area; and an aperture periphery area disposed between the aperture area and the display area. The circuit layer includes: an interlayer insulating layer disposed on the substrate; a first planarization layer disposed on the interlayer insulating layer; a protective portion disposed on the first planarization layer in the aperture periphery area and surrounding the aperture area; a second planarization layer disposed on the first planarization layer and covering the protective portion; and one or more sealing auxiliary grooves positioned between adjacent protective portions within the protective portion. Each of the one or more sealing auxiliary grooves includes: a first auxiliary groove penetrating the second planarization layer; and a second auxiliary groove recessedly formed in the first planarization layer. The slope of the side surface of the second auxiliary groove relative to the substrate is steeper than the slope of the side surface of the first auxiliary groove relative to the substrate.

[0013] In the direction where the protective parts face each other, at least a portion of the edge of each protective part may protrude beyond the second auxiliary groove of one or more sealing auxiliary grooves. An undercut structure may be provided between the protective part and the second auxiliary groove of one or more sealing auxiliary grooves.

[0014] The display device may also include a light-transmitting hole formed in the hole area and penetrating the substrate, circuit layer, component layer and sealing layer.

[0015] The display device may include: one or more perimeter dams disposed between the protective portion and the perimeter region, and surrounding the perimeter region. The one or more perimeter dams may be spaced apart from each of the first planarization layer, the second planarization layer, and the perimeter region. A sealing layer may include: a first sealing layer disposed on the element layer; a second sealing layer disposed on the first sealing layer and superimposed on the display area; and a third sealing layer disposed on the first sealing layer and covering the second sealing layer. The second sealing layer may extend to the one or more perimeter dams and includes an organic insulating material spaced apart from the perimeter region. The first and third sealing layers may include inorganic insulating materials and are in contact with each other in the region between the one or more perimeter dams and the perimeter region. The protective portion may be superimposed on the second sealing layer.

[0016] The component layer may include: an anode electrode disposed in the light-emitting region; a pixel defining layer disposed in the non-light-emitting region adjacent to the light-emitting region and covering the edge of each anode electrode in the anode electrode; a spacer layer disposed on a portion of the pixel defining layer; a first common layer disposed on the anode electrode; a light-emitting layer disposed on the first common layer; a second common layer disposed in the display region and the periphery region of the aperture and covering the pixel defining layer, the spacer layer and the light-emitting layer; and a cathode electrode disposed on the second common layer.

[0017] The component layer may also include separation grooves disposed around each light-emitting region in the light-emitting region and recessedly formed in the pixel defining layer.

[0018] The separation groove can be parallel to each side of the edge of each light-emitting area in the light-emitting region. The second common layer can be broken in the separation groove.

[0019] The portion of the second common layer located in the periphery region of the hole may include: a first partition portion disposed on the second planarization layer and superimposed on the protective portion; and one or more second partition portions disposed within a second auxiliary groove in one or more sealing auxiliary grooves and spaced apart from the first partition portion.

[0020] Within a second auxiliary groove of one or more sealed auxiliary grooves, the cathode electrode can contact the first planarization layer.

[0021] Each of one or more perimeter dams may include multiple dam layers.

[0022] Each of the multiple dam layers can be set on the same layer as one of the first planarization layer, the second planarization layer, the pixel definition layer, and the spacing layer.

[0023] In each of the regions between the first and second planarization layers and one or more perimeter dams, between one or more perimeter dams, and between one or more perimeter dams and the bore region, the first sealing layer may contact the interlayer insulation layer.

[0024] The circuit layer may further include: a first source-drain conductive layer disposed on the interlayer insulating layer in the display area and covered by a first planarization layer; and a second source-drain conductive layer disposed on the first planarization layer in the display area and covered by a second planarization layer. The protective portion and the second source-drain conductive layer may be disposed on the same layer.

[0025] The circuit layer may further include: a buffer layer disposed on the substrate; a first gate insulating layer disposed on the buffer layer; and a second gate insulating layer disposed on the first gate insulating layer. An interlayer insulating layer may be disposed on the second gate insulating layer. A light-transmitting aperture may penetrate the third sealing layer, the first sealing layer, the cathode electrode, the second common layer, the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, the buffer layer, and the substrate.

[0026] According to the disclosed aspects, a method for manufacturing a display device includes: preparing a substrate, the substrate including a display area in which a light-emitting area is arranged, a non-display area adjacent to the display area, an aperture area surrounded by the display area, and an aperture periphery area disposed between the aperture area and the display area; forming a circuit layer on the substrate; forming a component layer on the circuit layer; forming a sealing layer on the component layer; and forming a light-transmitting aperture in the aperture area that sequentially penetrates the substrate, the circuit layer, the component layer, and the sealing layer. The step of forming the component layer includes: forming an anode electrode on the circuit layer in the light-emitting area; forming a pixel defining layer on the circuit layer in the non-light-emitting area adjacent to the light-emitting area, and forming a spacer layer on a portion of the pixel defining layer; forming a sealing auxiliary groove in the aperture periphery area, and forming a separation groove in the display area; forming a first common layer on the anode electrode; forming a light-emitting layer on the first common layer; forming a second common layer covering the pixel defining layer, the spacer layer, and the light-emitting layer in the display area and the aperture periphery area; and forming a cathode electrode on the second common layer.

[0027] The steps of setting the circuit layer may include: setting an interlayer insulating layer on a substrate; setting a first source-drain conductive layer on the interlayer insulating layer in a display area; setting a first planarization layer on the interlayer insulating layer covering the first source-drain conductive layer; setting a second source-drain conductive layer on the first planarization layer in the display area and setting a protective portion in a hole periphery area; and setting a second planarization layer on the first planarization layer covering the second source-drain conductive layer and the protective portion. In the step of setting the second source-drain conductive layer and the protective portion, the protective portion surrounds the hole area. In the step of forming a sealing auxiliary groove and a separation groove, the sealing auxiliary groove includes a first auxiliary groove positioned between the protective portions and penetrating the second planarization layer and a second auxiliary groove recessed in the first planarization layer. The separation groove is positioned around each light-emitting area in the light-emitting area and is recessed in the pixel defining layer.

[0028] The steps of forming the sealing auxiliary groove and the separation groove may include: setting an oxide material layer covering a pixel defining layer in the display area and a second planarization layer in the aperture peripheral area, and setting a first photomask on the oxide material layer; preparing a first oxide mask layer by partially removing the oxide material layer via the first photomask; forming a first temporary groove penetrating the second planarization layer and a second temporary groove recessed in the first planarization layer by partially removing the second planarization layer and the first planarization layer in the aperture peripheral area via the first oxide mask layer; preparing a second photomask by partially removing the first photomask; preparing a second oxide mask layer by partially removing the first oxide mask layer via the second photomask; forming a separation groove by partially removing the pixel defining layer via the second oxide mask layer, and forming a sealing auxiliary groove by additionally removing the second planarization layer and the first planarization layer via the second oxide mask layer, the first temporary groove, and the second temporary groove; and removing the second photomask and the second oxide mask layer.

[0029] In the step of setting the oxide material layer and the first photomask, the first photomask may include a first transmissive portion superimposed on the region between the protective portion, a first blocking portion superimposed on the portion adjacent to each luminous region in the same luminous region of the non-luminous region and having a first thickness, and a second blocking portion including the portion other than the first transmissive portion and the first blocking portion and having a second thickness greater than the first thickness. In the step of preparing the first oxide mask layer, the first oxide mask layer includes a first opening corresponding to the first transmissive portion. In the step of forming the first temporary groove and the second temporary groove, the first temporary groove is formed by removing a portion of the second planarization layer through the first transmissive portion and the first opening, and the second temporary groove is formed by removing a portion of the first planarization layer through the first transmissive portion, the first opening, and the first temporary groove.

[0030] In the step of preparing the second photomask, the second photomask may include a second transmissive portion prepared by removing a portion of the second blocking portion disposed around the first transmissive portion, a third transmissive portion prepared by removing the first blocking portion, and a third blocking portion prepared as the remaining portion of the second blocking portion and having a third thickness smaller than the second thickness. In the step of preparing the second oxide mask layer, the second oxide mask layer includes a second opening corresponding to the second transmissive portion and a third opening corresponding to the third transmissive portion. In the steps of forming the sealing auxiliary groove and the separation groove, the first auxiliary groove may be prepared by removing a portion of the second planarization layer disposed around the first temporary groove through the second opening, the second auxiliary groove may be prepared by removing a portion of the first planarization layer disposed around the second temporary groove through the second opening and the first auxiliary groove, and the separation groove may be prepared by removing a portion of the pixel defining layer through the third opening.

[0031] In the steps of forming the sealing auxiliary groove and the separation groove, in the direction in which the protective parts face each other, the slope of the side surface of the second auxiliary groove relative to the base may be steeper than the slope of the side surface of the first auxiliary groove relative to the base, at least a portion of the edge of each protective part in the protective part may protrude beyond the second auxiliary groove of the sealing auxiliary groove, and the undercut structure may be positioned between the protective part and the second auxiliary groove of the sealing auxiliary groove.

[0032] In the step of setting the second common layer, the portion of the second common layer located in the periphery region of the hole may include a first partition portion disposed on the second planarization layer and overlapping with the protective portion, and one or more second partition portions disposed within a second auxiliary groove of the sealing auxiliary groove and spaced apart from the first partition portion. In the step of setting the cathode electrode, the cathode electrode may contact the first planarization layer within the second auxiliary groove of the sealing auxiliary groove.

[0033] The display device according to an embodiment includes a substrate, a circuit layer disposed on the substrate, a component layer disposed on the circuit layer, and a sealing layer disposed on the component layer.

[0034] The substrate includes a display area in which a light-emitting area is arranged, a non-display area disposed around the display area, an aperture area surrounded by the display area, and an aperture periphery area disposed between the aperture area and the display area.

[0035] The circuit layer may include an interlayer insulating layer disposed on a substrate, a first planarization layer disposed on the interlayer insulating layer, a protective portion disposed on the first planarization layer in the periphery region of the hole and sequentially surrounding the hole region, a second planarization layer disposed on the first planarization layer and covering the protective portion, and one or more sealing auxiliary grooves positioned between the protective portions.

[0036] Each of the one or more sealing auxiliary grooves may include a first auxiliary groove penetrating the second planarization layer and a second auxiliary groove recessed in the first planarization layer.

[0037] The slope of the side surface of the second auxiliary groove relative to the substrate can be steeper than the slope of the side surface of the first auxiliary groove relative to the substrate.

[0038] According to an embodiment, in a direction where the protective portions face each other, at least a portion of the edge of each protective portion may protrude beyond one or more sealing auxiliary grooves. For example, an undercut structure may be formed between the protective portion and a second auxiliary groove of one or more sealing auxiliary grooves.

[0039] According to an embodiment, the element layer may include an anode electrode disposed in a light-emitting region, a pixel defining layer disposed in a non-light-emitting region between light-emitting regions and covering the edge of each anode electrode in the anode electrode, a spacer layer disposed on a portion of the pixel defining layer, a first common layer disposed on the anode electrode, a light-emitting layer disposed on the first common layer, a second common layer disposed in a display area and a hole periphery area and covering the pixel defining layer, the spacer layer and the light-emitting layer, and a cathode electrode disposed on the second common layer.

[0040] As described above, according to the embodiment, since the protective part and one or more sealing auxiliary grooves are provided in the periphery area of ​​the hole, the portion of the second common layer provided in the periphery area of ​​the hole can be separated or disconnected by the undercut structure provided between the protective part and the second auxiliary groove.

[0041] For example, the portion of the second common layer located in the periphery region of the hole may include a first partition portion disposed on the second planarization layer and superimposed on the protective portion, and one or more second partition portions disposed within one or more sealing auxiliary grooves and spaced apart from the first partition portion.

[0042] In other words, one or more second partitions can be separated from the first partition by an undercut structure disposed between the protective part and the second auxiliary groove.

[0043] Therefore, the permeation path of oxygen or moisture through the second common layer located in the periphery of the aperture can be delayed. As a result, the lifespan of the display device including the light-transmitting aperture can be improved.

[0044] Furthermore, according to an embodiment, the element layer may also include separation grooves disposed around each light-emitting region in the light-emitting region and recessedly formed in the pixel defining layer.

[0045] Due to the slope of the side surface of the separation groove, the second common layer can be provided with a non-uniform thickness. For example, the second common layer can have a relatively thin thickness at the separation groove, so that the second common layer can be broken or separated by the separation groove.

[0046] As a result, leakage current through the second common layer can be reduced between adjacent light-emitting areas within the light-emitting area, thus improving the image quality of the display device.

[0047] A method for manufacturing a display device according to an embodiment may include: preparing a substrate; providing a circuit layer on the substrate; providing a component layer on the circuit layer; providing a sealing layer on the component layer; and forming a light-transmitting hole in the hole region.

[0048] The steps of setting the component layer may include: setting an anode electrode; setting a pixel defining layer and a spacer layer; forming a sealing auxiliary groove and a separation groove; setting a first common layer; setting a second common layer; and setting a cathode electrode.

[0049] According to the embodiment, since the sealing auxiliary groove and the separation groove are formed together, the number of masking processes can be reduced. Therefore, even with the sealing auxiliary groove and the separation groove included, the number of manufacturing processes for the display device can be reduced.

[0050] However, the effects of the disclosed embodiments are not limited to those illustrated above, and various other effects are included herein. Attached Figure Description

[0051] The above and other aspects and features of the disclosure will become clearer from the detailed description of the disclosed embodiments with reference to the accompanying drawings, in which:

[0052] Figure 1 This is a schematic perspective view showing a display device according to an embodiment;

[0053] Figure 2 It is shown Figure 1 A schematic plan view of the display device;

[0054] Figure 3 It is along Figure 2 A schematic cross-sectional view taken by line A-A';

[0055] Figure 4 It is shown Figure 2 A schematic layout diagram of part B;

[0056] Figure 5 It is shown Figure 4 A schematic diagram of the equivalent circuit of the light-emitting pixel driver;

[0057] Figure 6 It is shown Figure 5A schematic cross-sectional view of the first transistor, the sixth transistor, and the light-emitting element;

[0058] Figure 7 It is shown Figure 2 A schematic layout diagram of part C;

[0059] Figure 8 It is according to the embodiment along Figure 7 A schematic cross-sectional view taken by line D-D';

[0060] Figure 9 It is shown Figure 8 A schematic enlarged view of part D;

[0061] Figure 10 It is according to the embodiment along Figure 7 A schematic cross-sectional view taken by line D-D';

[0062] Figure 11 , Figure 12 , Figure 13 and Figure 14 This is a schematic flowchart illustrating a method for manufacturing a display device according to an embodiment; and

[0063] Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25 It is shown Figure 11 , Figure 12 , Figure 13 and Figure 14 The process diagrams for some of the steps in the process. Detailed Implementation

[0064] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be arranged in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals denote the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0065] In order to describe the disclosed embodiments, some parts that are not relevant to the description may be omitted.

[0066] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on said other layer or substrate, or an intermediary layer may be present. Conversely, when an element is referred to as being "directly on" another element, an intermediary element may not be present.

[0067] Furthermore, the phrase "in a plan view" refers to the view of a portion of an object from above, and the phrase "in a schematic sectional view" refers to the view of a schematic section taken by vertically cutting through a portion of an object from the side. The terms "overlapping" or "coinciding" indicate that the first object may be above, below, or to the side of the second object, or vice versa. Furthermore, the term "overlapping" can include cascading, stacking, facing or oriented, extending above, covering or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The expression "not overlapping" can include meanings such as "separated from," "offset from," or "offset from," and any other suitable equivalents that will be understood and appreciated by one of ordinary skill in the art. The terms "facing" and "oriented" can indicate that the first object may be directly or indirectly opposite the second object. In cases where a third object is placed between the first and second objects, the first and second objects can be understood as indirectly opposite each other, although still facing each other.

[0068] For ease of description, the spatial relative terms “below,” “under,” “lower,” “above,” “upper,” etc., as shown in the accompanying drawings, are used to describe the relationship between one element or component and another element or component. It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device shown in the drawings is flipped, the device positioned “below” or “under” another device may be placed “above” another device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatial relative terms can be interpreted differently depending on the orientation.

[0069] When an element is referred to as being "connected" or "joined" to another element, the element may be "directly connected" or "directly joined" to the other element, or "electrically connected" or "electrically joined" to the other element, with one or more intermediary elements positioned between them. It will also be understood that when the terms "comprising," "including," "having," and / or variations thereof are used, they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0070] It will be understood that although the terms “first,” “second,” or “third,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or to facilitate its description and interpretation. For example, when “first element” is discussed in the description, it may be referred to as “second element” or “third element,” and “second element” and “third element” may be named in a similar manner without departing from the teaching herein.

[0071] The terms “about” or “approximately” as used herein include the stated value and mean an acceptable deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and errors associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0072] In the specification and claims, for the purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood to be equivalent to "and / or". In the specification and claims, for the purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one of the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0073] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0074] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0075] Figure 1 This is a schematic perspective view illustrating a display device according to an embodiment. Figure 2 It is shown Figure 1 A schematic plan view of the display device. Figure 3 It is along Figure 2 A sectional view taken by line A-A'. Figure 4 It is shown Figure 2 A schematic layout diagram of part B.

[0076] Reference Figure 1 and Figure 2 The display device 100 is a device for displaying moving or still images and can be used as a display screen for each of various products such as televisions, laptops, monitors, billboards and Internet of Things (IoT) devices and portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices and ultra-mobile PCs (UMPCs).

[0077] Display device 100 can be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, and a micron or nano light-emitting display device using micron or nano LEDs. In the following description, it will be based primarily on the fact that display device 100 is an organic light-emitting display device. However, the disclosure is not limited thereto, and can be applied to display devices including organic insulating materials, organic light-emitting materials, and metallic materials.

[0078] The display device 100 may be formed as flat, but is not limited thereto. For example, the display device 100 may include curved surface portions formed at its left and right distal ends and having constant or variable curvature. The display device 100 may be flexibly formed as curved, bent, folded, or rolled up.

[0079] like Figure 1 , Figure 2 and Figure 3 As shown, the display device 100 may include a substrate 110.

[0080] The substrate 110 may include a main region MA corresponding to the display surface of the display device 100 and a sub-region SBA protruding from a portion of the main region MA.

[0081] like Figure 2 As shown, the main area MA may include the display area DA and the non-display area NDA disposed around the display area DA.

[0082] The display area DA can be formed into a rectangular shape, having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. In another example, the display area DA can have a short side extending in the second direction DR2 and a long side extending in the first direction DR1. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be rounded to have a predetermined curvature, or it can be formed at a right angle. The planar shape of the display area DA is not limited to a quadrilateral shape, and the display area DA can be formed into other polygonal shapes, circular shapes, or elliptical shapes.

[0083] The non-display area NDA can be set at the edge of the main area MA to surround the display area DA.

[0084] The sub-region SBA can be the region that protrudes from the non-display region NDA of the main region MA on the second direction DR2.

[0085] Figure 2 and Figure 3 A display device 100 with a portion of the sub-region SBA bent is shown.

[0086] like Figure 2 and Figure 3 As shown, a portion of the sub-region SBA (e.g., the portion attached to the main region MA) can be bent into a curved shape, such that another portion of the sub-region SBA (e.g., the portion not attached to the main region MA) can be disposed on the rear surface of the substrate 110 opposite to the display surface.

[0087] Reference Figure 3 The display device 100 according to the embodiment may include a substrate 110, a circuit layer 120 disposed on the substrate 110, a component layer 130 disposed on the circuit layer 120, and a sealing layer 140 disposed on the component layer 130 and partially disposed on the circuit layer 120.

[0088] The display device 100 according to an embodiment may further include a cover window 150 disposed on a sealing layer 140. The cover window 150 may be engaged to face the substrate 110. As another example, the cover window 150 may be engaged to a bracket located under the rear surface of the substrate 110. The bracket may accommodate the substrate 110 and the display driving circuitry 300.

[0089] The display device 100 according to an embodiment may further include a touch sensor layer disposed on the sealing layer 140. Figure 6 (160 in the middle).

[0090] The display device 100 according to an embodiment may further include a polarizing layer disposed on the sealing layer 140 to reduce the reflection of external light.

[0091] The substrate 110 can be made of an insulating material such as a polymer resin. For example, the substrate 110 can be made of polyimide. The substrate 110 can be a flexible substrate that can be bent, folded and rolled.

[0092] As another example, the substrate 110 can be made of an insulating material such as glass.

[0093] The substrate 110 may include a main region MA and a sub-region SBA. The main region MA may include a display region DA and a non-display region NDA.

[0094] Circuit layer 120 may include a conductive layer, one or more semiconductor layers, and an insulating layer disposed therebetween. Circuit layer 120 may include transistors having one or more semiconductor layers and one or more conductive layers, as well as signal lines each having at least one conductive layer.

[0095] The element layer 130 may include a light-emitting element that emits light according to a drive current applied from the circuit layer 120.

[0096] The sealing layer 140 can cover the circuit layer 120 and the component layer 130, and can prevent oxygen or moisture from penetrating into the component layer 130.

[0097] The cover window 150 may include a light-transmitting material. The cover window 150 may be made of an inorganic material such as glass, or an organic material such as plastic or polymer. However, the material of the cover window 150 is not limited to these.

[0098] Reference Figure 4 According to an embodiment, the display area DA of the substrate 110 of the display device 100 may include a light-emitting area EA. The display area DA may also include a non-light-emitting area disposed in the intervals between the light-emitting areas EA.

[0099] Component layer ( Figure 3 130 in the text may include a light-emitting element ( Figure 5 (LE in the image), and each of the light-emitting elements can be set in the light-emitting area EA.

[0100] Circuit layer ( Figure 3 120 in the main region MA may include a light-emitting pixel driver EPD, which is arranged in the main region MA as parallel to each other in a first direction DR1 and a second direction DR2. The light-emitting pixel driver EPD may be electrically connected to the light-emitting elements of the element layer 130. Figure 5 Each of the LEs in the LEs.

[0101] The luminescent region EA can have a rhomboid planar shape or a rectangular planar shape. However, the planar shape of the luminescent region EA is not limited to this. Figure 4The planar shape shown is illustrated. For example, the luminescent area EA can have a polygonal planar shape such as a square planar shape, a pentagonal planar shape, or a hexagonal planar shape, or a circular planar shape or an elliptical planar shape including curved edges.

[0102] The emitting region EA may include a first emitting region EA1 that emits light of a first color in a first wavelength band, a second emitting region EA2 that emits light of a second color in a second wavelength band lower than the first wavelength band, and a third emitting region EA3 that emits light of a third color in a third wavelength band lower than the second wavelength band.

[0103] As an example, the first color could be red in the wavelength range of approximately 600 nm to approximately 750 nm. The second color could be green in the wavelength range of approximately 480 nm to approximately 560 nm. The third color could be blue in the wavelength range of approximately 370 nm to approximately 460 nm.

[0104] The first light-emitting region EA1 and the third light-emitting region EA3 can be alternately set on at least one of the first direction DR1 and the second direction DR2.

[0105] The second luminescent region EA2 can be arranged to be parallel to each other in at least one of the first direction DR1 and the second direction DR2.

[0106] The second luminous region EA2 can be configured to be adjacent to the first luminous region EA1 and the third luminous region EA3 on oblique directions DR4 and DR5, which intersect the first direction DR1 and the second direction DR2. In this case, the third luminous region EA3 can be configured to be adjacent to the second luminous region EA2 on oblique direction DR4 or DR5. Similarly, the first luminous region EA1 can be configured to be adjacent to the second luminous region EA2 on oblique direction DR4 or DR5.

[0107] like Figure 4 As shown, the size of each of the second light-emitting regions EA2 can be larger than the size of each of the first light-emitting regions EA1. The size of each of the first light-emitting regions EA1 can be larger than the size of each of the third light-emitting regions EA3.

[0108] The pixels PX that display different brightness and color can be set by the first light-emitting area EA1, the second light-emitting area EA2, and the third light-emitting area EA3 that are adjacent to each other in the light-emitting area EA.

[0109] In other words, a pixel (PX) can be a basic unit that displays various colors, including white, at a predetermined brightness.

[0110] Each pixel PX may include at least one first light-emitting region EA1, at least one second light-emitting region EA2, and at least one third light-emitting region EA3 that are adjacent to each other. For example, each pixel PX may include one first light-emitting region EA1, two second light-emitting regions EA2, and one third light-emitting region EA3. Therefore, each pixel PX can display various colors by mixing the light emitted from the adjacent first light-emitting regions EA1, EA2, and EA3.

[0111] Figure 5 It shows Figure 4 A schematic diagram of the equivalent circuit of the light-emitting pixel driver.

[0112] Reference Figure 5 One of the light-emitting elements LE in element layer 130 can be electrically connected between one of the light-emitting pixel drivers EPD in circuit layer 120 and the second power supply ELVSS.

[0113] For example, the anode electrode of the light-emitting element LE can be electrically connected to the light-emitting pixel driver EPD, and a second power supply ELVSS with a voltage level lower than the first power supply ELVDD can be applied to the cathode electrode of the light-emitting element LE.

[0114] The capacitor Cel connected in parallel with the light-emitting element LE represents the parasitic capacitance between the anode and cathode electrodes.

[0115] The circuit layer 120 may include a first power line VDL for transmitting a first power supply ELVDD, a first initialization voltage line VGIL for transmitting a first initialization voltage VGINT, and a second initialization voltage line VAIL for transmitting a second initialization voltage VAINT.

[0116] The circuit layer 120 may also include a scan write line GWL for transmitting scan write signals GW, a scan initialization line GIL for transmitting scan initialization signals GI, a transmit control line ECL for transmitting transmit control signals EC, and a data line DL for transmitting data signals Vdata.

[0117] The light-emitting pixel driver EPD of circuit layer 120 may include a first transistor T1 that generates a drive current for driving the light-emitting element LE, two or more transistors T2 to T7 electrically connected to the first transistor T1, and at least one capacitor PC1. In this case, transistors T1 to T7 may be electrically connected to the light-emitting element LE.

[0118] The first transistor T1 can be located between the first node N1 and the second node N2.

[0119] The first electrode (e.g., the source electrode) of the first transistor T1 can be electrically connected to the first node N1, and can be electrically connected to the first power line VDL through the fifth transistor T5.

[0120] The second electrode (e.g., the drain electrode) of the first transistor T1 can be electrically connected to the second node N2, and can be electrically connected to the anode of the light-emitting element LE through the sixth transistor T6.

[0121] The gate electrode of the first transistor T1 can be electrically connected to the third node N3.

[0122] The second transistor T2 can be electrically connected between the data line DL and the first node N1.

[0123] For example, the first electrode of the first transistor T1 can be electrically connected to the data line DL through the second transistor T2.

[0124] The second transistor T2 can be turned on by the scan write signal GW of the scan write line GWL.

[0125] The first capacitor PC1 can be electrically connected between the third node N3 and the first power line VDL. In this case, one end of the first capacitor PC1 can be electrically connected to the first power supply ELVDD, and the other end of the first capacitor PC1 can be electrically connected to the third node N3.

[0126] Therefore, the potential of the gate electrode of the first transistor T1 can be maintained at the voltage charged in the first power line VDL.

[0127] When the data signal Vdata of data line DL is transmitted to the first electrode of the first transistor T1 through the conducting second transistor T2, the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 can be the voltage difference between the first power supply ELVDD and the data signal Vdata.

[0128] In this case, when the voltage difference (e.g., gate-source voltage difference) between the gate electrode and the first electrode of the first transistor T1 is substantially equal to or greater than the threshold voltage, the first transistor T1 can be turned on, thereby generating the drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0129] Subsequently, with the fifth transistor T5 and the sixth transistor T6 turned on, the first transistor T1 can be connected in series with the light-emitting element LE between the first power supply ELVDD and the second power supply ELVSS. Therefore, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be supplied as the driving current for the light-emitting element LE.

[0130] Therefore, the light-emitting element LE can emit light with a brightness corresponding to the data signal Vdata.

[0131] The third transistor T3 can be disposed between the second node N2 and the third node N3. For example, the third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode (e.g., the drain electrode) of the first transistor T1.

[0132] The third transistor T3 may include a plurality of sub-transistors connected in series. As an example, the third transistor T3 may include a first sub-transistor T31 and a second sub-transistor T32 connected in series with the first sub-transistor T31.

[0133] The first electrode of the first sub-transistor T31 can be electrically connected to the gate electrode of the first transistor T1, the second electrode of the first sub-transistor T31 can be electrically connected to the first electrode of the second sub-transistor T32, and the second electrode of the second sub-transistor T32 can be electrically connected to the second electrode (e.g., the drain electrode) of the first transistor T1.

[0134] In this case, the potential of the gate electrode of the first transistor T1 can be prevented from changing due to leakage current caused by the non-conducting third transistor T3.

[0135] The first sub-transistor T31 and the second sub-transistor T32 can be turned on by the scan write signal GW of the scan write line GWL.

[0136] With the first sub-transistor T31 and the second sub-transistor T32 turned on, the voltage difference between the second node N2 and the third node N3 can be initialized.

[0137] The fourth transistor T4 can be electrically connected between the third node N3 and the first initialization voltage line VGIL. For example, the fourth transistor T4 can be electrically connected between the gate electrode of the first transistor T1 and the first initialization voltage line VGIL.

[0138] The fourth transistor T4 may include a plurality of sub-transistors connected in series. As an example, the fourth transistor T4 may include a third sub-transistor T41 and a fourth sub-transistor T42 connected in series with the third sub-transistor T41.

[0139] The first electrode of the third sub-transistor T41 can be electrically connected to the gate electrode of the first transistor T1, the second electrode of the third sub-transistor T41 can be electrically connected to the first electrode of the fourth sub-transistor T42, and the second electrode of the fourth sub-transistor T42 can be electrically connected to the first initialization voltage line VGIL.

[0140] In this case, the potential of the gate electrode of the first transistor T1 can be prevented from changing due to leakage current caused by the non-conducting fourth transistor T4.

[0141] The third sub-transistor T41 and the fourth sub-transistor T42 can be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0142] With the third sub-transistor T41 and the fourth sub-transistor T42 turned on, the potential of the third node N3 can be initialized to the first initialization voltage VGINT.

[0143] The fifth transistor T5 can be disposed between the first node N1 and the first power line VDL. In this case, the fifth transistor T5 can be electrically connected between the first node N1 and the first power line VDL.

[0144] The sixth transistor T6 can be disposed between the second node N2 and the fourth node N4. In this case, the sixth transistor T6 can be electrically connected between the second node N2 and the fourth node N4.

[0145] The fourth node N4 can be electrically connected to the anode electrode of the light-emitting element LE.

[0146] The fifth transistor T5 and the sixth transistor T6 can be turned on by the emit control signal EC on the emit control line ECL.

[0147] The seventh transistor T7 can be positioned between the fourth node N4 and the second initialization voltage line VAIL. In this case, the seventh transistor T7 can be electrically connected between the fourth node N4 and the second initialization voltage line VAIL.

[0148] The seventh transistor T7 can be turned on by the gate control signal GC of the gate control line GCL.

[0149] The potential of the fourth node N4 can be initialized to the second initialization voltage VAINT by the conducting seventh transistor T7.

[0150] According to an embodiment, the first transistor T1 to the seventh transistor T7 can be configured as P-type MOSFETs. As another example, the third transistor T3 and the fourth transistor T4 among the first transistor T1 to the seventh transistor T7 can be configured as N-type MOSFETs instead of P-type MOSFETs.

[0151] Figure 6 It is shown Figure 5 A schematic cross-sectional view of the first transistor, the sixth transistor, and the light-emitting element.

[0152] Reference Figure 6The display device 100 according to the embodiment may include a substrate 110, a circuit layer 120 disposed on the substrate 110, a component layer 130 disposed on the circuit layer 120, and a sealing layer 140 disposed on the component layer 130.

[0153] The display device 100 according to an embodiment may further include a touch sensor layer 160 disposed on a sealing layer 140 and a cover window 150 disposed on the touch sensor layer 160. The display device 100 may further include a polarizing layer disposed between the touch sensor layer 160 and the cover window 150.

[0154] According to an embodiment, the circuit layer 120 may include an interlayer insulating layer 124 disposed on the substrate 110, a first source-drain conductive layer SDCDL1 (ANCE1) disposed on the interlayer insulating layer 124, a first planarization layer 125 covering the first source-drain conductive layer SDCDL1 (ANCE1), a second source-drain conductive layer SDCDL2 (ANCE2) disposed on the first planarization layer 125, and a second planarization layer 126 covering the second source-drain conductive layer SDCDL2 (ANCE2).

[0155] The circuit layer 120 may further include semiconductor layers CH1, E11, E21, CH6, E16 and E26 disposed on the substrate 110, a first gate insulating layer 122 covering the semiconductor layers CH1, E11, E21, CH6, E16 and E26, first gate conductive layers G1 and G6 disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layers G1 and G6, and a second gate conductive layer (e.g., capacitor electrode CAE) disposed on the second gate insulating layer 123.

[0156] Interlayer insulating layer 124 may be disposed on second gate insulating layer 123 and may cover second gate conductive layer (e.g., capacitor electrode CAE).

[0157] The circuit layer 120 may also include a buffer layer 121 disposed on the substrate 110.

[0158] In this case, semiconductor layers CH1, E11, E21, CH6, E16 and E26 can be disposed on buffer layer 121.

[0159] According to an embodiment, each of the light-emitting pixel drivers EPD may include a first transistor T1 and a light-emitting element electrically connected to the first transistor T1 or the light-emitting element. Figure 5 The second to seventh transistors of LE in ( Figure 5 (T2 to T7) and at least one capacitor ( Figure 5 PC1 in the middle.

[0160] Figure 6 It shows Figure 5 The first transistor T1, the sixth transistor T6, and the light-emitting element LE of the light-emitting pixel driver EPD.

[0161] The semiconductor layer disposed on the buffer layer 121 may include channel portions CH1 and CH6, first electrode portions E11 and E16, and second electrode portions E21 and E26 of each of the first transistors T1 to the seventh transistors T7.

[0162] In each of the first transistor T1 and the sixth transistor T6, the first electrode portions E11 and E16 can be electrically connected to one end of the channel portions CH1 and CH6, and the second electrode portions E21 and E26 can be electrically connected to the other end of the channel portions CH1 and CH6.

[0163] The second electrode portion E21 of the first transistor T1 can be electrically connected to the first electrode portion E16 of the sixth transistor T6.

[0164] The first gate conductive layer disposed on the first gate insulating layer 122 may include the gate electrode of each of the first transistor T1 to the seventh transistor T7.

[0165] In each of the first transistor T1 and the sixth transistor T6, the gate electrodes G1 and G6 may be stacked with the channel portions CH1 and CH6.

[0166] Due to the second transistor of the light-emitting pixel driver EPD ( Figure 5 T2 in the middle), the first sub-transistor ( Figure 5 T31 in the middle), the second sub-transistor ( Figure 5 T32 in the middle), the third sub-transistor ( Figure 5 T41 in the middle), the fourth sub-transistor ( Figure 5 T42 in the middle), the fifth transistor ( Figure 5 T5 in the middle) and the seventh transistor ( Figure 5 T7 in the diagram is set to be the same P-type MOSFET as the first transistor T1 and the sixth transistor T6, so repeated descriptions will be omitted below.

[0167] The second gate conductive layer disposed on the second gate insulating layer 123 may include a capacitor electrode CAE.

[0168] The capacitor electrode CAE can be stacked with the gate electrode G1 of the first transistor T1.

[0169] Therefore, the first pixel capacitor ( Figure 5 PC1 in the first transistor T1 can be provided through the capacitor electrode CAE, the gate electrode G1 of the first transistor T1, and the overlapping region between the capacitor electrode CAE and the gate electrode G1 of the first transistor T1.

[0170] The first source-drain conductive layer SDCDL1 disposed on the interlayer insulating layer 124 may include a first anode connection electrode ANCE1.

[0171] The first anode connection electrode ANCE1 can be electrically connected to the second electrode portion E26 of the sixth transistor T6 through the first anode connection hole ANCH1 that penetrates the first gate insulating layer 122, the second gate insulating layer 123 and the interlayer insulating layer 124.

[0172] The second source-drain conductive layer SDCDL2 disposed on the first planarization layer 125 may include a second anode connection electrode ANCE2.

[0173] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2 that penetrates the first planarization layer 125.

[0174] The anode electrode 131 of the element layer 130 can be disposed on the second planarization layer 126, and can be electrically connected to the second anode connection electrode ANCE2 through the third anode connection hole ANCH3 penetrating the second planarization layer 126.

[0175] As a result, the anode electrode 131 can be electrically connected to the second electrode portion E26 of the sixth transistor T6 via the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2.

[0176] The component layer 130 disposed on the circuit layer 120 may include light-emitting elements LE disposed in the light-emitting regions EA1, EA2 and EA3 respectively.

[0177] Each of the light-emitting elements LE may include a structure in which a light-emitting layer 133 is disposed between an anode electrode 131 and a cathode electrode 134 facing each other.

[0178] According to an embodiment, the element layer 130 may include an anode electrode 131 disposed in the light-emitting region EA and partially disposed in the non-light-emitting region NEA, a pixel defining layer 132 disposed in the non-light-emitting region NEA and covering a portion of the anode electrode 131, a spacer layer 132' disposed on a portion of the pixel defining layer 132, a light-emitting layer 133 disposed on the anode electrode 131, and a cathode electrode 134 disposed on the light-emitting layer 133, the pixel defining layer 132, and the spacer layer 132'.

[0179] Each of the light-emitting elements LE may further include a first common layer 135 disposed between the anode electrode 131 and the light-emitting layer 133 and a second common layer 136 disposed between the light-emitting layer 133 and the cathode electrode 134.

[0180] According to an embodiment, the element layer 130 may further include a separation groove SPG disposed around each of the light-emitting regions EA and recessedly formed in the pixel defining layer 132.

[0181] The second common layer 136 can be set not only in the light-emitting area EA of the display area DA, but also in the non-light-emitting area NEA. In this case, the second common layer 136 can be set entirely in the display area DA.

[0182] As a result, the second common layer 136 can be disposed not only on the light-emitting layer 133, but also on the pixel limiting layer 132 and the spacing layer 132'.

[0183] According to an embodiment, the portion of the second common layer 136 disposed on the pixel defining layer 132 can be configured to have a relatively thin thickness on the side surface of the separation groove SPG. As an example, since the second common layer 136 is disposed on the side surface of the separation groove SPG with a sufficiently thin thickness, the second common layer 136 can be disconnected to block current flow through it. As another example, in the process of disposing of the second common layer 136, since the amount of material flowing into the separation groove SPG becomes relatively small, the second common layer 136 can also be separated within the separation groove SPG.

[0184] For example, the second common layer 136 can be disconnected or separated in the separation groove SPG.

[0185] In this configuration, leakage current through the second common layer 136 can be prevented between adjacent light-emitting regions EA. Therefore, defects such as light emission from light-emitting elements LE in which no driving current is applied due to leakage current transmitted from adjacent light-emitting regions EA can be prevented. Consequently, the image quality of the display device 100 can be improved.

[0186] The sealing layer 140 can be disposed on the circuit layer 120 to cover the component layer 130.

[0187] The sealing layer 140 can be used to prevent oxygen or moisture from penetrating into the component layer 130 and to mitigate electrical or physical shocks to the circuit layer 120 and the component layer 130.

[0188] The sealing layer 140 may include a first sealing layer 141, a second sealing layer 142, and a third sealing layer 143. The first sealing layer 141 is disposed on the element layer 130 and includes an inorganic insulating material. The second sealing layer 142 is disposed on the first sealing layer 141, stacked with the element layer 130 of the display area DA, and includes an organic insulating material. The third sealing layer 143 is disposed on the first sealing layer 141, covers the second sealing layer 142, and includes an inorganic insulating material.

[0189] Touch sensor layer 160 may be disposed on sealing layer 140. Touch sensor layer 160 may include touch electrodes for detecting signals that change according to touch of a person or object and sensing the point in the main area MA where the touch of a person or object occurs.

[0190] The overlay window 150 can be set on the touch sensor layer 160.

[0191] Figure 7 It is shown Figure 2 A schematic layout diagram of part C.

[0192] Reference Figure 7 The substrate of the display device 100 according to the embodiment ( Figure 3 110 in the document may include a hole region HLA surrounded by a display region DA and a hole periphery region PHA disposed between the hole region HLA and the display region DA.

[0193] Penetrating the substrate ( Figure 3 110 in the middle), circuit layer ( Figure 3 120 in the middle), component layer ( Figure 3 130 in the middle) and sealing layer ( Figure 3 The light-transmitting hole (140) in the middle Figure 3 The TRH in the pore region can be set in the HLA.

[0194] According to an embodiment, the circuit layer ( Figure 3 120 in the document may include a protective portion RF disposed in the periphery region PHA and sequentially surrounding the periphery region HLA, and one or more sealing auxiliary grooves EAG positioned between adjacent protective portions RF.

[0195] As shown above (refer to the reference) Figure 6 As described, due to the component layer ( Figure 10 The second common layer of 130) Figure 6 The second common layer 136 is set in the display area DA, so the second common layer 136 can also be set in the hole periphery area PHA surrounded by the display area DA.

[0196] The protective element RF and one or more sealing auxiliary grooves EAG located in the periphery region PHA can be used to separate the second common layer located in the periphery region PHA. Figure 6 136 in the middle). As a result, the passage of oxygen or moisture through the light-transmitting pores in the HLA pore region can be delayed ( Figure 3 The second common layer in the periphery region PHA (TRH) and the surrounding region of the hole (TRH) Figure 6 The infiltration of 136 in the middle.

[0197] The display device 100 according to the embodiment may further include a protective portion RF disposed between the hole peripheral region PHA and the hole region HLA and surrounding the hole region HLA, and one or more hole peripheral dams HPDM.

[0198] One or more orifice perimeter dams (HPDM) can be a barrier sealing layer ( Figure 10 The second sealing layer (140 in the text) includes organic materials. Figure 6 (142) The barrier diffuses into the pore region of HLA.

[0199] According to an embodiment, the component layer of the display device 100 ( Figure 6 130 in the figure may also include a separation recess SPG, the separation recess SPG being located in the non-light-emitting area of ​​the display area DA ( Figure 6 The NEA is disposed around each of the light-emitting regions EA and is recessed in the pixel-defining layer 132.

[0200] Because the separation groove SPG can create a second common layer between adjacent light-emitting areas EA ( Figure 6 The 136 in the middle is disconnected, so it can not completely surround each luminous area EA.

[0201] As an example, the separation groove SPG can be set to be parallel to each side of the edge of each of the light-emitting regions EA. For example, the separation groove SPG can be set to be parallel only to each side of the edge of each of the light-emitting regions EA, and can be not set around each vertex.

[0202] In other words, if each of the light-emitting regions EA has a square shape, the edge of each light-emitting region EA can be adjacent to four separate grooves SPG.

[0203] According to an embodiment, the circuit layer ( Figure 3 120 in the figure may include a light-emitting pixel driver EPD arranged in the display area DA along a first direction DR1 and a second direction DR2, and a data signal extending along the second direction DR2. Figure 5 The Vdata in the data is transmitted to the data line DL of the luminous pixel driver EPD.

[0204] Since the light-emitting pixel driver EPD is arranged on both sides of the aperture peripheral region PHA in the second direction DR2, the data line DL can include an aperture cross data line HIDL that intersects with the aperture region HLA or the aperture peripheral region PHA.

[0205] For example, a data line DL may include a hole-crossing data line HIDL that crosses the hole region HLA or the hole periphery region PHA, as well as a regular data line NDL other than a hole-crossing data line HIDL.

[0206] Each of the via cross data lines HIDL may include a first via separation line HINL1, a second via separation line HINL2, and a via bypass line HDE. The first via separation line HINL1 faces the via peripheral region PHA on one side in the second direction DR2, and the second via separation line HINL2 faces the via peripheral region PHA on the other side in the second direction DR2. The via bypass line HDE is disposed in the via peripheral region PHA and electrically connects the first via separation line HINL1 to the second via separation line HINL2.

[0207] The hole bypass line HDE can be set between the sealing auxiliary groove EAG and the display area DA, and can be in the form of a curved arc extending parallel to the periphery of the sealing auxiliary groove EAG.

[0208] Each line in a standard data line NDL can be configured to not intersect with the via region HLA and the via perimeter region PHA, and does not include a curved via bypass line HDE set in the via perimeter region PHA.

[0209] According to an embodiment, circuit layer 120 may also include a dummy light-emitting pixel driver DEPD located closest to the periphery region PHA of the hole.

[0210] Except for the dummy luminescent pixel driver DEPD, which can be not electrically connected to the component layer ( Figure 3 The light-emitting element (130) in the middle Figure 5 Apart from the LE in the image, the dummy emitting pixel driver DEPD can have the same structure as the emitting pixel driver EPD.

[0211] Light-transmitting holes are set in the HLA aperture area ( Figure 3 In the TRH process, physical or chemical shocks can be buffered by using a dummy LED driver DEPD, thus reducing the impact of setting the light-transmitting aperture (THA). Figure 3 The possibility of damaging the light-emitting pixel driver EPD in the TRH process.

[0212] Figure 8 It is according to the embodiment along Figure 7 A schematic cross-sectional view taken by line D-D'. Figure 9 It is shown Figure 8 A schematic enlarged view of part D.

[0213] Reference Figure 8According to the embodiment, the circuit layer 120 of the display device 100 may include an interlayer insulating layer 124 disposed on a substrate 110, a first planarization layer 125 disposed on the interlayer insulating layer 124, two or more protective portions RF disposed on the first planarization layer 125 in the hole peripheral region PHA and sequentially surrounding the hole region HLA, a second planarization layer 126 disposed on the first planarization layer 125 and covering the two or more protective portions RF, and one or more sealing auxiliary grooves EAG positioned between the two or more protective portions RF.

[0214] As an example, two or more protective sections RF and one or more sealing auxiliary grooves EAG can be provided in the sealing auxiliary regions ENAA spaced apart from each of the hole peripheral region PHA and the hole region HLA and the display region DA.

[0215] Each of one or more sealing auxiliary grooves EAG may include a first auxiliary groove ASG1 penetrating the second planarization layer 126 and a second auxiliary groove ASG2 recessed in the first planarization layer 125.

[0216] like Figure 9 As shown, according to an embodiment, the slope INC2 of the side surface of the second auxiliary groove ASG2 can be steeper than the slope INC1 of the side surface of the first auxiliary groove ASG1.

[0217] In the direction in which two or more protective sections RF face each other (e.g., the direction between the hole region HLA and the display region DA), at least a portion of the edge of each of the two or more protective sections RF may protrude beyond the second auxiliary groove ASG2 of one or more sealing auxiliary grooves EAG.

[0218] For example, in the direction where two or more protective parts RF face each other, the width of the gap region between the protective parts RF can be less than the width of the second auxiliary groove ASG2 of one or more sealing auxiliary grooves EAG.

[0219] As a result, in the space between two or more protective sections RF, an undercut structure UC can be formed in which the edges of two or more protective sections RF protrude beyond the second auxiliary groove ASG2.

[0220] Since the second common layer 136 and the cathode electrode 134 of the element layer 130 are completely disposed in the display area DA, the second common layer 136 and the cathode electrode 134 can also be disposed in the hole periphery area PHA surrounded by the display area DA.

[0221] The second common layer 136 can be disposed on the light-emitting layer 133, the pixel limiting layer 132 and the spacing layer 132' in the display area DA.

[0222] The pixel limiting layer 132 can be disposed in the display area DA and does not need to extend to the aperture periphery area PHA. Therefore, the second common layer 136 can be disposed on the second planarization layer 126 in the aperture periphery area PHA.

[0223] Since the second common layer 136 comprises an organic material that is relatively easy to be permeated by oxygen or moisture, oxygen or moisture may easily flow into the circuit layer 120 and component layer 130 of the display area DA through the light-transmitting aperture TRH in the aperture region HLA and the second common layer 136 in the aperture periphery region PHA.

[0224] like Figure 8 As shown, the circuit layer 120 of the display device 100 according to the embodiment may include a protective portion RF disposed in the periphery region PHA of the hole and one or more sealing auxiliary grooves EAG to prevent or delay such penetration.

[0225] Since one or more sealing auxiliary grooves EAG may include a second auxiliary groove ASG2 with a width greater than the gap between the protective parts RF, an undercut structure UC can be formed between the protective part RF and the second auxiliary groove ASG2.

[0226] Therefore, in the process of setting the second common layer 136, since the protective portion RF protrudes beyond the second auxiliary groove ASG2, it is difficult for the organic material to be stacked in a manner that extends from the side surface of the protective portion RF to the side surface of the second auxiliary groove ASG2. For example, the portion of the second common layer 136 located in the periphery region PHA of the hole can be separated by the undercut structure UC. In this case, the second common layer 136 can be broken by the undercut structure UC.

[0227] In other words, the portion of the second common layer 136 disposed in the periphery region PHA may include two or more first partitions 1361 disposed on the second planarization layer 126 and superimposed on two or more protective portions RF, and one or more second partitions 1362 disposed in a second auxiliary groove ASG2 of one or more sealing auxiliary grooves EAG and spaced apart from the two or more first partitions 1361.

[0228] Although the display device 100 according to the embodiment includes a light-transmitting aperture TRH surrounded by a display area DA and a second common layer 136 disposed in a periphery region PHA, the second common layer 136 of the periphery region PHA can be separated by two or more protective portions RF and one or more sealing auxiliary grooves EAG disposed in the periphery region PHA. As a result, the penetration of oxygen or moisture through the second common layer 136 in the periphery region PHA can be delayed. Since the rapid reduction of the lifespan of the display device 100 due to the light-transmitting aperture TRH can be prevented, the overall lifespan of the display device 100 can be improved accordingly.

[0229] like Figure 8 As shown in the embodiment, the protective portion RF disposed in the periphery region PHA on the first planarization layer 125 can be disposed on the same layer as the second source-drain conductive layer SDCDL2 disposed in the display region DA on the first planarization layer 125.

[0230] The second source-drain conductive layer SDCDL2 may include data lines ( Figure 7 (DL in the text).

[0231] Data cable ( Figure 7 The DL in the data path can include a crossover data line ( Figure 7 HIDL (in the context of data cables) and NDL (standard data cables). Crossover data cables (with holes) Figure 7 The HIDL in the middle may include the first hole separation line ( Figure 7 HINL1 in the middle), the second hole separation line ( Figure 7 HINL2) and hole bypass line HDE.

[0232] Crossover data cable ( Figure 7 The hole bypass line HDE of HIDL can be set in the bypass area DETA, which is set between the non-light-emitting area NEA of the display area DA and the sealing auxiliary area ENAA of the hole periphery area PHA.

[0233] According to an embodiment, the display device 100 may further include one or more perimeter dams HPDM, which are disposed between and around the perimeter region HLA and two or more protective portions RF of the perimeter region PHA. For example, one or more perimeter dams HPDM may be sequentially disposed in the perimeter dam region HDMA between the sealing auxiliary region ENAA and the perimeter region HLA in the perimeter region PHA.

[0234] Each of one or more perimeter dams in a HPDM may include two or more dam layers DML11, DML12, DML21, DML22, DML31, DML32 and DML41.

[0235] Each of the dam layers DML11, DML12, DML21, DML22, DML31, DML32 and DML41 can be disposed on the same layer as one of the first planarization layer 125, the second planarization layer 126, the pixel definition layer 132 and the spacing layer 132'.

[0236] As an example, one or more perimeter dams HPDM may include a first perimeter dam HPDM1 adjacent to the sealing auxiliary area ENAA and a second perimeter dam HPDM2 disposed between the first perimeter dam HPDM1 and the perimeter area HLA.

[0237] The first perimeter dam HPDM1 may include a first dam layer DML11 disposed on the same layer as the first planarization layer 125, a second dam layer DML21 disposed on the same layer as the second planarization layer 126, a third dam layer DML31 disposed on the same layer as the pixel defining layer 132, and a fourth dam layer DML41 disposed on the same layer as the spacing layer 132'.

[0238] The second perimeter dam HPDM2 may include a first dam layer DML12 disposed on the same layer as the second planarization layer 126, a second dam layer DML22 disposed on the same layer as the pixel defining layer 132, and a third dam layer DML32 disposed on the same layer as the spacing layer 132'.

[0239] The sealing layer 140 of the display device 100 according to the embodiment may include a first sealing layer 141 disposed on the element layer 130, a second sealing layer 142 disposed on the first sealing layer 141 and superimposed on the display area DA, and a third sealing layer 143 disposed on the second sealing layer 142 and covering the second sealing layer 142.

[0240] The second sealing layer 142 may extend to one or more perimeter dams HPDM and include an organic insulating material spaced apart from the orifice region HLA.

[0241] Each of the first sealing layer 141 and the third sealing layer 143 may include an inorganic insulating material.

[0242] Since the second sealing layer 142 extends to one or more borehole perimeter dams HPDM, the first sealing layer 141 and the third sealing layer 143 can contact each other in the bonding region JNA between the borehole region HLA and the borehole perimeter region PHA, one or more borehole perimeter dams HPDM.

[0243] Since the second sealing layer 142 extends to one or more hole perimeter dams HPDM, and the sealing auxiliary area ENAA is disposed between the hole perimeter dam area HDMA and the display area DA, the protective part RF disposed in the sealing auxiliary area ENAA and one or more sealing auxiliary grooves EAG can be superimposed on the second sealing layer 142.

[0244] In this case, the undercut structure UC formed by the protective part RF and one or more sealing auxiliary grooves EAG can be protected from physical impact by the second sealing layer 142.

[0245] The circuit layer 120 may further include a buffer layer 121 disposed on the substrate 110, a first gate insulating layer 122 disposed on the buffer layer 121, and a second gate insulating layer 123 disposed on the first gate insulating layer 122. An interlayer insulating layer 124 may be disposed on the second gate insulating layer 123.

[0246] Each of the buffer layer 121, the first gate insulating layer 122, the second gate insulating layer 123, and the interlayer insulating layer 124 may include an inorganic insulating material.

[0247] Each of the second common layer 136 and the cathode electrode 134 can be fully positioned within the display area DA.

[0248] Each of the first sealing layer 141 and the third sealing layer 143 may include an inorganic insulating material and may be completely disposed within the display area DA.

[0249] Therefore, the light-transmitting aperture TRH of the aperture region HLA can penetrate the third sealing layer 143, the first sealing layer 141, the cathode electrode 134, the second common layer 136, the interlayer insulating layer 124, the second gate insulating layer 123, the first gate insulating layer 122, the buffer layer 121, and the substrate 110.

[0250] Figure 10 It is according to the embodiment along Figure 7 A schematic cross-sectional view taken by line D-D'.

[0251] Since, in addition to the gaps between two or more protective sections RF being large enough to allow the second sealing layer 142 to be disposed in the second auxiliary groove ASG2 of one or more sealing auxiliary grooves EAG, according to Figure 10 The display device 100 of the embodiment shown herein and according to Figure 8 and Figure 9 The display device 100 shown in the embodiments is basically the same, so repeated descriptions will be omitted below.

[0252] In this case, since the second auxiliary groove ASG2 can be protected by the second sealing layer 142, damage to the second auxiliary groove ASG2 can be prevented due to external physical impacts applied during the manufacturing process and transportation of the display device 100, such as the arrangement of the light-transmitting hole TRH.

[0253] Figure 11 , Figure 12 , Figure 13 and Figure 14 This is a schematic flowchart illustrating a method for manufacturing a display device according to an embodiment. Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 and Figure 25 It is shown Figure 11 , Figure 12 , Figure 13 and Figure 14 Some of the process diagrams in the steps.

[0254] Reference Figure 11 The method for manufacturing a display device 100 according to an embodiment may include the steps of preparing a substrate 110 (S10), forming a circuit layer 120 on the substrate 110 (S20), forming a component layer 130 on the circuit layer 120 (S30), forming a sealing layer 140 on the component layer 130 (S40), and forming a hole region ( Figure 2 The step (S50) of forming a light-transmitting hole TRH that penetrates the substrate 110, circuit layer 120, component layer 130 and sealing layer 140 in the HLA.

[0255] In the step (S10) of preparing the substrate 110, the substrate 110 may include a light-emitting region disposed therein. Figure 4 The display area of ​​EA in ( Figure 2 The DA in the display area), and the non-display area surrounding the DA in the display area ( Figure 2 The NDA in the display area (DA) and the hole area surrounded by the display area DA Figure 2 The HLA in the display area DA and the hole periphery area set between the hole area HLA (in the display area DA) and the hole periphery area set between the hole area DA and the hole area HLA (in the display area DA) Figure 2 (PHA in the middle).

[0256] Reference Figure 12 The step (S20) of setting the circuit layer 120 according to the embodiment may include setting an interlayer insulating layer on the substrate 110. Figure 8In step (S210) of step 124, a first source-drain conductive layer is formed on the interlayer insulating layer 124 in the display area DA. Figure 6 Step (S220) of forming SDCDL1), step (S230) of forming a first planarization layer 125 covering the first source-drain conductive layer SDCDL1 on the interlayer insulating layer 124, and step (S230) of forming a second source-drain conductive layer of display area DA on the first planarization layer 125. Figure 6 and Figure 8 SDCDL2 in the middle) and the protective part of PHA in the periphery of the hole ( Figure 8 The steps (S240) of the first planarization layer 125 and the second planarization layer 126 covering the second source-drain conductive layer SDCDL2 and the protection part RF are performed (S250).

[0257] The step (S20) of setting the circuit layer 120 according to the embodiment may further include setting a semiconductor layer on the substrate 110 before the step (S210) of setting the interlayer insulating layer 124. Figure 6 Step (S201) of CH1, E11, E21, CH6, E16 and E26 in the above, and setting the first gate insulating layer covering the semiconductor layer ( Figure 6 and Figure 8 In step (S202) of 122), a first gate conductive layer is formed on the first gate insulating layer 122. Figure 6 Steps (S203) of G1 and G6 in the above steps, and setting a second gate insulating layer covering the first gate conductive layer. Figure 6 and Figure 8 Step (S204) of 123) and the formation of a second gate conductive layer on the second gate insulating layer 123. Figure 6 Step (S205) of the capacitor electrode (CAE) in the capacitor.

[0258] Reference Figure 13 According to the embodiment, the step (S30) of setting the element layer 130 may include setting the anode electrode of the light-emitting region EA on the second planarization layer 126. Figure 6 In step (S310) of step 131), a pixel definition layer is set on the second planarization layer 126 in the non-light-emitting region NEA between the light-emitting regions EA. Figure 6 and Figure 8 (132 in the middle) and a spacer layer is provided on a portion of the pixel-limiting layer 132. Figure 6 and Figure 8 Step (S320) of 132' in the middle, forming a sealing auxiliary groove in the periphery region PHA of the hole ( Figure 8 (EAG in the display area) and form a separation groove in the display area DA ( Figure 6 and Figure 8 In step (S330) of SPG), a first common layer is formed on the anode electrode 131. Figure 6 Step (S340) of 135 in the first common layer 135: setting a light-emitting layer on the first common layer 135. Figure 6 Step 133 (S350) involves setting a second common layer covering the pixel-defining layer 132, the spacing layer 132', and the light-emitting layer 133 in the display area DA. Figure 6 and Figure 8 Step 136) and setting a cathode electrode on the second common layer 136 Figure 6 and Figure 8 Step (S370) in step 134 of the above.

[0259] The step of setting the sealing layer 140 (S40) may include setting the first sealing layer ( Figure 8 Step (S410) of 141) involves setting a second sealing layer. Figure 8 Step (S420) of 142) and setting the third sealing layer ( Figure 8 Step (S430) in 143).

[0260] Reference Figure 14 A sealing auxiliary groove is formed in the PHA area surrounding the hole. Figure 8 (EAG in the display area) and form a separation groove in the display area DA ( Figure 6 and Figure 8 Step (S330) of the SPG may include setting an oxide material layer covering the pixel defining layer 132 in the display area DA and the second planarization layer 126 in the hole peripheral area PHA. Figure 15 In the OXL layer, a first photomask is formed on the oxide material layer (OXL). Figure 15 In step (S331) of PMSK1, the first oxide mask layer is prepared by partially removing the oxide material layer (OXL) via the first photomask (PMSK1). Figure 16 In step (S332) of OXML1, a first temporary groove penetrating the second planarization layer 126 is formed by partially removing the second planarization layer 126 and the first planarization layer 125 in the periphery region PHA of the hole via the first oxide mask layer OXML1. Figure 17 TMG1 in the middle) and a second temporary groove recessed in the first planarization layer 125 Figure 17 Step (S333) of TMG2), step (S334) of preparing the second photomask PMSK2 by partially removing the first photomask PMSK1, and step (S335) of preparing the second oxide mask layer by partially removing the first oxide mask layer OXML1 via the second photomask PMSK2. Figure 19In step (S335) of OXML2, a separation groove is formed by partially removing the pixel defining layer 132 via the second oxide mask layer OXML2. Figure 8 The sealing auxiliary groove is formed by additionally removing the second planarization layer 126 and the first planarization layer 125 via the second oxide mask layer OXML2, the first temporary groove TMG1 and the second temporary groove TMG2. Figure 8 The steps of (S336) of removing the EAG in the photomask and the steps of removing the second photomask PMSK2 and the second oxide mask layer OXML2 are as follows (S337).

[0261] Reference Figure 15 In step (S331) of setting the oxide material layer OXL and the first photomask PMSK1, the oxide material layer OXL can be set to cover the pixel defining layer 132 in the display area DA and the second planarization layer 126 in the aperture peripheral area PHA by stacking oxide materials. Next, the first photomask PMSK1 can be set by partially removing the photomask material stacked on the oxide material layer OXL.

[0262] The oxide material layer OXL can be integrally disposed within the display area DA and the non-display area NDA of the substrate 110. The oxide material layer OXL can also be disposed within the peri-hole area PHA and the hole area HLA surrounded by the display area DA. Therefore, the oxide material layer OXL can also cover the spacer layer 132' in the display area DA, the peri-hole dam HPDM in the peri-hole area PHA, the interlayer insulating layer 124 surrounding the peri-hole dam HPDM, and the interlayer insulating layer 124 surrounding the hole area HLA.

[0263] The first photomask PMSK1 may include a first transmissive portion PNT1 that exposes the oxide material layer OXL, a first blocking portion BLK1 having a first thickness TH1 on the third direction DR3, and a second blocking portion BLK2 having a second thickness TH2 on the third direction DR3 that is greater than the first thickness TH1.

[0264] The first transmissive part PNT1 can be superimposed on the third-direction DR3 in the area between the protective part RF located in the sealing auxiliary area ENAA of the hole peripheral area PHA.

[0265] The first photomask PMSK1 may include one or more first transmissive elements PNT1 superimposed on the third-direction DR3 in the region between adjacent protective elements RF in the protective elements RF.

[0266] The first blocking part BLK1 can be superimposed on each adjacent part of the co-emitting area EA of the non-emitting area NEA of the display area DA.

[0267] As an example, the first blocking part BLK1 can be superimposed on the adjacent parts on each side of the edge of each of the non-luminous area NEA and the co-luminous area EA.

[0268] The second blocking part BLK2 can be the remaining part of the first photomask PMSK1, excluding the first transmitting part PNT1 and the first blocking part BLK1.

[0269] Reference Figure 16 In the step (S332) of preparing the first oxide mask layer OXML1, the oxide material layer can be partially removed via the first transmissive portion PNT1 of the first photomask PMSK1. Figure 15 The first oxide mask layer OXML1, including the first opening OP1, is prepared using OXL.

[0270] The first opening OP1 may correspond to the first transmissive portion PNT1. For example, the first opening OP1 may be connected to the first transmissive portion PNT1 and may expose the second planarization layer 126 in the periphery region PHA of the aperture.

[0271] Reference Figure 17 In step (S333) of forming the first temporary groove TMG1 and the second temporary groove TMG2, the first temporary groove TMG1 can be formed by partially removing the portion of the second planarization layer 126 exposed through the first opening OP1 of the first oxide mask layer OXML1.

[0272] The first temporary groove TMG1 can penetrate the second planarization layer 126 and expose the first planarization layer 125.

[0273] Next, the second temporary groove TMG2 can be formed by partially removing the portion of the first planarization layer 125 exposed through the first temporary groove TMG1.

[0274] The second temporary groove TMG2 may not completely penetrate the first planarization layer 125 and may be recessed into the first planarization layer 125.

[0275] Reference Figure 18 In step (S334) of preparing the second photomask PMSK2, the second photomask PMSK2 can be prepared by partially removing the first photomask PMSK1.

[0276] As an example, a second photomask PMSK2 can be prepared by performing an ashing process on a first photomask PMSK1 until the entire first blocking portion BLK1 with a first thickness TH1 is removed.

[0277] The second photomask PMSK2 may include a second transmissive portion PNT2 superimposed on the third-direction DR3 in the region between the protective portion RF of the aperture periphery region PHA, a third transmissive portion PNT3 superimposed on each adjacent portion of the co-emitting region EA of the non-emitting region NEA of the display region DA, and a third blocking portion BLK3 having a third thickness TH3 smaller than the second thickness TH2.

[0278] By removing the second blocking portion BLK2 of the first photomask PMSK1 from the first transmitting portion ( Figure 17 The portion surrounding PNT1 is used to prepare the second transmission part PNT2.

[0279] For example, the second transmissive portion PNT2 can correspond to the first transmissive portion ( Figure 17 PNT1 in the middle), and can have a larger than the first transmission part ( Figure 17 The width of PNT1 in the text.

[0280] Therefore, the portion of the first oxide mask layer OXML1 around the first temporary groove TMG1 can be exposed without being covered by the second photomask PMSK2.

[0281] By removing the first blocking part ( Figure 17 The third transmission part PNT3 is prepared by (BLK1 in the text). For example, the third transmission part PNT3 can correspond to the first blocking part (BLK1 in the text). Figure 17 BLK1 in the middle).

[0282] It can be used as a second blocking part ( Figure 17 The remaining part of BLK2 is used to prepare the third blocking part BLK3.

[0283] Reference Figure 19 In step (S335) of preparing the second oxide mask layer OXML2, the second oxide mask layer OXML2, including the second opening OP2 and the third opening OP3, can be prepared by partially removing the first oxide mask layer OXML1 via the second transmission portion PNT2 and the third transmission portion PNT3 of the second photomask PMSK2.

[0284] The second opening OP2 may correspond to the second transmissive portion PNT2. For example, the second opening OP2 may be connected to the second transmissive portion PNT2, and may expose the first temporary groove TMG1 and the second planarization layer 126 surrounding the first temporary groove TMG1.

[0285] The third opening OP3 may correspond to the third transmissive section PNT3. For example, the third opening OP3 may be connected to the third transmissive section PNT3, and the pixel limiting layer 132 of the display area DA may be exposed.

[0286] Reference Figure 20 In step (S336) of forming the sealing auxiliary groove EAG, the first auxiliary groove ASG1 can be prepared by removing the portion of the second planarization layer 126 around the first temporary groove TMG1 through the second opening OP2 of the second oxide mask layer OXML2. The second auxiliary groove ASG2 can be prepared by removing the portion of the first planarization layer 125 around the second temporary groove TMG2 through the second opening OP2 of the second oxide mask layer OXML2 and the first auxiliary groove ASG1.

[0287] Similar to the lower width of the first temporary groove TMG1, the lower width of the first auxiliary groove ASG1 is limited by the gap between the protective parts RF. However, due to the second opening OP2, which is wider than the first opening OP1, the upper width of the first auxiliary groove ASG1 becomes wider than the upper width of the first temporary groove TMG1. Therefore, the slope of the side surface of the first auxiliary groove ASG1 can be less than the slope of the side surface of the first temporary groove TMG1.

[0288] The second auxiliary groove ASG2 can be prepared by additionally removing a portion around the second temporary groove TMG2 using etching material introduced through the region between the first auxiliary groove ASG1 and the protective portion RF. Therefore, the second auxiliary groove ASG2 can be formed to have a greater depth in the third direction DR3 than the second temporary groove TMG2. Furthermore, the upper width of the second auxiliary groove ASG2 is limited by the gap between the protective portions RF, while the lower width of the second auxiliary groove ASG2 can be wider than the lower width of the second temporary groove TMG2 due to the additional etching process. Therefore, the slope of the side surface of the second auxiliary groove ASG2 can be steeper than the slope of the side surface of the second temporary groove TMG2.

[0289] In this case, the slope of the side surface of the second auxiliary groove ASG2 can be steeper than the slope of the side surface of the first auxiliary groove ASG1.

[0290] As a result, one or more sealing auxiliary grooves EAG, including a first auxiliary groove ASG1 and a second auxiliary groove ASG2, can be prepared.

[0291] Due to the etch ratio between the first planarization layer 125 and the protective portion RF, at least a portion of the edge of each of the protective portions RF can protrude beyond the sealing auxiliary groove EAG in the direction in which the protective portions RF face each other.

[0292] For example, an undercut structure UC can be formed between the protective part RF and the second auxiliary groove ASG2 of the sealing auxiliary groove EAG.

[0293] The separation groove SPG can be formed by partially removing the pixel-limiting layer 132 exposed through the third opening OP3 of the second oxide mask layer OXML2.

[0294] The separation groove SPG can be recessed in the pixel-defining layer 132.

[0295] As described above, according to the embodiment, since the number of mask processes during the manufacturing process of the display device 100 can be reduced by using the same mask process as the sealing auxiliary groove EAG to prepare the separation groove SPG, this can help reduce manufacturing costs and improve the yield of the display device 100.

[0296] Reference Figure 21 After forming the sealing auxiliary groove EAG and the separation groove SPG, the step of removing the second photomask PMSK2 and the second oxide mask layer OXML2 can be performed (S337).

[0297] Reference Figure 22 In the step of setting the first common layer 135 (S340), the first common layer 135 can be set by stacking organic materials on the anode electrode 131. Next, in the step of setting the light-emitting layer 133 (S350), the light-emitting layer 133 can be set by stacking light-emitting materials on the first common layer 135. Next, in the step of setting the second common layer in the display area DA (S360), the second common layer 136 can be set by sequentially stacking organic materials covering the pixel defining layer 132, the spacer layer 132', and the light-emitting layer 133 throughout the entire display area DA.

[0298] In this case, since the second common layer 136 is configured to have a relatively thin width in the separation groove SPG of the display area DA, the second common layer 136 can be disconnected or separated through the separation groove SPG.

[0299] The portion of the second common layer 136 located in the periphery region PHA can be separated by the undercut structure UC formed between the second auxiliary groove ASG2 of the protective part RF and the sealing auxiliary groove EAG.

[0300] For example, the portion of the second common layer 136 disposed in the periphery region PHA may include two or more first partitions 1361 disposed on the second planarization layer 126 and superimposed on two or more protective portions RF, and one or more second partitions 1362 disposed in a second auxiliary groove ASG2 of one or more sealing auxiliary grooves EAG and spaced apart from the two or more first partitions 1361.

[0301] Reference Figure 23In step (S370) of setting the cathode electrode 134, the cathode electrode 134 can be set by stacking conductive material covering the second common layer 136. As an example, the cathode electrode 134 may include a transparent conductive material. In other embodiments, the cathode electrode 134 may contact the first planarization layer 125 within a second auxiliary groove ASG2 of one or more sealing auxiliary grooves EAG.

[0302] Reference Figure 24 In step (S40) of setting the sealing layer 140, a first sealing layer 141 covering the cathode electrode 134 of the element layer 130 can be set by completely stacking inorganic insulating material over the display area DA and the non-display area NDA. A second sealing layer 142 can be set by diffusing and then curing organic insulating material that falls onto the first sealing layer 141. A third sealing layer 143 covering the second sealing layer 142 can be set by completely stacking inorganic insulating material over the display area DA and the non-display area NDA. In other embodiments, in each of the regions between the first planarization layer 125 and the second planarization layer 126 and one or more peri-hole dams HPDM, between one or more peri-hole dams HPDM, and between one or more peri-hole dams HPDM and the hole area HLA, the first sealing layer 141 may contact the interlayer insulating layer 124.

[0303] Reference Figure 25 In the step (S50) of forming the light-transmitting aperture TRH, the light-transmitting aperture TRH can be formed by partially removing the aperture region HLA of the substrate 110 and the portion of each of the circuit layer 120, the component layer 130 and the sealing layer 140 stacked on the aperture region HLA.

[0304] The above description is an example of the disclosed technical features, and those skilled in the art will be able to make various modifications and variations. Therefore, the disclosed embodiments described above can be implemented individually or in combination with each other.

[0305] The embodiments disclosed herein are not intended to limit the spirit of the disclosed technology, but rather to describe it, and the scope of the disclosed spirit of the technology is not limited by these embodiments. The scope of protection of the disclosure should be interpreted by the claims, and should be construed as including all technical spirit within the equivalent scope within the scope of the disclosure.

Claims

1. A display device, characterized by comprising: The display device includes: a substrate; a circuit layer disposed on the substrate; an element layer disposed on the circuit layer; and a sealing layer disposed on the element layer, wherein the display device includes: a display area in which a light emitting area is arranged; a non-display area disposed adjacent to the display area; a hole area surrounded by the display area; and a hole peripheral area disposed between the hole area and the display area, the circuit layer includes: an interlayer insulating layer disposed on the substrate; a first planarization layer disposed on the interlayer insulating layer; a protection portion disposed in the hole peripheral area on the first planarization layer and surrounding the hole area; a second planarization layer disposed on the first planarization layer and covering the protection portion; and one or more sealing auxiliary grooves positioned between adjacent protection portions in the protection portion, each of the one or more sealing auxiliary grooves includes: a first auxiliary groove penetrating the second planarization layer; and a second auxiliary groove recessed formed in the first planarization layer, a slope of a side surface of the second auxiliary groove with respect to the substrate is steeper than a slope of a side surface of the first auxiliary groove with respect to the substrate, wherein at least a portion of an edge of each of the protection portions protrudes more than the second auxiliary groove of the one or more sealing auxiliary grooves in a direction in which the protection portions face each other, and an undercut structure is positioned between the protection portion and the second auxiliary groove of the one or more sealing auxiliary grooves.

2. The display device according to claim 1, wherein The display device further includes: a light-transmitting hole formed in the hole area and penetrating the substrate, the circuit layer, the element layer, and the sealing layer; and one or more hole peripheral dams disposed between the protection portion and the hole area and surrounding the hole area, wherein the one or more hole peripheral dams are spaced apart from each of the first planarization layer, the second planarization layer, and the hole area, the sealing layer includes: a first sealing layer disposed on the element layer; a second sealing layer disposed on the first sealing layer and superposed with the display area; and a third sealing layer disposed on the first sealing layer and covering the second sealing layer, the second sealing layer extends to the one or more hole peripheral dams and includes an organic insulating material spaced apart from the hole area, the first sealing layer and the third sealing layer include an inorganic insulating material and are in contact with each other in an area between the one or more hole peripheral dams of the hole peripheral area and the hole area, and the protection portion is superposed with the second sealing layer.

3. The display device according to claim 2, wherein The element layer includes: an anode electrode disposed in the light emitting area; a pixel defining layer disposed in a non-light emitting area adjacent to the light emitting area and covering an edge of each of the anode electrodes; a spacer layer disposed on a portion of the pixel defining layer; a first common layer disposed on the anode electrode; a light emitting layer disposed on the first common layer; and a second common layer disposed on the light emitting layer. a second common layer disposed in the display area and the hole peripheral area and covering the pixel defining layer, the spacer layer, and the light emitting layer; and a cathode electrode disposed on the second common layer.

4. The display device according to claim 3, wherein The element layer further includes a separation groove disposed around each of the light emitting areas and recessed in the pixel defining layer. 5.The display device according to claim 4, wherein the separation groove is parallel to each side of an edge of each of the light emitting areas, and the second common layer is broken in the separation groove.

6. The display device according to claim 5, wherein The portion of the second common layer disposed in the hole peripheral area includes: a first partition portion disposed on the second planarization layer and superposed with the protection portion; and one or more second partition portions disposed in the second auxiliary groove of the one or more sealing auxiliary grooves and spaced apart from the first partition portion.

7. The display device according to claim 6, wherein The cathode electrode contacts the first planarization layer in the second auxiliary groove of the one or more sealing auxiliary grooves. 8.The display device according to claim 3, wherein each of the one or more hole peripheral dams includes a plurality of dam layers, and each of the plurality of dam layers is disposed in the same layer as one of the first planarization layer, the second planarization layer, the pixel defining layer, and the spacer layer, wherein the first sealing layer contacts the interlayer insulating layer in each of an area between the first planarization layer and the second planarization layer and the one or more hole peripheral dams, an area between the one or more hole peripheral dams, and an area between the one or more hole peripheral dams and the hole area. 9.The display device according to claim 3, wherein the circuit layer further includes a first source-drain conductive layer disposed in the display area on the interlayer insulating layer and covered by the first planarization layer, and a second source-drain conductive layer disposed in the display area on the first planarization layer and covered by the second planarization layer, and the protection portion and the second source-drain conductive layer are disposed in the same layer. 10.The display device according to claim 3, wherein the circuit layer further includes a buffer layer disposed on the substrate, a first gate insulating layer disposed on the buffer layer, and a second gate insulating layer disposed on the first gate insulating layer, the interlayer insulating layer is disposed on the second gate insulating layer, and the light-transmitting hole penetrates the third sealing layer, the first sealing layer, the cathode electrode, the second common layer, the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, the buffer layer, and the substrate.

Images