Inter-board connection module, inter-board connector and electronic connection system
By designing the inter-board connection module using a 50-row × 6-column pin arrangement in the FPGA motherboard design, the problems of large size and low pin utilization of FMC connectors are solved, achieving miniaturization of connectors and efficient use of space.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2026-03-17
AI Technical Summary
In existing FPGA motherboard designs, the FMC connector is too large and has low integration due to the large number of pins, which limits the layout space of other devices on the board and results in low pin utilization.
The inter-board connection module is designed with a 50-row × 6-column pin arrangement, including a high-speed differential signal area, a low-speed single-ended signal area, a first power signal area, and a second power signal area. The pin layout is optimized, and the female connector is electrically connected to the motherboard, while the male connector is electrically connected to the daughterboard, achieving a compact pin design.
It significantly reduces the space volume of the board-to-board connector, improves the effective utilization of pins, provides more layout space for other components on the motherboard and daughterboard, and improves the overall effective space utilization.
Smart Images
Figure CN224006154U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of electrical connector technology, and in particular to an inter-board connection module, an inter-board connector, and an electronic connection system. Background Technology
[0002] In existing FPGA (Field Programmable Gate Array) motherboard designs, FMC (FPGA Mezzanine Card) connectors with a pin arrangement of 40 rows × 10 columns or 40 rows × 16 columns are mostly used as inter-board connectors. However, the large number of pins on FMC connectors results in excessive size and low integration, severely limiting the layout space of other devices on the board and reducing the overall effective space. In addition, the excessive number of pins on FMC connectors is often not fully utilized, reducing the effective utilization rate of connector pins.
[0003] Therefore, while improving the effective utilization rate of connector pins, how to reduce the space volume of inter-board connectors is a technical problem that urgently needs to be solved. Utility Model Content
[0004] The main purpose of this invention is to propose an inter-board connection module, an inter-board connector, and an electronic connection system, which aims to reduce the spatial volume of the inter-board connector while improving the effective utilization rate of the connector pins.
[0005] To achieve the above objectives, this utility model proposes an inter-board connection module, which is disposed between a daughter board and a mother board. The female connector of the inter-board connection module is electrically connected to the mother board, and the male connector of the inter-board connection module is electrically connected to the daughter board. The pin arrangement of the inter-board connection module is 50 rows × 6 columns.
[0006] In one embodiment, the inter-board connection module includes a pin area consisting of pins arranged in 50 rows × 6 columns.
[0007] In one embodiment, the pin region includes a high-speed differential signal region, a low-speed single-ended signal region, a first power signal region, and a second power signal region;
[0008] One side of the low-speed single-ended signal area is close to the right edge of the pin area, and the side of the low-speed single-ended signal area close to the right edge is the right boundary side of the low-speed single-ended signal area.
[0009] The high-speed differential signal region is arranged around the target boundary side, and the target boundary side is the other boundary side in the low-speed single-ended signal region except for the right boundary side;
[0010] The first power signal region and the second power signal region are respectively provided on both sides of the high-speed differential signal region.
[0011] In one embodiment, the high-speed differential signal region includes a differential signal region, a first high-speed serial signal region, and a signal collection region;
[0012] The first high-speed serial signal region and the signal collection region are respectively provided on both sides of the differential signal region. The side of the first high-speed serial signal region away from the differential signal region is close to the first power signal region, and the side of the signal collection region away from the differential signal region is close to the second power signal region.
[0013] The differential signal region and the low-speed single-ended signal region are arranged side by side, with the left boundary of the low-speed single-ended signal region being close to the differential signal region.
[0014] In one embodiment, the signal collection area includes a clock signal area and a second high-speed serial signal area;
[0015] The differential signal region and the low-speed single-ended signal region are arranged side by side to form a signal side by side layer;
[0016] The clock signal area and the second high-speed serial signal area are arranged side by side between the signal side by side arrangement layer and the second power signal area.
[0017] In one embodiment, the inter-board connection module includes differential signal pins, high-speed serial signal pins, power signal pins, clock signal pins, and single-ended signal pins;
[0018] The differential signal pins are located in the differential signal region; the high-speed serial signal pins are located in the first high-speed serial signal region and the second high-speed serial signal region, respectively; the power signal pins are located in the first power signal region and the second power signal region, respectively; the clock signal pin is located in the clock signal region; and the single-ended signal pin is located in the low-speed single-ended signal region.
[0019] There are multiple numbers of differential signal pins, high-speed serial signal pins, power signal pins, clock signal pins, and single-ended signal pins.
[0020] In one embodiment, the inter-board connection module includes a grounding pin, which is disposed in any one or more of the high-speed differential signal area, the low-speed single-ended signal area, the first power signal area, and the second power signal area.
[0021] In one embodiment, the mother plate has first bolt holes at each of its four corner edges, and the daughter plate has second bolt holes at the edges corresponding to the four corner edges.
[0022] Each of the first bolt holes is aligned with the second bolt holes located at the corresponding edge positions and is fixedly connected by bolt posts.
[0023] In addition, this utility model also proposes an inter-board connector, which includes at least the inter-board connection module described in any of the above-mentioned claims.
[0024] In addition, this utility model also proposes an electronic connection system, which includes at least the above-mentioned inter-board connector.
[0025] To address the issues of bulky FMC connectors, excessive pin count, and low effective utilization in existing FPGA motherboard / daughterboard designs, this invention proposes an inter-board connection module positioned between the daughterboard and motherboard. The female connector of the inter-board connection module is electrically connected to the motherboard, while the male connector is electrically connected to the daughterboard. Crucially, this application innovates the pin arrangement of the inter-board connection module from the traditional 40x10 or 40x16 layout to a more compact 50x6 layout. This not only ensures effective pin utilization but also significantly reduces the space volume of the inter-board connector used in the module, thereby achieving miniaturization and freeing up more layout space for other components on the daughterboard and motherboard. This significantly improves the overall effective space utilization of the daughterboard and motherboard. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.
[0027] Figure 1 A schematic diagram of the structure of an embodiment of the inter-plate connection module provided by this utility model;
[0028] Figure 2 This is a schematic diagram of the pin arrangement involved in an embodiment of the present utility model;
[0029] Figure 3 This is a schematic diagram of the pin signals of the power signal area according to an embodiment of the present invention;
[0030] Figure 4 This is a schematic diagram of the pin signals of the low-speed single-ended signal area involved in an embodiment of this utility model;
[0031] Figure 5This is a schematic diagram of the pin signals of the high-speed differential signal region involved in an embodiment of this utility model;
[0032] Figure 6 This is a block diagram of the 3U board structure involved in the embodiments of this utility model;
[0033] Figure 7 This is a block diagram of the 6U board structure involved in the embodiment of this utility model.
[0034] The diagram shows the following symbols: 100, inter-board connection module; 200, daughter board; 300, mother board.
[0035] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0036] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present utility model.
[0037] It should be noted that if the embodiments of this utility model involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.
[0038] Furthermore, if the embodiments of this utility model involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.
[0039] In existing FPGA (Field Programmable Gate Array) motherboard designs, FMC (FPGA Mezzanine Card) connectors with a pin arrangement of 40 rows × 10 columns or 40 rows × 16 columns are mostly used as inter-board connectors. However, due to the large number of pins, these FMC connectors result in increased connector size and relatively low integration, significantly limiting the layout space of other critical components on the motherboard. Specifically, the large size of the FMC connector not only occupies a large area of the motherboard but also further compresses the placement space of other components such as resistors, capacitors, and processors, leading to a significant reduction in overall effective space. Furthermore, in practical applications, due to the diversity of system designs and differences in functional requirements, many pins of the FMC connector are often not fully utilized, leaving a large number of pins idle. This not only results in a significant waste of hardware resources but also further highlights the problem of low effective utilization of connector pins.
[0040] In summary, in order to overcome the above-mentioned technical defects, this utility model proposes an inter-board connection module, an inter-board connector, and an electronic connection system.
[0041] In one embodiment of this utility model, please refer to Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the inter-board connection module 100 provided by this utility model. The inter-board connection module 100 is disposed between the daughter board 200 and the mother board 300. The female connector of the inter-board connection module 100 is electrically connected to the mother board 300, and the male connector of the inter-board connection module 100 is electrically connected to the daughter board 200. The pin arrangement of the inter-board connection module 100 is 50 rows × 6 columns.
[0042] In this embodiment, the inter-board connection module 100 is disposed between the daughter board 200 and the mother board 300. Electrical connections are achieved between the daughter board 200 and the mother board 300 through the female connector of the inter-board connection module 100, and between the male connector of the inter-board connection module 100 and the daughter board 200. The pins of the inter-board connection module 100 adopt a 50-row × 6-column pin arrangement, which significantly optimizes the size and pin layout of the inter-board connection. This not only saves a lot of space on the mother and daughter boards, providing more space for other devices, but also improves the effective utilization rate of pins through a more compact and efficient pin design. Thus, while ensuring connection performance and signal integrity, efficient and reliable inter-board connection between the daughter board 200 and the mother board 300 is achieved.
[0043] In summary, addressing the issues of bulky FMC connectors, excessive pins, and low effective utilization in existing FPGA motherboard / daughterboard designs, this invention proposes an inter-board connection module 100 positioned between the daughter board 200 and the mother board 300. The female connector of the inter-board connection module 100 is electrically connected to the mother board 300, while the male connector is electrically connected to the daughter board 200. Crucially, the inter-board connection module 100 of this application innovates the pin arrangement from the traditional 40x10 or 40x16 layout to a more compact 50x6 layout. This not only ensures effective pin utilization but also significantly reduces the spatial volume of the inter-board connector used in the module 100, thereby achieving miniaturization of the connector and freeing up more layout space for other devices on the daughter board 200 and mother board 300. This significantly improves the overall effective space utilization of the daughter board 200 and mother board 300.
[0044] Furthermore, in some feasible embodiments, reference is made to Figure 2 , Figure 2 This is a schematic diagram of the pin arrangement according to an embodiment of the present invention. The inter-board connection module 100 includes a pin area consisting of pins arranged in 50 rows × 6 columns.
[0045] In this embodiment, refer to Figure 2 The board-to-board connection module 100 includes a pin area consisting of pins arranged in 50 rows × 6 columns, meaning that the pin area has 300 pins of the board-to-board connection module 100.
[0046] Furthermore, in some other feasible embodiments, reference is made to... Figure 2 The pin area includes a high-speed differential signal area, a low-speed single-ended signal area, a first power signal area, and a second power signal area. One side of the low-speed single-ended signal area is close to the right edge of the pin area, and the side of the low-speed single-ended signal area close to the right edge is the right boundary side of the low-speed single-ended signal area. The high-speed differential signal area is arranged around the target boundary side, and the target boundary side is the other boundary side of the low-speed single-ended signal area except for the right boundary side. The first power signal area and the second power signal area are respectively arranged on both sides of the high-speed differential signal area.
[0047] In this embodiment, the high-speed differential signal region is composed of Figure 2The diagram shows a first high-speed serial signal area, a differential signal area, a clock signal area, and a second high-speed serial signal area. The first high-speed serial signal area can be understood as the region defined by all columns in rows 4 to 15; the differential signal area can be understood as the region defined by columns C to F in rows 16 to 35; the clock signal area can be understood as the region defined by columns D to F in rows 36 to 47; the second high-speed serial signal area can be understood as the region defined by columns A to C in rows 36 to 47; the low-speed single-ended signal area can be understood as the region defined by columns A to B in rows 16 to 35; the first power signal area can be understood as the region defined by all columns in rows 1 to 3; and the second power signal area can be understood as the region defined by all columns in rows 48 to 50.
[0048] It should be noted that the inter-board connection module 100 is equipped with 12V, 3.3V, 2.5V, 1.8V, and GND level signals in the first and second power signal areas to meet the power supply requirements between the mother and daughter boards and to provide a signal reference ground. For example, Figure 3 The pins shown in the diagram (row 1, column F), (row 50, column F), (row 2, column E), (row 3, column E), (row 48, column E), (row 49, column E), (row 1, column D), (row 50, column D), (row 2, column C), (row 3, column C), (row 48, column C), (row 49, column C), (row 2, column B), (row 49, column B), (row 1, column A), (row 3, column A), (row 48, column A), and (row 50, column A) are ground pins and are configured to connect to the GND signal. Figure 3 The “GND” shown is the ground level signal; Figure 3 The "1P8V" shown indicates a 1.8V level signal. Figure 3 The "2P5V" shown indicates a 2.5V level signal. Figure 3 The "3P3V" shown indicates a 3.3V level signal; Figure 3 The “12P0V” shown indicates a 12V level signal.
[0049] The signals connected to each pin of the inter-board connection module 100 in the low-speed single-ended signal area are as follows: Figure 4 As shown; Figure 4 The “GND” shown is the ground level signal; Figure 4 The “HR” shown This indicates a low-speed single-ended signal, which can be a control level signal or a logic I / O signal. Figure 4 The “PRSNT_M2C_L” shown indicates that the daughterboard 200 is grounded and the motherboard 300 is pulled up at 3.3V. Figure 4The “PG_M2C” indicator shows that the power supply of the daughterboard 200 is Power Good, and the motherboard 300 is pulled down.
[0050] Furthermore, in some feasible embodiments, the high-speed differential signal region includes a differential signal region, a first high-speed serial signal region, and a signal collection region; the first high-speed serial signal region and the signal collection region are respectively arranged on both sides of the differential signal region, the side of the first high-speed serial signal region away from the differential signal region is close to the first power signal region, and the side of the signal collection region away from the differential signal region is close to the second power signal region; the differential signal region is arranged side by side with the low-speed single-ended signal region, and the left boundary side of the low-speed single-ended signal region is close to the differential signal region.
[0051] In this embodiment, Figure 5 In the middle (a), it represents the first high-speed serial signal region, and Figure 5 The “DP(n)_M2C_P, DP(n)_M2C_N” shown in (a) can be understood as a pair of differential signals used to transmit high-speed serial data on the (n+1)th data channel, where n represents an integer greater than or equal to 0. Figure 5 In (a), “I2C_SCL, I2C_SDA” indicates the EEPROM used for expanding daughterboard 200, 3.3V.
[0052] Figure 5 (b) represents the differential signal region. Figure 5 The "HP" shown in (b) _P, HP _N” and “HP” _P_C, HP "_N_C" indicates LVDS (Low-Voltage Differential Signaling).
[0053] The signal collection area includes Figure 5 The clock signal region shown in Figure (c) and the second high-speed serial signal region shown in Figure (b) Figure 5 The “CLK2_FPGA_C2M_P, CLK2_FPGA_C2M_N” shown in (c) can be understood as a pair of differential clock signals transmitted from the FPGA (Field-Programmable Gate Array) to the daughterboard 200.
[0054] Furthermore, in some other feasible embodiments, the signal collection area includes a clock signal area and a second high-speed serial signal area; the differential signal area and the low-speed single-ended signal area are arranged side by side to form a signal side-by-side arrangement layer; the clock signal area and the second high-speed serial signal area are arranged side by side between the signal side-by-side arrangement layer and the second power signal area.
[0055] Furthermore, in some feasible embodiments, the inter-board connection module 100 includes differential signal pins, high-speed serial signal pins, power signal pins, clock signal pins, and single-ended signal pins; the differential signal pins are disposed in the differential signal area, the high-speed serial signal pins are respectively disposed in the first high-speed serial signal area and the second high-speed serial signal area, the power signal pins are respectively disposed in the first power signal area and the second power signal area, the clock signal pins are disposed in the clock signal area, and the single-ended signal pins are disposed in the low-speed single-ended signal area; wherein, there are multiple numbers of differential signal pins, high-speed serial signal pins, power signal pins, clock signal pins, and single-ended signal pins.
[0056] Furthermore, in some other feasible embodiments, the inter-board connection module 100 includes a grounding pin, which is disposed in any one or more of the high-speed differential signal area, the low-speed single-ended signal area, the first power signal area, and the second power signal area.
[0057] Furthermore, in some feasible embodiments, the four corner edges of the mother plate 300 are provided with first bolt holes, and the edges of the daughter plate 200 corresponding to the four corner edges are provided with second bolt holes; each first bolt hole is aligned with the second bolt hole provided at the corresponding edge position and is fixedly connected by bolt posts.
[0058] In summary, addressing the issues of bulky FMC connectors, excessive pins, and low effective utilization in existing FPGA motherboard / daughterboard designs, this invention proposes an inter-board connection module 100 positioned between the daughter board 200 and the mother board 300. The female connector of the inter-board connection module 100 is electrically connected to the mother board 300, while the male connector is electrically connected to the daughter board 200. Crucially, the inter-board connection module 100 of this application innovates the pin arrangement from the traditional 40x10 or 40x16 layout to a more compact 50x6 layout. This not only ensures effective pin utilization but also significantly reduces the spatial volume of the inter-board connector used in the module 100, thereby achieving miniaturization of the connector and freeing up more layout space for other devices on the daughter board 200 and mother board 300. This significantly improves the overall effective space utilization of the daughter board 200 and mother board 300.
[0059] This utility model also proposes an inter-board connector. The inter-board connector includes at least the aforementioned inter-board connection module. The specific structure of the inter-board connection module is as described in the above embodiments. Since the inter-board connector adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here.
[0060] In a specific embodiment, the board-to-board connector provided in this application can be a novel HPMC motherboard-daughter board connector. The novel HPMC motherboard-daughter board connector has a reasonable pin distribution, with pin definitions mainly divided into three parts: high-speed differential signals, low-speed single-ended signals, and power and ground. High-speed differential signals are used to distribute high-speed signals such as clock, SERDES, Ethernet, and optical ports. Low-speed single-ended signals are mainly distributed for control levels and logic I / O signals. Power and ground are allocated with 12V, 3.3V, 2.5V, 1.8V, and GND levels to meet the power supply requirements between the motherboard and daughter boards and to provide a signal reference ground. The pin rate supports high-speed signals up to 25Gb / s, greatly ensuring the transmission performance of high-speed signals.
[0061] Reference Figures 6 to 7 The new HPMC motherboard architecture is compatible with standard 3U and 6U boards and supports daughterboard sizes (93mm). 93mm or 186mm (93mm), ensuring the needs of commonly used signals while compressing connector space and increasing the available space in the PCB layout, achieving an optimal solution for the motherboard / daughterboard design. For example, Figure 6 The sub-board shown is 93mm in size. 93mm, Figure 7 The sub-board shown is 186mm in size. 93mm, Figures 6 to 7 The 301 shown is the motherboard connector; among which, Figure 7 (a) indicates double width (i.e., sub-board size is 186mm). 93mm) - Dual connector, Figure 7 (b) indicates double width (i.e., sub-board size is 186mm). 93mm) - Single connector.
[0062] In summary, this utility model proposes a novel pin distribution definition for HPMC motherboard connectors, which has the following advantages: 1) This application adopts a non-standard customized design, with customizable interconnect connector pins, adapting to more flexible application scenarios; 2) The connector is small in size, saving space, and compared with the FMC+ connector (i.e., the pin arrangement is 40 rows × 16 columns), it improves the effective space of the board layout; 3) The connector pin definition is reasonable and highly integrated, and compared with the FMC connector (i.e., the pin arrangement is 40 rows × 10 columns), it has the same high-speed differential signal differential pairs, maximizing the satisfaction of design requirements; 4) The connector pins fully consider the isolation between signals and ground, ensuring signal integrity.
[0063] This utility model also proposes an electronic connection system, which includes at least the above-mentioned inter-board connector. The specific structure of the electronic connection system is as described in the above embodiments. Since the electronic connection system adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.
[0064] The above description is merely an exemplary embodiment of this utility model and does not limit the patent scope of this utility model. Any equivalent structural transformations made based on the technical concept of this utility model and the contents of this utility model specification and drawings, or direct / indirect applications in other related electrical connector technology fields, are included within the patent protection scope of this utility model.
Claims
1. An inter-board connection module, characterized by, The inter-board connection module is arranged between the daughter board and the mother board, a female seat of the inter-board connection module is electrically connected with the mother board, a male head of the inter-board connection module is electrically connected with the daughter board, and a pin arrangement mode of the inter-board connection module is 50 rows by 6 columns; The inter-board connection module comprises a pin region composed of pins arranged in 50 rows by 6 columns; The pin region comprises a high-speed differential signal area, a low-speed single-end signal area, a first power signal area and a second power signal area; One side of the low-speed single-end signal area is close to a right side edge of the pin region, and the side of the low-speed single-end signal area close to the right side edge is a right boundary side of the low-speed single-end signal area; The high-speed differential signal area is arranged around a target boundary side, and the target boundary side is other boundary side of the low-speed single-end signal area except the right boundary side; The high-speed differential signal area is provided with the first power signal area and the second power signal area on two sides thereof; The high-speed differential signal area comprises a differential signal area, a first high-speed serial signal area and a signal collection area; The differential signal area is provided with the first high-speed serial signal area and the signal collection area on two sides thereof, the side of the first high-speed serial signal area away from the differential signal area is close to the first power signal area, and the side of the signal collection area away from the differential signal area is close to the second power signal area; The differential signal area is arranged side by side with the low-speed single-end signal area, and a left boundary side of the low-speed single-end signal area is close to the differential signal area; The signal collection area comprises a clock signal area and a second high-speed serial signal area; The differential signal area and the low-speed single-end signal area are arranged side by side to form a signal side-by-side arrangement layer; The clock signal area and the second high-speed serial signal area are arranged side by side between the signal side-by-side arrangement layer and the second power signal area; The inter-board connection module comprises differential signal pins, high-speed serial signal pins, power signal pins, clock signal pins and single-end signal pins; The differential signal pins are arranged in the differential signal area, the high-speed serial signal pins are arranged in the first high-speed serial signal area and the second high-speed serial signal area respectively, the power signal pins are arranged in the first power signal area and the second power signal area respectively, the clock signal pins are arranged in the clock signal area, and the single-end signal pins are arranged in the low-speed single-end signal area; wherein the number of the differential signal pins, the number of the high-speed serial signal pins, the number of the power signal pins, the number of the clock signal pins and the number of the single-end signal pins are multiple; The inter-board connection module comprises ground pins, and the ground pins are arranged in any one or multiple of the high-speed differential signal area, the low-speed single-end signal area, the first power signal area and the second power signal area; First bolt holes are arranged at four corner edges of the mother board, and second bolt holes are arranged at edge positions corresponding to the four corner edges of the daughter board; Each first bolt hole is aligned with a second bolt hole arranged at a corresponding edge position and is fixedly connected through a bolt column.
2. An interboard connector characterized by comprising: The inter-board connector at least comprises the inter-board connection module of claim 1.
3. An electronic connection system, characterized by The electronic connection system comprises at least the interboard connector of claim 2.