Device

Abstract

The utility model relates to a device. A power MOSFET device includes at least one air gap between a buried polysilicon source and a sidewall of a recessed substrate. The device includes a plurality of insulating layers on a substrate and defining an air gap.

Description

Technical Field

[0001] Power metal-oxide-semiconductor field-effect transistor (MOSFET) devices include at least one air gap spaced apart from the source polysilicon region in a recessed substrate. Background Technology

[0002] During MOSFET device operation, there is an on-resistance, or Ron, between the drain and gate-source terminals. The Ron value contributes to the device's power dissipation. Therefore, a lower Ron value results in lower power loss.

[0003] Trench field plate power MOSFETs are low-voltage power MOSFETs with low Ron values. The dielectric material of this device contributes to its performance and gate capacitance. Silicon dioxide is commonly used as the dielectric material in this device, with a dielectric constant k or kappa equal to 3.9.

[0004] When silicon dioxide is replaced by an insulating material with a lower dielectric constant, the on-resistance (Rsil) contributed by the silicon composition decreases, through a reduction in resistance from mΩ to mm. 2 Measurements are performed using units that are indicated.

[0005]

[0006] Where γ FP ε represents the aspect ratio of the unit of the field plate. s and ε i The dielectric constants of the semiconductor and the insulator are t and t, respectively. FP For the thickness of the plate, W n Let W be the width of the n pillars. i The width of the insulator.

[0007] The lowest possible dielectric constant is k=1 from air. Air pockets are formed during the copper interconnect at the back end of the line to reduce the effective capacitance, thereby reducing the signal propagation RC (resistance-capacitance) delay. Summary of the Invention

[0008] A power MOSFET device includes at least one air gap in an insulating layer and a buried polysilicon source. The air gap is located between the buried polysilicon source and a recess sidewall in a substrate.

[0009] This disclosure relates to a device including a power MOSFET, the power MOSFET including a substrate having a recess in a first surface extending in a first direction, the first surface extending in a second direction transverse to the first direction, the recess including a second surface extending in the first direction between the sidewalls. The device includes: an insulating layer on the first surface of the substrate and in the recess; a first polysilicon region in the insulating layer extending in the second direction in a first dimension; and an air gap in the insulating layer between the first polysilicon region and the substrate, the air gap extending in the second direction in a second dimension smaller than the first dimension.

[0010] Replacing silicon dioxide with air in the air gap of the field plate region achieves better Rsil performance. The air gap (k=1) in the field plate power MOSFET device helps overcome the Si limitation.

[0011] According to one aspect of this disclosure, a device is provided, comprising: a power MOSFET, including: a substrate, including: a groove in a first surface of the substrate, the first surface extending in a first direction, the groove having sidewalls extending in a second direction transverse to the first direction, the groove including a second surface extending in the first direction between the sidewalls; an insulating layer in the first surface of the substrate and in the groove; a first polysilicon region in the insulating layer, the first polysilicon region extending in the second direction in a first dimension; and an air gap in the insulating layer between the first polysilicon region and the substrate, the air gap extending in the second direction in a second dimension less than the first dimension.

[0012] According to one or more embodiments, the air gap extends in a first direction less than a third dimension of the second dimension.

[0013] According to one or more embodiments, the first polysilicon region extends in a first direction into a third dimension smaller than the first dimension.

[0014] According to one or more embodiments, the first polysilicon region has a first end spaced apart from the second surface of the groove in a third dimension.

[0015] According to one or more embodiments, the air gap has a first end spaced apart from the second surface of the groove by a fourth dimension, and the third dimension is smaller than the fourth dimension.

[0016] According to one or more embodiments, the device includes a field plate oxide layer in the recess and between the substrate and the insulating layer, the field plate oxide layer having a first surface extending in a first direction adjacent to a first surface of the substrate.

[0017] According to one or more embodiments, a first polycrystalline silicon region extends in the field plate oxide layer.

[0018] According to one or more embodiments, the device includes a gate polysilicon region on a first surface of a field plate oxide layer, the gate polysilicon region including protrusions extending into the insulating layer.

[0019] According to one or more embodiments, the device includes a source region and a body region, the source region being on the body region, the body region being in contact with a first surface of the substrate, and a portion of the insulating layer being between the gate polysilicon region and the source region and the body region.

[0020] According to one or more embodiments, the device includes a nitride layer between the field plate oxide layer and the insulating layer, with a first polysilicon region extending through the nitride layer.

[0021] According to one or more embodiments, the air gap is surrounded by the insulating layer.

[0022] According to another aspect of this disclosure, a device is provided, comprising: a power MOSFET, including: a recessed substrate; an insulating layer on the recessed substrate; a first polysilicon region in the insulating layer; a first air gap in the insulating layer; and a second air gap in the insulating layer, the first polysilicon region being between the first air gap and the second air gap.

[0023] According to one or more embodiments, the first air gap and the second air gap are each equidistant from the first polysilicon region in a first direction.

[0024] According to one or more embodiments, the first air gap and the second air gap have substantially the same shape and dimensions.

[0025] According to one or more embodiments, the first air gap and the second air gap extend a first dimension in a second direction transverse to the first direction, the first polysilicon region extends a second dimension greater than the first dimension in the second direction, and the first polysilicon region extends through the insulating layer.

[0026] According to another aspect of this disclosure, a method is provided comprising: forming a power MOSFET device by: forming a first insulating layer on a substrate including a recess, the first insulating layer covering a first surface of the substrate, a recess sidewall, and a second surface of the recess extending between the sidewalls; forming a first polysilicon region in the insulating layer; and forming an air gap in the insulating layer on the substrate.

[0027] According to one or more embodiments, forming the first polysilicon region includes depositing a first polysilicon material on the first insulating layer and in the groove.

[0028] According to one or more embodiments, forming the air gap includes etching the insulating layer to expose the surface of the insulating layer that is recessed relative to a first surface of the substrate.

[0029] According to one or more embodiments, the method includes forming a gate region by depositing a second polysilicon material on the insulating layer and etching the second polysilicon material.

[0030] According to one or more embodiments, the method includes forming a source region and a drain region on the substrate. Attached Figure Description

[0031] In the accompanying drawings, the same reference numerals denote similar features or elements. The size and relative position of features in the drawings are not necessarily drawn to scale, but the relationships between features represent the relationships in the final product.

[0032] Figure 1 It is a power MOSFET device according to the embodiment.

[0033] Figure 2 It is a power MOSFET device including a nitride layer according to another embodiment.

[0034] Figure 3A-3R It is manufacturing Figure 2 The steps of the method for the device.

[0035] Figures 4A-4F It is manufacturing Figure 1 The steps of the method for the device. Detailed Implementation

[0036] The bottom and top are used for orientation and to simplify understanding of the accompanying drawings. The bottom and top are relative to the presented drawings, but may be placed upside down in the final product.

[0037] Figure 1 The device is a power MOSFET device 100, which includes a first insulating layer 120 on a recessed substrate 110. The device 100 includes a second insulating layer 124 on the first insulating layer 120. A polysilicon source 130 is located in the second insulating layer 124 and extends into the first insulating layer 120. The second insulating layer 124 has at least one air gap 160 between the sidewall 115 of the recessed substrate 110 and the polysilicon source 130. At least one gate 140 is located on the first insulating layer 120. A third insulating layer 125 separates the gate 140 from the recessed substrate 110, which has a drain region 116 and a source region 118, with the source region 118 located on the drain region 116.

[0038] The recessed substrate 110 has a first surface or top surface 112 opposite to a second surface or bottom surface 113. A groove or recess extends from the first surface 112 in a vertical direction or a first direction. The groove has opposing sidewalls 115 extending in a vertical direction to a third surface or bottom 114 of the groove. The bottom surface 114 of the groove extends between the sidewalls 115 in a horizontal direction transverse to the first direction or a second direction.

[0039] The bottom surface 114 of the groove extends in a first dimension or width in the horizontal direction. The sidewalls 115 of the groove extend in a second dimension in the first direction. In some embodiments, the first dimension of the bottom surface 114 of the groove is smaller than the second dimension of the sidewalls 115.

[0040] The recessed substrate 110 is made of silicon or other suitable semiconductor material.

[0041] The substrate 110 includes a source region 118 on a drain region 116. The source region 118 is adjacent to the top surface 112 of the substrate.

[0042] A first insulating or field plate oxide layer 120 is present on the substrate 110 and in the recess. The first insulating layer 120 completely coats or covers the bottom surface 114 of the recess. The sidewalls 115 of the recess are partially covered by the first insulating layer 120. In other words, the first surface or top surface 121 of the first insulating layer does not extend beyond the first surface 112 of the substrate. The top surface 121 of the first insulating layer is transverse to the sidewalls 115 of the recessed substrate.

[0043] In some embodiments, the top surface 121 of the first insulating layer is adjacent to and beneath the drain region 116. In other words, the first insulating layer 120 does not contact the drain region 116.

[0044] The first insulating layer 120 includes a second surface or side surface 123 transverse to a first surface 121 of the first insulating layer. The side surface 123 of the first insulating layer extends to a third surface or bottom recessed surface 122 of the first insulating layer. The bottom surface 122 of the insulating layer is opposite to the bottom surface 114 of the recess. The bottom surface 122 of the insulating layer extends between the side surfaces 123 of the first insulating layer.

[0045] The insulating layer is made of silicon dioxide or other suitable insulating material.

[0046] In some embodiments, the thickness of the first insulating layer 120 is not uniform across the entire surface. In one embodiment, the thickness of the first insulating layer 120 on the bottom surface 114 of the recessed substrate is less than the thickness of the first insulating layer 120 on the sidewall 115. In other embodiments, the thickness of the first insulating layer 120 is substantially uniform across the entire surface.

[0047] A second insulating layer 124 is on the first insulating layer 120. The second insulating layer 124 extends in and above a recess in the substrate 110. The second insulating layer 124 contacts a first surface 121, a second surface 122, and a third surface 123 of the first insulating layer 120. The second insulating layer 124 extends beyond the first surface 112 of the substrate. The second insulating layer 124 covers and defines the buried polysilicon source 130 and gate 140. The second insulating layer 124 covers and defines an air gap 160.

[0048] In some embodiments, the second insulating layer 124 is made of the same material as the first insulating layer 120. In this embodiment, the second insulating layer 124 is silicon dioxide.

[0049] In some embodiments, the first insulating layer 120 and the second insulating layer 124 are continuous and integral.

[0050] In some embodiments, the second insulating layer 124 has a groove or notch opposite to the first end 131 of the polysilicon source. In one embodiment, the groove is a central groove. The groove does not extend beyond the top surface 142 of the gate.

[0051] A third insulating layer 125 lies between the first insulating layer 120 and the second insulating layer 124. The third insulating layer 125 lies between the gate 140 and the substrate 110. The third insulating layer 125 covers the top surface 112 of the substrate. The third insulating layer 125 extends vertically on the top surface 112 of the substrate such that the top surface of the third insulating layer 125 is above the top surface 142 of the gate. The third insulating layer 125 covers a portion of the sidewall 115 of the recessed substrate. The third insulating layer 125 contacts the drain region 116 and the source region 118.

[0052] In this embodiment, the third insulating layer 125 has an "L" shape or an angle shape, meaning that the first portion is transverse to the second portion. The third insulating layer 125 covers the corners of the substrate 110. In other embodiments, the third insulating layer 125 has different shapes.

[0053] In some embodiments, the third insulating layer 125 is made of the same material as the first insulating layer 120. In this embodiment, the third insulating layer 125 is silicon dioxide.

[0054] Buried within the second insulating layer 124 is a polysilicon source electrode or field plate 130. The polysilicon source electrode 130 is located at the center of a recess in the substrate 110. The polysilicon source electrode 130 has a top surface 131 opposite to the bottom surface 132. The top surface 131 of the polysilicon source electrode is transverse to the side surface. The top surface 131 of the polysilicon source electrode is covered by the second insulating layer 124. The top surface 131 of the polysilicon source electrode does not extend beyond the first surface 121 of the first insulating layer.

[0055] The bottom surface 132 of the polysilicon source electrode is within the first insulating layer 120. The bottom surface 132 of the polysilicon source electrode is adjacent to and opposite to the bottom surface 114 of the recess. In other words, the polysilicon source electrode 130 does not extend through the first insulating layer 120 to contact the substrate 110. The first insulating layer 120 contacts the portion of the side surface of the polysilicon source electrode 130 adjacent to the bottom surface 132 of the polysilicon source electrode.

[0056] The polysilicon source 130 extends in a first dimension in the vertical direction. The polysilicon source 130 extends in a second dimension in the horizontal direction. The second dimension of the polysilicon source 130 is smaller than the first dimension of the polysilicon source 130.

[0057] In some embodiments, the polysilicon source 130 has an elongated shape in a first direction. In other embodiments, the polysilicon source 130 has different shapes.

[0058] Spaced apart from the polysilicon source 130 is at least one buried air gap or bubble 160. The air gap 160 is within and completely surrounded by the second insulating layer 124. In other words, the second insulating layer 124 defines the air gap 160 in the recess of the substrate 110.

[0059] The air gap 160 has a first end or top end 161 opposite to the second end or bottom end 162. The first end 161 of the air gap does not extend beyond the top surface 121 of the first insulating layer. The top end 161 of the air gap is adjacent to the top surface 131 of the polysilicon source. The second end 162 of the air gap is adjacent to the bottom surface 132 of the polysilicon source. The second end 162 of the air gap is opposite to and adjacent to the third surface 122 of the first insulating layer.

[0060] Air gap 160 extends a first dimension in the vertical direction. In other words, the first dimension is between the top 161 and the bottom 162. Air gap 160 extends a second dimension in the horizontal direction. The first dimension of air gap 160 is greater than the second dimension of air gap 160.

[0061] The first dimension of the air gap 160 is smaller than the first dimension of the polysilicon source 130. The polysilicon source 130 extends beyond the first end 161 and the second end 162 of the air gap.

[0062] In this embodiment, there are a plurality of air gaps 160 that are substantially similar in size and shape. Each air gap 160 is located between each corresponding sidewall 115 of the substrate and the polysilicon source 130. The polysilicon source 130 is substantially equidistant from each air gap 160. The polysilicon source 130 is separated from the air gaps 160 via a second insulating layer 124.

[0063] In some embodiments, the air gap 160 is located at the center between the polysilicon source 130 and the first insulating layer 120. In some embodiments, the air gap 160 is located at the center between the top surface 121 and the bottom surface 122 of the first insulating layer in a first direction.

[0064] In some embodiments, the first dimension of the air gap 160 is greater than half the first dimension of the polysilicon source 130.

[0065] In some embodiments, the air gap 160 has a similar size and shape to the polysilicon source 130, but with a smaller vertical dimension.

[0066] In some embodiments, the second dimension of the air gap 160 ranges from 0.1 to 0.3 μm. In one embodiment, the second dimension of the air gap 160 is approximately 0.2 μm.

[0067] At least one gate 140 is adjacent to the first end 161 of the air gap. The gate 140 is on the top surface 121 of the first insulating layer. The gate 140 does not extend beyond the first end 161 of the air gap. The top surface 142 of the gate is substantially flush with the first surface 112 of the substrate.

[0068] The gate 140 does not completely cover the top surface 121 of the first insulating layer. Instead, a third insulating layer 125 separates the gate 140 from the substrate 110. The third insulating layer 125 contacts the top surface 121 of the first insulating layer between the substrate 110 and the gate 140. The drain region 118 is opposite to the gate 140. The source region 116 is also opposite to the gate 140.

[0069] The top surface 142 of the gate is recessed relative to the top surface 125 of the third insulating layer. In other words, the top surface 142 of the gate is transverse to the surface 125 of the third insulating layer.

[0070] In some embodiments, the top surface 142 of the gate extends beyond the top surface 112 of the substrate. In other embodiments, the top surface 142 of the gate is coplanar with the top surface 112 of the substrate. In other embodiments, the top surface 142 of the gate is lower than or recessed relative to the top surface 112 of the substrate.

[0071] The bottom surface 143 of the gate is opposite to the top surface 142 of the gate. The gate 140 has side surfaces transverse to the bottom surface 143 and the top surface 142 of the gate. The side surfaces of the gate 140 are opposite to each other. The bottom surface 143 of the gate is adjacent to or in contact with the top surface 121 of the first insulating layer.

[0072] Gate 140 includes a protrusion 141 extending from the bottom surface 143 of the gate. The gate protrusion 141 extends on a side surface 123 of a first insulating layer. The gate protrusion 141 has a bottom surface 144 transverse to the side surface 123 of the first insulating layer. In other words, the gate protrusion surface 144 is opposite to the top surface 142 of the gate. A second insulating layer 124 covers the side surface of the gate protrusion 141. The side surface of the gate protrusion 141 is transverse to the bottom surface of the gate protrusion 144.

[0073] The gate 140 is made of polysilicon or other suitable material. In some embodiments, the gate region is made of the same material as the buried polysilicon region.

[0074] In some embodiments, the device 100 includes a plurality of gates 140. Each gate of the plurality of gates 140 faces each other and is separated by a second insulating layer 124. Each gate of the plurality of gates 140 is separated from a corresponding sidewall 115 of the recessed substrate via a third insulating layer 125.

[0075] Drain region 116 and source region 118 are located in or near the first surface 112 of substrate 110. Drain region 116 and source region 118 are doped regions, including n, p, or combinations thereof. Substrate 110 may also include a body region.

[0076] In some embodiments, the drain region 116 does not extend beyond the top surface 121 of the first insulating layer.

[0077] Figure 2 This is a power MOSFET device 200 according to another embodiment. For example... Figure 2 As shown, device 200 includes a first insulating layer 220 on a recessed substrate 210. A nitride layer 290 is on the first insulating layer 220. A second insulating layer 224 is on the nitride layer 290. A buried polysilicon source 230 is located in the second insulating layer 224. Device 200 includes at least one air gap 260 between the nitride layer 290 and the buried polysilicon source 230. Device 200 includes a drain region 216 and a source region 218 adjacent to a gate 240 in the substrate 210. The gate 240 is on the first insulating layer 220 and the nitride layer 290. A third insulating layer 225 separates the gate 240 from the recessed substrate 210.

[0078] like Figure 2 As shown, substrate 210 has a groove in its first surface 212. The first surface 212 of the substrate is opposite to the second surface 213 of the substrate. The sidewall 215 of the substrate extends to the third surface 214 of the substrate.

[0079] like Figure 2As shown, the first insulating layer 220 is a recess in the substrate 210 and completely covers the bottom surface 214 of the substrate. The first insulating layer 220 is on a portion of the sidewall 215 of the substrate. The first insulating layer 220 has a first surface or top surface 221 transverse to the sidewall 215 of the substrate. A second surface or sidewall 223 of the first insulating layer extends transverse to the first surface 221 of the first insulating layer. A third surface 222 of the first insulating layer extends transverse to the second surface 223 of the first insulating layer. The third surface 222 of the first insulating layer is opposite to the third surface 214 of the substrate and extends between the sidewalls 215 of the substrate.

[0080] The nitride layer 290 has a top surface or a first surface that is transverse to the second surface 223 of the first insulating layer. The top surface of the nitride layer 290 is located in a recess in the substrate 210. The first surface of the nitride layer 290 is recessed relative to the first surface 221 of the first insulating layer.

[0081] The second surface or sidewall 292 of the nitride layer extends transversely to the first surface of the nitride layer 290. The third surface 293 of the nitride layer extends transversely to the second surface 292 of the nitride layer. The third surface 293 of the nitride layer is opposite to the third surface 222 of the first insulating layer. A portion of the second surface 223 of the first insulating layer is exposed from the nitride layer 290.

[0082] The top surface of the nitride layer 290 is in contact with or adjacent to the gate 240, and the thickness of the nitride layer 290 is approximately equal to the thickness of the protrusion of the gate 240.

[0083] In some embodiments, the thickness of the nitride layer 290 is less than the thickness of the first insulating layer 220. In other embodiments, the thickness of the nitride layer 290 is substantially equal to the thickness of the first insulating layer 220.

[0084] In some embodiments, the thickness of the nitride layer ranges from 0.1 to 0.5 μm. In one embodiment, the thickness of the nitride layer is approximately 0.35 μm.

[0085] like Figure 2 As shown, gate 240 includes a top surface 242 opposite to bottom surface 243. Side surfaces of gate 240 are transverse to top surface 242 and bottom surface 243. A gate protrusion 241 extends from bottom surface 243 of gate. Gate protrusion 241 has a bottom surface 244 opposite to top surface 242 of gate.

[0086] The bottom surface 244 of the gate protrusion contacts the top surface of the nitride layer 290. The bottom surface 244 of the gate protrusion is transverse to the side surface of the first insulating layer 220. The bottom surface 244 of the gate protrusion is adjacent to the top surface 221 of the first insulating layer.

[0087] like Figure 2As shown, device 200 includes a buried polysilicon source 230. The polysilicon source 230 has a first surface or top surface 231 opposite to a second surface or bottom surface 232. The top surface 231 of the polysilicon source is completely covered by a second insulating layer 224. The bottom surface 232 of the polysilicon source is adjacent to a third surface 214 of the substrate.

[0088] The polysilicon source 230 extends through the nitride layer 290. In other words, a portion of the nitride layer 290 contacts a portion of the polysilicon source 230. The bottom surface 232 of the polysilicon source is within and completely covered by the first insulating layer 220. In other words, a portion of the first insulating layer 220 contacts a portion of the polysilicon source 230.

[0089] In some embodiments, the polysilicon source 230 extends at a midpoint in approximately the first insulating layer 220.

[0090] In this embodiment, the polysilicon source 230 divides the nitride layer 290 into two portions, each portion being coated with a corresponding sidewall 215 of the groove. The two portions of the nitride layer 290 have substantially the same size and shape. In one embodiment, the two portions of the nitride layer 290 are mirror images or reflections of each other.

[0091] The third insulating layer 225 has the same Figure 1 Similar features described in [the text].

[0092] like Figure 2 As shown, the second insulating layer 224 includes at least one air gap 260. The second insulating layer 224 completely surrounds and defines the air gap 260. The air gap 260 is located in a recess in the substrate 210 and is adjacent to the polysilicon source 230. The air gap 260 has a first end 261 opposite to the second end 262. The first end 261 of the air gap does not extend beyond the top surface 231 of the polysilicon source. The first end 261 of the air gap does not extend beyond the top surface of the nitride layer 290. The first end 261 of the air gap is adjacent to the top surface 231 of the polysilicon source. The first end 261 of the air gap is spaced apart from and adjacent to the bottom surface 244 of the gate protrusion.

[0093] An air gap 260 is located between the second surface 292 of the nitride layer and the polysilicon source 230. The second end 262 of the air gap is spaced apart from the third surface 293 of the nitride layer via a second insulating layer 224. The second end 262 of the air gap does not contact the nitride layer 290.

[0094] Figure 3A-3R It is manufacturing Figure 2 The steps of the method for device 200. Chemical vapor deposition (CVD) can be used to easily coat the sidewalls and then clamp the middle portion, thereby forming a closed air gap in a single step.

[0095] Figure 3A The substrate 310 has a first surface or top surface 312 opposite to a second surface or bottom surface 313. The substrate 310 has a plurality of grooves or trenches 311 of substantially similar size and shape in the first surface 312. The grooves 311 are spaced apart from each other. Each groove has a sidewall 315 extending from the first surface 312 to a corresponding bottom surface 314 of the groove. The bottom surface 314 of the groove is opposite to the second surface 313 of the substrate. The substrate 310 is made of silicon or other suitable material.

[0096] In one embodiment, the bottom surface 314 of the groove extends 1 to 2 μm in the second direction. In one embodiment, the bottom surface 314 of the groove extends approximately 1.6 μm in the horizontal direction. In some embodiments, the sidewalls 315 of the groove extend 4 to 6 μm in the vertical direction. In one embodiment, the sidewalls 315 of the groove extend approximately 5 μm in the vertical direction.

[0097] Next, in Figure 3B In this embodiment, a first insulating layer 320, a nitride layer 391, and a second insulating layer 325 are formed on a substrate 310 and in a recess 311. The nitride layer 391 is located between the first insulating layer 320 and the second insulating layer 325. The first insulating layer 320 covers a first surface 312 of the substrate, the sidewalls 315 of the recess, and the bottom surface 314. The first insulating layer 320 has a first thickness. In one embodiment, the thickness of the first insulating layer 320 is [missing information].

[0098] The nitride layer 391 has a second thickness less than the first thickness of the first insulating layer 320. The nitride layer 391 covers the top surface of the first insulating layer 320. In one embodiment, the nitride layer 391 has... The thickness of the nitride layer 391 is silicon nitride or other suitable material.

[0099] The second insulating layer or sacrificial oxide layer 325 has a third thickness that is less than the first thickness of the first insulating layer 320. The first insulating layer 320 and the second insulating layer 325 can be made of the same material. The second insulating layer 325 completely covers the top surface of the nitride layer 391. In one embodiment, the thickness of the second insulating layer 325 is... In other embodiments, the thickness of the second insulating layer 325 is 0.35 μm.

[0100] Next, in Figure 3CIn the process, portions of the nitride layer 391, the first insulating layer 320, and the second insulating layer 325 are removed. A groove 382 defined by the first insulating layer 320, the second insulating layer 325, and the nitride layer 391 is formed. The surfaces of the first insulating layer 320, the second insulating layer 325, and the nitride layer 391 defining the groove 382 are coplanar. After removal, the top surfaces of the first insulating layer 320, the nitride layer 391, and the second insulating layer 325 are exposed. The top surfaces of the first insulating layer 320, the nitride layer 391, and the second insulating layer 325 are coplanar. The bottom surface 383 of the groove is defined by the first insulating layer 320. The bottom surface 383 of the groove is opposite to the bottom surface 314 of the substrate groove.

[0101] In some embodiments, removal is performed via nitride dry etching.

[0102] In some embodiments, removal is performed by etching in the vertical direction.

[0103] Next, in Figure 3D In this process, polysilicon material 332 is deposited on substrate 310. Polysilicon material 332 completely fills groove 382. Polysilicon material 332 covers the top surfaces of the first insulating layer 320 and the second insulating layer 325, as well as the top surface of the nitride layer 391.

[0104] Next, in Figure 3E In the process, a portion of the deposited polycrystalline silicon material 332 is removed. The top surface of the polycrystalline silicon material 332 is exposed and is coplanar with the top surfaces of the first insulating layer 320, the second insulating layer 325, and the nitride layer 391.

[0105] In some embodiments, the polysilicon material 332 extends beyond the first surface 312 of the substrate. In other embodiments, the polysilicon material 332 does not extend beyond the first surface 312 of the substrate. In other words, the top surface of the polysilicon material 332 is coplanar with the first surface 312 of the substrate.

[0106] In some embodiments, removal is performed via chemical mechanical planarization or polishing.

[0107] Next, in Figure 3F A portion of the first insulating layer 320 and the second insulating layer 325 is removed. The removal is performed on the top surfaces of the first insulating layer 320 and the second insulating layer 325, exposing a plurality of recessed top surfaces 321, 327 of the first and second insulating layers. The recessed top surfaces 321, 327 are recessed relative to the first surface 312 of the substrate. The polysilicon material 332 and the nitride layer 391 extend beyond the recessed top surfaces 321, 327. The top surfaces of the polysilicon material 332 and the nitride layer 391 are coplanar. The polysilicon material 332 and the nitride layer 391 extend beyond the top surface 312 of the substrate.

[0108] In other embodiments, the polysilicon material 332 and the nitride layer 391 do not extend beyond the top surface 312 of the substrate.

[0109] In some embodiments, removal is performed via wet etching.

[0110] Next, in Figure 3G In the process, a portion of the nitride layer 391 is removed. The removed portion originates from the top surface of the nitride layer 391 and exposes a recessed top surface 392 of the nitride layer. The removal forms a plurality of grooves 384 defined by the top surface 392 of the nitride layer and the side surfaces of the first insulating layer 320 and the second insulating layer 325. The recessed top surface 392 of the nitride layer is recessed relative to the top surfaces 321, 327 of the first and second insulating layers. The grooves 384 are located between the first insulating layer 321 and the second insulating layer 327.

[0111] In some embodiments, removal is performed via wet etching.

[0112] Next, in Figure 3H In this process, a third insulating layer 328 is formed on the substrate 310. The third insulating layer 328 covers the top surface 312 of the substrate and extends along the sidewall 315 of the substrate. The third insulating layer 328 is in contact with the top surface of the first insulating layer 320. The exposed portion of the polysilicon material 332 is oxidized. The oxidized portion 337 extends beyond the top surface of the second insulating layer 325. Thus, a polysilicon source 336 including the oxidized upper portion 337 is formed.

[0113] A second polysilicon material is deposited on the first insulating layer 320 and the second insulating layer 325. The second polysilicon material fills the groove 384 and contacts the recessed top surface 392 of the nitride layer. The top and side surfaces of the first insulating layer 320 and the second insulating layer 325 are in contact with the second polysilicon material. The second polysilicon material is in contact with the first polysilicon source 336 and the third insulating layer 328.

[0114] Gate 350 is formed by removing a portion of the second polysilicon material. Removal exposes a top surface of gate 350 that is coplanar with the top surface of the oxide portion 337 of the polysilicon source. The top surface of gate 350 is recessed relative to the third insulating layer 328. In other words, the third insulating layer 328 extends beyond the top surface of gate 350. Gate 350 includes protrusions that contact the nitride layer 391.

[0115] In some embodiments, removal is performed by etching, chemical mechanical planarization, or a combination of both.

[0116] Next, in Figure 3IIn this embodiment, a source region 318 and a drain region 316 are formed in a substrate 310. In some embodiments, the formation is performed by implantation or doping. In some embodiments, the formation of the source region 318 and the drain region 316 is performed by a third insulating layer 328.

[0117] Next, in Figure 3J In this process, a mask 380 is formed on a substrate 310. The mask 380 is formed with a plurality of openings. The openings are on a first polysilicon source 336, such that a portion of the gate 350 is exposed from the mask 380. The openings have a dimension M1 in a second direction between the portions of the mask 380. In one embodiment, the dimension M1 is 1.2 μm.

[0118] Next, in Figure 3K In the first portion of device 200, a tilted gate 340 is formed. Formation is performed by etching a first polysilicon source 336 and a gate 350. A mask 380 is used to pattern the gate 350. The tilted gate 340 has a top surface 342 transverse to the side surface of the third insulating layer 328. The exposed tilted surface extends from the top surface 342 of the tilted gate to the second insulating layer 325. A bottom surface 343 of the tilted gate is opposite to the top surface 342. A protrusion 341 of the tilted gate extends from the bottom surface 343. The protrusion 341 of the tilted gate has a bottom surface 344 in contact with the nitride layer 391.

[0119] The first polysilicon source 336 is etched to form the second polysilicon source 330. The second polysilicon source 330 has a top surface 331 that is coplanar with the top surface of the second insulating layer 325. The bottom surface 333 of the second polysilicon source is opposite to the top surface 331. The bottom surface 333 is in the first insulating layer 322.

[0120] In some embodiments, formation is performed via photolithography. In this embodiment, the gate 350 is patterned using a photoresist layer. After etching, the photoresist layer is removed.

[0121] In some embodiments, the second insulating layer 325 has a thickness of 0.4 μm in the second direction. The second polysilicon source 330 has a thickness of 0.3 μm in the second direction. The dimension between the polysilicon source 330 and the substrate 310 in the second direction is 0.6 μm. In other words, the thickness of the nitride layer 391, the first insulating layer 322, and the second insulating layer 325 is 0.6 μm. The first insulating layer 322 has a thickness of 0.2 μm in the second direction.

[0122] Figure 3L This is a top view of device 200. Cross-sectional line A-A' passes through the first portion of device 200 with a tilted gate 340. Cross-sectional line B-B' passes through the second portion of the device with a gate 350.

[0123] Figure 3M yes Figure 3L The cross section of line A-A', and Figure 3N yes Figure 3L The cross-section of line B-B'. Next, the second insulating layer 325 is removed. In some embodiments, the removal is performed via wet etching.

[0124] exist Figure 3M In this process, an air gap 362 is formed by removal. The air gap 362 is buried beneath the gate 350. The air gap 362 is defined by the gate 350 and includes a gate protrusion 351, a nitride layer 391, and a polysilicon source 336. The top surface 352 of the gate is opposite to the bottom surface 353 of the gate. The portion of the bottom surface 353 of the gate between the polysilicon source 336 and the protrusion defines the air gap 362.

[0125] exist Figure 3N In the process, the side surface 333 of the polysilicon source electrode and the surface of the nitride layer 391 are exposed after removal. The surface of the tilted gate 340, including the surface of the gate protrusion, is also exposed.

[0126] Next, the fourth insulating layer 329 is formed. Figure 3O An air gap 360 is formed within the fourth insulating layer 329. The air gap 360 is embedded in the fourth insulating layer 329. The air gap has a first end 361 opposite to the second end 363. The first end 361 of the air gap does not extend beyond the top surface of the top surface of the first insulating layer.

[0127] In some embodiments, the air gap 360 is formed via non-conformal chemical vapor deposition of oxides.

[0128] exist Figure 3P In this process, a fourth insulating layer 329 is formed on the first surface 312 of the substrate, covering the third insulating layer 328 and the top surface of the gate 340.

[0129] Next, a conductive layer 370 is formed on the insulating layer 329. Figure 3Q and Figure 3R In this process, the conductive layer 370 is completely formed on the insulating layer 329.

[0130] In some embodiments, the conductive layer 370 is aluminum or other suitable material. In some embodiments, the conductive layer 370 is formed via plasma metal deposition and planarization.

[0131] exist Figure 3R In this embodiment, a metallization step is performed. Metallization includes forming a contact 372. The contact 372 is located between the conductive layer 370 and the gate 350. The contact 372 contacts the buried polysilicon source 336.

[0132] In some embodiments, contact 372 is made of tungsten or other suitable conductive material.

[0133] Figures 4A-4F It is manufacturing Figure 1 The steps of the method for device 100. Figure 4A and 4B Previously, conducting with Figure 3A-3L The steps described are similar to those described above.

[0134] Not shown, the substrate 410 has multiple grooves in its first surface 412, such as... Figure 3A As shown in the diagram, the second surface 413 of the substrate is opposite to the first surface 412.

[0135] Next, not shown, a first insulating layer 420, a nitride layer, and a second insulating layer are formed on the substrate 410, as follows: Figure 3B As shown in the image.

[0136] Next, not shown, the first insulating layer 420, the nitride layer, and the second insulating layer are etched, as follows: Figure 3C As shown, to form a groove.

[0137] Next, (not shown), a polycrystalline silicon material is deposited, such as... Figure 3D As shown in the image, polycrystalline silicon material fills the grooves.

[0138] Next, a planarization step is performed (not shown) to make the top surfaces of the first insulating layer 420, the nitride layer, the second insulating layer, the polysilicon material, and the substrate 410 coplanar, as shown below. Figure 3E As shown in the image.

[0139] Next, not shown, the first insulating layer 420 and the second insulating layer are etched, as follows: Figure 3F As shown in the diagram, the top surfaces of the first insulating layer 420 and the second insulating layer are recessed relative to the top surface of the polycrystalline silicon material.

[0140] Next, not shown, a third insulating layer 426 is formed on the substrate 410, such as... Figure 3H As shown in the diagram, a portion of the exposed polycrystalline silicon material is oxidized.

[0141] Next, (not shown), a source region 418 and a drain region 416 are formed in the substrate 410, as follows: Figure 3I As shown in the diagram. Formation can be accomplished via doping.

[0142] Next, not shown, a mask is formed on substrate 410, such as... Figure 3J As shown in the image.

[0143] Next, not shown, gate 440 is formed, as follows: Figure 3K As shown in the image.

[0144] Next, in Figure 4A and 4B In the process, the nitride layer and the second insulating layer are removed. The nitride layer is also removed in the same manner as the second insulating layer. Figure 4A It is the cross-section from line A-A', and Figure 4B It is the cross-section from line B-B', such as Figure 3L As shown in the image. Figure 4A It is a part of device 200 with a tilted gate 440, and Figure 4B It is a part of device 200 with an unetched gate 450.

[0145] exist Figure 4A In the middle, remove the second insulating layer, such as Figure 3N As shown in the diagram, the surface of the polysilicon source 430 is exposed after removal. The surface of the gate 440 is also exposed. The surfaces 422 and 423 of the first insulating layer are also exposed. The recessed surface 422 of the first insulating layer is opposite to the recessed surface 414 of the substrate. The side surface of the first insulating layer 423 defines an opening between the polysilicon source 430 and the first insulating layer 423.

[0146] exist Figure 4B In the middle, remove the second insulating layer, such as Figure 3M As shown in the diagram, this forms a buried air gap 462. The air gap 462 is between the first insulating layer and the polysilicon source 436. The air gap 462 is between the gate 450 and the first insulating layer. In other words, the polysilicon source 436, the first insulating layer, and the gate 450 define the air gap 462.

[0147] Next, in Figure 4C and 4D A fourth insulating layer 428 is formed in the middle.

[0148] exist Figure 4C In this configuration, a fourth insulating layer 428 fills the opening between the polysilicon source 430 and the first insulating layer 423. The fourth insulating layer 428 covers the third insulating layer 426 and the gate 440. The fourth insulating layer 428 forms a buried air gap 460 within the opening. The fourth insulating layer 428 contacts the recessed surface 422 of the first insulating layer. The first insulating layer 420, the third insulating layer 426, and the fourth insulating layer 428 can be integral and continuous.

[0149] In some embodiments, the air gap 460 is formed via non-conformal deposition of the fourth insulating layer 428.

[0150] exist Figure 4D In this configuration, the fourth insulating layer 428 is located on the gate 450 and the third insulating layer 426. The fourth insulating layer 428 is in contact with the top surface of the polysilicon source 326.

[0151] Next, in Figure 4E and 4F In the middle, a conductive layer 470 is formed on the fourth insulating layer 428.

[0152] exist Figure 4E In the middle, the conductive layer 470 completely covers the fourth insulating layer 428, such as Figure 3Q As shown in the image.

[0153] exist Figure 4F In this process, a contact 472 is formed between the conductive layer 470 and the gate 450, such as... Figure 3R As shown in the image.

[0154] The various embodiments described above can be combined to provide other embodiments. If necessary, aspects of the embodiments can be modified to incorporate concepts from various patents, applications, and publications to provide yet more embodiments.

[0155] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full scope of the equivalents enjoyed by these claims. Therefore, the claims are not limited by the disclosure.

Claims

1. A device, characterized by Comprising: a power MOSFET, comprising: a substrate, comprising: a recess in a first surface of the substrate, the first surface extending in a first direction, the recess having sidewalls extending in a second direction transverse to the first direction, the recess comprising a second surface extending in the first direction between the sidewalls; an insulating layer on the first surface of the substrate and in the recess; a first polysilicon region in the insulating layer, the first polysilicon region extending a first dimension in the second direction; and an air gap in the insulating layer between the first polysilicon region and the substrate, the air gap extending a second dimension in the second direction that is less than the first dimension.

2. The device of claim 1, wherein, wherein the air gap extends a third dimension in the first direction that is less than the second dimension.

3. The device of claim 1, wherein, wherein the first polysilicon region extends a third dimension in the first direction that is less than the first dimension.

4. The device of claim 1, wherein, wherein the first polysilicon region has a first end spaced apart from the second surface of the recess by the third dimension.

5. The device of claim 4, wherein, wherein the air gap has a first end spaced apart from the second surface of the recess by a fourth dimension, the third dimension being less than the fourth dimension.

6. The device of claim 1, wherein, a field plate oxide layer comprising in the recess and between the substrate and the insulating layer, the field plate oxide layer having a first surface extending in the first direction adjacent the first surface of the substrate.

7. The device of claim 6, wherein, wherein the first polysilicon region extends in the field plate oxide layer.

8. The device of claim 6, wherein, a gate polysilicon region comprising on the first surface of the field plate oxide layer, the gate polysilicon region comprising a protrusion extending into the insulating layer.

9. The device of claim 8, wherein, a source region and a body region, the source region on the body region, the body region in contact with the first surface of the substrate, a portion of the insulating layer between the gate polysilicon region and the source region and body region.

10. The device of claim 7, wherein, a nitride layer comprising between the field plate oxide layer and the insulating layer, the first polysilicon region extending through the nitride layer.

11. The device of claim 1, wherein, wherein the air gap is surrounded by the insulating layer.

12. A device, characterized by Comprising: a power MOSFET, comprising: a recessed substrate; an insulating layer on the recessed substrate; a first polysilicon region in the insulating layer; a first air gap in the insulating layer; and a second air gap in the insulating layer, the first polysilicon region between the first air gap and the second air gap.

13. The device of claim 12, wherein, wherein the first air gap and the second air gap are each equidistantly spaced apart from the first polysilicon region in a first direction.

14. The device of claim 12, wherein, wherein the first air gap and the second air gap have substantially the same shape and dimension.

15. The device of claim 13, wherein, wherein the first air gap and the second air gap extend a first dimension in a second direction transverse to the first direction, the first polysilicon region extending a second dimension in the second direction that is greater than the first dimension, the first polysilicon region extending through the insulating layer.

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