Semiconductor test structure and wafer

Abstract

The utility model provides a semiconductor test structure and a wafer, and the semiconductor test structure comprises a grid layer which is disposed on the surface of a substrate and forms a continuous pattern; the barrier layers are arranged on the two sides and the top of the gate layer; the metal silicide layer comprises a plurality of metal silicide sections, and the plurality of metal silicide sections are respectively arranged on the barrier layer; the bottom ends of the metal plugs face the metal silicide sections, and one metal silicide section corresponds to two metal plugs; the metal layer comprises a plurality of metal sections, and in the continuous path direction of the gate layer, one metal section is connected to the close ends of the two adjacent metal silicide sections and the top ends of the two corresponding metal plugs; and at the two ends of the gate layer, the top ends of the metal plugs on the metal silicide sections are connected with metal sections. According to the utility model, the detection efficiency of the contact resistance can be improved in the manufacturing process of self-aligned polycrystalline silicon.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a semiconductor testing structure and wafer. Background Technology

[0002] In the fabrication process of self-aligned polysilicon (SA-Poly), after forming a metal silicide on top of the gate, a contact hole (CT) can be formed above the metal silicide, and a metal plug is filled within the contact hole. There is contact resistance between the metal plug and the metal silicide, which currently requires detection at specific locations using transmission electron microscopy (TEM). However, detection at specific locations requires chip packaging for verification, which is very inefficient and prone to missing defect areas when the sample size is limited. Therefore, improvements are needed. Utility Model Content

[0003] This invention provides a semiconductor testing structure and wafer to improve the technical problems of low efficiency in contact resistance detection and easy omission of defect areas in the prior art.

[0004] This utility model provides a semiconductor testing structure, comprising:

[0005] A gate layer is disposed on the surface of a substrate, and the gate layer is formed with a continuous pattern;

[0006] A barrier layer is disposed on both sides and the top of the gate layer;

[0007] A metal silicide layer includes multiple metal silicide segments, each of which is disposed on the barrier layer.

[0008] Multiple metal plugs, the bottom ends of which face the metal silicide segment, and one metal silicide segment corresponds to two metal plugs;

[0009] The metal layer includes multiple metal segments, and along the continuous path direction of the gate layer, the near ends of two adjacent metal silicide segments are connected to the top ends of the corresponding two metal plugs.

[0010] Wherein, at both ends of the gate layer, the metal plugs on the metal silicide segments are connected to the metal segments, and the metal segments corresponding to the two ends of the gate layer are respectively referred to as the first test end and the second test end;

[0011] The first test terminal, the second test terminal, and the plurality of metal silicide segments, the plurality of metal plugs, and the plurality of metal segments between the two ends of the gate layer form a test circuit.

[0012] In one embodiment of this utility model, two metal segments connected to a metal silicide segment are respectively designated as the third test terminal and the fourth test terminal, and the third test terminal and the fourth test terminal form a test circuit with the metal silicide segment.

[0013] In one embodiment of the present invention, the metal plug is connected to both ends of the metal silicide segment.

[0014] In one embodiment of this invention, the bottom end of the metal plug faces the metal silicide segment corresponding to the top of the gate layer.

[0015] In one embodiment of the present invention, the bottom end of a metal plug is connected to the first or last end of the gate layer, and the top end of the metal plug is connected to a metal segment, which is referred to as the fifth test end.

[0016] Connect the first test terminal and the second test terminal to form the sixth test terminal;

[0017] The fifth test terminal and the sixth test terminal, together with the plurality of metal silicide segments, the plurality of metal plugs and the plurality of metal segments between the two ends of the gate layer, form a test circuit.

[0018] In one embodiment of the present invention, the semiconductor test structure further includes a plurality of sidewall structures, wherein the plurality of sidewall structures are disposed on both sides of the gate layer;

[0019] The bottom end of the metal plug faces the metal silicide segment corresponding to the outer side of the sidewall structure, or the bottom end of the metal plug faces the metal silicide segment corresponding to the top of the sidewall structure.

[0020] In one embodiment of the present invention, on one of the metal silicide segments, the bottom end of one metal plug faces the metal silicide segment corresponding to one side of the sidewall structure, and the bottom end of the other metal plug faces the metal silicide segment corresponding to the other side of the sidewall structure.

[0021] In one embodiment of the present invention, on one of the metal silicide segments, the bottom ends of the two metal plugs face the metal silicide segments corresponding to the same side of the sidewall structure.

[0022] In one embodiment of the present invention, the metal segment is located on the same side of the two adjacent metal silicide segments.

[0023] This invention also proposes a wafer including a dicing channel, wherein a semiconductor testing structure as described above is provided within the dicing channel.

[0024] The beneficial effects of this utility model are as follows: This utility model proposes a semiconductor testing structure and wafer. An unexpected technical effect is that by having the bottom end of a metal plug facing a metal silicide segment, with one metal silicide segment corresponding to two metal plugs, and a metal segment connecting the top of the metal plugs at the near ends of two adjacent metal silicide segments, a continuous structure can be formed between multiple metal segments, multiple metal plugs, and multiple metal silicide segments as follows: (metal segment-metal plug-metal silicide segment-metal plug)-(metal segment-metal plug-metal silicide segment-metal plug)-…-(metal segment-metal plug-metal silicide segment-metal plug)-metal segment. Therefore, by performing electrical tests on the metal segments at both ends of the gate layer, the contact resistance value between the metal plug and the metal silicide segment can be obtained, thereby determining whether a process defect has occurred. Wafer acceptance testing can be performed during the semiconductor device manufacturing process, thus improving the efficiency of contact resistance monitoring. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 An electron microscope image of a semiconductor test structure provided in an embodiment of this utility model.

[0027] Figure 2 Provided for an embodiment of this utility model Figure 1 Sectional view along line AA.

[0028] Figure 3 Provided for an embodiment of this utility model Figure 2 A schematic diagram showing the location where contact resistance is formed.

[0029] Figure 4 Provided for an embodiment of this utility model Figure 1 Sectional view along the BB direction.

[0030] Figure 5This is a schematic diagram of a semiconductor testing structure provided in an embodiment of the present invention.

[0031] Figure 6 Provided for an embodiment of this utility model Figure 5 The diagram does not show a schematic of the semiconductor test structure corresponding to the metal layer.

[0032] Figure 7 Provided for an embodiment of this utility model Figure 6 A top-view cross-sectional diagram of the CC section.

[0033] Figure 8 Provided for an embodiment of this utility model Figure 6 Another top-view cross-sectional diagram at point CC.

[0034] Figure 9 Provided for an embodiment of this utility model Figure 6 Another top-view cross-sectional diagram at point CC.

[0035] Figure 10 This is a schematic diagram of a semiconductor testing structure provided in another embodiment of the present invention.

[0036] Figure 11 Provided for an embodiment of this utility model Figure 10 The diagram does not show a schematic of the semiconductor test corresponding to the metal layer.

[0037] Figure 12 Provided for an embodiment of this utility model Figure 11 A top-view cross-section diagram of the DD section.

[0038] Figure 13 Provided for an embodiment of this utility model Figure 11 Another top-view cross-section diagram at point DD.

[0039] Figure 14 Provided for an embodiment of this utility model Figure 11 Another top-view cross-section diagram at point DD.

[0040] Explanation of icon numbers

[0041] 100, Substrate; 10, Gate; 110, Sidewall structure; 20, Barrier layer; 30, Metal silicide segment; 40, Metal plug; 50, Metal segment; 510, First test terminal; 520, Second test terminal; 530, Third test terminal; 540, Fourth test terminal; 550, Fifth test terminal. Detailed Implementation

[0042] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0043] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0044] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present invention.

[0045] Please see Figures 1 to 14 This invention proposes a semiconductor testing structure and wafer applicable to the fabrication process of self-aligned polysilicon (SA-Poly). It enables the detection of contact resistance between the metal plug at the bottom of the contact hole (CT) and the metal silicide during semiconductor device fabrication, thus improving testing efficiency. Detailed descriptions are provided below using specific embodiments.

[0046] Please see Figure 1 The image shows an electron microscope (EMS) image of a semiconductor test structure. The cross-sectional view along axis AA shows the location of the contact resistance (Rc) within the semiconductor test structure. Figure 2 and Figure 3 As shown. Contact resistance refers to the resistance of the interface between a metal and a semiconductor, caused by the Schottky barrier or ohmic contact formed between them. In this embodiment, contact resistance refers to the resistance value of the interface between the metal plug 40 and the metal silicide segment 30. In semiconductor devices, contact resistance has a significant impact on device performance, especially in high-frequency and high-speed devices. The magnitude of contact resistance directly affects signal transmission speed and power consumption. Reducing contact resistance can improve device reliability and reduce signal loss.

[0047] Please see Figure 1 , Figure 1 The BB cross-sectional view in the image shows the location where the block resistance (Rs) is formed in the semiconductor test structure, such as... Figure 4 As shown. Sheet resistance refers to the resistance within a unit square area, usually expressed in Ω / □ (ohms per square), and is an indicator of the conductivity of a material, especially in the case of thin films. In this embodiment, sheet resistance refers to the resistance value on a metal silicide segment 30. In semiconductor devices, sheet resistance measurement is crucial for evaluating the quality of materials such as polycrystalline silicon, doped silicon, and metallization layers. The level of sheet resistance directly affects the conductivity of the device, such as the source and drain regions of a transistor.

[0048] Please see Figure 5 , Figure 6 and Figure 7 In one embodiment of this utility model, a semiconductor test structure is proposed, which may include a gate layer 10, a barrier layer 20, a metal silicide layer, a metal plug 40, and a metal layer.

[0049] Specifically, a gate layer 10 is disposed on the surface of the substrate 100, and the gate layer 10 forms a continuous pattern. The substrate 10 provided in this embodiment is, for example, a silicon semiconductor substrate, and the substrate 10 can be an undoped substrate or a doped substrate, such as an N-type substrate or a P-type substrate. The thickness of the substrate 10 is not specifically limited and is selected according to the fabrication requirements. A gate layer 10 is formed on the surface of the substrate 100, and a gate dielectric layer, which is an insulating layer, may be provided between the substrate 100 and the gate layer 10. The main function of the gate layer 10 is to control the current flow between the source and drain. Figure 5 and Figure 6 As shown, in this embodiment, the gate layer 10 can be in the form of a continuous bent structure.

[0050] Specifically, the barrier layer 20 is disposed on both sides and the top surface of the gate layer 10. The barrier layer 20 is an insulating layer that can insulate the gate layer 10. The barrier layer 20 can be a silicon dioxide layer.

[0051] Specifically, the metal silicide layer may include multiple metal silicide segments 30, which may be respectively disposed on the barrier layer 20. The formation process of the metal silicide segments 30 can utilize a self-aligned polysilicon (SA-Poly) process. First, a polysilicon film is formed on the barrier layer 20, and a metal film can be formed on the polysilicon film. Second, a first annealing process is performed, causing the metal film to react with silicon atoms in the polysilicon film to form an intermediate silicide layer. Then, unreacted metal films are selectively removed by etching, and the intermediate silicide layer undergoes a second annealing process at a higher temperature than the first annealing process. After annealing, the intermediate silicide layer transforms into metal silicide segments 30, thereby reducing the source-drain resistance.

[0052] Specifically, a contact hole (CT) is formed on the top of the metal silicide layer, and a metal plug 40 is formed within the contact hole. The bottom end of the metal plug 40 faces the metal silicide segment 30, and one metal silicide segment 30 corresponds to two metal plugs 40. Under normal process conditions, the bottom end of the metal plug 40 contacts the metal silicide segment 30. When the process does not meet the process standards, the contact hole may penetrate the metal silicide segment 30, causing the bottom end of the metal plug 40 to contact the barrier layer 20, such as... Figure 8 As shown. Furthermore, if the manufacturing process severely deviates from process standards, contact holes may penetrate the barrier layer 20, causing the bottom end of the metal plug 40 to contact the gate layer 10, as shown. Figure 9 As shown.

[0053] Specifically, the metal layer includes multiple metal segments 50. Along the continuous path direction of the gate layer 10, a metal segment 50 is connected to the top of the corresponding two metal plugs 40 at the near ends of two adjacent metal silicide segments 30. A continuous path can be formed by connecting metal segments 50-metal plugs 40-metal silicide segments 30-metal plugs 40-metal segments 50-...

[0054] In this design, at both ends of the gate layer 10, the metal plugs 40 on the metal silicide segments 30 are connected to metal segments 50, and the corresponding metal segments 50 at both ends of the gate layer 10 are respectively designated as the first test terminal 510 and the second test terminal 520. The first test terminal 510 and the second test terminal 520, together with the multiple metal silicide segments 30, multiple metal plugs 40, and multiple metal segments 50 between the two ends of the gate layer 10, form a test circuit.

[0055] Please see Figure 5 , Figure 6 and Figure 7In one embodiment of this utility model, a wafer acceptance test (WAT) is performed on the first test terminal 510 and the second test terminal 520. If the metal plugs 40 are in contact with the metal silicide segment 30, the test resistance value between the first test terminal 510 and the second test terminal 520 should be within the normal resistance range.

[0056] Please see Figure 5 , Figure 6 , Figure 8 and Figure 9 In one embodiment of this utility model, wafer acceptance testing is performed on the first test terminal 510 and the second test terminal 520, although Figure 8 The middle metal plug 40 contacts the barrier layer 20. Figure 9 The metal plug 40 is in contact with the gate layer 10, but the outer side of the metal plug 40 is still in contact with the metal silicide segment 30. Therefore, the test resistance value between the first test terminal 510 and the second test terminal 520 should be slightly greater than the normal resistance value range.

[0057] Please see Figure 5 , Figure 6 , Figure 8 and Figure 9 In one embodiment of this utility model, due to... Figure 8 , Figure 9 In the test, the resistance values ​​between the first test terminal 510 and the second test terminal 520 are both slightly larger than the normal resistance range. Therefore, a test structure should be designed to determine this. Figure 8 , Figure 9 The defects in the process.

[0058] Specifically, the bottom end of a metal plug 40 is connected to the beginning or end of the gate layer 10, and the top end of the metal plug 40 is connected to a metal segment 50, which is designated as the fifth test terminal 550. The first test terminal 510 and the second test terminal 520 are connected to form the sixth test terminal. The fifth test terminal 550, the sixth test terminal, and the multiple metal silicide segments 30, multiple metal plugs 40, and multiple metal segments 50 between the two ends of the gate layer 10 form a test circuit. Wafer acceptance testing is performed on the fifth test terminal 550 and the sixth test terminal. If current flows, it indicates that the metal plug 40 is in contact with the gate layer 10, which is considered a positive result. Figure 9 The situation is as follows. Wafer acceptance testing is performed on the fifth test terminal 550 and the sixth test terminal. If no current flows, it indicates that the metal plug 40 is separated from the gate layer 10. This is in the case of... Figure 8 The situation in the middle.

[0059] In other embodiments of this utility model (not shown in the figure), if the contact hole does not extend to the metal silicide layer, that is, the bottom end of the metal plug 40 does not contact the metal silicide segment 30 and is in an open circuit condition, then the test resistance value between the first test terminal 510 and the second test terminal 520 should be very large.

[0060] Therefore, after performing wafer acceptance testing on the first test terminal 510 and the second test terminal 520, the positional relationship between the metal plug 40 and the metal silicide segment 30 can be determined based on the test resistance value between the first test terminal 510 and the second test terminal 520.

[0061] Please see Figure 5 and Figure 6 In one embodiment of this utility model, two metal segments 50 connected to a metal silicide segment 30 are respectively designated as the third test terminal 530 and the fourth test terminal 540. The third test terminal 530 and the fourth test terminal 540 form a test circuit with the metal silicide segment 30, which can be used to measure the sheet resistance on the metal silicide segment 30.

[0062] Please see Figure 5 and Figure 6 In one embodiment of this invention, a metal plug 40 is connected to both ends of a metal silicide segment 30. The bottom end of the metal plug 40 faces the metal silicide segment 30 corresponding to the top of the gate layer 10.

[0063] Please see Figure 10 and Figure 11 In one embodiment of the present invention, the semiconductor test structure further includes a plurality of sidewall structures 110, which are disposed on both sides of the gate layer 10. The bottom end of the metal plug 40 faces the metal silicide segment 30 corresponding to the outside of the sidewall structure 110, or the bottom end of the metal plug 40 faces the metal silicide segment 30 corresponding to the top of the sidewall structure 110.

[0064] Specifically, such as Figure 12 and Figure 13 As shown, the bottom end of the metal plug 40 faces the outer side of the sidewall structure 110, corresponding to the metal silicide segment 30. Figure 14 As shown, the bottom end of the metal plug 40 faces the metal silicide segment 30 corresponding to the top of the side wall structure 110.

[0065] Please see Figure 10 and Figure 11In one embodiment of this utility model, on a metal silicide segment 30, the bottom end of one metal plug 40 is near the side of the sidewall structure 110 corresponding to the metal silicide segment 30, and the bottom end of another metal plug 40 is near the other side of the sidewall structure 110 corresponding to the metal silicide segment 30. Furthermore, between two adjacent metal silicide segments 30, the metal segment 50 is located on the same side of the two metal silicide segments 30.

[0066] In another embodiment of this invention (not shown in the figures), on a metal silicide segment 30, the bottom ends of two metal plugs 40 are close to the corresponding metal silicide segment 30 on the same side of the sidewall structure 110. Furthermore, between two adjacent metal silicide segments 30, a metal segment 50 is located on the same side of the two metal silicide segments 30.

[0067] Please see Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 In one embodiment of the present invention, the bottom of the metal plug 40 is provided with a metal silicide segment 30 and a barrier layer 20, and the bottom of the metal plug 40 is not provided with a gate layer 10.

[0068] Therefore, wafer acceptance testing is performed on the first test terminal 510 and the second test terminal 520. When the test resistance value between the first test terminal 510 and the second test terminal 520 is much greater than the normal resistance range, the metal plug 40 is separated from the metal silicide segment 30 (not shown in the figure). When the test resistance value between the first test terminal 510 and the second test terminal 520 is within the normal resistance range, the metal plug 40 is in contact with the metal silicide segment 30, such as... Figure 12 and Figure 13 When the test resistance value between the first test terminal 510 and the second test terminal 520 is slightly greater than the normal resistance range, the metal plug 40 contacts the barrier layer 20, such as... Figure 14 .

[0069] In one embodiment of this utility model, a wafer may be provided, which may include a dicing channel and a semiconductor test structure as described above is provided within the dicing channel.

[0070] In summary, this invention proposes a semiconductor testing structure and wafer. An unexpected technical advantage is that by having the bottom end of a metal plug facing a metal silicide segment, with one metal silicide segment corresponding to two metal plugs, and a metal segment connecting the top of the metal plugs at the near ends of two adjacent metal silicide segments, a continuous structure can be formed between multiple metal segments, multiple metal plugs, and multiple metal silicide segments as follows: (metal segment - metal plug - metal silicide segment - metal plug) - (metal segment - metal plug - metal silicide segment - metal plug) - ... - (metal segment - metal plug - metal silicide segment - metal plug) - metal segment. Therefore, by performing electrical tests on the metal segments at both ends of the gate layer, the contact resistance value between the metal plug and the metal silicide segment can be obtained, thereby determining whether a process defect has occurred. Wafer acceptance testing can be performed during the semiconductor device manufacturing process, thus improving the efficiency of contact resistance monitoring.

[0071] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model. As used herein and throughout the claims below, unless otherwise specified, "a" and "the" include plural references. Similarly, as used herein and throughout the claims below, unless otherwise specified, "in" means "in" and "on".

Claims

1. A semiconductor test structure, characterized by, The semiconductor test structure comprises: a gate layer disposed on a surface of a substrate, the gate layer forming a continuous pattern; a barrier layer disposed on both sides of the gate layer and on top of the gate layer; a metal silicide layer comprising a plurality of metal silicide segments, each of the metal silicide segments being disposed on the barrier layer; a plurality of metal plugs, the bottom end of each of the metal plugs being directed to one of the metal silicide segments, and two of the metal plugs being connected to one of the metal silicide segments; a metal layer comprising a plurality of metal segments, each of the metal segments being connected to the top end of two of the metal plugs, and the metal segments being connected to the top end of the metal plugs at the close end of two adjacent metal silicide segments along the direction of the continuous pattern of the gate layer; wherein the top end of the metal plugs on the metal silicide segments at both ends of the gate layer is connected to the metal segments, and the metal segments at both ends of the gate layer are respectively recorded as a first test end and a second test end; the first test end and the second test end, together with the metal silicide segments, the metal plugs, and the metal segments between the two ends of the gate layer, form a test loop.

2. The semiconductor test structure of claim 1, wherein, two of the metal segments connected to one of the metal silicide segments are respectively recorded as a third test end and a fourth test end, and the third test end and the fourth test end, together with the metal silicide segment, form a test loop.

3. The semiconductor test structure of claim 1, wherein, the metal plugs are connected to both ends of one of the metal silicide segments.

4. The semiconductor test structure of claim 3, wherein, the bottom end of each of the metal plugs is directed to the metal silicide segment corresponding to the top of the gate layer.

5. The semiconductor test structure of claim 4, wherein, the bottom end of one of the metal plugs is connected to the head end or the tail end of the gate layer, the top end of the metal plug is connected to one of the metal segments, and the metal segment is recorded as a fifth test end. the first test end and the second test end are connected to form a sixth test end. the fifth test end and the sixth test end, together with the metal silicide segments, the metal plugs, and the metal segments between the two ends of the gate layer, form a test loop.

6. The semiconductor test structure of claim 3, wherein, The semiconductor test structure further comprises a plurality of side wall structures disposed on both sides of the gate layer. the bottom end of each of the metal plugs is directed to the metal silicide segment corresponding to the outside of the side wall structure, or the bottom end of each of the metal plugs is directed to the metal silicide segment corresponding to the top of the side wall structure.

7. The semiconductor test structure of claim 6, wherein, on one of the metal silicide segments, the bottom end of one of the metal plugs is directed to the metal silicide segment corresponding to one side of the side wall structure, and the bottom end of the other metal plug is directed to the metal silicide segment corresponding to the other side of the side wall structure.

8. The semiconductor test structure of claim 7, wherein, on one of the metal silicide segments, the bottom end of both of the metal plugs is directed to the metal silicide segment corresponding to the same side of the side wall structure.

9. The semiconductor test structure of claim 7 or 8, wherein, between two adjacent metal silicide segments, the metal segment is located on the same side of the two metal silicide segments.

10. A wafer, characterized by, The semiconductor test structure comprises a cutting path, and the cutting path is provided with the semiconductor test structure according to any one of claims 1 to 9.

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