Band-gap reference circuit

Abstract

The utility model provides a band-gap reference circuit which comprises a bias starting circuit, a band-gap reference core circuit and a low-temperature compensation control circuit, and the power supply end of the bias starting circuit is connected with the power supply end of the band-gap reference core circuit and the power supply end of the low-temperature compensation control circuit and then connected into a power supply; the first bias output end of the bias starting circuit is connected to the mirror image input end of the band-gap reference core circuit and the mirror image input end of the low-temperature compensation control circuit, and the second bias output end of the bias starting circuit is connected to the voltage output control end of the band-gap reference core circuit and the temperature compensation end of the low-temperature compensation control circuit. The output end of the low-temperature compensation control circuit outputs reference voltage; the grounding end of the bias starting circuit is connected with the grounding end of the band-gap reference core circuit and the grounding end of the low-temperature compensation control circuit and then is connected to the power ground. By performing temperature compensation on the output voltage of the low-temperature section, power consumption and layout area are saved while the circuit structure is simplified.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a bandgap reference circuit. Background Technology

[0002] In traditional bandgap reference circuits with operational amplifiers, the operational amplifiers suffer from input offset voltage, leading to a decrease in the accuracy of the bandgap reference output voltage. Furthermore, when dealing with high and low temperatures, the commonly used temperature compensation methods for traditional bandgap reference circuits mainly include exponential curvature compensation, subthreshold compensation, and segmented compensation. Segmented compensation includes full-temperature and partial-temperature compensation. While full-temperature segmented temperature compensation can achieve excellent temperature drift performance, its circuit structure is more complex and has higher requirements for power consumption and area. Utility Model Content

[0003] In view of this, the purpose of this application is to provide at least one bandgap reference circuit. The bandgap reference circuit provided by this application mainly performs temperature compensation for the output voltage in the low-temperature range, which simplifies the circuit structure and saves power consumption and layout area.

[0004] This application mainly includes the following aspects:

[0005] In a first aspect, embodiments of this application provide a bandgap reference circuit, which includes a bias startup circuit, a bandgap reference core circuit, and a low-temperature compensation control circuit. The power supply terminal of the bias startup circuit is connected to the power supply terminals of both the bandgap reference core circuit and the low-temperature compensation control circuit, and is then connected to a power supply. A first bias output terminal of the bias startup circuit is connected to the mirror input terminal of both the bandgap reference core circuit and the low-temperature compensation control circuit. A second bias output terminal of the bias startup circuit is connected to the voltage output control terminal of both the bandgap reference core circuit and the temperature compensation terminal of the low-temperature compensation control circuit. The output terminal of the low-temperature compensation control circuit outputs a reference voltage. The ground terminal of the bias startup circuit is connected to the ground terminal of both the bandgap reference core circuit and the low-temperature compensation control circuit, and is then connected to the power supply ground.

[0006] In one possible implementation, the bias startup circuit includes a bias circuit and a startup circuit. The power supply terminal of the bias circuit and the power supply terminal of the startup circuit are connected to a power supply, and the ground terminal of the bias circuit and the ground terminal of the startup circuit are connected to a power ground. The first bias output terminal of the bias circuit is connected to the mirror input terminal of the bandgap reference core circuit and the mirror input terminal of the low temperature compensation control circuit, respectively. The second bias output terminal of the bias circuit is connected to the input terminal of the startup circuit, and the output terminal of the startup circuit is connected to the voltage output control terminal of the bandgap reference core circuit and the temperature compensation terminal of the low temperature compensation control circuit.

[0007] In one possible implementation, the bias circuit includes a first bias current mirror, a second bias current mirror, a first resistor, a second resistor, and a third resistor. The common source of the first bias current mirror is connected to a power supply. The first drain of the first bias current mirror is connected to the first collector of the second bias current mirror via the first resistor. The second drain of the first bias current mirror is connected to the second collector of the second bias current mirror via the second resistor. The first emitter of the second bias current mirror is connected to the power supply ground via the third resistor. The common gate of the first bias current mirror is connected to the mirror input of the bandgap reference core circuit and the mirror input of the low-temperature compensation control circuit, respectively. The first collector of the second bias current mirror is also connected to the input of the startup circuit.

[0008] In one possible implementation, the startup circuit includes a fourth resistor, a first control switch, a second control switch, and a third control switch. One end of the fourth resistor is connected to the power supply, and the other end of the fourth resistor is connected to the drain of the first control switch. The source of the first control switch is connected to the power supply ground, and the first control switch is a diode connection. The drain of the second control switch is connected to the second bias output terminal of the bias circuit. The gate of the second control switch is connected to the other end of the fourth resistor and the gate of the third control switch. The source of the second control switch is connected to the source of the third control switch, the voltage output control terminal of the bandgap reference core circuit, and the temperature compensation terminal of the low-temperature compensation control circuit. The drain of the third control switch is connected to the first connection terminal of the bandgap reference core circuit.

[0009] In one possible implementation, the startup circuit further includes a fourth control switch, wherein the gate of the fourth control switch is connected to a power supply, the drain of the fourth control switch is connected to a second connection terminal of the bandgap reference core circuit, and the source of the fourth control switch is connected to the drain of the second control switch and the second bias output terminal of the bias circuit, respectively.

[0010] In one possible implementation, the bandgap reference core circuit includes a first mirror current source, a common-source cascode current mirror, a reference voltage output current mirror, a fifth resistor, a sixth resistor, and a seventh resistor. The source of the first mirror current source is connected to a power supply; the gate of the first mirror current source is connected to the first bias output terminal of the bias startup circuit and the bias input terminal of the low-temperature compensation control circuit; the drain of the first mirror current source is connected to the common source of the common-source cascode current mirror and the drain of the fourth control switch in the bias startup circuit; and the first common gate of the common-source cascode current mirror is connected to one end of the fifth resistor and the first common gate of the common-source cascode current mirror. The drain of the common-source cascode current mirror is connected to the other end of the fifth resistor, the drain of the third control switch in the bias startup circuit, and the first collector of the reference voltage output current mirror. The second drain of the common-source cascode current mirror is connected to the second collector of the reference voltage output current mirror. The common base of the reference voltage output current mirror is connected to the source of the third control switch in the bias startup circuit and the temperature compensation terminal of the low-temperature compensation control circuit. The first emitter of the reference voltage output current mirror is connected to one end of the seventh resistor and the second emitter of the reference voltage output current mirror through the sixth resistor. The other end of the seventh resistor is connected to the power supply ground.

[0011] In one possible implementation, the bandgap reference circuit further includes a feedback circuit, wherein the power supply terminal of the feedback circuit is connected to the power supply, the ground terminal of the feedback circuit is connected to the power supply ground, the first input terminal of the feedback circuit is connected to the first bias output terminal of the bias start-up circuit, the second input terminal of the feedback circuit is connected to the second collector of the reference voltage output current mirror in the core bandgap reference circuit, and the output terminal of the feedback circuit is connected to the output terminal of the low temperature compensation control circuit to output a reference voltage.

[0012] In one possible implementation, the cryogenic compensation control circuit includes a second mirror current source, an eighth resistor, a ninth resistor, a tenth resistor, and a fifth control switch. The source of the second mirror current source is connected to the power supply, the gate of the second mirror current source is connected to the first bias output terminal of the bias start-up circuit, the drain of the second mirror current source is connected to one end of the eighth resistor and the gate of the fifth control switch, the drain of the fifth control switch is connected to one end of the ninth resistor and the voltage output control terminal of the bandgap reference core circuit, the source of the fifth control switch is connected to the power supply ground through the tenth resistor, and the other end of the ninth resistor is connected to the output terminal of the feedback circuit.

[0013] In one possible implementation, the feedback circuit includes a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a capacitor. The gate of the sixth control switch is connected to the first bias output terminal of the bias startup circuit. The source of the sixth control switch is connected to the source of the seventh control switch and then connected to a power supply. The gate of the seventh control switch is connected to the drain of the seventh control switch and then connected to the source of the eighth control switch. The gate of the eighth control switch is connected to the drain of the sixth control switch and then connected to one end of the capacitor and the drain of the ninth control switch. The drain of the eighth control switch is connected to the output terminal of the low-temperature compensation control circuit via the eleventh resistor and to power ground via the twelfth and thirteenth resistors. The gate of the ninth control switch is connected to the other end of the capacitor and the second collector of the reference voltage output current mirror in the bandgap reference core circuit. The source of the ninth control switch is connected to power ground.

[0014] In one possible implementation, the cryogenic compensation control circuit further includes a tenth control switch, wherein the collector of the tenth control switch is connected to the gate of the fifth control switch, the base of the tenth control switch is connected to the terminal between the twelfth and thirteenth resistors in the feedback circuit, and the emitter of the tenth control switch is connected to the power supply ground.

[0015] This application provides a bandgap reference circuit, which includes a bias startup circuit, a bandgap reference core circuit, and a low-temperature compensation control circuit. The power supply terminal of the bias startup circuit is connected to the power supply terminals of both the bandgap reference core circuit and the low-temperature compensation control circuit, and is then connected to a power supply. The first bias output terminal of the bias startup circuit is connected to the mirror input terminals of both the bandgap reference core circuit and the low-temperature compensation control circuit. The second bias output terminal of the bias startup circuit is connected to the voltage output control terminal of the bandgap reference core circuit and the temperature compensation terminal of the low-temperature compensation control circuit. The output terminal of the low-temperature compensation control circuit outputs a reference voltage. The ground terminal of the bias startup circuit is connected to the ground terminals of both the bandgap reference core circuit and the low-temperature compensation control circuit, and is then connected to the power ground. By performing temperature compensation on the output voltage in the low-temperature range, the circuit structure is simplified while saving power consumption and layout area.

[0016] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This illustration shows one of the structural schematic diagrams of a bandgap reference circuit provided in an embodiment of this application;

[0019] Figure 2 This illustration shows one of the structural schematic diagrams of a bandgap reference circuit provided in an embodiment of this application;

[0020] Figure 3 This illustration shows one of the structural schematic diagrams of a bandgap reference circuit provided in an embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0022] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0023] With the continuous development of technology, power management chips are being used more and more widely, and the requirements for power management chips are constantly increasing, including high-precision analog-to-digital converters and oscillators. High-precision products require high accuracy of their reference voltage, low temperature drift coefficient, and the ability to avoid the influence of factors such as noise and temperature.

[0024] Currently, commonly used temperature compensation methods mainly include exponential curvature compensation, subthreshold compensation, and segmented compensation. Among them, segmented compensation includes full-temperature and partial-temperature compensation. Although full-temperature segmented temperature compensation can achieve good temperature drift performance, its circuit structure is more complex and has higher requirements for power consumption and area. Furthermore, partial-temperature compensation is mainly performed in the high-temperature stage and lacks a compensation mechanism for the low-temperature stage.

[0025] Based on this, the embodiments of this application provide a bandgap reference circuit. The bandgap reference circuit provided by this application mainly performs temperature compensation for the output voltage in the low-temperature range, simplifying the circuit structure while saving power consumption and layout area, as detailed below:

[0026] Please see Figure 1 , Figure 1 This illustration shows one of the structural schematic diagrams of a bandgap reference circuit provided in an embodiment of this application. For example... Figure 1 As shown, the bandgap reference circuit provided in this application embodiment includes a bias start-up circuit 1, a bandgap reference core circuit 2, a low-temperature compensation control circuit 3, and a feedback circuit 4.

[0027] In a preferred embodiment, the power supply terminal of the bias startup circuit 1 is connected to the power supply terminal of the bandgap reference core circuit 2, the power supply terminal of the low temperature compensation control circuit 3, and the power supply terminal of the feedback circuit 4, respectively, and then connected to the power supply VCC. The first bias output terminal of the bias startup circuit 1 is connected to the mirror input terminal of the bandgap reference core circuit 2, the mirror input terminal of the low temperature compensation control circuit 3, and the input terminal of the feedback circuit 4, respectively. The second bias output terminal of the bias startup circuit 1 is connected to the voltage output control terminal of the bandgap reference core circuit 2 and the temperature compensation terminal of the low temperature compensation control circuit 3. The output terminal of the low temperature compensation control circuit 3 is connected to the output terminal of the feedback circuit 4 to output the reference voltage Vref. The ground terminal of the bias startup circuit 1 is connected to the ground terminal of the bandgap reference core circuit 2, the ground terminal of the low temperature compensation control circuit 3, and the ground terminal of the feedback circuit 4, respectively, and then connected to the power ground GND.

[0028] In a preferred embodiment, please refer to Figure 2 , Figure 2 This is a second schematic diagram of a bandgap reference circuit provided in an embodiment of this application. Figure 2 As shown, the bias start-up circuit 1 includes a bias circuit 11 and a start-up circuit 12.

[0029] Preferably, after the power supply terminal of the bias circuit 11 and the power supply terminal of the startup circuit 12 are connected, they are connected to the power supply VCC. After the ground terminal of the bias circuit 11 and the ground terminal of the startup circuit 12 are connected, they are connected to the power ground GND. The first bias output terminal of the bias circuit 11 is connected to the mirror input terminal of the bandgap reference core circuit 2, the mirror input terminal of the low temperature compensation control circuit 3, and the input terminal of the feedback circuit 4, respectively. The second bias output terminal of the bias circuit 11 is connected to the input terminal of the startup circuit 12. The output terminal of the startup circuit 12 is connected to the voltage output control terminal of the bandgap reference core circuit 2 and the temperature compensation terminal of the low temperature compensation control circuit 3.

[0030] In a preferred embodiment, please refer to Figure 3 , Figure 3 This is shown as a third schematic diagram of a bandgap reference circuit provided in an embodiment of this application. Figure 3 As shown, the bias circuit 11 includes a first bias current mirror 110, a second bias current mirror 111, a first resistor R1, a second resistor R2, and a third resistor R3. The common source of the first bias current mirror 110 is connected to the power supply VCC. The first drain of the first bias current mirror 110 is connected to the first collector of the second bias current mirror 111 through the first resistor R1. The second drain of the first bias current mirror 110 is connected to the second collector of the second bias current mirror 111 through the second resistor R2. The first emitter of the second bias current mirror 111 is connected to the second emitter of the second bias current mirror 111 through the third resistor R3 and then connected to the power ground GND. The common gate of the first bias current mirror 110 is connected to the mirror input terminal of the bandgap reference core circuit 2, the mirror input terminal of the low temperature compensation control circuit 3, and the input terminal of the feedback circuit 4. The first collector of the second bias current mirror 111 is also connected to the input terminal of the startup circuit 12.

[0031] In one specific embodiment, such as Figure 3As shown, the first bias current mirror 110 includes a first mirror switch M1 and a second mirror switch M2 connected by a common gate and a common source. The second bias current mirror 111 includes a third mirror switch M3 and a fourth mirror switch M4. The common source of the first mirror switch M1 and the second mirror switch M2 is connected to the power supply VCC. The common gate of the first mirror switch M1 and the second mirror switch M2 is connected to the mirror input terminal of the bandgap reference core circuit 2, the mirror input terminal of the low temperature compensation control circuit 3, and the input terminal of the feedback circuit 4, respectively. The gate of the first mirror switch M1 is connected to the drain of the first mirror switch M1 and then connected to the drain of the third mirror switch M3 through a first resistor R1. The drain of the second mirror switch M2 is connected to the drain of the fourth mirror switch M4 through a second resistor R2. The third mirror switch M3 and the fourth mirror switch M4 share a common base. The base of the fourth mirror switch M4 is connected to the drain of the fourth mirror switch M4. The emitter of the third mirror switch M3 is connected to the emitter of the fourth mirror switch M4 through a third resistor R3 and then connected to the power supply ground GND.

[0032] Specifically, the first mirror switch M1 and the second mirror switch M2 are PMOS transistors, while the third mirror switch M3 and the fourth mirror switch M4 are NPN transistors. In this application, the bias circuit 11 mainly provides bias current to the entire bandgap reference circuit, enabling the bandgap reference circuit to operate normally. The bias current generated by the bias circuit 11 is mainly generated by the third mirror switch M3, the fourth mirror switch M4, and the third resistor R3. The ratio of the number of parallel connections of the third mirror switch M3 and the fourth mirror switch M4 is K:1. Therefore, the bias current I provided by the bias circuit 11... bias Determined by the following formula:

[0033] I bias =V T ×lnK / R3

[0034] In this formula, V T The above bias current expression is based on the premise that the collector currents of the third mirror switch M3 and the fourth mirror switch M4 are equal. Therefore, the number of parallel connections of the first mirror switch M1 and the second mirror switch M2 is the same. Furthermore, the first resistor R1 and the second resistor R2 are added in this application so that the collector currents of the third mirror switch M3 and the fourth mirror switch M4 are almost the same.

[0035] Therefore, the bias current can be adjusted according to actual design requirements, and this bias current is almost independent of the power supply, thus avoiding the impact of power supply fluctuations.

[0036] In a preferred embodiment, such as Figure 3As shown, the startup circuit 12 includes a fourth resistor R4, a first control switch K1, a second control switch K2, a third control switch K3, and a fourth control switch K4. The first control switch K1, the second control switch K2, the third control switch K3, and the fourth control switch K4 are NMOS. The startup circuit 12 is designed to prevent the bandgap reference circuit from failing to operate due to a degeneracy point during startup.

[0037] Preferably, one end of the fourth resistor R4 is connected to the power supply VCC, and the other end of the fourth resistor R4 is connected to the drain of the first control switch K1. The source of the first control switch K1 is connected to the power ground GND. The first control switch K1 is a diode connection. The drain of the second control switch K2 is connected to the second bias output terminal of the bias circuit 11 (i.e., the drain of the third mirror switch M3). The gate of the second control switch K2 is connected to the other end of the fourth resistor R4 and the gate of the third control switch K3. The source of the second control switch K2 is connected to the source of the third control switch K3, the voltage output control terminal of the bandgap reference core circuit 2, and the temperature compensation terminal of the low temperature compensation control circuit 3. The drain of the third control switch K3 is connected to the first connection terminal of the bandgap reference core circuit 2.

[0038] The gate of the fourth control switch K4 is connected to the power supply VCC, the drain of the fourth control switch K4 is connected to the second connection terminal of the bandgap reference core circuit 2, and the source of the fourth control switch is connected to the drain of the second control switch K2 and the second bias output terminal of the bias circuit 11, respectively.

[0039] In one specific embodiment, the startup circuit 12 generates a bias voltage by connecting the fourth resistor R4 in series with the first control switch K1 to the power ground GND, so as to drive the second control switch K2 and the third control switch K3 to work normally through the bias voltage.

[0040] In another preferred embodiment, the bandgap reference core circuit 2 includes a first mirror current source Q1, a common-source cascode current mirror 20, a reference voltage output current mirror 21, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7, wherein the first mirror current source Q1 is a PMOS.

[0041] Preferably, the source of the first mirror current source Q1 is connected to the power supply VCC, the gate of the first mirror current source Q1 is connected to the first bias output terminal of the bias start-up circuit 1 (i.e., the gate of the first mirror switch M1) and the mirror input terminal of the low temperature compensation control circuit 3, the drain of the first mirror current source Q1 is connected to the common source of the common source and common gate current mirror 20 and the drain of the fourth control switch K4, the first common gate of the common source and common gate current mirror 20 is connected to one end of the fifth resistor R5 and the first drain of the common source and common gate current mirror 20, and the second common gate of the common source and common gate current mirror 20 is connected to the fifth resistor R5 and the first drain of the common source and common gate current mirror 20. The other end of resistor R5, the drain of the third control switch K3, and the first collector of the reference voltage output current mirror 21 are connected. The second drain of the common source and common gate current mirror 20 is connected to the second collector of the reference voltage output current mirror 21. The common base of the reference voltage output current mirror 21 is connected to the source of the third control switch K3 and the temperature compensation terminal of the low temperature compensation control circuit 3. The first emitter of the reference voltage output current mirror 21 is connected to one end of the seventh resistor R7 and the second emitter of the reference voltage output current mirror 21 through the sixth resistor R6. The other end of the seventh resistor R7 is connected to the power ground GND.

[0042] In one specific embodiment, the common-source common-gate current mirror 20 includes a fifth mirror switch M5, a sixth mirror switch M6, a seventh mirror switch M7, and an eighth mirror switch M8, and the reference voltage output current mirror 21 includes a ninth mirror switch M9 and a tenth mirror switch M10. The fifth mirror switch M5, the sixth mirror switch M6, the seventh mirror switch M7, and the eighth mirror switch M8 are PMOS transistors, and the ninth mirror switch M9 and the tenth mirror switch M10 are NPN transistors.

[0043] Preferably, the fifth mirror switch M5 and the sixth mirror switch M6 share a common gate and a common source, and the seventh mirror switch M7 and the eighth mirror switch M8 share a common gate. The sources of the fifth mirror switch M5 and the sixth mirror switch M6 are respectively connected to the drain of the first mirror current source Q1 and the drain of the fourth control switch K4. The common gate of the fifth mirror switch M5 and the sixth mirror switch M6 is connected to one end of the fifth resistor R5. The drain of the fifth mirror switch M5 is connected to the source of the seventh mirror switch M7, and the drain of the sixth mirror switch M6 is connected to the source of the eighth mirror switch M8. The gates of the seventh mirror switch M7 and the eighth mirror switch M8 are respectively connected to the other end of the fifth resistor R5, the drain of the third control switch K3 and the collector of the ninth mirror switch M9. The drain of the seventh mirror switch M7 is connected to one end of the fifth resistor R5. The drain of the eighth mirror switch M8 is respectively connected to the collector of the tenth mirror switch M10 and the second input terminal of the feedback circuit 4. The bases of the ninth mirror switch M9 and the tenth mirror switch M10 are respectively connected to the source of the third control switch K3 and the temperature compensation terminal of the low temperature compensation control circuit 3.

[0044] The emitter of the ninth mirror switch M9 is connected to the emitter of the tenth mirror switch M10 through the sixth resistor R6 and then connected to the power ground GND.

[0045] In one specific embodiment, referring to the startup circuit 12 and the bandgap reference core circuit 2, the drain of the second control switch K2 is connected to the collector of the third mirror switch M3, the drain of the third control switch K3 is connected to the collector of the ninth mirror switch M9, and the sources of the second control switch K2 and the third control switch K3 are connected together and connected to the base of the ninth mirror switch M9. This connection method can generate a path from the power supply voltage to the power supply ground GND when the bandgap reference circuit is started, thereby breaking the possible balance point of the bandgap reference circuit and enabling the bandgap reference circuit to start.

[0046] In this application, the sources of the second control switch K2 and the third control switch K3 are connected to the base of the ninth mirror switch M9. When the bandgap reference circuit is fully started, the base voltage of the ninth mirror switch M9 is at a high level, which can turn off the second control switch K2 and the third control switch K3, so that the start-up circuit 12 stops working immediately after the bandgap reference circuit is started.

[0047] Preferably, the fourth control switch K4 is configured to prevent the first mirror current source Q1 from entering the linear region.

[0048] In one specific embodiment, the bandgap reference core circuit 2 is the main circuit for generating the reference voltage. The bandgap reference core circuit 2 outputs a temperature-independent reference voltage, and the first mirror current source Q1 is used for the bias current output by the proportional mirror bias circuit 11.

[0049] M5-M8, together with the fifth resistor R5, form a common-source cascode current mirror 20 with a large output swing, making the collector currents of the ninth mirror switch M9 and the tenth mirror switch M10 almost identical. The voltage across the fifth resistor R5 is approximately an overdrive voltage. The ratio of the number of parallel connections of the ninth mirror switch M9 and the tenth mirror switch M10 is N:1. Therefore, the current I flowing through the sixth resistor R6... PTAT for:

[0050] I PTAT =V T ×lnN / R6

[0051] Current I PTAT Positively correlated with temperature, due to the presence of the current mirror, the current flowing through the seventh resistor R7 is 2 × I. PTAT Then the base voltage of the tenth mirror switch M10 is V. b_M10 =V be_M10 +2×I PTAT ×R7, V be_M10The voltage across the base and emitter of the tenth mirror switch M10 is given. Since the voltage across the base and emitter of the transistor is negatively correlated with temperature, a voltage that is almost independent of temperature can be generated by adjusting the sixth resistor R6, the seventh resistor R7, and the proportional coefficient N.

[0052] In a preferred embodiment, such as Figure 3 As shown, the low-temperature compensation control circuit 3 includes a second mirror current source Q2, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and a fifth control switch K5. The second mirror current source Q2 is a PMOS, and the fifth control switch K5 is an NMOS.

[0053] In this circuit, the source of the second current mirror Q2 is connected to the power supply VCC, the gate of the second current mirror Q2 is connected to the first bias output terminal of the bias start-up circuit 1, the drain of the second current mirror Q2 is connected to one end of the eighth resistor R8 and the gate of the fifth control switch K5, the drain of the fifth control switch K5 is connected to one end of the ninth resistor R9 and the voltage output control terminal of the bandgap reference core circuit 2 (the base of the ninth mirror switch M9), the source of the fifth control switch K5 is connected to the power supply ground through the tenth resistor R10, and the other end of the ninth resistor R9 is connected to the output terminal of the feedback circuit 4.

[0054] In another preferred embodiment, the feedback circuit 4 includes a sixth control switch K6, a seventh control switch K7, an eighth control switch K8, a ninth control switch K9, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a capacitor C1. The sixth control switch K6, the seventh control switch K7, and the eighth control switch K8 are PMOS, and the ninth control switch K9 is an NMOS.

[0055] In this circuit, the gate of the sixth control switch K6 is connected to the first bias output terminal of the bias start-up circuit 1. The source of the sixth control switch K6 is connected to the source of the seventh control switch K7 and then connected to the power supply VCC. The gate of the seventh control switch K7 is connected to the drain of the seventh control switch K7 and then connected to the source of the eighth control switch K8. The gate of the eighth control switch K8 is connected to the drain of the sixth control switch K6 and then connected to one end of the capacitor C1 and the drain of the ninth control switch K9. The drain of the eighth control switch K8 is connected to the output terminal of the low temperature compensation control circuit 3 through the eleventh resistor R11 and then connected to the power ground GND through the twelfth resistor R12 and the thirteenth resistor R13. The gate of the ninth control switch K9 is connected to the other end of the capacitor C1 and the collector of the tenth mirror switch M10. The source of the ninth control switch K9 is connected to the power ground GND.

[0056] Furthermore, the low-temperature compensation control circuit 3 also includes a tenth control switch K10, wherein the collector of the tenth control switch K10 is connected to the gate of the fifth control switch K5, the base of the tenth control switch K10 is connected to the terminal between the twelfth resistor R12 and the thirteenth resistor R13, and the emitter of the tenth control switch K10 is connected to the power ground GND.

[0057] In this application, the low-temperature compensation control circuit mainly performs temperature compensation on the low-temperature output voltage of the bandgap reference core circuit, and the compensation circuit stops working in the high-temperature range.

[0058] In one specific embodiment, for the low-temperature compensation control circuit 3, the second mirror current source Q2 is used to mirror the positive temperature coefficient current generated by the bias circuit 11. Combined with the eighth resistor R8, it generates the gate drive voltage of the fifth control switch K5, causing the fifth control switch K5 to open. The generated positive temperature coefficient current flows through the ninth resistor R9 to generate a positive temperature coefficient voltage. The final output reference voltage Vref is the sum of the base voltage of the tenth mirror switch M10 and the voltage across the ninth resistor R9. In the low-temperature range, the base voltage of the tenth mirror switch M10 is negatively correlated with the temperature, while the voltage across the ninth resistor R9 is positively correlated with the temperature. Therefore, the final output reference voltage Vref is temperature compensated.

[0059] Because the base voltage of the tenth mirror switch M10 is positively correlated with temperature in the high-temperature range, it cannot be compensated. Therefore, the low-temperature compensation control circuit needs to be turned off at higher temperatures. In this application, the low-temperature compensation control circuit is turned off by the tenth control switch K10. The collector of the tenth control switch K10 is connected to the gate of the fifth control switch K5, the emitter of the tenth control switch K10 is connected to the power ground GND, and the base of the tenth control switch K10 is connected between the twelfth resistor R12 and the thirteenth resistor R13. Since the voltage across the thirteenth resistor R13 is obtained by dividing the reference voltage Vref, it does not change much with temperature. However, the voltage across the base and collector of the tenth control switch K10 decreases continuously as the temperature rises. Therefore, the tenth control switch K10 can be turned on at the required temperature by adjusting the ratio of the twelfth resistor R12 and the thirteenth resistor R13, thereby turning off the fifth control switch K5 and causing the low-temperature compensation control circuit to fail.

[0060] In this application, the final expression for the reference voltage Vref is:

[0061]

[0062] In this expression, V D_Q2 V represents the drain voltage of the second current source Q2. GS_K5 T1 represents the gate-source voltage of the fifth control switch, and T represents the temperature at which the low-temperature compensation control circuit is turned off.

[0063] The feedback circuit mainly regulates the output reference voltage, and the feedback mechanism is negative feedback.

[0064] For feedback circuit 4, when the reference voltage Vref is too high, the collector voltage of the tenth mirror switch M10 drops, and the gate voltage of the eighth control switch K8 is increased through the ninth control switch K9, thereby reducing the reference voltage Vref, and the negative feedback mechanism is completed.

[0065] Since there is a negative feedback loop in the bandgap reference circuit, the loop stability problem must be considered. Specifically, in this application, the loop stability is compensated by capacitor C1, thereby making the negative feedback circuit 4 more stable.

[0066] The advantages of this application are:

[0067] 1. By avoiding the introduction of operational amplifiers, the entire bandgap reference circuit is free from the influence of op-amp input offset voltage, thereby improving the accuracy of the output reference voltage.

[0068] 2. Temperature compensation is only applied to the reference voltage in the low-temperature range, while the low-temperature compensation control circuit is turned off in the high-temperature range. This allows for reasonable and effective targeted compensation of the output reference voltage. The aim is to achieve good temperature compensation performance with a relatively simple circuit. Furthermore, a negative feedback circuit is introduced to make the output voltage more stable.

[0069] 3. It avoids the need for highly complex circuits for compensation across the entire temperature range, thereby reducing power consumption and area.

[0070] 4. While saving space and power consumption, the output voltage also has good temperature performance.

[0071] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A bandgap reference circuit, characterized in that, The bandgap reference circuit includes a bias start-up circuit, a bandgap reference core circuit, and a low-temperature compensation control circuit. The bias startup circuit is connected to the power supply of the bandgap reference core circuit and the low temperature compensation control circuit, respectively, and then connected to the power supply. The first bias output terminal of the bias start-up circuit is connected to the mirror input terminal of the bandgap reference core circuit and the mirror input terminal of the low temperature compensation control circuit, respectively. The second bias output terminal of the bias start-up circuit is connected to the voltage output control terminal of the bandgap reference core circuit and the temperature compensation terminal of the low temperature compensation control circuit. The output terminal of the low temperature compensation control circuit outputs the reference voltage. After the grounding terminal of the bias start-up circuit is connected to the grounding terminal of the bandgap reference core circuit and the grounding terminal of the low temperature compensation control circuit, it is connected to the power supply ground.

2. The bandgap reference circuit according to claim 1, characterized in that, The bias start-up circuit includes a bias circuit and a start-up circuit. The bias circuit's power supply terminal and the startup circuit's power supply terminal are connected to the power supply, and the bias circuit's ground terminal and the startup circuit's ground terminal are connected to the power supply ground. The first bias output terminal of the bias circuit is connected to the mirror input terminal of the bandgap reference core circuit and the mirror input terminal of the low temperature compensation control circuit, respectively. The second bias output terminal of the bias circuit is connected to the input terminal of the startup circuit. The output terminal of the startup circuit is connected to the voltage output control terminal of the bandgap reference core circuit and the temperature compensation terminal of the low temperature compensation control circuit.

3. The bandgap reference circuit according to claim 2, characterized in that, The bias circuit includes a first bias current mirror, a second bias current mirror, a first resistor, a second resistor, and a third resistor. In this configuration, the common source of the first bias current mirror is connected to the power supply, the first drain of the first bias current mirror is connected to the first collector of the second bias current mirror through a first resistor, the second drain of the first bias current mirror is connected to the second collector of the second bias current mirror through a second resistor, and the first emitter of the second bias current mirror is connected to the power supply ground through a third resistor. The common gate of the first bias current mirror is connected to the mirror input terminal of the bandgap reference core circuit and the mirror input terminal of the low temperature compensation control circuit, respectively. The first collector of the second bias current mirror is also connected to the input terminal of the startup circuit.

4. The bandgap reference circuit according to claim 2, characterized in that, The startup circuit includes a fourth resistor, a first control switch, a second control switch, and a third control switch. One end of the fourth resistor is connected to the power supply, the other end of the fourth resistor is connected to the drain of the first control switch, the source of the first control switch is connected to the power ground, and the first control switch is a diode connection. The drain of the second control switch is connected to the second bias output terminal of the bias circuit. The gate of the second control switch is connected to the other end of the fourth resistor and the gate of the third control switch. The source of the second control switch is connected to the source of the third control switch, the voltage output control terminal of the bandgap reference core circuit, and the temperature compensation terminal of the low temperature compensation control circuit. The drain of the third control switch is connected to the first connection terminal of the bandgap reference core circuit.

5. The bandgap reference circuit according to claim 4, characterized in that, The start-up circuit also includes a fourth control switch. The gate of the fourth control switch is connected to the power supply, the drain of the fourth control switch is connected to the second connection terminal of the bandgap reference core circuit, and the source of the fourth control switch is connected to the drain of the second control switch and the second bias output terminal of the bias circuit.

6. The bandgap reference circuit according to claim 1, characterized in that, The core circuit of the bandgap reference includes a first mirror current source, a common-source cascode current mirror, a reference voltage output current mirror, a fifth resistor, a sixth resistor, and a seventh resistor. In this configuration, the source of the first mirror current source is connected to the power supply, the gate of the first mirror current source is connected to the first bias output terminal of the bias start-up circuit and the bias input terminal of the low temperature compensation control circuit, the drain of the first mirror current source is connected to the common source of the common source and common gate current mirror and the drain of the fourth control switch in the bias start-up circuit, the first common gate of the common source and common gate current mirror is connected to one end of the fifth resistor and the first drain of the common source and common gate current mirror, the second common gate of the common source and common gate current mirror is connected to the other end of the fifth resistor, the drain of the third control switch in the bias start-up circuit and the first collector of the reference voltage output current mirror, and the second drain of the common source and common gate current mirror is connected to the second collector of the reference voltage output current mirror. The common base of the reference voltage output current mirror is connected to the source of the third control switch in the bias start-up circuit and the temperature compensation terminal of the low temperature compensation control circuit, respectively. The first emitter of the reference voltage output current mirror is connected to one end of the seventh resistor and the second emitter of the reference voltage output current mirror through the sixth resistor, respectively. The other end of the seventh resistor is connected to the power supply ground.

7. The bandgap reference circuit according to any one of claims 1-6, characterized in that, The bandgap reference circuit also includes a feedback circuit. The power supply terminal of the feedback circuit is connected to the power supply, the ground terminal of the feedback circuit is connected to the power supply ground, the first input terminal of the feedback circuit is connected to the first bias output terminal of the bias start-up circuit, the second input terminal of the feedback circuit is connected to the second collector of the reference voltage output current mirror in the bandgap reference core circuit, and the output terminal of the feedback circuit is connected to the output terminal of the low temperature compensation control circuit to output the reference voltage.

8. The bandgap reference circuit according to claim 7, characterized in that, The low-temperature compensation control circuit includes a second mirror current source, an eighth resistor, a ninth resistor, a tenth resistor, and a fifth control switch. The source of the second mirror current source is connected to the power supply, the gate of the second mirror current source is connected to the first bias output terminal of the bias start-up circuit, the drain of the second mirror current source is connected to one end of the eighth resistor and the gate of the fifth control switch, the drain of the fifth control switch is connected to one end of the ninth resistor and the voltage output control terminal of the bandgap reference core circuit, the source of the fifth control switch is connected to the power supply ground through the tenth resistor, and the other end of the ninth resistor is connected to the output terminal of the feedback circuit.

9. The bandgap reference circuit according to claim 7, characterized in that, The feedback circuit includes a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a capacitor. The gate of the sixth control switch is connected to the first bias output terminal of the bias start-up circuit. The source of the sixth control switch is connected to the source of the seventh control switch and then connected to the power supply. The gate of the seventh control switch is connected to the drain of the seventh control switch and then connected to the source of the eighth control switch. The gate of the eighth control switch is connected to the drain of the sixth control switch and then connected to one end of the capacitor and the drain of the ninth control switch respectively. The drain of the eighth control switch is connected to the output terminal of the low temperature compensation control circuit through the eleventh resistor and then connected to the power supply ground through the twelfth and thirteenth resistors in sequence. The gate of the ninth control switch is connected to the other end of the capacitor and the second collector of the reference voltage output current mirror in the bandgap reference core circuit, and the source of the ninth control switch is connected to the power supply ground.

10. The bandgap reference circuit according to claim 8, characterized in that, The low-temperature compensation control circuit also includes a tenth control switch. The collector of the tenth control switch is connected to the gate of the fifth control switch, the base of the tenth control switch is connected to the terminal between the twelfth and thirteenth resistors in the feedback circuit, and the emitter of the tenth control switch is connected to the power supply ground.

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