Memory device

Abstract

The memory device includes a first read data line coupled to the first memory segment; a second read data line coupled to the second memory segment and including a first portion passing through the first memory segment and a second portion passing through the second memory segment; and the first strip-shaped unit is inserted between the first memory body section and the second memory body section. A first portion of the second read data line terminates at the first strip unit and is coupled to a second portion of the second read data line.

Description

TECHNICAL FIELD

[0001] One embodiment of the present disclosure relates to a memory device, in particular, a memory device including read data lines of different configurations. BACKGROUND

[0002] In addition to cycle time, access time is another key performance indicator for high-performance computing (HPC) applications. SRAM is widely used in system-on-chip (SoC) designs, which utilize keepers to mitigate the effect of interference. However, increasing the number of bitcells per bitline (BL) requires stronger keepers, which in turn negatively impacts the discharge speed of the BL. SUMMARY

[0003] One embodiment of the present disclosure provides a memory device. The memory device includes a first read data line coupled to a first memory segment; a second read data line coupled to a second memory segment and including a first portion passing through the first memory segment and a second portion passing through the second memory segment; and a first strip cell interposed between the first memory segment and the second memory segment. The first portion of the second read data line terminates at the first strip cell and is coupled to the second portion of the second read data line.

[0004] One embodiment of the present disclosure provides a memory device including a first memory segment coupled to a first read data line; and a second memory segment separated from the first memory segment by a first strip cell and coupled to a second read data line passing through the first strip cell. The second read data line includes a first portion having a first width and a second portion having a second width smaller than the first width.

[0005] One embodiment of the present disclosure provides a memory device. The memory device includes a first read data line coupled to a first memory segment; a second read data line coupled to a second memory segment and including a first portion passing through the first memory segment and a second portion passing through the second memory segment; a first strip cell interposed between the first memory segment and the second memory segment, the first portion of the second read data line terminating at the first strip cell and being coupled to the second portion of the second read data line; a third read data line coupled to a third memory segment; and a fourth read data line coupled to a fourth memory segment, wherein a second strip cell is interposed between the third memory segment and the fourth memory segment. BRIEF DESCRIPTION OF DRAWINGS

[0006] The aspects of the disclosure disclosed in the specification and drawings Figure OneThe present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with industry standard practice, the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a memory device including memory cells corresponding to

[0008] Figure 2 is a schematic diagram of a memory device including memory cells corresponding to Figure 1

[0009] Figure 3A is a layout diagram of a portion of the memory device in Figure 2

[0010] Figure 3B is a cross-sectional view of a portion of the memory device along a centerline AA' in Figure 3A

[0011] Figure 4A is a layout diagram of a portion of the memory device in Figure 2

[0012] Figure 4B is a cross-sectional view of a portion of the memory device along a centerline BB' in Figure 4A

[0013] Figure 4C is a cross-sectional view of a portion of the memory device along a centerline CC' in Figure 4A

[0014] Figure 5 is a schematic circuit diagram of a read circuit according to various embodiments of the present disclosure;

[0015] Figure 6 is a schematic waveform diagram of signals in a memory device according to various embodiments of the present disclosure;

[0016] Figure 7 is a schematic diagram of a memory device according to various embodiments of the present disclosure;

[0017] Figure 8 is a schematic diagram of a memory device according to various embodiments of the present disclosure;

[0018] Figure 9 is a schematic diagram of a memory device according to various embodiments of the present disclosure;

[0019] Figure 10A ​​​​​​is a layout view of a portion of the memory device in Figure 9

[0020] Figure 10B is a cross-sectional view of a portion of the memory device along Figure 10A

[0021] Figure 11A is a layout view of a portion of the memory device in Figure 9

[0022] Figure 11B is a cross-sectional view of a portion of the memory device along Figure 11A

[0023] Figure 12 is a schematic circuit diagram of a read circuit and a signal generation circuit according to some embodiments of the present disclosure.

[0024] Figure 13 is a schematic waveform diagram of signals in the memory device according to some embodiments of the present disclosure.

[0025] Figure 14 is a schematic diagram of a memory device according to some embodiments of the present disclosure.

[0026] Figure 15 is a flowchart of a method for operating a memory device to perform a read operation according to some embodiments of the present disclosure.

[0027]

Symbol Explanation

[0028] 10: memory device

[0029] 10A-10B: layout view

[0030] 70: memory device

[0031] 80: memory device

[0032] 90: memory device

[0033] 90A-90B: layout view

[0034] 110: memory bank

[0035] 111: memory segment

[0036] 112: memory segment

[0037] 113: strip unit

[0038] 113a: connection layer ​​​​

[0039] 120: memory bank

[0040] 121: memory segment

[0041] 122: memory segment

[0042] 123: strip cell

[0043] 130: input and output circuit

[0044] 131-133: logic gate

[0045] 134: keeper circuit

[0046] 135: latch circuit

[0047] 136-137: inverter

[0048] 138-139: logic gate

[0049] 141: inverter

[0050] 142-146: signal generating circuit

[0051] 1411, 1421, 1431, 1441, 1451, 1461: inverter

[0052] 501: selection circuit

[0053] 502: selection circuit

[0054] 911: memory segment

[0055] 912: strip cell

[0056] 912a-912c: connection layer

[0057] 1200: memory device

[0058] 1301-1302: read circuit

[0059] 1411: inverter

[0060] 1421: inverter

[0061] 1431: inverter

[0062] 1441: inverter

[0063] 1451: inverter

[0064] 1461: inverter

[0065] 1500: method

[0066] S1501-S1504: operation

[0067] 1511: write data circuit

[0068] LDB_UP: signal

[0069] LDB_DN: signal

[0070] MC: memory cell

[0071] N1, N2, N3, N4: transistor

[0072] P1, P2: transistor

[0073] PG, PD: transistor

[0074] RBL: read data line

[0075] RBL_DN_F0: read data line

[0076] RBL_DN_N0 ~ RBL_DN_N1: read data line

[0077] RBL_DN_SEG2: read data line

[0078] RBL_UP_F0 ~ RBL_UP_F1: read data line

[0079] RBL_UP_N0 ~ RBL_UP_N2: read data line

[0080] RBL_UP_SEG2 ~ RBL_UP_SEG3: read data line

[0081] RBLEQB_UP: signal

[0082] RBLEQB_UP_F: signal

[0083] RBLEQB_UP_F0: signal

[0084] RBLEQ_UP: signal

[0085] RBLEQ_UP_F: signal

[0086] RBLEQ_UP_F0: signal

[0087] RBLEQB_DN: signal

[0088] RBLEQB_DN_F: signal

[0089] RBLEQB_DN_F0: signal

[0090] RBLEQ_DN: signal

[0091] RBLEQ_DN_F: signal

[0092] RBLEQ_DN_F0: signal

[0093] RPC: read port circuit

[0094] RWL: read word line

[0095] S1501-S1504: operation

[0096] T1-T31: transistor

[0097] V0_1-V0_2: via

[0098] V1_1-V1_2: via

[0099] V2_1: via

[0100] V3_1: via

[0101] VSS: supply voltage

[0102] VDD: supply voltage

[0103] W1, W2: width

[0104] WPC: write port circuit

[0105] WWL: write word line

[0106] WBL: write data line

[0107] WBLB: write data line

[0108] WBL_UP_F0: write data line

[0109] WBL_UP_N0-WBL_UP_N1: write data line

[0110] WBL_DN_F0: write data line

[0111] WBL_DN_N0-WBL_DN_N1: write data line

[0112] XT: storage node

[0113] XB: storage node

[0114] QB: output

[0115] RCKC, RCKT: clock signal DETAILED DESCRIPTION

[0116] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are in no way limiting of the scope of the present disclosure. For example, in the following description, the formation of a first feature over or on a second feature can include embodiments in which the first feature is formed directly on the second feature, as well as embodiments in which additional features can be formed between the first and second features such that the first and second features are not in direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0117] The terminology used in this specification generally has its ordinary meaning in the art and specific contexts in which the various terms are used. Examples of terminology used in this specification, including examples of any terminology discussed herein, are merely illustrative and in no way limit the scope and meaning of the present disclosure or any exemplified terminology. Likewise, the present disclosure is not limited to the various embodiments set forth in this specification.

[0118] Although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the examples. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0119] As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains," "containing," "involves," and the like can be used interchangeably with the term "consisting of" or "consists of."

[0120] As used herein, "about," "approximately," "near," or "substantially" shall generally mean any approximation of a given value or range, within which, depending on the various fields, the scope shall be construed in accordance with the broadest interpretation understood by those skilled in the art, so as to encompass all such modifications and similar structures. In some embodiments, it shall generally mean within 20% of a given value or range, more preferably within 10%, and even more preferably within 5%. Numerical values given herein are approximate, which means that unless expressly stated otherwise, the term "about," "approximately," "near," or "substantially" can be inferred as meaning or the other approximate value is meant.

[0121] Reference is now made to Figure 1 . Figure 1 is a schematic diagram of a memory cell MC in accordance with various embodiments of the present disclosure. In some embodiments, the memory cell MC is referred to as a dual-port cell. As shown, the memory cell MC includes a first memory element 10 and a second memory element 20.Figure 1 As shown, the memory cell MC includes a write port circuit WPC and a read port circuit RPC. The write port circuit WPC is coupled to complementary pair of write data lines WBL and WBLB. In some embodiments, the write data lines WBL and WBLB carry signals having bits of data, referred to as write bit lines. The read port circuit RPC is coupled to a read data line RBL, referred to as a read bit line. In some embodiments, the memory cell MC is implemented as an 8T static random access memory (SRAM).

[0122] The write port circuit WPC includes p-type transistors P1-P4 and n-type transistors N1-N4. The write port circuit WPC includes a first inverter formed by transistors P1 and N1 and a second inverter formed by transistors P2 and N2. The first and second inverters are cross-coupled as a data storage.

[0123] For illustration, the drains of transistors P1 and N1 are electrically connected together, forming a storage node XT. The gates of transistors P1 and N1 are electrically connected together. The source of transistor P1 is electrically connected to a supply voltage (i.e., a power line) VDD. The source of transistor N1 is electrically connected to a complementary supply line VSS (i.e., a supply voltage, or ground).

[0124] The drains of transistors P2 and N2 are electrically connected together, forming a storage node XB (also referred to as a complementary storage node XB). The gates of transistors P2 and N2 are electrically connected together. The source of transistor P2 is electrically connected to the supply voltage VDD. The source of transistor N2 is electrically connected to the supply voltage VSS.

[0125] Further, the storage node XT is electrically connected to the gates of transistors P2 and N2, and the storage node XB is electrically connected to the gates of transistors P1 and N1. Thus, as shown, Figure 1 The first and second inverters are cross-coupled.

[0126] In some embodiments, the write port circuit WPC further includes a pass gate device formed by n-type transistor N3 and another pass gate device formed by n-type transistor N4. The source of transistor N1 is electrically connected to the storage node XT, and the source of transistor N4 is electrically connected to the storage node XB, thereby forming a write port for data access. Further, the drain of transistor N3 is electrically connected to the write bit line WBL, and the gate of transistor N3 is electrically connected to a write word line WWL. Similarly, the drain of transistor N4 is electrically connected to the write bit line WBLB, and the gate of transistor N4 is electrically connected to the write word line WWL.

[0127] To illustrate, the read port circuit RPC of the dual-port unit MC includes n-type transistors PD and PG. Transistor PD is also called the read pull-down transistor (RPD), and transistor PG is also called the read channel gate transistor (RPG). Transistors PD and PG are connected in series between the supply voltage VSS and the read bit line RBL. Figure 1 In this example, the source of transistor PD is coupled to the supply voltage VSS, and its drain is coupled to the drain of transistor PG. The gate of transistor PD is coupled to the storage node XB. The source of transistor PG is coupled to the read bit line RBL, and the gate of transistor PG is controlled by the read word line RWL.

[0128] In some embodiments, during a write operation, the voltage on the write word line WWL rises above a predetermined level to turn on transistors N3 and N4. During a write operation, the voltage on the read word line RWL falls below the predetermined level, and transistor PG turns off. In some instances, the write word line WBL is pulled high and the complementary write word line WBLB is pulled low, or vice versa, to write a logic "1" or "0" to the memory cell MC.

[0129] In some embodiments, during a read operation, the voltage on the read word line RWL rises to a predetermined level to turn on transistor PG. During the read operation, if the current on the write word line WWL falls below a predetermined level, transistors N3-N4 are turned off. Then, the sensed current on the read word line RBL is detected by a sense amplifier to determine the logic state of the memory cell MC.

[0130] Figure 1 The configurations shown are for illustrative purposes. Various implementations are within the scope of this disclosure. For example, in some embodiments, the memory cell MC includes additional means, such as additional pull-down means and channel gate means. In various embodiments, each of the first and second inverters includes one or more pull-down means configured in parallel.

[0131] Now for reference Figure 2 . Figure 2 Other embodiments according to this disclosure include those corresponding to Figure 1 A schematic diagram of the memory device 10 of the memory unit MC.

[0132] like Figure 2 As shown, the memory device 10 includes two libraries 110 and 120 and an input and output (I / O) circuit 130. The I / O circuit 130 is inserted between libraries 110 and 120. (Regarding...) Figure 1 The embodiments are provided for ease of understanding. Figure 2Like elements in FIGS. 1-3 are denoted by the same reference numerals. For the sake of simplicity, the specific operations of like elements already discussed in the above paragraphs are omitted herein.

[0133] Input and output circuits 130 are key components in memory device 10, serving as the path for data to flow in and out. They allow memory cells to receive data from external systems (input circuits) and send stored data back (output circuits).

[0134] Memory bank 110 includes multiple memory segments, for example, 111 and 112, and a strip cell 113 inserted between memory segments 111 and 112. In some embodiments, each of memory segments 111 and 112 includes several memory cells MC arranged at the intersection of a column (along the y direction) and a row (along the x direction). Similarly, memory bank 120 includes multiple memory segments, for example, 121 and 122, and a strip cell 123 inserted between memory segments 121 and 122. The configuration of memory segments 121 and 122 is similar to that of memory segments 111 and 112. Thus, repeated description is omitted here. For the sake of simplicity, only memory cells MC in row ROW1 and in a column are shown for explanation.

[0135] In some embodiments, strip cells 113 and 123 include dummy cells. For example, the configuration of dummy cells is similar to that of memory cells MC, and they are not functionally activated during the operation of memory device 10. In some embodiments, the width of strip cells 113 and 123 along the x direction is about twice the width of memory cells MC.

[0136] In some embodiments, memory cells MC in the same column are coupled to the same pair of write word lines WWL and read word lines RWL.

[0137] Memory cells MC in the same row and in the same memory bank are coupled to the same pair of complementary write data lines WBL and WBLB. For example, memory cells MC in bank 110 are coupled to write data lines WBL and WBLB.

[0138] In some embodiments, write data line WBL is split into two parts, where the first part is coupled to memory cells MC in memory bank 110, and the second part is coupled to memory cells MC in memory bank 120. Similarly, write data line WBLB is split into two parts, where the first part is coupled to memory cells MC in memory bank 110, and the second part is coupled to memory cells MC in memory bank 120.

[0139] For illustration, pairs of write data lines WBL and WBLB extend along the X direction to pass through and couple to both of the memory segments in the memory bank. For example, write data lines WBL and WBLB couple to memory segments 111 and 112 in memory bank 110.

[0140] In some embodiments, input and output circuit 130 includes a selection circuit (not shown) to select one of the first portions of write data lines WBL and WBLB and one of the second portions of write data lines WBL and WBLB according to address information of the accessed memory cell MC to which data is to be written. For example, during an operation of writing data to a memory cell MC in memory bank 110, the selection circuit charges / discharges the first portions of write data lines WBL and WBLB coupled to memory bank 110 according to the data, while keeping the voltages of the second portions of write data lines WBL and WBLB coupled to memory bank 120.

[0141] In some embodiments, memory device 10 couples input and output circuit 130 to the memory segments closest to the configuration of input and output circuit 130 with a single conductive line of read data lines; on the other hand, memory device 10 couples input and output circuit 130 to the memory segments further away from input and output circuit 130 than the closest memory segments with a read data line having multiple divided portions.

[0142] For example, continuing to refer to Figure 2 , memory device 10 includes read data line RBL UP N0 coupled to memory segment 111 and read data line RBL UP SEG2 coupled to memory segment 112 and passing through strap cell 113.

[0143] Specifically, read data line RBL UP SEG2 includes two portions: read data line RBL UP N1 and read data line RBL UP F0. In some embodiments, read data line RBL UP F0 passes through memory segment 111 and read data line RBL UP N1 passes through memory segment 112. As Figure 2 shown, read data line RBL UP F0 is coupled to read data line RBL UP N1 at strap cell 113. Read data line RBL UP F0 also terminates at strap cell 113.

[0144] Similarly, memory device 10 also includes a read data line RBL_DN_N0 coupled to memory segment 121 and a read data line RBL_DN_SEG2 coupled to memory segment 122. Specifically, read data line RBL_DN_SEG2 includes two parts: read data line RBL_DN_N1 and read data line RBL_DN_F0. In some embodiments, read data line RBL_DN_F0 passes through memory segment 121, while read data line RBL_DN_N1 passes through memory segment 122. Figure 2 As shown, the read data line RBL_DN_F0 is coupled to the read data line RBL_DN_N1 at strip cell 123. The read data line RBL_DN_F0 also terminates at strip cell 123.

[0145] In some embodiments, read data lines RBL_UP_N0, RBL_UP_N1, RBL_DN_N0, and RBL_DN_N1 are conductive lines fabricated in a first metal layer (e.g., a "metal zero" layer, M0), and read data lines RBL_UP_F0 and RBL_DN_F0 are conductive lines fabricated in a second metal layer (e.g., a "metal two" layer, M2) different from the first metal layer. In some embodiments, the second metal layer is a layer higher than the first metal layer. In some embodiments, the conductive lines in the first metal layer have a smaller thickness and / or width along the y-direction than the conductive lines in the second metal layer. Alternatively, for read data lines RBL_UP_N0, RBL_UP_N1, RBL_DN_N0, and RBL_DN_N1 with the same length (along the x-direction) as read data lines RBL_UP_F0 and RBL_DN_F0, one of the read data lines RBL_UP_F0 and RBL_DN_F0 has a smaller resistance, which reduces data transmission load.

[0146] In some embodiments, the input and output circuitry 130 includes a read circuit (e.g., 1301) for reading data stored in a memory cell MC. In some embodiments, memory cells MC in the same row are coupled to a corresponding one of the read circuits. For example, in Figure 2 In the embodiment, the memory cells MC in the memory bank 110 of row ROW1 are coupled to the read circuit 1301 via read data lines RBL_UP_N0, RBL_UP_N1, and RBL_UP_F0. Similarly, the memory cells MC in the memory bank 120 of row ROW1 are coupled to the read circuit 1301 via read data lines RBL_DN_N0, RBL_DN_N1, and RBL_DN_F0. (Refer to...) Figure 5 and Figure 6 This paper discusses the specific operational configuration of the memory device 10 during the read operation.

[0147] Reference is now made to Figure 3A . Figure 3A is a layout of a portion of the memory device 10 according to other embodiments of the present disclosure Figure 2 . Figure 10A .

[0148] In some embodiments of the memory device 10, the read data lines RBL_UP_N0, RBL_UP_N1, and RBL_UP_F0 extend in the x-direction. The read data line RBL_UP_F0 is separated from the read data lines RBL_UP_N0 and RBL_UP_N1 in the y-direction. Figure 3A

[0149] The width W1 of the read data line RBL_UP_F0 is different from the width W2 of the read data lines RBL_UP_N0 and RBL_UP_N1. In some embodiments, the width W2 is smaller than the width W1.

[0150] The memory device 10 further includes a connection layer 113a formed in the strap cell 113 to couple the read data line RBL_UP_F0 to the read data line RBL_UP_N1. In some embodiments, the connection layer 113a is in a third metal layer (e.g., “metal one”, M1) inserted between a first metal layer (e.g., M0) and a second metal layer (e.g., M2). As shown in Figure 3A the connection layer 113a extends in the y-direction and overlaps the read data line RBL_UP_F0 and the read data line RBL_UP_N1.

[0151] Reference is now made to Figure 3A and Figure 3B wherein Figure 3A is a layout of a portion of the memory device 10 according to other embodiments of the present disclosure Figure 3A along the center line AA’.

[0152] The read data line RBL_UP_N1 is coupled to the read data line RBL_UP_F0 via a via V0_1 inserted between the read data line RBL_UP_N1 and the connection layer 113a, the connection layer 113a, and a via V1_1 inserted between the connection layer 113a and the read data line RBL_UP_F0.

[0153] According to Figure 4A is a layout of a portion of the memory device 10 according to different embodiments of the layout of Figure 2 . Figure 10B The read data line RBL_UP_N0 overlaps the read data line RBL_UP_F0 in the layout.

[0154] Figure 4B ​is a cross-sectional view along the center line BB' of the portion of the memory device 10 according to other embodiments of the present disclosure. Figure 4A The via V1_1 is directly above the via V0_1.

[0155] Figure 4C is a cross-sectional view along the center line CC' of the portion of the memory device 10 according to other embodiments of the present disclosure. Figure 4A The read data line RBL_UP_F0 is configured above the read data lines RBL_UP_N0 and RBL_UP_N1. The read data line RBL_UP_N0 is separated from the read data line RBL_UP_N1 along the x-direction.

[0156] The configuration of the read data line RBL_DN_F0 and the read data lines RBL_DN_N0 and RBL_DN_N1 is similar to that of the read data line RBL_UP_F0 and the read data lines RBL_UP_N0 and RBL_UP_N1 shown via Figures 3A to 4B . Thus, the repeated description is omitted here.

[0157] Figures 1 to 4C The configuration of the read data line RBL_DN_F0 and the read data lines RBL_DN_N0 and RBL_DN_N1 is similar to that of the read data line RBL_UP_F0 and the read data lines RBL_UP_N0 and RBL_UP_N1 shown via

[0158] Reference is now made to Figure 5 . Figure 5 is a schematic circuit diagram of the read circuit 1301 according to other embodiments of the present disclosure.

[0159] The read circuit 1301 includes a selection circuit 501 coupled to the read data lines RBL_UP_N0, RBL_UP_F0, RBL_DN_N0, and RBL_DN_F0. As shown via Figure 5 , a first portion of the selection circuit 501 is coupled to the read data line RBL_UP_N0 and the read data line RBL_UP_F0, and a second portion of the selection circuit 501 is coupled to the read data line RBL_DN_N0 and the read data line RBL_DN_F0.

[0160] The first portion of the selection circuit 501 includes transistors T1-T4 coupled in series between voltage terminals that provide a voltage V1. In some embodiments, the voltage V1 is a typical supply voltage VDD in the memory device 10. The transistors T1 and T3 are operated in response to a signal RBLEQB_UP. The transistors T2 and T4 are operated in response to a signal RBLEQB_UP_F.

[0161] The selection circuit 501 also includes a logic gate (e.g., NAND gate) 131, a keeper circuit 132, and a transistor T5. The keeper circuit 132 and the transistor T5 are coupled in series between the voltage terminal VI and an input of the logic gate 131. A gate terminal of the transistor T5 is coupled to an output of the logic gate 131.

[0162] A read data line RBL UP N0 is coupled to the input of the logic gate 131 and a node between the transistors T1 and T2. A read data line RBL UP F0 is coupled to the input of the logic gate 131 and a node between the transistors T3 and T4.

[0163] Similarly, a second portion of the selection circuit 501 includes transistors T6-T9 coupled in series between voltage terminals providing voltages VI and V2. The transistors T6 and T9 are operated in response to a signal RBLEQB DN. The transistors T7 and T8 are operated in response to a signal RBLEQB DN F.

[0164] The selection circuit 501 also includes a logic gate (e.g., NAND gate) 133, a keeper circuit 134, and a transistor T10. The keeper circuit 134 and the transistor T10 are coupled in series between the voltage terminal VI and an input of the logic gate 133. A gate terminal of the transistor T10 is coupled to an output of the logic gate 133.

[0165] A read data line RBL DN N0 is coupled to the input of the logic gate 133 and a node between the transistors T8 and T9. A read data line RBL DN F0 is coupled to the input of the logic gate 133 and a node between the transistors T6 and T7.

[0166] The read circuit 1301 further includes a latch circuit 135 coupled to the outputs of the logic gates 131 and 133. As shown, the latch circuit 135 includes transistors T11-T19 and inverters 136-137. The transistors T12-T15 are configured as a NOR gate. The transistor T11 is coupled in series with the NOR gate and is operated in response to a clock signal RCKC. The NOR gate is operated in response to the outputs of the logic gates 131 and 133. Specifically, the gates of the transistors T12 and T14 receive a signal LFB UP indicative of the read data RD UP output from the logic gate 131. The gates of the transistors T13 and T15 receive a signal LFB DN indicative of the read data output from the logic gate 133. The inverter 137 is used to generate an output read data Q in response to an output QB from the NOR gate, where the logic state of the output read data Q is opposite to the output QB. Figure 5

[0167] ​The latch circuit 135 further includes P-type transistors T16 and T17 coupled to N-type transistors T18 and T19 coupled in series at the output of the NOR gate. The P-type transistor T16 is operated in response to a clock signal RCKT different from the clock signal RCKC. The N-type transistor T19 is operated in response to the clock signal RCKC. An inverter 136 in the latch circuit 135 is coupled between the output terminal of the NOR gate and the gates of the P-type transistor T17 and the N-type transistor T19. The other terminals of the transistors T14, T15, and T19 are coupled to a typical supply voltage VSS in the memory device, which is less than the supply voltage VDD, for example, ground potential.

[0168] Reference is now made to Figure 5 and Figure 6 . Figure 6 is a schematic waveform diagram of signals in a memory device according to other embodiments of the disclosure.

[0169] In operation, according to some embodiments, the selection circuit 501 is to generate read data RD UP in response to the voltages of the read data lines RBL UP F0 and RBL UP N0, and to generate read data RD DN in response to the voltages of the read data lines RBL DN F0 and RBL DN N0. The latch circuit 135 is to generate output read data Q corresponding to data stored in the memory cell MC coupled to the selected one of RBL UP F0, RBL DN F0, RBL UP N0, and RBL DN N0 in response to the read data RD UP and RD DN.

[0170] For example, with reference to Figure 5 and Figure 6 , prior to performing a read operation on the memory cell MC in the memory segment 112 selected for access, the read data line RBL UP F0 is pre-charged to have a level corresponding to a logical high state in response to at least RBLE QB UP F having a voltage level corresponding to a logical low state.

[0171] When the read operation starts, the read word line RWL coupled to the selected memory cell MC (in the memory segment 112) goes high to turn on the pass gate transistor PG. In embodiments where the storage node XB stores data corresponding to “1” (e.g., a high logic state), the transistor PD turns on to couple the voltage VSS (e.g., a low logic state) to the read data line RBL UP N1 and the read data line RBL UP F0. Thus, as shown in Figure 6 , the voltage level of the read data line RBL UP F0 is pulled down, and the logic gate 131 correspondingly generates the signal LFB UP having a high logic state.

[0172] The latch circuit 135 latches the signal LFB UP in the read data RD UP in response to the clock signal RCKC falling and the clock signal RCKT rising, sequentially. Specifically, the output QB goes low, and the inverter 137 inverts the output QB to generate the output read data Q having a high logic state, which corresponds to the storage node XB of the selected memory cell MC.

[0173] Further, after the read operation is completed, the read word line RWL is deactivated. The clock signal RCKC rises to turn off the transistor T11 and turn on the transistor T19. The clock signal RCKT falls to turn on the transistor T16. The transistors T1-T4 are turned on to pre-charge the read data line, and further pull down the signal LFB UP. Alternatively, when the read data line RBL UP F0 is charged to a high logic state, the read circuit 1301 outputs the read data RD UP having a low logic state to turn off the latch circuit.

[0174] The configuration of the read operation of the memory cell MC coupled to the other read data line is similar to that coupled to the read data line RBL UP F0. Therefore, the repeated description is omitted here.

[0175] Reference is now made to Figure 7 .FIG. 1 is a schematic diagram of a memory device 10 according to embodiments of the present disclosure. With respect to the embodiments of the memory device 10, for ease of understanding, Figure 7 similar elements in FIG. 1 are denoted by the same reference numerals. In some embodiments, the memory device 10 is configured with respect to, for example, the memory device 10. Figures 1 to 6 Figure 7 In the embodiments of the memory device 10, the memory segment 111 and the memory segment 112 include the same number of memory cells MC in a row. The number of memory cells MC coupled to the read data line RBL UP SEG2 composed of the read data line RBL UP F0 and the read data line RBL UP N1 is consistent with the number of memory cells MC coupled to the read data line NRL UP N0.

[0176] Reference is now made to Figure 7 . FIG. 2 is a schematic diagram of a memory device 20 according to embodiments of the present disclosure. With respect to the embodiments of the memory device 20, for ease of understanding, similar elements in FIG. 2 are denoted by the same reference numerals. In some embodiments, the memory device 20 is configured with respect to, for example, the memory device 10.

[0177] Figure 8 Reference is now made to Figure 8 . FIG. 3 is a schematic diagram of a memory device 30 according to embodiments of the present disclosure. With respect to the embodiments of the memory device 30, for ease of understanding, Figures 1 to 7 similar elements in FIG. 3 are denoted by the same reference numerals. In some embodiments, the memory device 30 is configured with respect to, for example, the memory device 20. Figure 8 and

[0178] similar elements in FIG. 3 are denoted by the same reference numerals. In some embodiments, the memory device 30 is configured with respect to, for example, the memory device 20. Figure 7In contrast, memory segment 111 includes more memory cells MC in a row than memory segment 112. Thus, the number of memory cells MC coupled to read data line RBL UP SEG2, which is composed of read data line RBL UP F0 and read data line RBL UP N1, is different than the number of memory cells MC coupled to read data line RBL UP N0. In some embodiments, read data line RBL UP SEG2 is coupled to fewer memory cells MC than read data line RBL UP N0.

[0179] Reference is now made to Figure 9 . Figure 9 is a schematic diagram of a memory device 90 in accordance with other embodiments of the present disclosure. With respect to embodiments of Figures 1 to 8 , for ease of understanding, Figure 9 similar elements in are denoted by the same reference numbers. In some embodiments, memory device 90 is configured relative to, for example, memory device 10.

[0180] In contrast to memory device 10, memory device 90 further includes a read data line RBL UP SEG3 composed of read data line RBL UP F1 and read data line RBL UP N2. Read data line RBL UP SEG3 extends in the x-direction to be coupled to memory segment 911 in memory device 90. As shown in Figure 9 , memory segment 911 is separated from memory segment 112 by a band of cells 912. Specifically, read data line RBL UP F1 passes through memory segment 111 and memory segment 112. Read data line RBL UP N2 passes through memory segment 911. Read data line RBL UP F1 terminates at band of cells 912 and is coupled to read data line RBL UP N2.

[0181] Reference is now made to Figures 10A to 10B . In accordance with other embodiments of the present disclosure, Figure 10A is a layout diagram 90A of a portion of memory device 90 in Figure 9 , is a cross-sectional view of a portion of memory device 90 along line DD' in Figure 10B . Figure 10A

[0182] As shown in Figure 10A and Figure 10B ​As shown, the read data line RBL_UP_F1 is formed in the second metal layer M2 and extends in the x-direction to be coupled to the connection layer 912a formed in the first metal layer M1 via via V1_2. The read data line RBL_UP_F1 is separated from the read data lines RBL_UP_F0 and RBL_UP_N0 to RBL_UP_N2 along the y-direction. The connection layer 912a is further coupled to the read data line RBL_UP_N2 via via V0_2.

[0183] Now for reference Figures 11A to 11B . Figure 11A Other embodiments according to this disclosure Figure 9 The layout diagram 90B shows the memory device portion of the memory. Figure 11B It is along part 90 of the memory device Figure 11A Cross-sectional view of the centerline EE'.

[0184] and Figure 4A In contrast, the read data line RBL_UP_F1 is formed in a metal layer (e.g., "metal quad", M4) above the read data line RBL_UP_F0. In some embodiments, the width W3 of the read data line RBL_UP_F1 is greater than the width W1 of the read data line RBL_UP_F0 along the y-direction.

[0185] like Figure 11A As shown in the layout diagram, the read data line RBL_UP_F1 overlaps with the read data line RBL_UP_F0 and further overlaps with the read data lines RBL_UP_N0 to RBL_UP_N2.

[0186] Specifically, such as Figures 11A to 11B As shown, the read data line RBL_UP_F1 is coupled to the read data line RBL_UP_N2 via via V3_1, the connection layer 912c formed in the metal layer M3 below the metal layer M4, via V2_1, the connection layer 912b formed in the metal layer M2, via V1_2, the connection layer 912a, and via V0_2.

[0187] exist Figure 9 In some embodiments of the memory device 90, read data lines RBL_UP_F0, RBL_UP_F1, and RBL_UP_N0 are coupled to read circuit 1302 for read operations.

[0188] Now for reference Figure 12 . Figure 12 This is a schematic circuit diagram of the readout circuit 1302 and the signal generation circuits 141-146 according to other embodiments of this disclosure.

[0189] like Figure 12As shown, the read circuit 1302 includes a latch circuit 135 and a select circuit 502 configured relative to, for example, select circuit 501. Select circuit 502 is coupled to read data lines RBL_UP_F0, RBL_UP_F1, and RBL_UP_N0, and read data lines RBL_DN_F0, RBL_DN_F1, and RBL_DN_N0. Select circuit 502 includes transistors T5 and T10, P-type transistors T20 to T31, hold circuits 132 and 134, and logic gates (e.g., NAND gates) 138 to 139.

[0190] Specifically, transistor T20 is coupled between transistor T5 and the first input of logic gate 138. Transistor T23 is coupled between the first input of logic gate 138 and the voltage terminal providing voltage VDD. The first input of logic gate 138 is coupled to the read data line RBL_UP_F1. The gate of transistor T23 receives the signal RBLEQB_UP_F1 generated by the inverter 1451 in signal generation circuit 145 based on the signal RBLEQ_UP_F1 sent to the gate of transistor T20.

[0191] Transistor T21 is coupled between transistor T5 and the second input of logic gate 138. Transistor T24 is coupled between the second input of logic gate 138 and the voltage terminal providing voltage VDD. The second input of logic gate 138 is coupled to the read data line RBL_UP_F0. The gate of transistor T24 receives the signal RBLEQB_UP_F0 generated by the inverter 1431 in signal generation circuit 143 based on the signal RBLEQ_UP_F0 sent to the gate of transistor T21.

[0192] Transistor T22 is coupled between transistor T5 and the third input of logic gate 138. Transistor T25 is coupled between the third input of logic gate 138 and the voltage terminal providing voltage VDD. The third input of logic gate 138 is coupled to the read data line RBL_UP_N0. The gate of transistor T25 receives the signal RBLEQB_UP generated by the inverter 1411 in signal generation circuit 141 based on the signal RBLEQ_UP sent to the gate of transistor T22.

[0193] In some embodiments, logic gate 138 is further configured to perform a NAND operation based on the voltage at the input of logic gate 138 to generate the signal LFB_UP.

[0194] Similarly, transistor T26 is coupled between transistor T10 and the first input of logic gate 139. Transistor T29 is coupled between the first input of logic gate 139 and the voltage terminal providing voltage VDD. The first input of logic gate 139 is coupled to the read data line RBL_DN_N0. The gate of transistor T29 receives the signal RBLEQB_DN generated by the inverter 1421 in signal generation circuit 142 based on the signal RBLEQ_DN sent to the gate of transistor T26.

[0195] Transistor T27 is coupled between transistor T10 and the second input of logic gate 139. Transistor T30 is coupled between the second input of logic gate 139 and the voltage terminal providing voltage VDD. The second input of logic gate 139 is coupled to the read data line RBL_DN_F0. The gate of transistor T30 receives the signal RBLEQB_DN_F0 generated by inverter 1441 in signal generation circuit 144 based on the signal RBLEQ_DN_F0 sent to the gate of transistor T27.

[0196] Transistor T28 is coupled between transistor T10 and the third input of logic gate 139. Transistor T31 is coupled between the third input of logic gate 139 and the voltage terminal providing voltage VDD. The third input of logic gate 139 is coupled to the read data line RBL_DN_F1. The gate of transistor T31 receives the signal RBLEQB_DN_F1 generated by inverter 1461 in signal generation circuit 146 based on the signal RBLEQ_DN_F1 sent to the gate of transistor T28.

[0197] Regarding the operation of the read circuit 1302, refer to the following: Figure 13 . Figure 13 This is a schematic waveform diagram of signals in a memory device 90 according to other embodiments of the present disclosure.

[0198] Before performing a read operation on the memory cell MC in the memory segment 112 selected for access, at least in response to the signal RBLEQB_UP_F0 having a voltage level corresponding to a low logic state and the signal RBLEQ_UP_F0 having a voltage level corresponding to a high logic state, the read data line RBL_UP_F0 is precharged according to the voltage VDD to have a voltage level corresponding to a high logic state.

[0199] The configuration for reading operations of memory cells MC in memory segment 112 of the memory device is similar to that in the reference. Figures 5 to 6 The configuration described above. Therefore, repeated descriptions are omitted here.

[0200] In some embodiments of the read circuits 1301 and 1302, only one read data line is selected and precharged to voltage VDD in order to save power consumption in memory devices 10 and 90.

[0201] Now for reference Figure 14 . Figure 14 This is a schematic diagram of a memory device 1200 according to other embodiments of this disclosure. About Figures 1 to 13 The embodiments are provided for ease of understanding. Figure 14 Similar elements are denoted by the same reference numerals. In some embodiments, memory device 1200 is configured relative to, for example, memory device 10.

[0202] and Figure 2 Compared to memory device 10, memory cells MC in different memory segments are coupled to different pairs of write data lines in the memory device. For example... Figure 14 As shown, the memory cell MC in memory segment 111 is coupled to a pair of write data lines WBL_UP_N0 and WBLB_UP_N0. The memory cell MC in memory segment 112 is coupled to another pair of write data lines, for example, write data line WBL_UP_N0 and a write data line consisting of write data lines WBL_UP_F0 and WBL_UP_N1.

[0203] In some embodiments, write data lines WBL_UP_N0, WBL_UP_N1, WBLB_UP_N0, and WBLB_UP_N1 are formed in metal layer M0, while write data lines WBL_UP_F0 and WBLB_UP_F0 are formed in metal layer M2. In some embodiments, write data lines WBL_UP_N0, WBL_UP_N1, WBLB_UP_N0, and WBLB_UP_N1 are configured relative to, for example, read data line RBL_UP_N0. Write data lines WBL_UP_F0 and WBLB_UP_F0 are configured relative to, for example, read data line RBL_UP_F0.

[0204] The configuration of the write data lines in memory bank 120 is similar to that in memory bank 110. Therefore, repeated descriptions are omitted here.

[0205] For illustration, the input and output circuit 130 further includes a write data circuit 1511 coupled to write data lines WBL_UP_N0, WBLB_UP_N0, WBL_UP_F0, WBLB_UP_F0, WBL_DN_N0, WBLB_DN_N0, WBL_DN_F0, and WBLB_DN_F0. In some embodiments, the write data circuit 1511 selectively writes data to one of the paired write data lines.

[0206] Now for reference Figure 15 . Figure 15 This is a flowchart of a method 1500 for operating a memory device to perform a read operation according to some embodiments of the present disclosure. It should be understood that, for additional embodiments of the method, [further details may be needed]. Figure 15 Additional operations are provided before, during, and after the process shown, and some of the operations described below can be replaced or eliminated. The order of operations / processes is interchangeable. Throughout the various views and illustrative embodiments, similar reference numerals are used to denote similar elements. Method 1500 has operations S1501 to S1504, and references... Figures 1 to 14 The embodiments will be discussed.

[0207] In operation S1501, such as Figures 3A to 3B As shown, read data lines RBL_UP_N0 and RBL_UP_N1 are formed in metal layer M0. Read data lines RBL_UP_N0 and RBL_UP_N1 are separated from each other in the x-direction.

[0208] In operation S1502, such as Figure 2 As shown, write data lines WBLB and WBL are formed in the metal layer M0. Write data lines WBLB and WBL are coupled to both memory segment 111 and memory segment 112.

[0209] In operation S1503, a connection layer 113a is formed in the metal layer M1 above the metal layer M0 to be coupled to the read data line RBL_UP_N1 via the via V0_1.

[0210] In operation S1504, a read data line RBL_UP_F0 is formed in the metal layer M2 above the metal layer M1 to be coupled to the connection layer 113a via the via V1_1.

[0211] In some embodiments, method 1500 further includes the following operations: forming a read data line RBL_UP_N2 in metal layer M0 to be coupled to memory segment 911, and forming a read data line RBL_UP_F1 in metal layer M2 to be coupled to read data line RBL_UP_N2. Figure 10A As shown, along the x-direction, the length of the read data line RBL_UP_F1 is greater than the length of the read data line RBL_UP_N2.

[0212] In some embodiments, such as Figure 11AAs shown, the method 1500 further includes operations of forming a connection layer 912a in the metal layer M1, forming a connection layer 912b in the metal layer M2, forming a connection layer 912c in the metal layer M3, which are coupled to the read data line RBL UP N2 via the via V0 1, and forming a read data line RBL UP F1 in the metal layer M4, which is coupled to the read data line RBL UP N2 via the connection layers 912a-912c.

[0213] As described above, the memory device in the present disclosure provides split read bit lines for memory segments away from input and output circuit configurations, which utilizes higher metal layers to serve lower bit line loads in read operations. It optimizes read operation speed. Compared with other methods, access time is reduced by about 20% and area is reduced by about 10% due to the configuration of memory banks on the opposite side of the input and output circuit. In addition, the feasibility of the read bit lines in the present disclosure (such as Figure 8 The number of memory cells coupled to a particular read data line as shown helps to balance the load between read data lines. Specifically, the total load of a read data line is associated with the length and number of memory cells coupled thereto. By reducing the number of memory cells coupled to the read data line RBL UP SEG2 and forming the read data line RBL UP F0 in a high metal layer, the load on the read data line RBL UP N0 is more balanced with the load on the read data line RBL UP SEG2, which improves the delay difference in the read data lines. Therefore, the performance of the memory device is enhanced.

[0214] In some embodiments, a memory device is disclosed. The memory device includes a first read data line coupled to a first memory segment; a second read data line coupled to a second memory segment and including a first portion passing through a first portion of the first memory segment and a second portion passing through a second portion of the second memory segment; and a first belt cell inserted between the first memory segment and the second memory segment. The first portion of the second read data line terminates at the first belt cell and is coupled to the second portion of the second read data line.

[0215] In some embodiments, the memory device further includes a pair of write data lines extending along a first direction to pass through the first memory segment and the second memory segment.

[0216] In some embodiments, the first portion of the second read data line and the second portion of the second read data line extend in a first direction and are separated from each other in a second direction different from the first direction.

[0217] In some embodiments, the first portion of the second read data line and the second portion of the second read data line extend in a first direction and are separated from each other in a second direction different from the first direction.

[0218] In some embodiments, the first strip unit includes a plurality of dummy memory cells.

[0219] In some embodiments, a first number of memory cells coupled to the first data line is different from a second number of memory cells coupled to the second read data line.

[0220] In some embodiments, the first number is greater than the second number.

[0221] In some embodiments, the memory device further includes a third read data line extending in the first direction to couple to a third memory segment, and including: a first portion through the first memory segment and the first portion of the second memory segment; and a second portion through the second portion of the third memory segment; and a second strip unit interposed between the second memory segment and the third memory segment. The first portion of the third read data line terminates at the second strip unit and couples to the second portion of the third read data line.

[0222] In some embodiments, along a second direction different from the first direction, a width of the first portion of the third read data line is greater than a width of the second portion of the third read data line.

[0223] In some embodiments, the memory device further includes a third read data line coupled to a third memory segment; and a fourth read data line coupled to a fourth memory segment, wherein a second strip unit is interposed between the third memory segment and the fourth memory segment. The fourth read data line includes a first portion through the third memory segment and a second portion through the fourth memory segment. The first portion of the fourth read data line terminates at the second strip unit and couples to the second portion of the fourth read data line.

[0224] In some embodiments, the memory device further includes a read circuit including: a selection circuit coupled to the first read data line to the fourth read data line and to generate a first read data from voltages of the first read data line and the second read data line and a second read data from voltages of the third read data line and the fourth read data line; and a latch circuit to generate an output read data corresponding to data stored in memory cells coupled to a selected one of the first to fourth data lines in response to the first read data and the second read data.

[0225] Also disclosed is a memory device including a first memory segment coupled to a first read data line; and a second memory segment separated from the first memory segment by a first strip unit and coupled to a second read data line through the first strip unit. The second read data line includes a first portion having a first width and a second portion having a second width less than the first width.

[0226] In some embodiments, the memory device further includes a pair of write data lines extending along the first direction to be coupled to the first memory segment and the second memory segment.

[0227] In some embodiments, the memory device further includes a third memory segment coupled to a third read data line, a fourth memory segment separated from the third memory segment by a second strap cell and coupled to a fourth read data line through the second strap cell, and a read circuit including a selection circuit to generate first read data according to voltages of the first read data line and the second read data line and to generate second read data according to voltages of the third read data line and the fourth read data line, and a latch circuit to generate output read data in response to the first read data and the second read data.

[0228] In some embodiments, the latch circuit includes a NOR gate to operate in response to the first read data and the second read data, a first inverter to generate the output read data in response to an output from the NOR gate, a first P-type transistor coupled in series with the NOR gate and to operate in response to a first clock signal, a second P-type transistor and a third P-type transistor coupled to the first N-type transistor and the second N-type transistor coupled in series at an output terminal of the NOR gate, the second P-type transistor to operate in response to a second clock signal different from the first clock signal, the second N-type transistor to operate in response to the first clock signal, and a second inverter coupled between the output terminal of the NOR gate and gates of the third P-type transistor and the first N-type transistor.

[0229] In some embodiments, the read circuit is to output the first read data having a low logic state to turn off the latch circuit when the second read data line is charged to a high logic state.

[0230] A method is also disclosed, the method including operations of forming a first conductive line and a second conductive line in a first metal layer, wherein the first conductive line and the second conductive line are separated from each other in a first direction, wherein the first conductive line is coupled to a first memory segment and the second conductive line is coupled to a second memory segment, forming a first connection layer in a second metal layer above the first metal layer to be coupled to a second conductive layer via a first via, forming a third conductive line in a third metal layer above the second metal layer to be coupled to the first connection layer via a second via, wherein a first width of the first conductive line and the second conductive line is smaller than a second width of the third conductive line, and forming a fourth conductive line and a fifth conductive line in the first metal layer, wherein the fourth conductive line and the fifth conductive line are coupled to the first memory segment and the second memory segment.

[0231] In some embodiments, the first conductive line and the third conductive line are separated from each other in a layout.

[0232] In some embodiments, the method further includes forming a sixth conductive line in the first metal layer to be coupled to the third memory segment; and forming a seventh conductive line in the third metal layer to be coupled to the sixth conductive line, wherein a length of the seventh conductive line is greater than a length of the third conductive line.

[0233] In some embodiments, the method further includes forming a sixth conductive line in the first metal layer to be coupled to the third memory segment; forming a second connection layer in the second metal layer, a third connection layer in the third metal layer, and a fourth connection layer in the fourth metal layer, the connection layers being coupled to the second conductive layer via a first via; and forming a seventh conductive line in a fifth metal layer above the fourth metal layer to be coupled to the sixth conductive line via the second connection layer to the fourth connection layer.

[0234] The foregoing outlines features of several embodiments so that a person of ordinary skill in the art can better understand the aspects of the disclosure. Those of ordinary skill in the art should appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A memory device, characterized in that, Include: A first read data line is coupled to a first memory segment; A second read data line, coupled to a second memory segment, and including a first portion passing through the first memory segment and a second portion passing through the second memory segment; and A first strip-shaped unit is inserted between the first memory segment and the second memory segment. The first portion of the second read data line terminates at the first strip unit and is coupled to the second portion of the second read data line.

2. The memory device as claimed in claim 1, characterized in that, It further includes: A pair of write data lines extending along a first direction to pass through the first memory segment and the second memory segment.

3. The memory device as claimed in claim 2, characterized in that, The first portion and the second portion of the second read data line extend in the first direction and are separated from each other in a second direction different from the first direction.

4. The memory device as claimed in claim 2, characterized in that, In a layout diagram, the first read data line and the first portion of the second read data line overlap each other.

5. The memory device as claimed in claim 1, characterized in that, The first strip cell contains multiple dummy memory cells.

6. The memory device as claimed in claim 1, characterized in that, The first number of memory cells coupled to the first read data line is different from the second number of memory cells coupled to the second read data line.

7. The memory device as claimed in claim 6, characterized in that, The first number is greater than the second number.

8. The memory device as claimed in claim 1, characterized in that, It further includes: A third read data line, extending in a first direction to be coupled to a third memory segment, and comprising: A first part, which passes through the first memory segment and the second memory segment; and The second part, which passes through the third memory segment; and A second strip-shaped unit is inserted between the second memory segment and the third memory segment. The first portion of the third read data line terminates at the second strip unit and is coupled to the second portion of the third read data line.

9. A memory device, characterized in that, Include: A first memory segment, coupled to a first read data line; and A second memory segment, which is separated from the first memory segment by a first strip cell and coupled to a second read data line through the first strip cell. The second read data line includes a first portion having a first width and a second portion having a second width smaller than the first width.

10. A memory device, characterized in that, Include: A first read data line is coupled to a first memory segment; A second read data line is coupled to a second memory segment and includes a first portion passing through the first memory segment and a second portion passing through the second memory segment; A first strip-shaped unit is inserted between the first memory segment and the second memory segment. The first portion of the second read data line terminates at the first strip unit and is coupled to the second portion of the second read data line; A third read data line, which is coupled to a third memory segment; and A fourth read data line is coupled to a fourth memory segment, wherein a second strip cell is inserted between the third memory segment and the fourth memory segment.

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