Semiconductor device

Abstract

A semiconductor device includes a substrate. The semiconductor layers are stacked on each other on the substrate. The gate structure surrounds each semiconductor layer. The epitaxial layer is located above the substrate and is in contact with the opposite end of the bottommost semiconductor layer. The source / drain epitaxial structures are respectively disposed on the epitaxial layers and are in contact with the epitaxial layers. The dielectric structures are vertically disposed between the epitaxial layers and the corresponding source / drain epitaxial structures, respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs, each designed to improve processing performance, increase capacity, and reduce cost of the IC. Generally, the shrinkage of IC dimensions, i.e., the size of transistors used to create an integrated circuit, has allowed more components to be incorporated into ICs. However, as the dimensions of ICs shrink, so do the features therein, and thus, fabrication processes become increasingly difficult to perform. SUMMARY

[0003] In some embodiments of the disclosure, a semiconductor device includes a substrate. Semiconductor layers are stacked together on the substrate. Gate structures surround each semiconductor layer. Epitaxial layers are located above the substrate and in contact with opposite ends of a bottommost semiconductor layer. Source / drain epitaxial structures are located on and in contact with the epitaxial layers, respectively. Dielectric structures are vertically disposed between the epitaxial layers and the respective source / drain epitaxial structures, respectively.

[0004] In some embodiments of the disclosure, a semiconductor device includes a first transistor and a second transistor. The first transistor includes first semiconductor layers, first gate structures surrounding each first semiconductor layer, and first source / drain epitaxial structures on opposite sides of the first gate structures, wherein the first source / drain epitaxial structures are separated from at least one of the first semiconductor layers. The second transistor includes second semiconductor layers, second gate structures surrounding each second semiconductor layer, and second source / drain epitaxial structures on opposite sides of the second gate structures, wherein the second source / drain epitaxial structures are in contact with the second semiconductor layers. First epitaxial layers are located below the first source / drain epitaxial structures, respectively, wherein a top surface of one of the first epitaxial layers is in contact with a top surface of a respective first source / drain epitaxial structure.

[0005] In some embodiments of the disclosure, a semiconductor device includes a substrate. Semiconductor layers are stacked together on the substrate. Gate structures surround each semiconductor layer. Epitaxial layers are located above the substrate and in contact with opposite ends of a bottommost semiconductor layer. Source / drain epitaxial structures are located on and in contact with the epitaxial layers, respectively. Dielectric structures are vertically disposed between the epitaxial layers and the respective source / drain epitaxial structures, respectively, wherein the dielectric structures have a triangular cross-sectional profile. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figures 1 to 17 This describes a method for forming a semiconductor device at various stages according to some embodiments of the present disclosure;

[0008] Figure 18 An enlarged view of a semiconductor device according to some embodiments of this disclosure;

[0009] Figure 19 An enlarged view of a semiconductor device according to some embodiments of this disclosure;

[0010] Figure 20 An enlarged view of a semiconductor device according to some embodiments of this disclosure;

[0011] Figure 21 An enlarged view of a semiconductor device according to some embodiments of this disclosure;

[0012] Figure 22 A cross-sectional view of a semiconductor device according to some embodiments of this disclosure;

[0013] Figures 23 to 26 This describes a method for forming a semiconductor device at various stages according to some embodiments of the present disclosure;

[0014] Figure 27 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0015] [Symbol Explanation]

[0016] 100:Substrate

[0017] 102, 102A, 102B, 104: Semiconductor layers

[0018] 115: Gate spacer

[0019] 116: Internal spacers

[0020] 130A, 130B, 130C: Dummy gate structure

[0021] 132: Dummy gate dielectric layer

[0022] 134: Dummy gate electrode

[0023] 136: Dielectric Structure

[0024] 140A, 140B: source / drain epitaxial structure

[0025] 142A, 142B, 144A, 144B: epitaxial layer

[0026] 144A_1: top portion

[0027] 144A_2: bottom portion

[0028] 150, 180: interlayer dielectric layer

[0029] 172: gate dielectric layer

[0030] 174: gate electrode

[0031] 185: conductive via

[0032] 170A, 170B, 170C: metal gate structure

[0033] 192A, 192B: silicide layer

[0034] 194A, 194B: source / drain contact

[0035] 200: backside dielectric layer

[0036] 212A, 212B: silicide layer

[0037] hi: height difference

[0038] h DE , h in , h Si : height

[0039] MA1-MA3: patterned mask

[0040] 01, 02: source / drain opening

[0041] TR1: first transistor

[0042] TR2: second transistor

[0043] W1, W2, W DE : width

[0044] 01, 02: angle DETAILED DESCRIPTION

[0045] The following disclosure provides many different embodiments, or examples, for implementing various characteristics of the provided subject matter. The following description is presented in terms of particular examples for simplicity and clarity. It should be appreciated that these are examples only and are not intended to be limiting unless otherwise specifically indicated. For example, forming a first feature over or on a second feature in the following description can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Furthermore, the disclosure can repeat use of particular elements or names of elements in various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments or configurations discussed.

[0046] Furthermore, spatial or directional terms, such as "below", "under", "below", "above", "on", "over", and the like, can be used herein for purposes of clarity. Unless specifically stated otherwise, the spatial or directional terms are intended to encompass different orientations of the device in use or operation. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial or directional descriptions used herein can be interpreted accordingly. As used herein, "left", "right", "about", "approximately", or "substantially" can generally mean within 20% of a given value or range, or within 10% of a given value or range, or within 5% of a given value or range. Numerical values given herein are approximate, and the terms "about", "approximately", or "substantially" can be inferred if not explicitly stated. However, those skilled in the art will recognize that the values or ranges recited in the description are merely examples and can be reduced as integrated circuits shrink.

[0047] Gate all around (GAA) transistor structures can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern the structures, including a double patterning process or a multiple patterning process. Generally, double patterning processes or multiple patterning processes combine lithography with a self-alignment process, allowing for the creation of patterns with a pitch, for example, that is less than that obtained using a single, direct lithography process. For example, in some embodiments, a sacrificial layer formed over a substrate is patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern the GAA structure.

[0048] Figures 1 to 17 Methods of forming semiconductor devices at various stages are described in accordance with some embodiments of the present disclosure. While the following description is presented in terms of particular examples for simplicity and clarity, it should be appreciated that these are examples only and are not intended to be limiting unless otherwise specifically indicated. For example, forming a first feature over or on a second feature in the following description can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. Furthermore, the disclosure can repeat use of particular elements or names of elements in various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments or configurations discussed. Figures 1 to 17Described as a series of acts, but it is to be appreciated that the acts are not limited to the order described herein, as some acts can occur in different orders, or be performed concurrently, that the disclosed methods are not limited to only those acts described, and that not all acts are required for a particular implementation. In other embodiments, one or more acts can be omitted from the disclosed methods.

[0049] Referring to Figure 1 A substrate 100 is shown. In general, the substrate 100 can include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulator layer under a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but can include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., Ga x Al 1-x As, Ga x Al 1-x N, In x Ga 1-x As, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor materials can be doped or undoped. Other substrates that can be used include multilayer substrates, graded substrates or hybrid orientation substrates.

[0050] A stack of alternating semiconductor layers 102 and semiconductor layers 104 is formed on the substrate 100. In some embodiments, the semiconductor layers 102 can be made of pure silicon layers that do not contain germanium. The semiconductor layers 102 can also be substantially pure silicon layers, e.g., with a percentage of germanium that is less than about 1%. The semiconductor layers 104 can be made of silicon-germanium. For example, the semiconductor layers 104 can have a percentage of germanium (atomic percent concentration) in a range from about 20% and about 50%. In some embodiments, the semiconductor layers 102 and 104 can be deposited using suitable deposition processes, such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE) or other suitable processes.

[0051] Referring to Figure 2Dummy gate structures 130A, 130B, and 130C are formed on the substrate 100 and through the stack of alternating semiconductor layers 102 and 104, with dummy gate structure 130C laterally between dummy gate structures 130A and 130B. In some embodiments, each dummy gate structure 130A, 130B, and 130C includes a dummy gate dielectric layer 132 and a dummy gate electrode 134 on the dummy gate dielectric layer 132. The dummy gate dielectric layer 132 can be, for example, silicon oxide, silicon nitride, combinations thereof, and the like, and can be deposited or thermally grown according to accepted techniques. The dummy gate electrode 134 can be a conductive or non-conductive material, and can be selected from the group consisting of amorphous silicon, polysilicon, poly-SiGe, metal nitride, metal silicide, metal oxide, and metal.

[0052] The dummy gate electrode 134 and the dummy gate dielectric layer 132 can be formed by, for example, depositing a dummy dielectric layer and a dummy gate electrode layer on the substrate 100, forming a patterned mask MA1 on the dummy gate electrode layer, and then etching the dummy dielectric layer and the dummy gate electrode layer with the patterned mask MA1 as an etch mask. In some embodiments, the dummy gate electrode 134 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputter deposition, or other techniques of selected materials. In some embodiments, the dummy gate dielectric layer 132 can be formed by thermal oxidation. In some embodiments, the patterned mask MA1 can include silicon oxide, silicon nitride, combinations thereof, or other suitable materials.

[0053] Gate spacers 115 are formed on opposing sidewalls of each dummy gate structure 130A, 130B, and 130C. In some embodiments, the gate spacers 115 can be composed of silicon oxide, silicon nitride, silicon oxynitride, combinations thereof. In some embodiments, the gate spacers 115 can be formed by, for example, depositing a spacer layer blanket on the substrate, followed by an anisotropic etching process to remove horizontal portions of the spacer layer, such that vertical portions of the spacer layer remain on the sidewalls of the dummy gate structures 130A, 130B, and 130C. In some embodiments, the remaining vertical portions of the spacer layer on the sidewalls of the dummy gate structures 130A, 130B, and 130C can be referred to as gate spacers 115. In some embodiments, the spacer layer can be deposited using techniques such as CVD, ALD, and the like.

[0054] Referring to Figure 3The stack of alternating semiconductor layers 102 and 104 and substrate 100 are etched using the gate spacers 115 and the patterned mask MA1 (or dummy gate structures 130A, 130B, and 130C) as an etch mask to form openings in the stack of alternating semiconductor layers 102 and 104 and substrate 100. In more detail, the openings on opposite sides of dummy gate structure 130A are referred to as source / drain openings Ol, while the openings on opposite sides of dummy gate structure 130B are referred to as source / drain openings 02. In some embodiments, the etching process is performed until the bottommost ends of source / drain openings Ol and 02 are below the bottommost semiconductor layer 104. The etching process can include dry etching, wet etching, or a combination thereof.

[0055] Referring to Figure 4 The semiconductor layers 104 are laterally etched to form sidewall recesses. Then, interior spacers 116 are formed in the sidewall recesses at opposite ends of each semiconductor layer 104. In some embodiments, the interior spacers 116 can be formed by, for example, depositing an interior spacer layer blanket over the substrate 100 and filling the sidewall recesses on opposite sides of the semiconductor layers 104, and then performing an anisotropic etch to remove portions of the interior spacer layer outside the sidewall recesses, leaving the remaining portions of the interior spacer layer in the sidewall recesses as the interior spacers 116. The interior spacers 116 can be deposited by a conformal deposition process, such as CVD, ALD, etc. The interior spacer layer can include a material such as SiN, SiOCN, SiCN, SiOC, although any suitable material can be used, such as a low-k material having a k value less than about 3.5.

[0056] Referring to Figure 5 Epitaxial layers 142A and 142B are formed on the bottoms of source / drain openings Ol and 02, respectively. Thereafter, epitaxial layers 144A and 144B are formed over epitaxial layers 142A and 142B, respectively. In more detail, epitaxial layers 142A and 142B are formed from the bottoms of source / drain openings Ol and 02 until the top surfaces of epitaxial layers 142A and 142B are above the top surface of substrate 100 (or above the bottom surface of the bottommost semiconductor layer 104). Then, epitaxial layers 144A and 144B are formed over epitaxial layers 142A and 142B until the sidewalls of the bottommost semiconductor layer 102 are covered by epitaxial layers 144A and 144B. In some embodiments, epitaxial layers 142A / 142B and 144A / 144B are undoped.

[0057] In some embodiments, the formation of epitaxial layers 142A and 142B can include one or more deposition cycles, where each deposition cycle can include a selective epitaxial growth (SEG) process and an etch process. In some embodiments, the SEG process can selectively grow a semiconductor material on exposed semiconductor surfaces, such as the exposed surfaces of substrate 100 and the exposed surfaces of semiconductor layers 102. However, since the exposed area of substrate 100 is larger than the exposed area of each semiconductor layer 102, the semiconductor material on the exposed area of substrate 100 can include a higher growth rate than on the exposed area of each semiconductor layer 102. That is, the amount of semiconductor material grown on the exposed area of substrate 100 will be greater than the amount grown on the exposed area of each semiconductor layer 102. Accordingly, the etch process in each deposition cycle of epitaxial layers 142A and 142B can remove a portion of the semiconductor material formed on the exposed area of each semiconductor layer 102, while a portion of the semiconductor material can remain on substrate 100 after the etch process. Thus, performing at least one deposition cycle can allow for a bottom-up deposition of epitaxial layers 142A and 142B. That is, epitaxial layers 142A and 142B can be formed from the bottom up from the bottom of source / drain openings Ol and 02.

[0058] Similarly, the formation of epitaxial layers 144A and 144B can also include one or more deposition cycles, where each deposition cycle can include a selective epitaxial growth (SEG) process and an etch process. Since epitaxial layers 142A and 142B include a larger exposed area than semiconductor layers 102, epitaxial layers 144A and 144B can also be formed from the bottom up from the bottom of source / drain openings Ol and 02.

[0059] Epitaxial layers 142A and 142B can include silicon (Si) or silicon germanium (Si 1-x Ge x ). In some embodiments, x is in a range from about 0 to about 0.4. Epitaxial layers 144A and 144B can include silicon germanium (Si 1-y Ge y ). In some embodiments, y is in a range from about 0 to about 0.4. In some embodiments, x is less than y.

[0060] In some embodiments, both epitaxial layers 142A / 142B and epitaxial layers 144A / 144B are made of silicon germanium (SiGe). The deposition of epitaxial layers 142A / 142B and epitaxial layers 144A / 144B can include supplying a silicon-containing precursor and a germanium-containing silicon precursor. Exemplary silicon-containing precursors include SiH4, Si2H6, H2SiCl2, Si x H 2x+2Higher order silanes, etc. Exemplary germanium-containing silicon precursors include GeH4, etc. Hydrochloric acid (HC1) can also be provided as a reactant gas (or etching gas) during deposition of epitaxial layers 142A / 142B and 144A / 144B for performing the etching process described above in the deposition cycle. In some embodiments, the deposition temperature is in a range from about 500 °C to about 800 °C (e.g., 600 °C to 700 °C in some embodiments). The pressure is in a range from about 10 Torr to about 130 Torr (e.g., 50 Torr in some embodiments).

[0061] In some embodiments, the flow rate of hydrochloric acid (HC1) used to deposit epitaxial layers 142A / 142B can be different from the flow rate of hydrochloric acid (HC1) used to deposit epitaxial layers 144A / 144B. This will result in epitaxial layers 142A / 142B can include a different top surface profile than epitaxial layers 144A / 144B. For example, the flow rate of hydrochloric acid (HC1) used to deposit epitaxial layers 144A / 144B is greater than the flow rate of hydrochloric acid (HC1) used to deposit epitaxial layers 142A / 142B. Thus, epitaxial layers 142A / 142B can include a substantially flat top surface profile, while epitaxial layers 144A / 144B can include a non-flat top surface profile, such as a trapezoidal top surface profile. In other words, the top surface of epitaxial layers 142A / 142B can be flatter than the top surface of epitaxial layers 144A / 144B. The trapezoidal top surface profile can include two sloped surfaces and a horizontal surface connecting the sloped surfaces, relative to epitaxial layers 144A / 144B. In some embodiments, the non-flat top surface profile can be advantageous to avoid edge defects to preserve the crystalline strain of the source / drain epitaxial structure (e.g., source / drain epitaxial structure 140A) formed therefrom. Figure 9

[0062] Referring to Figure 6 A patterned mask MA2 is formed over substrate 100. In more detail, patterned mask MA2 covers dummy gate structures 130A, 130B, and 130C, and fills source / drain openings 02 to cover epitaxial layer 144B. On the other hand, patterned mask MA2 can include an opening that exposes source / drain openings 01, such that epitaxial layer 144A in source / drain openings 01 is exposed by patterned mask MA2. In some embodiments, patterned mask MA2 can be a hard mask, and can be made of metal oxide or other suitable material.

[0063] Referring to Figure 7 ​A dielectric layer 135 is deposited on the substrate 100 and fills the source / drain openings Ol. The dielectric layer 135 can be formed by, for example, depositing a dielectric material on the substrate 100 and overfilling the source / drain openings Ol, followed by performing a planarization process, such as CMP, to remove the excess dielectric material until the top surface of the patterned mask MA2 is exposed. In some embodiments, the dielectric layer 135 can include silicon (Si), carbon (C), oxygen (O), and / or nitrogen (N). For example, the dielectric layer 135 can include silicon carbide (SiC), silicon oxide (Si02), silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN). The dielectric layer 135 can be deposited using a suitable deposition process, such as chemical CVD, ALD, etc.

[0064] Referring to Figure 8 A back-etch process is performed on the dielectric layer 135 to lower the top surface of the dielectric layer 135 until the top surface of the epitaxial layer 144A is exposed. In more detail, the horizontal surface of the epitaxial layer 144A can be exposed due to the back-etch process. On the other hand, after the back-etch process is completed, a portion of the dielectric layer 135 can remain in contact with the sloped surface of the epitaxial layer 144A. That is, after the back-etch process is completed, the remaining portion of the dielectric layer 135 is located on opposite sides of each epitaxial layer 144A. In the following discussion, the remaining portion of the dielectric layer 135 is referred to as a dielectric structure 136. In some embodiments, the back-etch process can include a wet etch, a dry etch, or a combination thereof.

[0065] Referring to Figure 9 A source / drain epitaxial structure 140A is formed on opposite ends of each semiconductor layer 102 through the source / drain openings Ol. The source / drain epitaxial structure 140A can be formed by a suitable deposition process, such as a selective epitaxial growth (SEG) process. In some embodiments, the SEG process can selectively grow a semiconductor material on exposed semiconductor surfaces, such as the exposed surface of the epitaxial layer 144A and the exposed surface of the semiconductor layer 102. In some embodiments, the source / drain epitaxial structure 140A can be subjected to a doping process. For example, the source / drain epitaxial structure 140A can be doped with a p-type dopant, such as boron (B), gallium (Ga), indium (In), aluminum (Al), etc. In some embodiments, the source / drain epitaxial structure 140A can be doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), etc.

[0066] Since the etch-back dielectric layer 135 exposes the epitaxial layer 144A, the exposed epitaxial layer 144A can provide additional nucleation sites for the source / drain epitaxial structure 140A, and thus the source / drain epitaxial structure 140A can be formed to have a void-free structure. If the epitaxial layer 144A is covered by the dielectric layer 135, a void can be formed between the source / drain epitaxial structure 140A and the dielectric layer 135. In addition, the remaining dielectric structure 136 can also provide electrical isolation between the source / drain epitaxial structure 140A and the bottommost semiconductor layer 102, and will prevent current leakage from the source / drain epitaxial structure 140A to the bottommost semiconductor layer 102. With this configuration, device performance can be improved.

[0067] Referring to Figure 10 After the source / drain epitaxial structure 140A is formed, the patterned mask MA2 is removed, thereby exposing the source / drain opening O2. In some embodiments, the patterned mask MA2 can be removed using a suitable etching process, such as dry etching or wet etching.

[0068] Referring to Figure 11 The patterned mask MA3 is formed on the substrate 100. In more detail, the patterned mask MA3 covers the dummy gate structures 130A, 130B, and 130C, and covers the source / drain epitaxial structure 140A. On the other hand, the patterned mask MA3 can include an opening that exposes the source / drain opening O2, such that the epitaxial layer 144B in the source / drain opening O2 is exposed by the patterned mask MA3. In some embodiments, the patterned mask MA3 can be a hard mask, and can be made of metal oxide or other suitable materials.

[0069] Referring to Figure 12 An etch-back process is performed on the epitaxial layer 144B, thereby lowering the top surface of the epitaxial layer 144B to a position below the bottommost semiconductor layer 102. In more detail, the epitaxial layer 144B is etched back to expose the sidewall of the bottommost semiconductor layer 102 underneath the dummy gate structure 130B. In some embodiments, each etched epitaxial layer 144B can include a substantially planar top surface profile. The top surface of the etched epitaxial layer 144B can be lower than, and can be more planar than, the top surface of the epitaxial layer 144A. In some embodiments, the etch-back process can include wet etching, dry etching, or a combination thereof.

[0070] Referring to Figure 13The source / drain epitaxial structures 140B are formed in each semiconductor layer 102 at opposite ends by the source / drain openings 02. Due to the etch-back of the epitaxial layer 144B, the source / drain epitaxial structures 140B can be formed in contact with the bottommost semiconductor layer 102 under the dummy gate structures 130B. Thus, the bottom surface of the source / drain epitaxial structures 140B can be lower than the bottom surface of the source / drain epitaxial structures 140A. The source / drain epitaxial structures 140B can be formed by a suitable deposition process, such as a selective epitaxial growth (SEG) process. In some embodiments, the SEG process can selectively grow semiconductor material on exposed semiconductor surfaces, such as the exposed surfaces of the epitaxial layer 144B and the exposed surfaces of the semiconductor layer 102. In some embodiments, the source / drain epitaxial structures 140B can be subjected to a doping process. For example, the source / drain epitaxial structures 140B can be doped with p-type dopants, such as boron (B), gallium (Ga), indium (In), aluminum (Al), etc. In some embodiments, the source / drain epitaxial structures 140B can be doped with n-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb), etc.

[0071] Referring to Figure 14 An interlayer dielectric layer 150 is formed on the substrate 100 and covers the source / drain epitaxial structures 140A and 140B. Then, a planarization process, such as CMP, is performed to remove excess material of the interlayer dielectric layer 150 until the dummy gate structures 130A, 130B, and 130C are exposed. In some embodiments, the patterned mask MA1 is removed during planarization. In some embodiments, a contact etch stop layer (CESL) (not shown) can be formed on the substrate 100 prior to forming the interlayer dielectric layer 150.

[0072] In some embodiments, the CESL can be a dielectric layer including silicon nitride, silicon oxynitride, or other suitable material. In some embodiments, the interlayer dielectric layer 150 can include silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and / or other suitable dielectric material. Examples of low-k dielectric material include, but are not limited to, fluorosilicate glass (FSG), carbon-doped silicon oxide, amorphous fluorocarbon, parylene, bisbenzocyclobutene (BCB), or polyimide.

[0073] Referring to Figure 15 The dummy gate structures 130A, 130B, and 130C are removed to form gate trenches between each pair of gate spacers 115. Thereafter, the semiconductor layer 104 is removed such that the semiconductor layer 102 is suspended on the substrate 100.

[0074] Referring to Figure 16 Metal gate structures 170A, 170B, and 170C are formed in the gate trenches and around the respective semiconductor layers 102. Each metal gate structure 170A, 170B, and 170C can include a gate dielectric layer 172 and a gate electrode 174 over the gate dielectric layer 172. The metal gate structures 170A, 170B, and 170C can be formed by, for example, sequentially depositing a gate dielectric material and a gate electrode material in the gate trenches and around the respective semiconductor layers 102, followed by a planarization process such as CMP to remove excess gate dielectric material and excess gate electrode material until the interlayer dielectric layer 150 is exposed.

[0075] In some embodiments, the gate dielectric layer 172 can include an interface layer and a high-k dielectric layer over the interface layer. In some embodiments, the interface layer can be made of an oxide such as aluminum oxide (AI2O3), silicon oxide (SiO2), etc. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium oxide-aluminum oxide (HfO2— AI2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof.

[0076] The gate electrode 174 can include a work function metal layer and a fill metal. The work function metal layer can be an n-type or a p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer can include multiple layers. The fill metal can include tungsten (W), aluminum (Al), copper (Cu), or other suitable conductive materials.

[0077] After the metal gate structures 170A, 170B, and 170C are formed, a hybrid sheet structure is formed. The hybrid sheet structure includes a first transistor TR1 and a second transistor TR2. For the first transistor TR1, the first transistor TR1 includes a semiconductor layer 102A, a source / drain epitaxial structure 140A in contact with opposite ends of each semiconductor layer 102A, and a metal gate structure 170A around each semiconductor layer 102A. In particular, the bottommost semiconductor layer 102A is in contact with an undoped epitaxial layer 144A, so no or negligible current will flow through the bottommost semiconductor layer 102A. That is, the bottommost semiconductor layer 102A can be “disabled” and cannot serve as a channel layer for the first transistor TR1.

[0078] On the other hand, for the second transistor TR2, the second transistor TR2 includes the semiconductor layer 102B, the source / drain epitaxial structure 140B in contact with the opposite end of the semiconductor layer 102B, and the metal gate structure 170B surrounding the semiconductor layer 102B. Unlike the first transistor TR1, the source / drain epitaxial structure 140B is in contact with all of the semiconductor layer 102B, and thus the second transistor TR2 can include more active channel layers than the first transistor TR1.

[0079] It should be noted that the number of the semiconductor layers 102 is for illustration only, and the disclosure is not limited thereto. In some embodiments, the total number of the semiconductor layers 102 can be N, where 2≤N≤6. In some embodiments, the number of the disabled semiconductor layers 102 can be n, where 1≤n≤N-1.

[0080] Referring to Figure 17 The interlayer dielectric layer 150 is removed by a suitable process, such as an etching process, to expose the underlying source / drain epitaxial structures 140A and 140B. Silicide layers 192A and 192B are formed on the exposed surfaces of the source / drain epitaxial structures 140A and 140B, respectively. Thereafter, source / drain contacts 194A and 194B are formed on the silicide layers 192A and 192B, respectively, such that the source / drain contacts 194A and 194B are electrically connected to the corresponding source / drain epitaxial structures 140A and 140B. Thereafter, an interlayer dielectric layer 180 is formed on the substrate 100 and covers the metal gate structures 170A, 170B, and 170C, and the source / drain contacts 194A and 194B. Conductive vias 185 are formed in the interlayer dielectric layer 180 and are in contact with the corresponding metal gate structures 170A, 170B, and 170C, and the corresponding source / drain contacts 194A and 194B. In some embodiments, the conductive vias 185 in contact with the metal gate structures 170A, 170B, and 170C can be referred to as gate vias, and the conductive vias 185 in contact with the source / drain contacts 194A and 194B can be referred to as source / drain vias.

[0081] In some embodiments, the silicide layers 192A and 192B can include CoSi2, TiSi2, WSi2, NiSi2, MoSi2, TaSi2, PtSi, etc. In some embodiments, each source / drain contact 194A and 194B can include a diffusion barrier layer and a contact plug over the diffusion barrier layer. In some embodiments, the diffusion barrier layer can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or other suitable material. The contact plug can include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive material. In some embodiments, the interlayer dielectric layer 180 can include similar materials as the interlayer dielectric layer 150. The conductive via 185 can include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), molybdenum (Mo), nickel (Ni), or other suitable conductive material.

[0082] Figure 18 is a magnified view of the semiconductor device according to some embodiments of the present disclosure. More details of the semiconductor device are shown in FIG. 1C. Figure 18 is a magnified view of the semiconductor device according to some embodiments of the present disclosure. More details of the semiconductor device are shown in FIG. 1C. Figure 17 is a magnified view of the first transistor TR1. It is noted that some elements of FIG. 1A have been described above, and thus related details are not repeated for brevity. In some embodiments, the dielectric structure 136 has a top surface that is substantially coplanar with a top surface of the epitaxial layer 144A. Figure 18 Figure 18 In some embodiments of the semiconductor device, a top surface of the dielectric structure 136 is substantially coplanar with a top surface of the epitaxial layer 144A.

[0083] For the epitaxial layer 142A, the epitaxial layer 142A has a width W1, where in some embodiments the width W1 is in a range from about 10 nm to about 50 nm. In some embodiments, a height difference h1 between a top surface of the epitaxial layer 142A and a top surface of the substrate 100 is in a range from about -10 nm to about 5 nm. That is, the top surface of the epitaxial layer 142A can be higher or lower than the top surface of the substrate 100. The inner spacer 116 has a height h in where in some embodiments the height h in is in a range from about 3 nm to about 15 nm. The semiconductor layer 102 has a height h Si where in some embodiments the height h Si is in a range from about 3 nm to about 15 nm.

[0084] ​For epitaxial layer 144A, epitaxial layer 144A can include a bottom portion 144A_2 and a top portion 144A_1 above bottom portion 144A_2. In some embodiments, bottom portion 144A_2 can include a rectangular cross-sectional profile, while top portion 144A_1 can include a trapezoidal cross-sectional profile. That is, the width of top portion 144A_1 can decrease upwardly. Bottom portion 144A_2 has a height h dep , where in some embodiments height h dep is in a range from about 3 nm to about 90 nm. Top portion 144A_1 has a height h tra , where in some embodiments height h tra is in a range from about 3 nm to about 20 nm. That is, bottom portion 144A_2 can be thicker than top portion 144A_1. Bottom portion 144A_2 can also include a width W1. A horizontal surface of top portion 144A_1 has a width W2, where in some embodiments width W2 is in a range from about 1 nm to about 30 nm.

[0085] For dielectric structure 136, each dielectric structure 136 can include a triangular cross-sectional profile. Dielectric structure 136 has a height h DE , where in some embodiments height h DE is in a range from about 3 nm to about 20 nm. In some embodiments, height h DE 10 of dielectric structure 136 can be greater than or equal to height h Si of semiconductor layer 102. Dielectric structure 136 has a width W DE , where width W DE , width W2, and width W1 substantially satisfy W1 > W2 and W1 = W2 + 2W DE . Dielectric structure 136 can include an angle θ1 defined by a vertical sidewall of dielectric structure 136 and an inclined sidewall of dielectric structure 136, where 15° ≤ θ1 ≤ 75°. Dielectric structure 136 can include an angle θ2 defined by a vertical sidewall of dielectric structure 136 and a top surface of dielectric structure 136, where 30° ≤ θ2 ≤ 150°.

[0086] Figure 19 is a magnified view of a semiconductor device according to some embodiments of the present disclosure. Figure 19 is similar to Figure 18 , Figure 19 is similar to Figure 18 , except that a top surface of dielectric structure 136 is lower than a horizontal surface of epitaxial layer 144A. Thus, source / drain epitaxial structure 140A can be in contact with and form an interface with the inclined surface of epitaxial layer 144A.

[0087] Figure 20An enlarged view of a semiconductor device according to some embodiments of the disclosure. Figure 20 Unlike Figure 18 , Figure 20 Unlike Figure 18 ,the difference being that the dielectric structure 136 can also include a trapezoidal cross-sectional profile.

[0088] Figure 21 An enlarged view of a semiconductor device according to some embodiments of the disclosure. Figure 21 Unlike Figure 18 , Figure 21 Unlike Figure 18 , the difference being that the top surface of the source / drain epitaxial structure 140A includes a circular profile. In other words, each source / drain epitaxial structure 140A can include a convex top surface. In some embodiments, a portion of the convex top surface of the source / drain epitaxial structure 140A can protrude above the respective dielectric structure 136.

[0089] Figure 22 A cross-sectional view of a semiconductor device according to some embodiments of the disclosure. Figure 22 Unlike Figure 17 , Figure 21 Unlike Figure 18 , the difference being that in Figure 22 , a dielectric structure 137 is present on opposite sides of each epitaxial layer 144B. The material of the dielectric structure 137 is similar to that of the dielectric structure 136. The structural relationship between the dielectric structure 137 and the respective epitaxial layer 144B is similar to that described with respect to the dielectric structure 136 and the respective epitaxial layer 144A. In addition, the dielectric structure 137 and the corresponding epitaxial layer 144B can also include variations similar to those described with respect to Figures 18 to 21 .

[0090] The formation of Figure 22 structures is discussed below. In an etch-back process as discussed below, an etching process can lower the top surface of the epitaxial layer 144B such that each etched epitaxial layer 144B can include a non-planar top surface profile, such as a trapezoidal top surface profile. The dielectric structure 137 can then be formed in a similar manner to the formation of the dielectric structure 136 (see Figure 12 and Figure 7 ). For example, a dielectric layer is deposited on the epitaxial layer 144B, and then an etch-back process is performed on the dielectric layer such that the remaining portion of the dielectric layer is disposed on opposite sides of each epitaxial layer 144B. The remaining portion of the dielectric layer is referred to as the dielectric structure 137. Figure 8

[0091] Due to the etch-back of the epitaxial layers 144B, the source / drain epitaxial structures 140B formed below can be in contact with the three semiconductor layers 102B to obtain a hybrid finFET device. The epitaxial layers 144B exposed by the dielectric structure 137 provide additional nucleation sites for the source / drain epitaxial structures 140B. The dielectric structure 137 can also provide electrical isolation between the source / drain epitaxial structures 140B and the substrate 100, and will prevent current leakage from the source / drain epitaxial structures 140B to the substrate 100. With this configuration, device performance can be improved.

[0092] Figures 23 to 26 Methods of forming semiconductor devices at various stages in accordance with some embodiments of the disclosure are described. In more detail, Figures 23 to 26 Methods of forming backside interconnect structures on Figure 17 structures are described. It should be noted that the processes discussed Figures 23 to 26 can be performed by flipping the structures of Figure 17 by 180 degrees.

[0093] Referring to Figure 23 . A grinding process is performed on the backside of the structure shown in Figure 17 . In more detail, a grinding process is performed on the backside of the substrate 100, thereby reducing the thickness of the substrate 100 until the epitaxial layers 142A and 142B are exposed.

[0094] Referring to Figure 24 . A backside dielectric layer 200 is formed on the backside of the substrate 100 and covers the exposed epitaxial layers 142A and 142B. In some embodiments, the backside dielectric layer 200 can include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0095] Referring to Figure 25 . The backside dielectric layer 200 is then etched, and the epitaxial layers 142A, 144A, 142B, 144B are removed to form openings O3 and O4. In more detail, the epitaxial layers 142A and 144A are removed to form an opening O3 exposing the source / drain epitaxial structure 140A, and the epitaxial layers 142B and 144B are removed to form an opening O4 exposing the source / drain epitaxial structure 140B. In some embodiments, the dielectric structure 136 can be used as an etch stop layer in the etching process, thereby reducing damage to the source / drain epitaxial structure 140A.

[0096] Referring to Figure 26Silicide layers 212A and 212B are formed in openings O3 and O4, respectively, and on exposed surfaces of source / drain epitaxial structures 140A and 140B. Silicide layers 212A and 212B can include similar materials as silicide layers 192A and 192B. Thereafter, backside vias 214A and 214B are formed in openings O3 and O4, respectively, and on silicide layers 212A and 212B, such that backside vias 214A and 214B are electrically connected to respective source / drain epitaxial structures 140A and 140B. Backside vias 214A and 214B can include similar materials as source / drain contacts 194A and 194B. In some embodiments, dielectric structures 136 are disposed on opposite sides of backside vias 214A and 214B.

[0097] Figure 27 A cross-sectional view of a semiconductor device according to some embodiments of the disclosure. Figure 27 A structure resulting from performing processes as described in Figure 22 on a structure as shown in Figures 23 to 26 . That is, as described in Figure 25 , dielectric structures 136 and 137 can be used as etch stop layers when etching backside dielectric layer 200 and epitaxial layers 142B and 144B to reduce damage to source / drain epitaxial structures 140A and 140B.

[0098] From the foregoing embodiments, it will be appreciated that the disclosure offers advantages in fabricating integrated circuits. However, it should be understood that other embodiments can offer additional advantages, and not all advantages need be realized by any particular embodiment. Embodiments of the disclosure provide a hybrid sheet structure. Dielectric structures are formed on opposite ends of an undoped epitaxial cap layer while exposing a top surface of the undoped epitaxial cap layer. The exposed epitaxial cap layer can provide additional nucleation sites for source / drain epitaxial structures, thus enabling formation of source / drain epitaxial structures with void-free structures. Furthermore, the dielectric structures can also provide electrical isolation between the source / drain epitaxial structures and the disabled semiconductor layer, and prevent current leakage from the source / drain epitaxial structures to the disabled semiconductor layer. In addition, the dielectric structures can also serve as etch stop layers when forming backside interconnect structures to prevent damage to the source / drain epitaxial structures. With this configuration, device performance can be improved.

[0099] In some embodiments of the disclosure, a semiconductor device includes a substrate. Semiconductor layers are stacked on the substrate. A gate structure surrounds each semiconductor layer. An epitaxial layer is located above the substrate and in contact with opposite ends of a bottommost semiconductor layer. Source / drain epitaxial structures are located on and in contact with the epitaxial layer, respectively. Dielectric structures are disposed vertically between the epitaxial layer and respective source / drain epitaxial structures, respectively.

[0100] In some embodiments, the epitaxial layers have a trapezoidal top surface profile.

[0101] In some embodiments, the dielectric structures have a triangular cross-sectional profile.

[0102] In some embodiments, a top surface of each epitaxial layer has two sloped portions and a horizontal portion connecting the two sloped portions, and the dielectric structure contacts the two sloped portions.

[0103] In some embodiments, the horizontal portion of the top surface of each epitaxial layer is not covered by the corresponding dielectric structure.

[0104] In some embodiments, a top surface of the dielectric structure is substantially coplanar with the horizontal portion of the top surface of the corresponding epitaxial layer.

[0105] In some embodiments, a top surface of the dielectric structure is lower than the horizontal portion of the top surface of the corresponding epitaxial layer.

[0106] In some embodiments, the epitaxial layers are made of undoped silicon germanium.

[0107] In some embodiments of the disclosure, a semiconductor device includes first and second transistors. The first transistor includes first semiconductor layers, first gate structures surrounding each first semiconductor layer, and first source / drain epitaxial structures on opposite sides of the first gate structures, wherein the first source / drain epitaxial structures are separated from at least one of the first semiconductor layers. The second transistor includes second semiconductor layers, second gate structures surrounding each second semiconductor layer, and second source / drain epitaxial structures on opposite sides of the second gate structures, wherein the second source / drain epitaxial structures are in contact with the second semiconductor layers. First epitaxial layers are respectively under the first source / drain epitaxial structures, wherein a top surface of one of the first epitaxial layers is in contact with a top surface of a corresponding first source / drain epitaxial structure.

[0108] In some embodiments, the semiconductor device further includes first dielectric structures in contact with a top surface of one of the first epitaxial layers and a bottom surface of one of the first source / drain epitaxial structures.

[0109] In some embodiments, the semiconductor device further includes second epitaxial layers respectively under the second source / drain epitaxial structures. Second dielectric structures are in contact with a top surface of one of the second epitaxial layers and a bottom surface of a corresponding second source / drain epitaxial structure.

[0110] In some embodiments, the first and second dielectric structures are at different levels.

[0111] In some embodiments, a top surface of one of the first epitaxial layers has a trapezoidal profile.

[0112] In some embodiments, the top surface of one of the first epitaxial layers has two sloped portions and a horizontal portion connecting the two sloped portions, and the horizontal portion of the top surface of one of the first epitaxial layers is in contact with the corresponding first epitaxial structure.

[0113] In some embodiments, the two sloped portions of the top surface of one of the first epitaxial layers are in contact with the corresponding epitaxial structure of the first epitaxial layer.

[0114] In some embodiments of the disclosure, a method includes forming a first stack of semiconductor layers on a substrate; forming a gate structure on the first stack of semiconductor layers; etching the first stack of semiconductor layers to form a source / drain opening; forming an epitaxial layer at the source / drain opening; forming a dielectric layer covering the epitaxial layer; etching back the dielectric layer until a top surface of the epitaxial layer is exposed; and forming a source / drain epitaxial structure in contact with the top surface of the epitaxial layer at the source / drain opening.

[0115] In some embodiments, after etching back the dielectric layer, a portion of the dielectric layer remains on opposite sides of the epitaxial layer.

[0116] In some embodiments, the step of forming the epitaxial layer is performed such that sidewalls of the bottommost semiconductor layer are covered by the epitaxial layer.

[0117] In some embodiments, the epitaxial layer has a trapezoidal top surface profile.

[0118] In some embodiments, the source / drain epitaxial structure is in contact with a remaining portion of the dielectric layer.

[0119] In some embodiments of the disclosure, a semiconductor device includes a substrate. Semiconductor layers are stacked on the substrate. A gate structure surrounds each of the semiconductor layers. An epitaxial layer is located above the substrate and in contact with opposite ends of the bottommost semiconductor layer. Source / drain epitaxial structures are respectively located on and in contact with the epitaxial layer. Dielectric structures are respectively vertically disposed between the epitaxial layer and the corresponding source / drain epitaxial structure, wherein the dielectric structures have a triangular cross-sectional profile.

[0120] The foregoing overview of features of the various embodiments is presented for purposes of illustration and description. It is readily apparent to those skilled in the art that various alternatives, modifications and variations can be made to the embodiments presented herein without departing from the spirit and scope of the disclosure. It is intended that the disclosure encompass such alternatives, modifications and variations as fall within the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, Include: One substrate; Multiple semiconductor layers are stacked on top of each other on this substrate; A gate structure surrounds each of the plurality of semiconductor layers; Multiple epitaxial layers are located above the substrate and are in contact with the opposite end of the bottommost of the multiple semiconductor layers; Multiple source / drain epitaxial structures are respectively located above and in contact with the multiple epitaxial layers; and Multiple dielectric structures are respectively vertically disposed between the multiple epitaxial layers and the corresponding multiple source / drain epitaxial structures.

2. The semiconductor device as claimed in claim 1, characterized in that, The plurality of epitaxial layers have a trapezoidal top surface profile.

3. The semiconductor device as claimed in claim 1, characterized in that, The plurality of dielectric structures described herein have a triangular cross-sectional profile.

4. The semiconductor device as claimed in claim 1, characterized in that, One of the plurality of epitaxial layers has two inclined portions on its top surface and a horizontal portion connecting the two inclined portions, and the plurality of dielectric structures are in contact with the two inclined portions.

5. The semiconductor device as claimed in claim 4, characterized in that, The horizontal portion of the top surface of one of the plurality of epitaxial layers is not covered by the corresponding plurality of dielectric structures.

6. The semiconductor device as claimed in claim 4, characterized in that, The plurality of top surfaces of the plurality of dielectric structures are substantially coplanar with the horizontal portion of the top surface of the corresponding layer of the plurality of epitaxial layers.

7. The semiconductor device as claimed in claim 4, characterized in that, The plurality of top surfaces of the plurality of dielectric structures are lower than the horizontal portion of the top surface of the corresponding layer of the plurality of epitaxial layers.

8. A semiconductor device, characterized in that, Include: A first transistor, comprising: Multiple first semiconductor layers; A first gate structure surrounding each of the plurality of first semiconductor layers; and A plurality of first source / drain epitaxial structures are located on opposite sides of the first gate structure, wherein the plurality of first source / drain epitaxial structures are separated from at least one of the plurality of first semiconductor layers; A second transistor, comprising: Multiple second semiconductor layers; A second gate structure surrounding each of the plurality of second semiconductor layers; and Multiple second source / drain epitaxial structures are located on opposite sides of the multiple second gate structures, wherein the multiple second source / drain epitaxial structures are in contact with the multiple second semiconductor layers; and Multiple first epitaxial layers are located below the multiple first source / drain epitaxial structures, wherein a top surface of one of the multiple first epitaxial layers is in contact with a corresponding one of the multiple first source / drain epitaxial structures.

9. The semiconductor device as claimed in claim 8, characterized in that, It further includes a first dielectric structure that contacts the top surface of one of the plurality of first epitaxial layers and the bottom surface of a corresponding one of the plurality of first source / drain epitaxial structures.

10. A semiconductor device, characterized in that, Include: One substrate; Multiple semiconductor layers are stacked on top of each other on this substrate; A gate structure surrounds each of the plurality of semiconductor layers; Multiple epitaxial layers are located above the substrate and are in contact with the opposite end of the bottommost of the multiple semiconductor layers; Multiple source / drain epitaxial structures are respectively located above and in contact with the multiple epitaxial layers; and Multiple dielectric structures are respectively vertically disposed between the multiple epitaxial layers and the corresponding multiple source / drain epitaxial structures, wherein the multiple dielectric structures have a triangular cross-sectional profile.

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