Semiconductor structure and semiconductor package
By setting an arc-shaped chamfered metal sheet on the electrode pads of a semiconductor chip and adding a metal protective layer, the problem of bonding wires damaging the electrode pads is solved, improving the reliability of semiconductor packaging and reducing the probability of chip failure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2026-03-20
AI Technical Summary
In the prior art, the reliability of semiconductor packaging is relatively low, mainly because the bonding wires are easily damaged when bonding to the electrode pads on the surface of the semiconductor chip.
A metal sheet is placed on the electrode pads of a semiconductor chip. The metal sheet presents a first planar shape when viewed from above, and at least one corner is an arc-shaped chamfer. The metal sheet is bonded to the bonding wire, and a metal protective layer is placed on it to protect the electrode pads.
It effectively protects the electrode pads from damage during bonding, improves the reliability of semiconductor packaging, reduces the probability of chip failure, and provides additional protection during testing.
Smart Images
Figure CN224022255U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor packaging, and in particular to a semiconductor structure and a semiconductor package. BACKGROUND
[0002] Semiconductor packages are generally used to house and protect semiconductor chips including silicon, silicon carbide (SiC), gallium nitride (GaN), etc. These semiconductor chips can be configured to have various different device types, such as microprocessors, discrete devices, amplifiers, controllers, sensors, etc.
[0003] In the related art, some electrode pads on the surface of a semiconductor chip are electrically connected to a substrate or a terminal by a bonding wire. However, when the bonding wire is bonded to the electrode pads on the surface of the semiconductor chip, the electrode pads on the surface of the semiconductor chip are prone to damage, which results in low reliability of the package. CONTENT OF THE INVENTION
[0004] The present application provides a semiconductor structure and a semiconductor package, which mainly solve the problem of low reliability of the semiconductor package in the prior art.
[0005] To solve the above technical problems, one technical solution adopted by the present application is to provide a semiconductor structure, comprising:
[0006] a semiconductor chip having a top surface and a bottom surface arranged oppositely, the top surface of the semiconductor chip being configured with a first electrode pad;
[0007] a metal sheet arranged on the first electrode pad, the metal sheet having a first planar pattern in a top view, the first planar pattern having a plurality of corners, at least one of the corners being configured as an arc-shaped chamfer.
[0008] Another technical solution adopted by the present application is to provide a semiconductor structure, comprising:
[0009] a semiconductor chip having a top surface and a bottom surface arranged oppositely, the top surface of the semiconductor chip being configured with a first electrode pad;
[0010] a metal sheet arranged on the first electrode pad, an upper surface of the metal sheet away from the first electrode pad being provided with a metal protective layer, the metal protective layer comprising at least one inert metal.
[0011] Another technical solution adopted by the present application is to provide a semiconductor package, comprising a substrate, any one of the semiconductor structures as described above, a terminal, a bonding wire and a package body, the semiconductor chip in the semiconductor structure is arranged on the substrate, the bottom surface of the semiconductor chip is connected with the substrate, the top surface of the semiconductor chip is arranged away from the substrate, one end of the bonding wire is electrically connected with the metal sheet, the other end of the bonding wire is electrically connected with the substrate or the terminal, and the package body encapsulates the semiconductor structure, the bonding wire, at least part of the substrate and part of the terminal.
[0012] Compared with the prior art, the semiconductor structure provided by the present application has the beneficial effects that the metal sheet is arranged on the first electrode pad on the top surface of the semiconductor chip, the bonding wire is bonded with the metal sheet, so that the first electrode pad can be protected from damage during the bonding process, and the protection effect can also be achieved during the packaging test such as reliability test, temperature cycle test, power cycle test and the like, thereby effectively reducing the probability of chip failure and improving the reliability of the semiconductor package. BRIEF DESCRIPTION OF DRAWINGS
[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0014] Figure 1 The structure schematic diagram of the semiconductor structure provided by an embodiment of the present application in the top view;
[0015] Figure 2 The structure schematic diagram of the metal sheet in the semiconductor structure provided by an embodiment of the present application in the top view;
[0016] Figure 3 The sectional view schematic diagram of the metal sheet in the semiconductor structure provided by an embodiment of the present application;
[0017] Figure 4 The sectional view schematic diagram of the metal sheet in the semiconductor structure provided by another embodiment of the present application. DETAILED DESCRIPTION
[0018] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0019] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the application.
[0020] The terms "first", "second", "third", etc. are used herein only to describe different instances, and cannot be construed to refer to a relative importance or a specific number of the technical features indicated. Thus, the features defined with "first", "second", "third" can explicitly or implicitly include at least one of the features. In the description of the application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly and specifically limited. All directional indications (such as upper, lower, left, right, front, back, etc.) in the embodiments of the application are only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the certain posture changes, the directional indications also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product or device.
[0021] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearance of the phrase in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative embodiments to each other. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0022] The application will be described in detail below with reference to the accompanying drawings and embodiments.
[0023] Please refer to Figures 1 to 4 , Figure 1 A schematic structural diagram of a semiconductor structure provided by an embodiment of the application is shown from a top view; Figure 2 A schematic structural diagram of a metal sheet in a semiconductor structure provided by an embodiment of the application is shown from a top view; Figure 3 A schematic cross-sectional view of a metal sheet in a semiconductor structure provided by an embodiment of the application is shown; Figure 4 A schematic cross-sectional view of a metal sheet in a semiconductor structure provided by another embodiment of the application is shown.
[0024] An embodiment of the application provides a semiconductor structure, comprising:
[0025] Semiconductor chip 1 has a top surface 11 and a bottom surface disposed opposite to each other, and a first electrode pad 12 is disposed on the top surface 11 of the semiconductor chip 1.
[0026] A metal sheet 2 is disposed on the first electrode pad 12. The metal sheet 2 has a first planar shape 21 when viewed from above. The first planar shape 21 has a plurality of corners 211, and at least one of the corners 211 is configured as an arc chamfer.
[0027] In this embodiment, the semiconductor chip 1 can be a semiconductor chip made of silicon, silicon carbide (SiC), gallium nitride (GaN), etc., such as an IGBT chip, SBD chip, MOS chip, or HEMT chip. The first electrode pad 12 can be one of a source pad, a gate pad, a gate pad, and a Kelvin source pad. In addition to the first electrode pad 12, the semiconductor chip 1 may also have other electrode pads such as a second electrode pad 13, a third electrode pad 14, and a fourth electrode pad. In one specific embodiment, the first electrode pad 12 can be, for example, a source pad, the second electrode pad 13 can be, for example, a gate pad, the third electrode pad 14 can be, for example, a Kelvin source pad, and the fourth electrode pad can be, for example, a drain pad. The gate pad and the Kelvin source pad can be disposed on the top surface 11 of the semiconductor chip 1, and the drain pad can be disposed on the top surface 11 or the bottom surface of the semiconductor chip 1.
[0028] The metal sheet 2 can be a copper sheet, an aluminum sheet, or another metal sheet. The metal sheet 2 being disposed on the first electrode pad 12 can mean that the metal sheet 2 is connected to the first surface 121 of the first electrode pad 12 that faces away from the bottom surface of the semiconductor chip 1. The metal sheet 2 can be sintered or soldered onto the first electrode pad 12.
[0029] The aforementioned top-down viewpoint refers to the viewpoint observed from the top surface 11 to the bottom surface of the semiconductor chip 1, such as... Figure 1 The diagram shown is a top-view structural schematic of the semiconductor chip 1 and metal sheet 2 in an embodiment of this application. Figure 2 The diagram shown is a top-view structural schematic of the metal sheet 2 in an embodiment of this application. From this top-view perspective, the metal sheet 2 presents a first planar shape 21. The first planar shape 21 can be a planar shape with multiple corners 211, which can be two corners 211, three corners 211, four corners 211, or more. Figure 1 and Figure 2For example, the first planar pattern 21 has four corners 211 (as shown in the schematic diagram). Among the plurality of corners 211 of the first planar pattern 21, only one corner 211 can be configured as an arc-shaped chamfer, or two or more corners 211 can be configured as arc-shaped chamfers, or each corner 211 can be configured as an arc-shaped chamfer, which is not limited in the embodiments of the present application.
[0030] The semiconductor structure provided by the present application sets a metal sheet on the first electrode pad on the top surface of the semiconductor chip, and the metal sheet is bonded with the bonding wire, so as to protect the first electrode pad during the bonding process, and also to protect the chip during the packaging test such as reliability test, temperature cycle, power cycle test and the like, thereby effectively reducing the probability of chip failure and improving the reliability of the semiconductor packaging. In addition, by configuring at least one corner of the first planar pattern in the top view as an arc-shaped chamfer, the stress on the first electrode pad on the chip surface during the bonding and packaging test and the like can be further reduced, the cracking phenomenon on the chip surface can be reduced, the probability of chip failure can be effectively reduced, and the reliability of the semiconductor packaging can be further improved.
[0031] Optionally, the arc-shaped chamfer is a circular arc chamfer.
[0032] Since the circular arc chamfer is more uniform at each position, the arc-shaped chamfer is set as a circular arc chamfer, so as to further reduce stress concentration and reduce fatigue cracks on the chip surface, thereby more effectively reducing the probability of chip failure and further improving the reliability of the semiconductor packaging.
[0033] Optionally, the radius of the circular arc chamfer is greater than or equal to 0.3 mm.
[0034] In the embodiments of the present application, the radius of the circular arc chamfer is greater than or equal to 0.3 mm, for example, the Radius as shown in the Radius can be greater than or equal to 0.3 mm, such as 0.3 mm, 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.6 mm, 0.8 mm or other sizes greater than 0.3 mm. Figure 2
[0035] Setting the radius of the arc-shaped chamfer to 0.3 mm or more can more effectively reduce the stress on the chip surface and the pad during the bonding and testing process, more effectively reduce fatigue cracks on the chip surface, thereby more effectively reducing the probability of chip failure and further improving the reliability of the semiconductor packaging.
[0036] Optionally, each of the corners 211 is configured as an arc-shaped chamfer.
[0037] By configuring each corner as an arc chamfer, stress on the chip surface and pads can be effectively reduced during bonding and testing, fatigue cracks on the chip surface can be effectively reduced, the probability of chip failure can be effectively reduced, and the reliability of semiconductor packaging can be further improved.
[0038] Optionally, the first planar pattern 21 is a rectangle in which the four corners 211 are configured as arc chamfers.
[0039] In the embodiments of the present application, the first planar pattern 21 can be formed by a plurality of edges 212 and a plurality of corners 211. The number of edges 212 can be the same as the number of corners 211. For example, the first planar pattern 21 can be composed of four edges and four corners 211. It should be noted that in other embodiments, the first planar pattern 21 can also be composed of other numbers of edges 212, such as three edges 212, five edges 212, six edges 212, or ten edges 212, and other numbers of corners 211, such as three corners 211, five corners 211, six corners 211, eight corners 211, or ten corners 211. In comparison, the embodiments of the present application are not limited.
[0040] The first planar pattern 21 is a rectangle in which the four corners 211 are configured as arc chamfers. Specifically, the first planar pattern 21 can include a first edge, a second edge, a third edge, a fourth edge, and the plurality of corners 211. The first edge and the third edge are opposite and spaced apart. The second edge and the fourth edge are opposite and spaced apart. The second edge and the fourth edge are between the first edge and the third edge. The number of corners 211 is four. The first edge and the second edge, the second edge and the third edge, the third edge and the fourth edge, and the fourth edge and the first edge are connected by one corner 211, respectively, to form the first planar pattern 211. The first edge and the third edge are parallel. The second edge and the fourth edge are parallel. The first edge and the third edge are perpendicular. The four corners 211 are configured as arc chamfers.
[0041] Since the first planar pattern of the metal sheet in the top view is a rectangle in which the four corners are configured as arc chamfers, the production and processing of the metal sheet can be more convenient and easy, and the manufacturing cost can be further reduced. Moreover, since the four corners are configured as arc chamfers, the stress on the chip surface and pads can be greatly reduced, fatigue cracks on the chip surface can be effectively reduced, the probability of chip failure can be effectively reduced, and the reliability of semiconductor packaging can be further improved.
[0042] Optionally, the metal sheet 2 is a metal foil.
[0043] In the embodiments of the present application, the metal foil can be a copper foil, an aluminum foil or other metal foil.
[0044] The use of the metal foil as the metal sheet is more convenient for process implementation, can better reduce the stress on the chip surface and the pad, and is conducive to reducing the self-weight of the semiconductor structure.
[0045] Optionally, the metal sheet 2 is a copper foil, and the metal sheet 2 is connected to the first electrode pad 12 through a silver-containing sintering layer.
[0046] The use of the copper foil as the metal sheet can make the bonding effect with the bonding wire better, and can better protect the first electrode pad. In addition, the metal sheet is connected to the first electrode pad through the silver-containing sintering layer, which can make the connection reliability and electrical conductivity between the metal sheet and the first electrode pad better.
[0047] Optionally, the first electrode pad 45 is a source pad, the top surface 11 of the semiconductor chip 1 is further provided with a gate pad, and the top surface 11 of the semiconductor chip 1 or the bottom surface of the semiconductor chip 1 is further provided with a drain pad.
[0048] Optionally, the top surface 11 of the semiconductor chip 1 is provided with one first electrode pad 12 or a plurality of first electrode pads 12 arranged apart from each other, and the metal sheet 2 is connected to the first surface 121 of each first electrode pad 12 away from the bottom surface.
[0049] In the embodiments of the present application, the number of the first electrode pad 12 can be one or multiple. When there is only one first electrode pad 12, the metal sheet 2 is connected to the first electrode pad 12. When there are a plurality of first electrode pads 12 arranged apart from each other, the metal sheet 2 is respectively connected to each first electrode pad 12. In this way, the metal sheet 2 covers the plurality of first electrode pads 12 at the same time, which eliminates the cumbersome process of arranging the metal sheet 2 on each first electrode pad 12 one by one, and the process and connection are simpler and more convenient, which can greatly improve the process efficiency.
[0050] Optionally, in the case where the number of the first electrode pad 12 is one, the size of the metal sheet 2 is smaller than the size of the first electrode pad 12, and the orthographic projection of the metal sheet 2 on the top surface 11 is located in the area where the orthographic projection of the first electrode pad 12 on the top surface 11 is located.
[0051] In the case that the number of the first electrode pads 12 is multiple, the top surface 11 of the semiconductor chip 1 has a first region, all the first electrode pads 12 are located in the first region of the top surface 11, the size of the metal sheet 2 is smaller than the sum of the sizes of all the first electrode pads 12, and the orthographic projection of the metal sheet 2 on the top surface 11 is located in the first region of the top surface 11.
[0052] In the embodiments of the present application, since the size of the metal sheet is smaller than the total size of the first electrode pads, the orthographic projection of the metal sheet on the top surface is located in the region where the projection of the first electrode pads on the top surface is located or in the setting region of the first electrode pads on the top surface, so that the metal sheet is not easy to be miscontacted or short-circuited with the remaining components other than the first electrode pads, which can further reduce the risk of electric leakage and improve the reliability of the package.
[0053] Optionally, a metal protective layer 3 containing at least one inert metal is arranged on the upper surface of the metal sheet 2 away from the first electrode pads 12.
[0054] In the embodiments of the present application, the metal protective layer 3 can be a single metal layer or a composite metal layer with anti-oxidation performance. The metal protective layer 3 can include one or more inert metals, which can be gold, silver, platinum, or palladium, etc.
[0055] In this way, by arranging the metal protective layer containing at least one inert metal on the upper surface of the metal sheet away from the first electrode pads, the metal sheet can be further prevented from being oxidized during the packaging process before bonding, so that no additional deoxidization treatment is needed during bonding, thereby further reducing the time length of product process and reducing the packaging cost.
[0056] Optionally, the metal protective layer 3 is a metal plating layer, and the metal protective layer 3 contains at least one of palladium, gold, and silver.
[0057] In the embodiments of the present application, the metal plating layer can be prepared by electroplating, chemical plating, or physical vapor deposition (PVD), etc.
[0058] Since the metal protective layer is a metal plating layer, the combination of the metal protective layer and the metal sheet is more compact, thereby providing better anti-oxidation effect on the metal sheet. In addition, the metal protective layer includes at least one of palladium, gold, and silver, which is convenient for process implementation and can provide better anti-oxidation effect.
[0059] Optionally, the metal sheet 2 is a copper foil, and the metal protective layer 3 includes a plurality of metal sub-layers.
[0060] For example, the metal protective layer 3 includes a first metal sub-layer and a second metal sub-layer, the first metal sub-layer is arranged on the upper surface of the metal sheet 2 away from the first electrode pads 12, and the second metal sub-layer is arranged on the first metal sub-layer. Figure 3As shown, the plurality of metal sub-layers include a nickel layer 31 plated on the upper surface of the metal sheet 2, a palladium layer 32 plated on the surface of the nickel layer 31 away from the first electrode pad 12, and a gold layer 33 plated on the surface of the palladium layer 32 away from the first electrode pad 12; or, as shown, Figure 4 As shown, the plurality of metal sub-layers include a nickel layer 31 plated on the upper surface of the metal sheet 2, and a silver layer 34 plated on the surface of the nickel layer 31 away from the first electrode pad 12.
[0061] In the embodiments of the present application, by plating nickel-palladium-gold (NiPdAu) or nickel-silver (NiAg) on the surface of the metal sheet, the copper foil has better oxidation resistance in the packaging process before bonding, so that no additional deoxidization treatment is needed during bonding, the product processing time is reduced, and the packaging cost is lowered.
[0062] The present application also provides a semiconductor structure, comprising:
[0063] A semiconductor chip 1 having a top surface 11 and a bottom surface arranged oppositely, the top surface 11 of the semiconductor chip 1 being configured with a first electrode pad 12;
[0064] A metal sheet 2 arranged on the first electrode pad 12, the upper surface of the metal sheet 2 away from the first electrode pad 12 being provided with a metal protective layer 3, the metal protective layer 3 comprising at least one inert metal.
[0065] In the embodiments of the present application, the semiconductor chip 1, the metal sheet 2, and the metal protective layer 3 are described above, and thus will not be described here.
[0066] The semiconductor structure provided by the present application has the metal sheet arranged on the first electrode pad on the top surface of the semiconductor chip, and the metal sheet is bonded with the bonding wire, so that the first electrode pad can be protected during bonding, and the chip can also be protected during the packaging test such as reliability test, temperature cycle, power cycle test, etc., thereby effectively reducing the probability of chip failure and improving the reliability of semiconductor packaging. In addition, the inert metal layer is arranged on the upper surface of the metal sheet away from the first electrode pad, so that the metal sheet is less likely to be oxidized during the packaging process before bonding, thereby no additional deoxidization treatment is needed during bonding, so that the product processing time can be further reduced, and the packaging cost can be lowered.
[0067] The embodiment of the present application further provides a semiconductor package, comprising a substrate, any of the semiconductor structures described above, a terminal, a bonding wire and a package, wherein the semiconductor chip 1 in the semiconductor structure is arranged on the substrate, the bottom surface of the semiconductor chip 1 is connected with the substrate, the top surface 11 of the semiconductor chip 1 is arranged away from the substrate, one end of the bonding wire is electrically connected with the metal sheet 2, the other end of the bonding wire is electrically connected with the substrate or the terminal, and the package encapsulates the semiconductor structure, the bonding wire, at least part of the substrate and part of the terminal.
[0068] In the embodiment of the present application, the substrate can be a ceramic copper-attached substrate, such as an active metal brazing ceramic substrate (AMB) or a direct bond copper (DBC), or other types of substrates with circuit design, which are not limited herein.
[0069] The terminal can be a source terminal, a gate terminal or a Kelvin terminal. The bonding wire can be a metal wire, such as a copper wire or an aluminum wire, etc. The one end of the bonding wire electrically connected with the metal sheet 2 can be the one end of the bonding wire electrically connected with the upper surface of the metal sheet 2 away from the bottom surface of the semiconductor chip 1. When the metal protective layer 3 is arranged on the upper surface of the metal sheet, the one end of the bonding wire can be electrically connected with the metal protective layer 3.
[0070] The plastic package can protect the inside of the device from water vapor and mechanical stability. Specifically, the plastic package can comprise an epoxy material. The plastic package encapsulating at least part of the substrate can comprise a case where the plastic package only encapsulates part of the substrate, or a case where the plastic package encapsulates the entire substrate. The plastic package encapsulating part of the terminal can mean that part of the terminal is encapsulated by the plastic package, and the other part is exposed outside the plastic package.
[0071] The semiconductor package provided by the present application can protect the first electrode pad on the top surface of the semiconductor chip during the bonding process by arranging the metal sheet on the first electrode pad and bonding the metal sheet with the bonding wire, and can also protect the chip during the packaging test, such as reliability test, temperature cycle, power cycle test, etc., thereby effectively reducing the probability of chip failure and improving the reliability of the semiconductor package.
[0072] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalent elements of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0073] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A semiconductor structure, characterized in that, include: A semiconductor chip has a top surface and a bottom surface disposed opposite to each other, and the top surface of the semiconductor chip is provided with a first electrode pad; A metal sheet is disposed on the first electrode pad. The metal sheet has a first planar shape when viewed from above. The first planar shape has multiple corners, and at least one of the corners is configured as an arc chamfer.
2. The semiconductor structure according to claim 1, characterized in that, The arc-shaped chamfer is a rounded chamfer, and the radius of the rounded chamfer is greater than or equal to 0.3 mm.
3. The semiconductor structure according to claim 1, characterized in that, Each of the aforementioned corners is configured as a rounded chamfer; And / or, the first planar shape is: a rectangle in which all four corners are configured as rounded chamfers; And / or, the metal sheet is a metal foil; And / or, the metal sheet is a copper foil, and the metal sheet is connected to the first electrode pad through a silver-containing sintered layer; And / or, the first electrode pad is a source pad, the top surface of the semiconductor chip is also provided with a gate pad, and the top surface or the bottom surface of the semiconductor chip is also provided with a drain pad.
4. The semiconductor structure according to claim 1, characterized in that, The top surface of the semiconductor chip is provided with a first electrode pad or a plurality of first electrode pads spaced apart from each other, and the metal sheet is connected to a first surface of each first electrode pad that is away from the bottom surface.
5. The semiconductor structure according to claim 4, characterized in that, When there is only one first electrode pad, the size of the metal sheet is smaller than the size of the first electrode pad, and the orthographic projection of the metal sheet on the top surface is located in the area where the orthographic projection of the first electrode pad on the top surface is located. When there are multiple first electrode pads, the top surface of the semiconductor chip has a first region, all of the first electrode pads are located in the first region of the top surface, the size of the metal sheet is smaller than the sum of the sizes of all the first electrode pads, and the orthographic projection of the metal sheet on the top surface is located in the first region of the top surface.
6. The semiconductor structure according to claim 1, characterized in that, A metal protective layer is provided on the upper surface of the metal sheet away from the first electrode pad.
7. The semiconductor structure according to claim 6, characterized in that, The metal protective layer is a metal plating layer, and the metal protective layer is an inert metal.
8. The semiconductor structure according to claim 7, characterized in that, The metal sheet is copper foil, and the metal protective layer includes multiple metal sublayers; The plurality of metal sublayers include a nickel layer plated on the upper surface of the metal sheet, a palladium layer plated on the surface of the nickel layer away from the first electrode pad, and a gold layer plated on the surface of the palladium layer away from the first electrode pad; or, the plurality of metal sublayers include a nickel layer plated on the upper surface of the metal sheet and a silver layer plated on the surface of the nickel layer away from the first electrode pad.
9. A semiconductor structure, characterized in that, include: A semiconductor chip has a top surface and a bottom surface disposed opposite to each other, and the top surface of the semiconductor chip is provided with a first electrode pad; A metal sheet is disposed on the first electrode pad, and a metal protective layer is disposed on the upper surface of the metal sheet away from the first electrode pad. The metal protective layer is an inert metal.
10. A semiconductor package, characterized in that, The device includes a substrate, a semiconductor structure as described in any one of claims 1-9, terminals, bonding wires, and a package. The semiconductor chip in the semiconductor structure is disposed on the substrate, the bottom surface of the semiconductor chip is connected to the substrate, and the top surface of the semiconductor chip is disposed away from the substrate. One end of the bonding wire is electrically connected to the metal sheet, and the other end of the bonding wire is electrically connected to the substrate or the terminal. The package encapsulates the semiconductor structure, the bonding wire, at least a portion of the substrate, and a portion of the terminal.