Hardware mutual exclusion switching circuit
By designing a hardware mutual exclusion switching circuit, and utilizing NPN and PNP transistor circuits and switching circuits, mutual exclusion switching of power supply or signal source is achieved, solving the problems of power supply conflict and system instability, and ensuring circuit safety and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2026-03-24
AI Technical Summary
The lack of mutually exclusive switching circuits in existing technologies may lead to power conflicts, short circuits, system instability, and safety hazards when switching between multiple power or signal sources.
A hardware mutual exclusion switching circuit is adopted, which uses NPN and PNP transistor circuit design, combined with switching circuit and bypass NPN transistor circuit, to achieve mutual exclusion switching of the circuit and avoid multiple power supplies or signal sources from supplying power at the same time.
It effectively avoids power conflicts and short circuit risks, ensures stable system operation, reduces safety hazards, and lowers processor resource consumption.
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Figure CN224037341U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of electronic circuits, and particularly relates to a hardware mutual exclusion switching circuit. BACKGROUND
[0002] In some application scenarios, the power input end or the signal input end may be connected with multiple power sources or signal sources respectively. Taking the power input end of a load as an example, when two power sources supply power to the load at the same time, if the voltage or current characteristics of the two power sources do not match, a conflict between the power sources may occur, and even a short circuit may be caused. This not only damages the power sources and the load, but also may cause serious impact on the entire circuit system.
[0003] The switching circuit lacking of mutual exclusion may cause the system to frequently switch between different power sources or signal sources, thereby causing instability of the system. Such instability may manifest as system restart, data loss or device failure and the like. In the power system, if two power sources supply power to the same load at the same time, it may cause safety problems such as excessive current, overheating or fire.
[0004] In the prior art, the connection switching between the power input end and different power sources can be realized through a relay or a triode. These switching schemes lack of relevant protection circuits in the design, which may cause circuit safety defects such as power source conflict, short circuit, system instability and safety hazards. Practical new type content
[0005] Therefore, the present disclosure provides a hardware mutual exclusion switching circuit to solve the technical problem of circuit safety defects in the switching process of multiple power sources or signal sources in the prior art.
[0006] To achieve the above object, the technical scheme adopted by the present disclosure is as follows:
[0007] The embodiment of the present disclosure provides a hardware mutual switching circuit, which comprises: a first input branch comprising a first branch NPN transistor circuit, a first branch PNP transistor circuit and a first switch circuit, the base of the first branch NPN transistor circuit being connected with a first input control signal, the collector of the first branch NPN transistor circuit being connected with the base of the first branch PNP transistor circuit, the collector of the first branch PNP transistor circuit being connected with the control end of the first switch circuit, the input end and the output end of the first switch circuit being connected with a first input signal and a first output signal respectively; a second input branch comprising a second branch NPN transistor circuit, a second branch PNP transistor circuit and a second switch circuit, the base of the second branch NPN transistor circuit being connected with a second input control signal, the collector of the second branch NPN transistor circuit being connected with the base of the second branch PNP transistor circuit, the collector of the second branch PNP transistor circuit being connected with the control end of the second switch circuit, the input end and the output end of the second switch circuit being connected with a second input signal and a second output signal respectively, the collector of the first branch PNP transistor circuit and the base of the second branch NPN transistor circuit being connected with a first bypass NPN transistor circuit, the base and the collector of the first bypass NPN transistor circuit being connected with the collector of the first branch PNP transistor circuit and the base of the second branch NPN transistor circuit respectively.
[0008] In some embodiments, the hardware mutual switching circuit further comprises a third input branch comprising a third branch NPN transistor circuit, a third branch PNP transistor circuit and a third switch circuit, the base of the third branch NPN transistor circuit being connected with a third input control signal, the collector of the third branch NPN transistor circuit being connected with the base of the third branch PNP transistor circuit, the collector of the third branch PNP transistor circuit being connected with the control end of the third switch circuit, the input end and the output end of the third switch circuit being connected with a third input signal and a third output signal respectively; the collector of the second branch PNP transistor circuit and the base of the third branch NPN transistor circuit being connected with a second bypass NPN transistor circuit, the base and the collector of the second bypass NPN transistor circuit being connected with the collector of the second branch PNP transistor circuit and the base of the third branch NPN transistor circuit respectively; the collector of the first branch PNP transistor circuit and the base of the third branch NPN transistor circuit being connected with a third bypass NPN transistor circuit, the base and the collector of the third bypass NPN transistor circuit being connected with the collector of the first branch PNP transistor circuit and the base of the third branch NPN transistor circuit respectively.
[0009] In some embodiments, the PNP triode circuit comprises a PNP triode, a PNP current-limiting resistor connected between the base of the PNP triode and the control signal input terminal, and a PNP cutoff resistor connected between the base and the emitter of the PNP triode, wherein the PNP triode circuit comprises a first branch PNP triode circuit, a second branch PNP triode circuit, or a third branch PNP triode circuit; the NPN triode circuit comprises an NPN triode, an NPN current-limiting resistor connected between the base of the NPN triode and the upper-level signal input terminal, and an NPN cutoff resistor connected between the base and the emitter of the NPN triode, wherein the NPN triode circuit comprises a first branch NPN triode circuit, a second branch NPN triode circuit, a third branch NPN triode circuit, a first bypass NPN triode circuit, a second bypass NPN triode circuit, or a third bypass NPN triode circuit.
[0010] In some embodiments, the switch circuit comprises a relay circuit, the relay circuit comprises a relay and a first diode, the relay comprises a first control terminal, a second control terminal, a signal input terminal, and a signal output terminal, the negative electrode of the first diode is connected to the first control terminal of the relay, the positive electrode of the first diode is connected to the second control terminal of the relay, the signal input terminal is connected to the input signal, and the signal output terminal is connected to the output signal, wherein the switch circuit comprises a first switch circuit, a second switch circuit, or a third switch circuit.
[0011] In some embodiments, the switch circuit comprises a semiconductor switch and a second diode connected between the gate of the semiconductor switch and the output terminal of the first switch circuit, the gate of the semiconductor switch is connected to the collector of the first branch PNP triode circuit, the signal input terminal of the semiconductor switch is connected to the input signal, and the signal output terminal of the semiconductor switch is connected to the output signal, wherein the switch circuit comprises a first switch circuit, a second switch circuit, or a third switch circuit.
[0012] In some embodiments, the emitter of the PNP triode is connected to a power supply.
[0013] In some embodiments, the emitter of the NPN triode is grounded.
[0014] In some embodiments, the semiconductor switch comprises an insulated gate bipolar transistor (IGBT), the signal input terminal of the semiconductor switch is the collector of the IGBT, and the signal output terminal of the semiconductor switch is the emitter of the IGBT.
[0015] In some embodiments, the semiconductor switch comprises an N-type metal-oxide-semiconductor field-effect transistor (MOS), the signal input terminal of the semiconductor switch is the drain of the MOS, and the signal output terminal of the semiconductor switch is the source of the MOS.
[0016] In some embodiments, the second diode comprises a zener diode.
[0017] The beneficial effects of the embodiments of the present disclosure compared with the prior art are: the first input branch controls the on-off of the first switch circuit, the second input branch controls the on-off of the second switch circuit, and the first bypass NPN transistor circuit connects the first input branch and the second input branch, so as to turn on the first input branch and inhibit the second input branch from being turned on when the first input branch and the second input branch input power or electrical signals at the same time, thereby ensuring the safety of the circuit during the switching process of the mutual exclusion circuit. BRIEF DESCRIPTION OF DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.
[0019] Figure 1 is a circuit diagram of a hardware mutual exclusion switching circuit provided by the embodiments of the present disclosure;
[0020] Figure 2 is a circuit diagram of another hardware mutual exclusion switching circuit provided by the embodiments of the present disclosure;
[0021] Figure 3 is a circuit diagram of still another hardware mutual exclusion switching circuit provided by the embodiments of the present disclosure. DETAILED DESCRIPTION
[0022] The embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure can be implemented in many different forms and should not be construed as being limited to the embodiments specifically set forth herein; rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the concept of the embodiments to those skilled in the art, so that the present disclosure can be implemented by those skilled in the art. In the drawings, the same reference numerals indicate the same elements, and thus their descriptions will be omitted.
[0023] It should be understood that when an element is referred to as being connected to or being connected with another element, the element can be directly connected to the other element, or there can be an intervening element between them. In contrast, when an element is referred to as being directly connected to another element, there is no intervening element between them.
[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments of the present disclosure belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
[0025] The term "…er" used in the embodiments can be a software component or a hardware component configured to perform a specific function. The hardware component can include a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC). The software component can refer to data used by an executable code and / or data stored in an addressable storage medium and used by an executable code. Thus, the software component can be, for example, an object-oriented software component, a class component, and a work component, and can include a process, a function, an attribute, a procedure, a subroutine, a program code segment, a driver, firmware, microcode, a circuit, data, a database, a data structure, a table, an array, or a variable.
[0026] The phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. It should be appreciated that the terms "comprising," "including," "containing," and "having," etc., when used in this specification, indicate the presence of the stated features, numbers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or groups thereof.
[0027] The hardware mutual switching circuit according to the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
[0028] Figure 1 is a circuit diagram of a hardware mutual switching circuit provided by the embodiments of the present disclosure; Figure 2 is a circuit diagram of another hardware mutual switching circuit provided by the embodiments of the present disclosure; Figure 3 is a circuit diagram of still another hardware mutual switching circuit provided by the embodiments of the present disclosure. The hardware mutual switching circuit provided by the embodiments of the present disclosure will be described below in conjunction with Figures 1 to 3
[0029] As shown in Figure 1 , the hardware mutual switching circuit provided by the embodiments of the present disclosure includes:
[0030] The first input branch comprises a first branch NPN transistor circuit, a first branch PNP transistor circuit and a first switch circuit, a base of a transistor Q8 in the first branch NPN transistor circuit is connected with a first input control signal MCU LSD3, a collector of the transistor Q8 in the first branch NPN transistor circuit is connected with a base of a transistor Q9 in the first branch PNP transistor circuit, a collector of the transistor Q9 in the first branch PNP transistor circuit is connected with a control end LSD3 of the first switch circuit, and an input end and an output end of the first switch circuit are connected with a first input signal IN DRV3 and a first output signal OUT DRV3 respectively.
[0031] The second input branch comprises a second branch NPN transistor circuit, a second branch PNP transistor circuit and a second switch circuit, a base of a transistor Q5 in the second branch NPN transistor circuit is connected with a second input control signal MCU LSD2, a collector of the transistor Q5 in the second branch NPN transistor circuit is connected with a base of a transistor Q6 in the second branch PNP transistor circuit, a collector of the transistor Q6 in the second branch PNP transistor circuit is connected with a control end LSD2 of the second switch circuit, an input end and an output end of the second switch circuit are connected with a second input signal IN DRV2 and a second output signal OUT DRV2 respectively, and a collector of the transistor Q8 in the first branch PNP transistor circuit and the base of the transistor Q6 in the second branch NPN transistor circuit are connected with a first bypass NPN transistor circuit.
[0032] In the embodiment of the present disclosure, the first switch circuit and the second switch circuit both use a relay as a switching device. According to the technical scheme in the embodiment of the present disclosure, when only the first input control signal MCU LSD3 is low, the transistor Q8 is turned on, the transistor Q9 is also driven to be turned on, and then the coil of the relay B3 is attracted, and the IN DRV3 signal is output as the OUT DRV3; when only the second input control signal MCU LSD2 is low, the transistor Q5 is turned on, the transistor Q6 is also driven to be turned on, and then the coil of the relay B2 is attracted, and the IN DRV2 signal is output as the OUT DRV2; when the first input control signal MCU LSD3 and the second input control signal MCU LSD2 are both low, the transistor Q8 is turned on, the transistor Q7 is also driven to be turned on, so that the Q6 is not turned on, and the relay B2 cannot be attracted, and since the Q9 is turned on, the coil of the relay B3 is normally attracted, and the IN DRV3 signal is output as the OUT DRV3, so that the mutual exclusion between the B2 and the B3 is achieved.
[0033] The hardware mutual exclusion circuit in the technical solution of this disclosure can avoid power conflict and short circuit risks, avoid system instability risks, reduce safety hazards, reduce processor resource occupation, and prevent multiple relays from closing at the same time from a hardware logic perspective, thus ensuring the safe and stable operation of the circuit.
[0034] like Figure 3 As shown, in one embodiment of this disclosure, the hardware mutual exclusion circuit may further include a third input branch, which includes a third branch NPN transistor circuit, a third branch PNP transistor circuit, and a third switch circuit. The third switch circuit uses a relay as the switching device. The base of transistor Q1 in the third branch NPN transistor circuit is connected to a third input control signal, the collector of transistor Q1 in the third branch NPN transistor circuit is connected to the base of transistor Q2 in the third branch PNP transistor circuit, the collector of transistor Q1 in the third branch PNP transistor circuit is connected to the control terminal LSD1 of the third switch circuit, and the input and output terminals of the third switch circuit are respectively connected to the third input signal IN_DRV1 and the third output signal OUT_DRV1. A second bypass NPN transistor is connected between the collector of transistor Q5 in the second branch PNP transistor circuit and the base of transistor Q2 in the third branch NPN transistor circuit. In the transistor circuit, the base and collector of transistor Q4 in the second bypass NPN transistor circuit are connected to the collector of transistor Q5 in the second branch PNP transistor circuit and the base of transistor Q2 in the third branch NPN transistor circuit, respectively. A third bypass NPN transistor circuit is connected between the collector of transistor Q8 in the first branch PNP transistor circuit and the base of transistor Q2 in the third branch NPN transistor circuit. The base and collector of transistor Q3 in the third bypass NPN transistor circuit are connected to the collector of transistor Q8 in the first branch PNP transistor circuit and the base of transistor Q2 in the third branch NPN transistor circuit, respectively.
[0035] like Figure 3 The three input control signals of the hardware mutual exclusion switching circuit shown are mutually exclusive, comprising three branches. Specifically:
[0036] When the MCU controls the MCU_LSD1 signal to be in a low level state, Q1 is turned on, drive Q2 is also turned on, the coil of relay B1 is energized, and the IN_DRV1 signal is output as OUT_DRV1.
[0037] When the MCU controls the MCU_LSD2 signal to be in a low level state, Q5 is turned on, and the drive Q6 is also turned on, the coil of relay B2 is energized, and the IN_DRV2 signal is output as OUT_DRV2.
[0038] When MCU controls MCU_LSD3 signal to be low, Q8 is on, Q9 is on, the coil of relay B3 is attracted, IN_DRV3 signal is output as OUT_DRV3.
[0039] When MCU_LSD1 and MCU_LSD2 are both low, Q1, Q4, Q5, Q6 are on, but Q2 is not on because Q4 is on and Q2 base is low, relay B1 is not attracted, the coil of relay B2 is normally attracted because Q6 is on, IN_DRV2 signal is output as OUT_DRV2, and the mutual exclusion between B1 and B2 is achieved.
[0040] When MCU_LSD2 and MCU_LSD3 are both low, Q5, Q7, Q8, Q9 are on, but Q6 is not on because Q7 is on and Q6 base is low, relay B2 is not attracted, the coil of relay B3 is normally attracted because Q9 is on, IN_DRV3 signal is output as OUT_DRV3, and the mutual exclusion between B2 and B3 is achieved.
[0041] When MCU_LSD1 and MCU_LSD3 are both low, Q1, Q3, Q7, Q8, Q9 are on, but Q2 is not on because Q3 is on and Q2 base is low, relay B1 is not attracted, the coil of relay B3 is normally attracted because Q9 is on, IN_DRV3 signal is output as OUT_DRV3, and the mutual exclusion between B1 and B3 is achieved.
[0042] When MCU_LSD1, MCU_LSD2, MCU_LSD3 are all low, Q1, Q3, Q5, Q7, Q8, Q9 are on, but Q2 is not on because Q3 is on and Q2 base is low, relay B1 is not attracted, Q6 is not on because Q7 is on and Q6 base is low, relay B2 is not attracted, the coil of relay B3 is normally attracted because Q9 is on, IN_DRV3 signal is output as OUT_DRV3, and the mutual exclusion between B1, B2 and B3 is achieved.
[0043] As Figure 1 and Figure 2As shown in FIG. 1, the first branch PNP transistor circuit, the second branch PNP transistor circuit and the third branch PNP transistor circuit can be collectively referred to as a PNP transistor circuit. Taking the first branch PNP transistor circuit as an example, the PNP transistor circuit comprises a PNP transistor, i.e., a transistor Q8, a PNP current-limiting resistor, i.e., a resistor R16, connected between the base of the transistor Q8 and a control signal input end, and a PNP cut-off resistor, i.e., a resistor R15, connected between the base and the emitter of the transistor Q8. Among them, the PNP current-limiting resistor mainly plays a current-limiting role to reduce the power consumption of the transistor, and the PNP cut-off resistor can make the transistor reliably cut off. In the embodiment of the present disclosure, the emitter of the PNP transistor is connected to a power supply, and when the PNP transistor is turned on, the collector of the PNP transistor outputs a high level.
[0044] As shown in FIG. 1, Figure 1 and Figure 2 the first branch NPN transistor circuit, the second branch NPN transistor circuit, the third branch NPN transistor circuit, the first bypass NPN transistor circuit, the second bypass NPN transistor circuit and the third bypass NPN transistor circuit can be collectively referred to as an NPN transistor circuit. Taking the first branch PNP transistor circuit as an example, the NPN transistor circuit comprises an NPN transistor, i.e., a transistor Q9, an NPN current-limiting resistor, i.e., a resistor R17, connected between the base of the transistor Q9 and an upper signal input end, and an NPN cut-off resistor, i.e., a resistor R18, connected between the base and the emitter of the transistor Q9. Among them, the NPN current-limiting resistor mainly plays a current-limiting role to reduce the power consumption of the transistor, and the NPN cut-off resistor can make the transistor reliably cut off. In the embodiment of the present disclosure, the emitter of the NPN transistor is connected to a power supply, and when the NPN transistor is turned on, the collector of the NPN transistor outputs a low level.
[0045] The first switch circuit, the second switch circuit and the third switch circuit can be collectively referred to as a switch circuit. As shown in FIG. 1, Figure 1 and Figure 2 the switch circuit can be a relay circuit, and the relay circuit comprises a relay and a first diode, the relay comprises a first control end, a second control end, a signal input end and a signal output end, the negative electrode of the first diode is connected to the first control end of the relay, the positive electrode of the first diode is connected to the second control end of the relay, the signal input end is connected to an input signal, and the signal output end is connected to an output signal, wherein the switch circuit comprises the first switch circuit, the second switch circuit or the third switch circuit.
[0046] Taking the first switch circuit as an example, the diode D1 is the first diode, which can provide a reverse current, provide a discharge path for the current in the inductive coil of the relay when the transistor is turned off from on, and clamp the voltage to +12V.
[0047] AsFigure 3 As shown, the switch circuit includes a semiconductor switch and a second diode connected between the gate of the semiconductor switch and the output of the first switch circuit, the collector of the first branch PNP transistor circuit is connected to the gate of the semiconductor switch, the signal input of the semiconductor switch is connected to the input signal, and the signal output of the semiconductor switch is connected to the output signal. Taking the first switch circuit as an example, the diode D6 is the second diode. The second diode can be a voltage stabilizing diode.
[0048] In the embodiments of the present disclosure, the semiconductor switch can be an IGBT (Insulate-Gate Bipolar Transistor) or an N-type MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor), and is not limited thereto.
[0049] When the semiconductor switch is an IGBT, the signal input of the semiconductor switch is the collector of the IGBT, and the signal output of the semiconductor switch is the emitter of the IGBT.
[0050] When the semiconductor switch includes an N-type MOS tube, the signal input of the semiconductor switch is the drain of the MOS tube, and the signal output of the semiconductor switch is the source of the MOS tube.
[0051] According to the hardware mutual exclusion switching circuit provided by the embodiments of the present disclosure, the first switch circuit is controlled to be turned on or turned off through the first input branch, the second switch circuit is controlled to be turned on or turned off through the second input branch, and the first input branch and the second input branch are connected through the first bypass NPN transistor circuit, so that when the first input branch and the second input branch simultaneously input a power supply or an electrical signal, the first input branch is turned on and the second input branch is inhibited from being turned on, so as to ensure the safety of the circuit during the switching process of the mutual exclusion circuit.
[0052] The above only describes the preferred embodiments of the present disclosure and should not be used to limit the present disclosure. Any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A hardware mutual exclusion switching circuit, characterized by, The hardware mutual exclusion switching circuit comprises: a first input branch comprising a first branch NPN transistor circuit, a first branch PNP transistor circuit and a first switch circuit, a base of the first branch NPN transistor circuit being connected to a first input control signal, a collector of the first branch NPN transistor circuit being connected to a base of the first branch PNP transistor circuit, a collector of the first branch PNP transistor circuit being connected to a control end of the first switch circuit, an input end and an output end of the first switch circuit being connected to a first input signal and a first output signal respectively; a second input branch comprising a second branch NPN transistor circuit, a second branch PNP transistor circuit and a second switch circuit, a base of the second branch NPN transistor circuit being connected to a second input control signal, a collector of the second branch NPN transistor circuit being connected to a base of the second branch PNP transistor circuit, a collector of the second branch PNP transistor circuit being connected to a control end of the second switch circuit, an input end and an output end of the second switch circuit being connected to a second input signal and a second output signal respectively, a first bypass NPN transistor circuit being connected between the collector of the first branch PNP transistor circuit and the base of the second branch NPN transistor circuit, a base and a collector of the first bypass NPN transistor circuit being connected to the collector of the first branch PNP transistor circuit and the base of the second branch NPN transistor circuit respectively.
2. The hardware mutual-exclusion toggle circuit of claim 1, wherein, The hardware mutual exclusion switching circuit comprises: a third input branch comprising a third branch NPN transistor circuit, a third branch PNP transistor circuit and a third switch circuit, a base of the third branch NPN transistor circuit being connected to a third input control signal, a collector of the third branch NPN transistor circuit being connected to a base of the third branch PNP transistor circuit, a collector of the third branch PNP transistor circuit being connected to a control end of the third switch circuit, an input end and an output end of the third switch circuit being connected to a third input signal and a third output signal respectively; a second bypass NPN transistor circuit being connected between the collector of the second branch PNP transistor circuit and the base of the third branch NPN transistor circuit, a base and a collector of the second bypass NPN transistor circuit being connected to the collector of the second branch PNP transistor circuit and the base of the third branch NPN transistor circuit respectively; a third bypass NPN transistor circuit being connected between the collector of the first branch PNP transistor circuit and the base of the third branch NPN transistor circuit, a base and a collector of the third bypass NPN transistor circuit being connected to the collector of the first branch PNP transistor circuit and the base of the third branch NPN transistor circuit respectively.
3. The hardware mutual-exclusion handoff circuit of claim 1 or 2, wherein, The PNP triode circuit comprises a PNP triode, a PNP current-limiting resistor connected between the base of the PNP triode and a control signal input end, and a PNP cut-off resistor connected between the base and the emitter of the PNP triode, wherein the PNP triode circuit comprises a first branch PNP triode circuit, a second branch PNP triode circuit, or a third branch PNP triode circuit. The NPN triode circuit comprises an NPN triode, an NPN current-limiting resistor connected between the base of the NPN triode and a higher-level signal input end, and an NPN cut-off resistor connected between the base and the emitter of the NPN triode, wherein the NPN triode circuit comprises a first branch NPN triode circuit, a second branch NPN triode circuit, a third branch NPN triode circuit, a first bypass NPN triode circuit, a second bypass NPN triode circuit, or a third bypass NPN triode circuit.
4. The hardware mutual-exclusion toggle circuit of claim 1, wherein, The switch circuit comprises a relay circuit, and the relay circuit comprises a relay and a first diode, the relay comprises a first control end, a second control end, a signal input end, and a signal output end, the negative electrode of the first diode is connected with the first control end of the relay, the positive electrode of the first diode is connected with the second control end of the relay, the signal input end is connected with an input signal, and the signal output end is connected with an output signal, wherein the switch circuit comprises a first switch circuit, a second switch circuit, or a third switch circuit.
5. The hardware mutual-exclusion toggle circuit of claim 1, wherein, The switch circuit comprises a semiconductor switch and a second diode connected between the gate of the semiconductor switch and the output end of the first switch circuit, the gate of the semiconductor switch is connected with the collector of the first branch PNP triode circuit, the signal input end of the semiconductor switch is connected with an input signal, and the signal output end of the semiconductor switch is connected with an output signal, wherein the switch circuit comprises a first switch circuit, a second switch circuit, or a third switch circuit.
6. The hardware mutual-exclusion toggle circuit of claim 3, wherein, The emitter of the PNP triode is connected with a power supply.
7. The hardware mutual-exclusion toggle circuit of claim 3, wherein, The emitter of the NPN triode is grounded.
8. The hardware mutual-exclusion toggle circuit of claim 5, wherein, The semiconductor switch comprises an insulated gate bipolar transistor (IGBT), the signal input end of the semiconductor switch is the collector of the IGBT, and the signal output end of the semiconductor switch is the emitter of the IGBT.
9. The hardware mutual-exclusion toggle circuit of claim 5, wherein, The semiconductor switch comprises an N-type metal oxide semiconductor field effect transistor (MOS), the signal input end of the semiconductor switch is the drain of the MOS, and the signal output end of the semiconductor switch is the source of the MOS.
10. The hardware mutual-exclusion toggle circuit of claim 5, wherein, The second diode comprises a voltage stabilizing diode.