RAM multiplexing circuit and chip

Abstract

The embodiment of the utility model discloses an RAM multiplexing circuit and a chip, and relates to the field of integrated circuits. According to the RAM multiplexing circuit technology, efficient multiplexing of memory resources is realized through an integrated switching circuit and a dynamic connection mechanism. According to the technical scheme, the memory utilization rate is remarkably improved, especially when the function module runs in a non-full-load mode, the CPU can dynamically access and reuse the idle RAM, and the data processing speed is increased. Besides, the flexibility and the expandability of the system are enhanced, the CPU is allowed to flexibly access different RAM resources according to needs, and convenience is provided for future upgrading and function expansion.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of integrated circuit, especially to a RAM multiplexing circuit and chip. BACKGROUND

[0002] In current integrated circuit design, a chip usually contains a central processing unit (CPU) and multiple functional modules, which work together to realize complex system functions. Referring to the chip structure diagram shown in Figure 1 In order to improve data processing efficiency and reduce access delay, the CPU and each functional module are usually configured with fixed random access memory (RAM). The CPU uses a dedicated system-specific RAM to store and execute programs and data required for its operation, while each functional module uses its own module RAM to store and process data related to the module function.

[0003] However, this fixed allocation of RAM configuration has the problem of low memory resource utilization. First of all, due to the significant differences in workload and data processing requirements of different functional modules over time, some functional modules may not work at all during certain periods, but their allocated RAM resources remain occupied, resulting in waste of memory resources. Secondly, as the system function continues to increase and become more complex, the demand for memory resources is also increasing, and the fixed RAM allocation method may not meet this dynamic demand, thereby limiting the improvement of system performance.

[0004] In addition, the fixed RAM configuration may also cause memory access conflicts and bottlenecks. When multiple functional modules need to access their respective RAMs at the same time, memory access conflicts may occur, resulting in increased data access delay and affecting the overall performance of the system. At the same time, due to the independent memory access between the CPU and the functional modules, there is a lack of effective memory sharing and cooperation mechanism, which also limits the efficient use of system resources. SUMMARY

[0005] The present application provides a RAM multiplexing circuit and chip, which can solve the problem of low memory resource utilization of the chip. The technical solution is as follows:

[0006] In the first aspect, the present application provides a RAM multiplexing circuit, comprising:

[0007] CPU, functional module 1~functional module n, switch circuit, system-specific RAM, module RAM 1~module RAM n, n is an integer greater than 1;

[0008] The CPU is connected to port A0 of the switch circuit, functional module 1 is connected to port A1 of the switch circuit, and functional module n is connected to port An of the switch circuit.

[0009] Port B0 of the switch circuit is connected to the system-specific RAM, port B1 of the switch circuit is connected to module RAM1, and port Bn of the switch circuit is connected to module RAMn.

[0010] The control end of the switch circuit is connected to the control end of functional module 1 to functional module n.

[0011] Port A0 is connected to port B0, port A1 is connected to port B1, and port An is connected to port Bn.

[0012] The switch circuit receives a working state indication signal of any one of the functional modules i through the control end. When it is determined that functional module i is in a non-working state according to the received working state indication signal, the control end controls port A0 and port Bi to be connected, so as to realize the purpose that the CPU uses the system-specific RAM and RAMi simultaneously. When it is determined that functional module i is in a working state according to the received working state indication signal, the control end controls port A0 and port Bi to be disconnected; i = 1, 2, …, n.

[0013] In a second aspect, the present application provides a chip comprising the RAM multiplexing circuit.

[0014] The technical solutions provided by some embodiments of the present application have at least the following beneficial effects:

[0015] This scheme allows the CPU to dynamically access and multiplex the RAM resources of the functional modules when they are not working. This greatly improves the overall utilization of memory, especially when there are multiple functional modules in the system and they are not always running at full load.

[0016] By reducing memory access conflicts and waiting time, this scheme optimizes the data transmission path, thereby improving the overall performance of the system. The CPU can more efficiently utilize available memory resources, thereby speeding up data processing.

[0017] The dynamic connection feature of the switch circuit enables the CPU to flexibly access different RAM resources as needed. This flexibility not only improves the scalability of the system, but also provides convenience for future system upgrades and functional expansion.

[0018] When the functional modules are not working, their RAM resources can be multiplexed by the CPU, thereby reducing the energy consumption caused by idle memory. This is particularly important for embedded systems that pursue low power consumption and high performance.

[0019] By integrating the switch circuit and the dynamic connection mechanism, the complexity of system design is simplified. Designers do not need to design memory access logic for each functional module, but can rely on the switch circuit to automatically manage the allocation and reuse of memory resources.

[0020] The dynamic connection mechanism of the switch circuit helps to avoid data conflicts and memory access errors, thereby improving the stability and reliability of the system. When the functional module is working, its RAM resource is exclusively accessed, ensuring the integrity and consistency of the data. BRIEF DESCRIPTION OF DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0022] Figure 1 is a structural diagram of a chip in the prior art;

[0023] Figure 2 is a structural diagram of a RAM reuse circuit provided by the embodiments of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0025] Please refer to Figure 2 The present application provides a structural diagram of a RAM reuse circuit.

[0026] In Figure 2 , the RAM reuse circuit of the embodiments of the present application comprises: a CPU, functional modules 1 to n, a switch circuit, system-specific RAM, and module RAMs 1 to n, where n is an integer greater than 1.

[0027] The CPU is a central processing unit, responsible for executing program instructions, processing data, and controlling the operation of the entire system.

[0028] The functional modules 1 to n perform specific system functions or data processing tasks. Each functional module has a control end for sending a working state indication signal to the switch circuit.

[0029] The switch circuit has a plurality of ports (A0-An and B0-Bn) and one or more control terminals. The port A0 is connected to the CPU, and the ports A1-An are connected to the functional module 1, the functional module n, respectively. The port B0 is connected to the system special RAM, and the ports B1-Bn are connected to the module RAM1, the module RAMn, respectively. The switch circuit dynamically controls the connection or disconnection between the port A0 and the port Bi (i=1, 2, …, n) according to the received functional module working state indication signal.

[0030] The system special RAM provides a special storage space for the CPU, and is used for storing the operating system, the application program code, the global variable and the like. The module RAM1-module RAMn provide a special storage space for the respective functional module, and are used for storing the temporary variable and the intermediate result required by the functional module for processing data.

[0031] In the embodiment of the application, the connection relationship of each module in the RAM multiplexing circuit includes that the CPU is connected to the port A0 of the switch circuit, the functional module 1 is connected to the port A1 of the switch circuit, …, and the functional module n is connected to the port An of the switch circuit.

[0032] The port B0 of the switch circuit is connected to the system special RAM, the port B1 of the switch circuit is connected to the module RAM1, …, and the port Bn of the switch circuit is connected to the module RAMn.

[0033] The control terminals of the switch circuit are connected to the control terminals of the functional module 1-functional module n, respectively.

[0034] The port A0 is connected to the port B0, the port A1 is connected to the port B1, …, and the port An is connected to the port Bn. In the initial state, the port A0 is connected to the port B0, allowing the CPU to access the system special RAM. The port A1 is connected to the port B1, the port A2 is connected to the port B2, …, and the port An is connected to the port Bn, allowing the functional module to access the corresponding module RAM.

[0035] The working principle of the RAM multiplexing circuit in the embodiment of the application includes that the switch circuit receives the working state indication signal of any one of the functional modules i through the control terminal, determines that the functional module i is in the non-working state according to the received working state indication signal, controls the connection between the port A0 and the port Bi to achieve the purpose that the CPU simultaneously uses the system special RAM and the RAMi, and determines that the functional module i is in the working state according to the received working state indication signal, and controls the disconnection between the port A0 and the port Bi; i=1, 2, …, n.

[0036] Each functional module sends a working status indication signal to the switch circuit through its control terminal. The signal can be a simple binary signal indicating whether the functional module is in working status. The control terminal of the switch circuit receives the working status indication signal from the functional module. When the functional module i is in non-working status, the switch circuit connects port A0 and port Bi. In this way, the CPU can access both the system dedicated RAM and the module RAM i, realizing the reuse of RAM resources. When the functional module i is in working status, the switch circuit disconnects port A0 and port Bi. This ensures that the functional module can exclusively access its RAM resources when it is working, avoiding data conflicts.

[0037] In some embodiments of the present application, the switch circuit continuously monitors the working status indication signal from the functional module. When the working status indication signal of the functional module i is low (i.e. the functional module i is in non-working status), the switch circuit connects the data bus, clock bus and address bus of CPU port A0 to the corresponding buses of module RAM i port Bi, allowing the CPU to access both the system dedicated RAM and the module RAM i. When the working status indication signal of the functional module i is high (i.e. the functional module i is in working status), the switch circuit disconnects CPU port A0 and module RAM i port Bi, ensuring that the functional module can exclusively access its RAM resources while maintaining the CPU's access to the system dedicated RAM.

[0038] The switch circuit of the embodiments of the present application mainly consists of a multiplexer, a control logic circuit and a switch element.

[0039] The multiplexer is used to select the connection path of the input or output according to the control signal. In the present scheme, the multiplexer has multiple input terminals (connected to the functional modules) and multiple output terminals (connected to the RAMs).

[0040] The control logic circuit is responsible for receiving the working status indication signal from the functional module and determining the selection path of the multiplexer according to these signals. It specifically includes logic gate circuits, flip-flops and the like, which are used to realize complex logic control functions.

[0041] The switch element (such as a transistor, a relay, etc.) is used to actually establish or disconnect the circuit connection. In the present scheme, the switch element can be used to control the connection between the CPU and the RAMs.

[0042] In some embodiments of the present application, each port of port A0 to port An and port B0 to port Bn includes a data bus, an address bus and a clock bus.

[0043] The data bus is used to transmit data between the CPU, functional modules, and RAM. The data bus width determines the number of data bits that can be transmitted at a time and is a key factor in determining the speed of data transmission.

[0044] The clock bus provides a synchronous clock signal to ensure that data transmission and operations between the CPU, functional modules, and RAM are synchronized. The clock frequency determines the operating speed of the system.

[0045] The address bus is used to specify the RAM address that the CPU or functional module wants to access. The address bus width determines the addressable memory range.

[0046] The RAM multiplexing circuit in this application achieves efficient multiplexing and optimized allocation of RAM resources by introducing a port design that includes data bus, clock bus, and address bus, as well as a dynamic connection mechanism, providing strong support for improving system performance and memory utilization.

[0047] The embodiments of the present application have the following technical effects:

[0048] This scheme allows the CPU to dynamically access and multiplex the RAM resources of the functional modules when they are not working. This greatly improves the overall utilization of memory, especially in the case of multiple functional modules in the system and they are not always running at full load.

[0049] By reducing memory access conflicts and waiting time, this scheme optimizes the data transmission path, thereby improving the overall performance of the system. The CPU can more efficiently utilize available memory resources, thereby speeding up data processing.

[0050] The dynamic connection feature of the switch circuit allows the CPU to flexibly access different RAM resources as needed. This flexibility not only improves the scalability of the system, but also provides convenience for future system upgrades and functional expansions.

[0051] When the functional modules are not working, their RAM resources can be multiplexed by the CPU, thereby reducing the energy consumption caused by idle memory. This is particularly important for embedded systems that pursue low power consumption and high performance.

[0052] By integrating the switch circuit and the dynamic connection mechanism, this scheme simplifies the complexity of system design. Designers do not need to design memory access logic for each functional module separately, but can rely on the switch circuit to automatically manage the allocation and multiplexing of memory resources.

[0053] The dynamic connection mechanism of the switch circuit helps to avoid data conflicts and memory access errors, thereby improving the stability and reliability of the system. When the functional modules are working, their RAM resources are exclusively accessed, ensuring the integrity and consistency of the data.

[0054] The chip provided by the embodiment of the present application is provided with the RAM multiplexing circuit, and the chip in the present application includes but is not limited to: a processor chip, a microcontroller, an application specific integrated circuit chip and a field programmable gate array lamp, and the processor chip is, for example, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP) and the like. These chips usually contain a large number of functional modules for performing various complex computing and processing tasks. Through implementation of the above technical solutions, flexible configuration of the pins of these chips can be realized, thereby meeting different application requirements.

[0055] The above-described embodiments do not constitute a limitation on the protection scope of the technical solutions. Any modifications, equivalent replacements, improvements and the like made within the spirit and principles of the above-described embodiments shall be included in the protection scope of the technical solutions.

Claims

1. A RAM multiplexing circuit, characterized by, The application relates to a RAM multiplexing circuit. The CPU is connected with port A0 of the switch circuit, function module 1 is connected with port A1 of the switch circuit, function module n is connected with port An of the switch circuit, port B0 of the switch circuit is connected with the system special RAM, port B1 of the switch circuit is connected with module RAM1, port Bn of the switch circuit is connected with module RAMn, the control end of the switch circuit is connected with the control end of function module 1-function module n, port A0 is connected with port B0, port A1 is connected with port B1, port An is connected with port Bn, the switch circuit receives the working state indication signal of any function module i through the control end, the control end controls the connection between port A0 and port Bi when function module i is in the non-working state according to the received working state indication signal, so as to realize the purpose that the CPU uses the system special RAM and RAMi at the same time, the control end disconnects port A0 and port Bi when function module i is in the working state according to the received working state indication signal, i=1, 2,..., n, the working state indication signal is a high-level signal, function module i is in the working state, the working state indication signal is a low-level signal, function module i is in the non-working state, the switch circuit comprises a multiplexer, a control logic circuit and a switch element. Each port comprises a data bus, a clock bus and an address bus. The application further relates to a RAM multiplexing circuit comprising the RAM multiplexing circuit of claim 1 or 2. ​ ​ ​ ​ 2. The RAM multiplexing circuit of claim 1, wherein, ​ 3. A chip, characterized by ​

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