Impulse current suppression circuit and power supply

Abstract

The utility model relates to the technical field of power supplies, and discloses an impact current suppression circuit and a power supply, the impact current suppression circuit comprises an anti-reverse circuit, a suppression circuit and a control circuit, after the power supply is powered on, the control circuit controls the anti-reverse circuit and the suppression circuit to be opened, at the moment, because the impedance of the suppression circuit is large, the peak value of the impact current is effectively reduced, and the impact current is suppressed. As the impedance of the suppression circuit is reduced slowly, the energy of the impact current enters the system slowly, so that the safety lower than the front end is ensured, the situation that the impact current triggers the safety by mistake is avoided, and the stability of the system is improved.

Description

TECHNICAL FIELD

[0001] The utility model relates to power supply technical field, concretely relates to a kind of impact current suppression circuit and power supply. BACKGROUND

[0002] With the increasing requirement of the reliability of automobile controller, more and more customers pay attention to the size of the impact current of the controller, especially the front end has the design of fuse, and the impact current of the hardware power supply of the controller cannot trigger the external controller, and the anti-reverse circuit is set in the current hardware design circuit, the anti-reverse circuit is mainly composed of NMOS, and the NMOS is opened after the power-on of the system, and the power circuit is powered. NMOS has a parasitic diode due to its process, so it cannot suppress the impact current when the power is turned on, so the control of the single anti-reverse MOS during the power-on of the hardware system cannot affect the impact current, and the size of the impact current depends on the overall impedance of the back-end load of the power supply, so in the case of excessive capacitive load and small resistance, the impact current will exceed the rated value of the fuse in the power supply circuit, causing the fuse to be triggered. The reliability of the system is affected, and the function of the vehicle is seriously affected, and the fault is reported. SUMMARY

[0003] Therefore, the utility model provides an impact current suppression circuit and power supply to solve the problem of how to suppress the impact current of the power supply.

[0004] In the first aspect, the utility model provides an impact current suppression circuit, which comprises: an anti-reverse circuit, a suppression circuit and a control circuit, wherein the first end of the anti-reverse circuit is connected with the first output end of the power supply, the second end of the anti-reverse circuit is connected with the second output end of the power supply and the second power supply end of the load, the third end of the anti-reverse circuit is connected with the second end of the control circuit, and the fourth end of the anti-reverse circuit is connected with the first end of the suppression circuit; the second end of the suppression circuit is connected with the first power supply end of the load, and the third end of the suppression circuit is connected with the second end of the control circuit; the first end of the control circuit is connected with the first output end of the power supply, and the power supply end of the control circuit is connected with the first output end of the power supply.

[0005] After the power-on of the utility model, the control circuit controls the opening of the anti-reverse circuit and the suppression circuit, at this time, the peak value of the impact current is effectively reduced due to the large impedance of the suppression circuit, and the energy of the impact current slowly enters the system as the impedance of the suppression circuit slowly decreases, so that the fuse in the front end can be lower than the fuse, and the situation of the impact current triggering the fuse is avoided, and the stability of the system is improved.

[0006] In an alternative embodiment, the anti-inversion circuit comprises a first NMOS transistor, a first resistor, a first diode and a first controllable switch, wherein the source of the first NMOS transistor is connected to the first output terminal of the power supply, the drain of the first NMOS transistor is connected to the first terminal of the suppression circuit, the gate of the first NMOS transistor is connected to the first terminal of the first resistor; the first terminal of the first controllable switch is connected to the gate of the first NMOS transistor and the second terminal of the control module, the first terminal of the first controllable switch is connected to the anode of the first diode, the control terminal of the first controllable switch is connected to the second output terminal of the power supply and the second power supply terminal of the load; the cathode of the first diode and the second terminal of the first resistor are both connected to the first output terminal of the power supply.

[0007] In an alternative embodiment, the suppression circuit comprises a second NMOS transistor, a second resistor, a third resistor, a first capacitor and a second capacitor, wherein the drain of the second NMOS transistor is connected to the drain of the first NMOS transistor, the source of the second NMOS transistor is connected to the first power supply terminal of the load, the gate of the second NMOS transistor is connected to the first terminal of the second resistor, the first terminal of the first capacitor and the first terminal of the second capacitor; the second terminal of the second resistor is connected to the first power supply terminal of the load; the second terminal of the first capacitor is connected to the drain of the first NMOS transistor; the first terminal of the second capacitor is connected to the second terminal of the control module through the third resistor, and the second terminal of the second capacitor is connected to the first power supply terminal of the load.

[0008] In an alternative embodiment, the control circuit comprises an MCU chip and its peripheral circuit, wherein the peripheral circuit and the internal charge pump of the MCU chip constitute a boost circuit.

[0009] In an alternative embodiment, the inrush current suppression circuit further comprises a power conversion circuit, wherein the power supply terminal of the control circuit is connected to the first output terminal of the power supply through the power conversion circuit.

[0010] In an alternative embodiment, the power conversion circuit comprises a third capacitor, a fourth capacitor, a fifth capacitor and a voltage stabilizing chip, wherein the first terminal of the voltage stabilizing chip is connected to the first output terminal of the power supply and the first terminal of the third capacitor, the second terminal of the voltage stabilizing chip is connected to the second terminal of the third capacitor and then grounded, and the third terminal of the voltage stabilizing chip is connected to the power supply terminal of the control circuit; the first terminal of the fourth capacitor is connected to the first terminal of the fifth capacitor and then to the power supply terminal of the control circuit, and the second terminal of the fourth capacitor is connected to the second terminal of the fifth capacitor and then grounded.

[0011] In an alternative embodiment, the inrush current suppression circuit further comprises a filter circuit, wherein the first terminal of the filter circuit is connected to the second terminal of the suppression circuit, the second terminal of the filter circuit is connected to the first power supply terminal of the load, and the third terminal of the filter circuit is connected to the second output terminal of the power supply.

[0012] In an alternative embodiment, the filter circuit comprises a sixth capacitor, a seventh capacitor and a first inductor, wherein a first end of the first inductor is connected to the second end of the suppression circuit and a first end of the sixth capacitor, a second end of the first inductor is connected to a first power supply end of the load and a first end of the seventh capacitor; a second end of the sixth capacitor and a second end of the seventh capacitor are connected to a second output end of the power supply and a second power supply end of the load.

[0013] In an alternative embodiment, the inrush current suppression circuit further comprises a switching circuit and a protection circuit, wherein a first end of the switching circuit is connected to the first output end of the power supply, a second end of the switching circuit is connected to a first end of the protection circuit; a second end of the protection circuit is connected to a power supply end of the control circuit and a first end of the anti-reverse circuit.

[0014] In a second aspect, the utility model provides a power supply, comprising: the inrush current suppression circuit and the power supply of the first aspect and any alternative embodiment thereof. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the specific embodiments of the utility model or the technical solutions in the prior art, the drawings needed to be used in the specific embodiments or the prior art description will be briefly introduced below, and obviously, the drawings in the following description are some embodiments of the utility model, and those skilled in the art can also obtain other drawings according to these drawings without creating creative labor.

[0016] Figure 1 It is the component diagram of the inrush current suppression circuit according to the utility model embodiment;

[0017] Figure 2 It is the specific circuit structure diagram of the inrush current suppression circuit according to the utility model embodiment;

[0018] Figure 3 It is the component diagram of another inrush current suppression circuit according to the utility model embodiment;

[0019] Figure 4 It is the component diagram of still another inrush current suppression circuit according to the utility model embodiment;

[0020] Figure 5 It is the component diagram of still another inrush current suppression circuit according to the utility model embodiment. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0022] In the description of this utility model, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0023] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0024] Furthermore, the technical features involved in the different embodiments of this utility model described below can be combined with each other as long as they do not conflict with each other.

[0025] This embodiment provides an inrush current suppression circuit, such as Figure 1 As shown, it includes: anti-reverse circuit 1, suppression circuit 2, and control circuit 3.

[0026] like Figure 1 As shown, the first terminal of the reverse protection circuit 1 is connected to the first output terminal of the power supply 4; the second terminal of the reverse protection circuit 1 is connected to the second output terminal of the power supply 4 and the second power supply terminal of the load; the third terminal of the reverse protection circuit 1 is connected to the second terminal of the control circuit 3; and the fourth terminal of the reverse protection circuit 1 is connected to the first terminal of the suppression circuit 2. The second terminal of the suppression circuit 2 is connected to the first power supply terminal of the load; the third terminal of the suppression circuit 2 is connected to the second terminal of the control circuit 3; the first terminal of the control circuit 3 is connected to the first output terminal of the power supply 4; and the power supply terminal of the control circuit 3 is connected to the first output terminal of the power supply 4.

[0027] Specifically, the anti-reverse circuit 1 has a built-in unidirectional conductive component to prevent current from flowing back to the power supply 4. The suppression circuit 2 also has a built-in unidirectional conductive component, but the connection methods of the unidirectional conductive components in the anti-reverse circuit 1 and the suppression circuit 2 are reversed.

[0028] Specifically, taking the unidirectional conduction component composed of an NMOS and a body diode in anti-parallel as an example, during the initial stage of starting of the power supply 4, the transient power-on of the power supply 4 will charge the capacitive load at the rear end, generating an inrush current. The NMOS in the anti-reverse circuit 1 has a parasitic body diode due to its process, and therefore cannot suppress the inrush current when the power supply 4 is turned on. Therefore, the control circuit 3 needs to control the NMOS in the suppression circuit 2 to be turned on, so that the resistance of the NMOS gradually decreases as the NMOS in the circuit is turned on, so that the inrush current energy slowly enters the system.

[0029] It should be noted that the control of the NMOS by the control circuit 3 is a mature control method in the related art, for example, PWM control, etc.

[0030] In some optional embodiments, as shown in Figure 2 The anti-reverse circuit 1 includes a first NMOS Q1, a first resistor R1, a first diode D1, and a first controllable switch S1.

[0031] As shown in Figure 2 The source of the first NMOS Q1 is connected to the first output end of the power supply 4, the drain of the first NMOS Q1 is connected to the first end of the suppression circuit 2 (i.e. the drain of the second NMOS Q2), and the gate of the first NMOS Q1 is connected to the first end of the first resistor R1. The first end of the first controllable switch S1 is connected to the gate of the first NMOS Q1 and the second end of the control module, and the first end of the first controllable switch S1 is connected to the anode of the first diode D1. The control end of the first controllable switch S1 is connected to the second output end of the power supply 4 and the second power supply end of the load Rd. The cathode of the first diode D1 and the second end of the first resistor R1 are both connected to the first output end of the power supply 4.

[0032] Specifically, Figure 2 As an equivalent circuit diagram, the control end of the first controllable switch S1 and the source of the first NMOS Q1 are not directly connected to the power supply 4, but are connected to the power supply 4 through a line impedance. However, in an ideal case, they can be directly connected to the power supply 4.

[0033] In some optional embodiments, as shown in Figure 2As shown, the suppression circuit 2 comprises a second NMOS tube Q2, a second resistor R2, a third resistor R3, a first capacitor C1 and a second capacitor C2, wherein the drain of the second NMOS tube Q2 is connected with the drain of the first NMOS tube Q1, the source of the second NMOS tube Q2 is connected with the first power supply end of the load Rd, the gate of the second NMOS tube Q2 is connected with the first end of the second resistor R2, the first end of the first capacitor C1 and the first end of the second capacitor C2; the second end of the second resistor R2 is connected with the first power supply end of the load Rd; the second end of the first capacitor C1 is connected with the drain of the first NMOS tube Q1; the first end of the second capacitor C2 is connected with the second end of the control module through the third resistor R3, and the second end of the second capacitor C2 is connected with the first power supply end of the load Rd.

[0034] Specifically, Figure 2 The source of the second NMOS tube Q2 in the suppression circuit 2 is not directly connected with the first power supply end of the load Rd, but is connected with the first power supply end of the load Rd through the filter circuit and the line impedance. In fact, the source of the second NMOS tube Q2 can be directly connected with the first power supply end of the load Rd.

[0035] Specifically, Figure 2 In the suppression circuit, after the power supply 4 is powered on, the first NMOS tube Q1 and the second NMOS tube Q2 are controlled by the control module. After the control module boosts the voltage to drive the first NMOS tube Q1 and the second NMOS tube Q2 to be turned on, the first controllable switch S1 is turned on. Since the first NMOS tube Q1 and the second NMOS tube Q2 are reversely connected, and since the body diode of the first NMOS tube Q1 exists, the first NMOS tube Q1 cannot suppress the impact current, but the second NMOS tube Q2 can suppress the impact current.

[0036] In some optional embodiments, the control circuit 3 comprises an MCU chip and a peripheral circuit thereof, wherein the peripheral circuit and an internal charge pump of the MCU chip constitute a boost circuit.

[0037] Specifically, referring to Figure 2 , the control circuit 3 comprises an MCU chip U1, capacitors C12-C14, the MCU chip U1 is built-in with a charge pump, the capacitors C12-C14 and the internal charge pump circuit of the MCU chip U1 constitute a boost circuit to provide an opening voltage for the opening of the second NMOS tube Q2 and the first controllable switch S1.

[0038] In some optional embodiments, as Figure 3 shown, the impact current suppression circuit further comprises a power conversion circuit 5, wherein the power supply end of the control circuit 3 is connected with the first output end of the power supply 4 through the power conversion circuit 5.

[0039] Specifically, the power conversion circuit 5 can realize the change of the voltage level of the direct current voltage, for example, a DC-DC circuit, which is not limited to a BUCK circuit, a BOOST voltage, a BUCK-BOOST circuit, and the like, without limitation.

[0040] In some optional embodiments, as shown in Figure 2 The power conversion circuit 5 includes a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, and a voltage stabilizing chip LDO. The first end of the voltage stabilizing chip LDO is connected with the first output end of the power supply 4 and the first end of the third capacitor C3. The second end of the voltage stabilizing chip LDO is connected with the second end of the third capacitor C3 and then grounded. The third end of the voltage stabilizing chip LDO is connected with the power supply end of the control circuit 3. The first end of the fourth capacitor C4 is connected with the first end of the fifth capacitor C5 and then connected with the power supply end of the control circuit 3. The second end of the fourth capacitor C4 is connected with the second end of the fifth capacitor C5 and then grounded.

[0041] In some optional embodiments, as shown in Figure 4 The impact current suppression circuit further includes a filter circuit 6. The first end of the filter circuit 6 is connected with the second end of the suppression circuit 2. The second end of the filter circuit 6 is connected with the first power supply end of the load Rd. The third end of the filter circuit 6 is connected with the second output end of the power supply 4.

[0042] Specifically, the filter circuit 6 can suppress the ripple generated by the NMOS tube and the first controllable switch S1 when turned on and turned off, so as to output a pure power supply voltage to the load Rd.

[0043] In some optional embodiments, as shown in Figure 2 The filter circuit 6 includes a sixth capacitor C6, a seventh capacitor C7, and a first inductor L1. The first end of the first inductor L1 is connected with the second end of the suppression circuit 2 and the first end of the sixth capacitor C6. The second end of the first inductor L1 is connected with the first power supply end of the load Rd and the first end of the seventh capacitor C7. The second end of the sixth capacitor C6 and the second end of the seventh capacitor C7 are both connected with the second output end of the power supply 4 and the second power supply end of the load Rd.

[0044] Specifically, Figure 2 The filter circuit 6 in the filter circuit 6 is connected with the load Rd and the suppression circuit 2 through the line impedance, and in actual application, the filter circuit 6 can be directly connected with the load Rd and the suppression circuit 2.

[0045] Specifically, Figure 2 The filter circuit 6 in the filter circuit 6 is a Π-type filter circuit, which can improve the EMC performance, but can also be other structures of filter circuits, for example, LC filter circuit, RLC filter circuit, and the like, without limitation.

[0046] In some alternative implementations, such as Figure 5 As shown, the surge current suppression circuit also includes a switching circuit 7 and a protection circuit 8. The first end of the switching circuit 7 is connected to the first output end of the power supply 4, and the second end of the switching circuit 7 is connected to the first end of the protection circuit 8. The second end of the protection circuit 8 is connected to the power supply end of the control circuit 3 and the first end of the anti-reverse circuit 1.

[0047] Specifically, Figure 2 In this circuit, power supply 4 consists of battery V1 and internal resistance R10. Switching circuit 7 mainly includes second controllable switch S2. After the second controllable switch is closed, power supply 4 outputs voltage. Protection circuit 8 mainly consists of fuse and its internal resistance R4. When the current is too large, the fuse trips. Resistors R5-R6, inductors L2-L3, and capacitor C8 represent the resistance, inductance, and capacitance parameters of the wiring harness. Resistor R7, inductor L4, and capacitor C9 represent the parasitic parameters of the wiring harness connector to the first NMOS transistor Q1. Resistor R8, inductor L5, and capacitor C10 constitute the parasitic parameters of resistance, inductance, and capacitance from the second NMOS transistor to the filter circuit 6. Resistor R9, inductor L6, and capacitors C11-C12 represent the resistance, inductance, and capacitance parameters from the filter circuit 6 to the load Rd.

[0048] Specifically, Figure 2When the second controllable switch S2 is closed, the instantaneous power-on of the power supply 4 charges the capacitive load Rd of the rear end, generating an impact current. Due to the body diode of the first NMOS tube Q1, even if the first NMOS tube Q1 is not conducting, the rear end is charged through the body diode, so that the impact current change of the traditional circuit only depends on the size of the impedance on the line of the capacitive load Rd of the rear end. The first controllable switch S1 uses the charge pump of the MCU chip U1 to open, and now the second NMOS tube Q2 is added. The connection of the drain and the source of the second NMOS tube Q2 is opposite to that of the first NMOS tube Q1. The second NMOS tube Q2 is also driven by the MCU-controlled charge pump, and C1, C2, R2 and R3 are added to form the suppression circuit 2. Capacitors C13-C15 and the internal integrated charge pump circuit of the MCU chip U1 form a boost circuit to provide an opening voltage for the opening of the first NOS tube and the second NMOS tube Q2. Even when the current of the power supply 4 is impacted, the body diode of the first NOS tube is opened, at this time the second NMOS tube Q2 has not started, and the body diode of the second NMOS tube Q2 is in a cut-off state, so that the impedance is very large, and the peak value of the impact current is effectively reduced and suppressed. With the opening of the second NMOS tube Q2, the resistance of the second NMOS tube Q2 slowly decreases, so that the impact current energy slowly enters the system and starts to work normally. By adjusting R2, R3 and C1, the opening time of the second NMOS tube Q2 can be adjusted, so as to adjust the peak value of the impact current of the power supply 4 and ensure that it is lower than the front-end fuse, avoiding the situation that the impact current triggers the fuse by mistake, and improving the stability of the system.

[0049] In the embodiment, a power supply is provided, which comprises the impact current suppression circuit and the power supply 4 of the above embodiments and any optional implementation manner thereof.

[0050] Specifically, the composition diagram and the specific structure diagram of the impact current suppression circuit are as shown in Figures 1-5 The specific principle is described in detail in the above embodiment, and will not be repeated here.

[0051] Although the embodiments of the utility model are described in combination with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the utility model, and such modifications and changes all fall within the scope defined by the appended claims.

Claims

1. An inrush current suppression circuit, characterized by, The application relates to an anti-reverse circuit, a suppression circuit and a control circuit. The first end of the anti-reverse circuit is connected with the first output end of a power supply, the second end of the anti-reverse circuit is connected with the second output end of the power supply and the second power supply end of a load, the third end of the anti-reverse circuit is connected with the second end of the control circuit, and the fourth end of the anti-reverse circuit is connected with the first end of the suppression circuit. The second end of the suppression circuit is connected with the first power supply end of the load, and the third end of the suppression circuit is connected with the second end of the control circuit. The first end of the control circuit is connected with the first output end of the power supply, and the power supply end of the control circuit is connected with the first output end of the power supply. The anti-reverse circuit comprises a first NMOS tube, a first resistor, a first diode and a first controllable switch.

2. The inrush current suppression circuit of claim 1, wherein The source of the first NMOS tube is connected with the first output end of the power supply, the drain of the first NMOS tube is connected with the first end of the suppression circuit, and the gate of the first NMOS tube is connected with the first end of the first resistor. The first end of the first controllable switch is connected with the gate of the first NMOS tube and the second end of a control module, the first end of the first controllable switch is connected with the anode of the first diode, and the control end of the first controllable switch is connected with the second output end of the power supply and the second power supply end of the load. The cathode of the first diode and the second end of the first resistor are both connected with the first output end of the power supply. The suppression circuit comprises a second NMOS tube, a second resistor, a third resistor, a first capacitor and a second capacitor.

3. The inrush current suppression circuit of claim 2, wherein The drain of the second NMOS tube is connected with the drain of the first NMOS tube, the source of the second NMOS tube is connected with the first power supply end of the load, and the gate of the second NMOS tube is connected with the first end of the second resistor, the first end of the first capacitor and the first end of the second capacitor. The second end of the second resistor is connected with the first power supply end of the load. The second end of the first capacitor is connected with the drain of the first NMOS tube. The first end of the second capacitor is connected with the second end of the control module through the third resistor, and the second end of the second capacitor is connected with the first power supply end of the load. The control circuit comprises an MCU chip and a peripheral circuit thereof.

4. The inrush current suppression circuit of claim 1, wherein The peripheral circuit and the internal charge pump of the MCU chip constitute a voltage boosting circuit. The application further comprises a power conversion circuit.

5. The inrush current suppression circuit of claim 1, wherein The power conversion circuit comprises a third capacitor, a fourth capacitor, a fifth capacitor and a voltage stabilizing chip. The first end of the voltage stabilizing chip is connected with the first output end of the power supply and the first end of the third capacitor, the second end of the voltage stabilizing chip is connected with the second end of the third capacitor and then grounded, and the third end of the voltage stabilizing chip is connected with the power supply end of the control circuit.

6. The inrush current suppression circuit of claim 5, wherein, The first end of the fourth capacitor is connected with the first end of the fifth capacitor and then connected with the power supply end of the control circuit, and the second end of the fourth capacitor is connected with the second end of the fifth capacitor and then grounded. The application further comprises ​ 7. The inrush current suppression circuit of claim 1, wherein ​ The filter circuit is connected between the second end of the suppression circuit and the first power supply end of the load. The filter circuit comprises a sixth capacitor, a seventh capacitor and a first inductor, wherein, 8. The inrush current suppression circuit of claim 7, wherein, The first end of the first inductor is connected to the second end of the suppression circuit and the first end of the sixth capacitor, and the second end of the first inductor is connected to the first power supply end of the load and the first end of the seventh capacitor. The second end of the sixth capacitor and the second end of the seventh capacitor are both connected to the second output end of the power supply and the second power supply end of the load. Further comprising:

9. The inrush current suppression circuit of claim 1, wherein, A switch circuit and a protection circuit, wherein, The first end of the switch circuit is connected to the first output end of the power supply, and the second end of the switch circuit is connected to the first end of the protection circuit. The second end of the protection circuit is connected to the power supply end of the control circuit and the first end of the anti-reverse circuit. The impact current suppression circuit and the power supply of any one of claims 1-9.

10. A power supply, comprising: ​ ​

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