Interface circuit based on eNTP client synchronization technology

Abstract

The technical scheme of the utility model discloses an interface circuit based on an eNTP client synchronization technology, which is characterized by comprising a CPU (Central Processing Unit) processing module, an FPGA (Field Programmable Gate Array) processing module and an eNTP network interface unit. The utility model provides a timed device based on an eNTP client synchronization technology, which performs high-precision network time synchronization through a network time synchronization NTP technology. According to the utility model, the function of the NTP protocol stack is completed on the FPGA hardware level, Ethernet unpacking and packing are completed through the FPGA processing module, hardware time scale writing is carried out, accurate hardware time scales are provided, and a good foundation is provided for further network time delay calculation and time deviation calculation.

Description

TECHNICAL FIELD

[0001] The utility model relates to an interface circuit based on eNTP client synchronization technology belongs to communication technical field. BACKGROUND

[0002] The client synchronization technology based on eNTP is a network time service technology based on Ethernet NTP, and through the mode of hardware time stamp in NTP Ethernet package, the NTP protocol package has accurate time stamp, and after synchronization with the time server using the same hardware NTP technology, high time accuracy can be achieved. Compared with PTP protocol, NTP protocol is simpler and more efficient, and NTP is easier to implement. eNTP (enhanced NTP) uses the hardware time stamp mode based on NTP and uses the time accuracy optimization algorithm of eNTP, and after practical application, good time accuracy can be provided, most use cases can be met, and the application market will be more extensive. The use of eNTP technology can save network traffic, and eNTP technology can achieve high accuracy with little network bandwidth. The use of eNTP technology can be implemented without large-scale network modification, saving the user's capital investment. CONTENT OF THE UTILITY MODEL

[0003] The utility model aims at: realizing eNTP client synchronization technology, obtaining high time synchronization accuracy, providing a low-bandwidth and easy-to-implement time service synchronization technology without increasing network investment.

[0004] In order to achieve the above object, the technical scheme of the utility model discloses an interface circuit based on eNTP client synchronization technology, characterized by comprising a CPU processing module, an FPGA processing module and an eNTP network interface unit, wherein the CPU processing module is connected with the FPGA processing module through an address data bus, a clock signal input end of the FPGA processing module is connected with a clock signal output end of the CPU processing module, an interrupt signal output end of the FPGA processing module is connected with an interrupt signal input end of the CPU processing module, a transceiving clock output end of the FPGA processing module is connected with a transceiving clock input end of the eNTP network interface unit, a data output end of the FPGA processing module is connected with a receiving data line of the eNTP network interface unit, a data input end of the FPGA processing module is connected with a sending data line of the eNTP network interface unit, and a control signal end of the FPGA processing module is connected with a control signal end of the eNTP network interface unit.

[0005] Preferably, the eNTP network interface unit comprises a network interface chip with model number DM9000E, a network transformer chip with model number HR601680 and an RJ45 connector, wherein:

[0006] The 38th pin, the 39th pin, the 40th pin and the 41st pin of the network interface chip are used as receiving data lines; the 50th pin, the 51st pin, the 52nd pin and the 53rd pin of the network interface chip are used as transmitting data lines;

[0007] The 47th pin of the network interface chip is used as a receiving clock interface of the FPGA processing module; the 46th pin of the network interface chip is used as a receiving validity indication interface of the FPGA processing module; the 49th pin of the network interface chip is used as a transmitting clock interface of the FPGA processing module; the 54th pin of the network interface chip is used as a transmitting enable pin interface of the FPGA processing module; the 56th pin of the network interface chip is used as a bidirectional configuration data line interface of the FPGA processing module; the 57th pin of the network interface chip is used as a configuration data clock interface of the FPGA processing module; and the 80th pin of the network interface chip is used as a hardware reset pin interface of the FPGA processing module;

[0008] The 5th pin, the 16th pin, the 17th pin, the 20th pin, the 67th pin, the 72nd pin, the 73rd pin, the 55th pin, the 90th pin, the 97th pin and the 98th pin of the network interface chip are connected to a 3.3V power supply, wherein the 67th pin of the network interface chip is connected to the 3.3V power supply via a resistor R301;

[0009] The 14th pin, the 15th pin, the 18th pin, the 19th pin, the 23rd pin, the 42nd pin, the 48th pin, the 58th pin and the 63rd pin of the network interface chip are connected to an analog ground AGND;

[0010] The 21st pin and the 22nd pin of the network interface chip are connected to a quartz oscillator X301, both ends of the quartz oscillator X301 are connected to a ground GND via a resonance capacitor C313 and a resonance capacitor C314 respectively; the 26th pin of the network interface chip is connected to the analog ground AGND via a resistor R307; and the 27th pin, the 28th pin and the 35th pin of the network interface chip are connected to an analog power supply AVCC;

[0011] The 33rd pin, the 34th pin, the 29th pin and the 30th pin of the network interface chip are respectively connected to the 1st pin, the 3rd pin, the 6th pin and the 8th pin of a network transformer chip;

[0012] One end of the 8th pin of the network transformer chip is connected to one end of a resistor R305, one end of the 6th pin of the network transformer chip is connected to one end of a resistor R306, the resistor R306 and the resistor R305 are simultaneously connected to one end of a capacitor C304, and the other end of the capacitor C304 is connected to the analog ground AGND; and the 7th pin of the network transformer chip is connected to the analog ground AGND via a capacitor C305;

[0013] The first pin of the network transformer chip HR601680 is connected with one end of the resistor R304, and the third pin is connected with one end of the resistor R303. The other ends of the resistor R304 and the resistor R303 are connected with the analog voltage AVCC. The second pin of the network transformer chip is connected with one end of the matching impedance L302 and the capacitor C303. The other end of the impedance L302 is connected with the analog power supply AVCC, and the other end of the capacitor C303 is connected with the ground GND.

[0014] The eleventh pin of the network transformer chip is connected with the RX+ pin of the RJ45 connector U301. The ninth pin of the network transformer chip is connected with the RX- pin of the RJ45 connector U301. The sixteenth pin of the network transformer chip is connected with the TX+ pin of the RJ45 connector U301. The fourteenth pin of the network transformer chip is connected with the TX- pin of the RJ45 connector U301. The tenth pin of the network transformer chip is connected with one end of the resistor R308. The fifteenth pin of the network transformer chip is connected with one end of the resistor R309. The other ends of the resistor R308 and the resistor R309 are connected with the analog ground AGND through the high-voltage capacitor C312.

[0015] The sixtieth pin of the network interface chip is connected with the eleventh pin of the RJ45 connector U301, and the sixty-second pin is connected with the ninth pin of the RJ45 connector U301. The eleventh pin of the RJ45 connector U301 is the speed indicator pin, and the ninth pin is the active indicator pin.

[0016] Preferably, the eighty-second pin, the eighty-third pin, the eighty-fourth pin, the eighty-fifth pin, the eighty-sixth pin, the eighty-seventh pin, the eighty-eighth pin, the eighty-ninth pin, the sixth pin, the seventh pin, the eighth pin, the ninth pin, the tenth pin, the eleventh pin, the twelfth pin, the thirteenth pin, the eightieth pin, the one hundredth pin, the ninety-second pin, the first pin, the second pin, the third pin, the fourth pin, the twenty-fourth pin, the thirty-seventh pin, the thirty-eighth pin, the thirty-ninth pin, the fortieth pin, the forty-first pin, the forty-third pin, the forty-fourth pin, the forty-fifth pin, the forty-sixth pin, the forty-seventh pin, the forty-ninth pin, the fiftieth pin, the fifty-first pin, the fifty-second pin, the fifty-third pin, the fifty-fourth pin, the fifty-sixth pin, the fifty-seventh pin, the fifty-ninth pin, the sixty-first pin, the sixty-fourth pin, the sixty-fifth pin, the sixty-sixth pin, the sixty-eighth pin, the sixty-ninth pin, the seventieth pin, the seventy-first pin, and the seventy-fourth pin of the network interface chip DM9000E are empty pins.

[0017] Preferably, the FPGA processing module adopts an FPGA processing chip with the model EP4CE10E22I7N.

[0018] The 110th pin, the 111th pin, the 113th pin, the 120th pin, the 124th pin, the 126th pin, the 128th pin, the 132th pin, the 135th pin, the 136th pin, the 137th pin, the 138th pin, the 141th pin, the 142th pin and the 143th pin of the FPGA processing chip are connected with the 16-bit address bus of the CPU processing module;

[0019] The 112th pin, the 114th pin, the 119th pin, the 125th pin, the 127th pin, the 129th pin and the 133th pin of the FPGA processing chip are connected with the 8-bit data bus of the CPU processing module;

[0020] The 144th pin of the FPGA processing chip is connected with the 1 interrupt pin of the CPU processing module; and the 90th pin of the FPGA processing chip is the clock input pin of the CPU processing module;

[0021] The 55th pin, the 54th pin, the 53th pin and the 52th pin of the FPGA processing chip are connected with the receiving data line of the network chip; and the 72th pin, the 71th pin, the 70th pin and the 69th pin of the FPGA processing chip are connected with the sending data line of the network chip;

[0022] The 50th pin of the FPGA processing chip is connected with the receiving validity indication of the network chip DM9000E; the 51th pin of the FPGA processing chip is connected with the receiving clock of the network chip; the 68th pin of the FPGA processing chip is connected with the sending clock of the network chip; the 59th pin of the FPGA processing chip is connected with the network chip as a bidirectional configuration data line; the 58th pin of the FPGA processing chip is connected with the network chip as a configuration data clock; and the 60th pin of the FPGA processing chip is connected with the network chip as a hardware network chip reset pin.

[0023] The utility model discloses a kind of time service equipment based on eNTP client synchronization technology, carry out high-precision network time synchronization by network time synchronization NTP technology.The utility model completes the function of NTP protocol stack in FPGA hardware level, completes Ethernet unpacking and packing by FPGA processing module, carries out the writing of hardware time mark, provides accurate hardware time mark, provides good foundation for further network delay calculation and time deviation calculation. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is schematic diagram of the utility model;

[0025] Figure 2 It is FPGA processing module circuit diagram;

[0026] Figure 3 It is network interface circuit diagram. DETAILED DESCRIPTION

[0027] The utility model is further described below in combination with specific embodiments. It should be understood that these embodiments are only used to illustrate the utility model and not to limit the scope of the utility model. In addition, it should be understood that after reading the content taught by the utility model, those skilled in the art can make various changes or modifications to the utility model, and these equivalent forms also fall within the scope defined by the appended claims of the present application.

[0028] As shown in Figure 1 The utility model provides an interface circuit based on eNTP client synchronization technology, which comprises an FPGA processing module for implementing an NTP protocol stack function, a CPU processing module and an eNTP network interface unit.

[0029] The FPGA processing module is connected with the eNTP network interface unit, and the FPGA processing module completes the analysis and transceiving of network packets according to the receiving bus, the sending bus and the related control signals. The FPGA processing module completes the sending of network NTP packets and stamps accurate hardware time labels, and stamps hardware time labels of the received packets after receiving the NTP packets returned by the time server, so that the time deviation between the device and the time server can be calculated, and the final time deviation between the local device and the time server can be obtained through a time filtering algorithm.

[0030] The eNTP network interface unit mainly comprises a network interface chip (DM9000E) (hereinafter referred to as "network interface chip DM9000E"), a network transformer chip (HR601680) (hereinafter referred to as "network transformer chip HR601680"), an RJ45 connector U301 and the like, and is combined with Figure 3 , and comprises the following contents:

[0031] The 38th pin, the 39th pin, the 40th pin and the 41st pin of the network interface chip DM9000E are used as receiving data lines (4-bit RGMII); the 50th pin, the 51st pin, the 52nd pin and the 53rd pin are used as sending data lines (4-bit RGMII).

[0032] The 47th pin of the network interface chip DM9000E is connected with the FPGA processing module and is used as a receiving clock; the 46th pin is connected with the FPGA processing module and is used as a receiving validity indication; the 49th pin is connected with the FPGA processing module and is used as a sending clock; the 54th pin is connected with the FPGA processing module and is used as a sending enable pin; the 56th pin is connected with the FPGA processing module and is used as a bidirectional configuration data line; the 57th pin is connected with the FPGA processing module and is used as a configuration data clock; and the 80th pin is connected with the FPGA processing module and is used as a hardware reset pin.

[0033] The 82nd pin, the 83rd pin, the 84th pin, the 85th pin, the 86th pin, the 87th pin, the 88th pin, the 89th pin, the 6th pin, the 7th pin, the 8th pin, the 9th pin, the 10th pin, the 11th pin, the 12th pin, the 13th pin, the 80th pin, the 100th pin, the 92nd pin, the 1st pin, the 2nd pin, the 3rd pin, the 4th pin, the 24th pin, the 37th pin, the 38th pin, the 39th pin, the 40th pin, the 41st pin, the 43rd pin, the 44th pin, the 45th pin, the 46th pin, the 47th pin, the 49th pin, the 50th pin, the 51st pin, the 52nd pin, the 53rd pin, the 54th pin, the 56th pin, the 57th pin, the 59th pin, the 61st pin, the 64th pin, the 65th pin, the 66th pin, the 68th pin, the 69th pin, the 70th pin, the 71st pin, the 74th pin, the 75th pin of the network interface chip DM9000E are empty pins.

[0034] The 5th pin, the 16th pin, the 17th pin, the 20th pin, the 67th pin, the 72nd pin, the 73rd pin, the 55th pin, the 90th pin, the 97th pin, the 98th pin of the network interface chip DM9000E are connected with a 3.3V power supply, wherein the 67th pin of the network interface chip DM9000E is connected with the 3.3V power supply via the resistor R301.

[0035] The 14th pin, the 15th pin, the 18th pin, the 19th pin, the 23rd pin, the 42nd pin, the 48th pin, the 58th pin, the 63rd pin of the network interface chip DM9000E are connected with an analog ground AGND.

[0036] The 21st pin and the 22nd pin of the network interface chip DM9000E are connected with a 25M quartz oscillator X301, the two ends of the quartz oscillator X301 are respectively connected with the ground GND via the resonance capacitor C313 and the resonance capacitor C314; the 26th pin is connected with the analog ground AGND via the resistor R307; the 27th pin, the 28th pin, and the 35th pin are connected with an analog power supply AVCC.

[0037] The 33rd pin, the 34th pin, the 29th pin, and the 30th pin of the network interface chip DM9000E are respectively connected with the 1st pin, the 3rd pin, the 6th pin, and the 8th pin of the network transformer chip HR601680.

[0038] The network transformer circuit realized by the network transformer chip HR601680 is divided into a receiving loop and a transmitting loop, wherein:

[0039] The receiving loop of the network transformer circuit: the 8th pin of the network transformer chip HR601680 is connected with one end of the resistor R305, and the 6th pin is connected with one end of the resistor R306; the other end of the resistor R306 and the other end of the resistor R305 are simultaneously connected with one end of the capacitor C304, and the other end of the capacitor C304 is connected with the analog ground AGND; the 7th pin is connected with the analog ground AGND via the capacitor C305.

[0040] The sending loop of the network transformer circuit: the first pin of the network transformer chip HR601680 is connected with one end of the resistor R304, and the third pin is connected with one end of the resistor R303, and the other ends of the resistors R304 and R303 are connected with the analog voltage AVCC; the second pin of the network transformer chip HR601680 is connected with one end of the matching impedance L302 and the capacitor C303, the other end of the impedance L302 is connected with the analog power supply AVCC, and the other end of the capacitor C303 is connected with the ground GND.

[0041] The eleventh pin of the network transformer chip HR601680 is connected with the third pin (i.e. the RX+ pin) of the RJ45 connector U301, the ninth pin of the network transformer chip HR601680 is connected with the sixth pin (i.e. the RX- pin) of the RJ45 connector U301, the sixteenth pin of the network transformer chip HR601680 is connected with the first pin (i.e. the TX+ pin) of the RJ45 connector U301, and the fourteenth pin of the network transformer chip HR601680 is connected with the second pin (i.e. the TX- pin) of the RJ45 connector U301. The tenth pin of the network transformer chip HR601680 is connected with one end of the resistor R308, the fifteenth pin of the network transformer chip HR601680 is connected with one end of the resistor R309, and the other ends of the resistors R308 and R309 are connected with the analog ground AGND through the high-voltage capacitor C312 to prevent electrostatic breakdown.

[0042] The sixtieth pin of the network interface chip DM9000E is connected with the eleventh pin of the RJ45 connector U301, and the sixty-second pin is connected with the ninth pin of the RJ45 connector U301; the eleventh pin of the RJ45 connector U301 is the speed indicator pin, and the ninth pin is the Active indicator pin.

[0043] The FPGA processing module is used for completing the functions of Ethernet unpacking, hardware time labeling, Ethernet protocol processing, simple time data processing, address and data bus response with the main control MCU, etc. In the embodiment, the FPGA processing module adopts the FPGA processing chip with the model of EP4CE10E22I7N (hereinafter referred to as “FPGA processing chip EP4CE10E22I7N”), which can complete the synchronization technology based on the eNTP client, mainly including:

[0044] The 110th pin, the 111th pin, the 113th pin, the 120th pin, the 124th pin, the 126th pin, the 128th pin, the 132th pin, the 135th pin, the 136th pin, the 137th pin, the 138th pin, the 141th pin, the 142th pin, the 143th pin of the FPGA processing chip EP4CE10E22I7N are connected with the 16-bit address bus of the CPU processing module.

[0045] The eighth pin, the 114th pin, the 119th pin, the 125th pin, the 127th pin, the 129th pin and the 133th pin of the FPGA processing chip EP4CE10E22I7N are connected with the 8-bit data bus of the CPU processing module.

[0046] The 144th pin of the FPGA processing chip EP4CE10E22I7N is connected with the 1st interrupt pin of the CPU processing module; and the 90th pin of the FPGA processing chip EP4CE10E22I7N is the clock input pin of the CPU processing module, so as to ensure the normal read-write communication between the CPU processing module and the FPGA processing module.

[0047] The 55th pin, the 54th pin, the 53th pin and the 52th pin of the FPGA processing chip EP4CE10E22I7N are connected with the receiving data line (4-bit RGMII) of the network chip DM9000E; the 72th pin, the 71th pin, the 70th pin and the 69th pin are connected with the sending data line (4-bit RGMII) of the network interface chip DM9000E;

[0048] The 50th pin of the FPGA processing chip EP4CE10E22I7N is connected with the receiving validity indication of the network chip DM9000E; the 51th pin is connected with the receiving clock of the network chip DM9000E; the 68th pin is connected with the sending clock of the network chip DM9000E; the 59th pin is connected with the network chip DM9000E as a bidirectional configuration data line; the 58th pin is connected with the network chip DM9000E as the clock of configuration data; and the 60th pin is connected with the network chip DM9000E as the hardware network chip reset pin.

[0049] The connection mode of other pins of the FPGA processing chip EP4CE10E22I7N is referred to the data sheet, that is, DataSheet, which is the common sense of the person skilled in the art, and will not be repeated here.

[0050] The CPU processing module is realized based on the CPU chip STM32F407, and the connection mode of specific pins is referred to the data sheet, that is, DataSheet, which is the common sense of the person skilled in the art, and will not be repeated here.

[0051] The utility model discloses a eNTP client synchronization technology is completed in FPGA hardware level, including NTP protocol stack, NTP protocol hardware time mark's writing, NTP protocol package's processing and ethernet protocol stack, ethernet routing function, through FPGA processing module, the writing function of hardware time mark is completed, and the calculation processing part of hardware time mark is given to the CPU processing module of the next stage, calculates time deviation, through time precision optimization algorithm, data redundancy algorithm, optimizes time deviation data, finally completes the synchronization technology of eNTP client.

Claims

1. An interface circuit based on eNTP client synchronization technique, characterized in that, The CPU processing module, the FPGA processing module and the eNTP network interface unit are connected via an address data bus, the clock signal input end of the FPGA processing module is connected with the clock signal output end of the CPU processing module, the interrupt signal output end of the FPGA processing module is connected with the interrupt signal input end of the CPU processing module, the transceiving clock output end of the FPGA processing module is connected with the transceiving clock input end of the eNTP network interface unit, the data output end of the FPGA processing module is connected with the receiving data line of the eNTP network interface unit, the data input end of the FPGA processing module is connected with the sending data line of the eNTP network interface unit, and the control signal end of the FPGA processing module is connected with the control signal end of the eNTP network interface unit.

2. The interface circuit based on eNTP client synchronization technology according to claim 1, wherein, The eNTP network interface unit comprises a network interface chip with a model number of DM9000E, a network transformer chip with a model number of HR601680 and an RJ45 connector, wherein: The 38th, 39th, 40th and 41st pins of the network interface chip are used as receiving data lines, and the 50th, 51st, 52nd and 53rd pins of the network interface chip are used as sending data lines; The 47th pin of the network interface chip is used as a receiving clock interface of the FPGA processing module, the 46th pin of the network interface chip is used as a receiving validity indication interface of the FPGA processing module, the 49th pin of the network interface chip is used as a sending clock interface of the FPGA processing module, the 54th pin of the network interface chip is used as a sending enable pin interface of the FPGA processing module, the 56th pin of the network interface chip is used as a bidirectional configuration data line interface of the FPGA processing module, the 57th pin of the network interface chip is used as a configuration data clock interface of the FPGA processing module, and the 80th pin of the network interface chip is used as a hardware reset pin interface of the FPGA processing module; The 5th, 16th, 17th, 20th, 67th, 72nd, 73rd, 55th, 90th, 97th and 98th pins of the network interface chip are connected with a 3.3V power supply, wherein the 67th pin of the network interface chip is connected with the 3.3V power supply via a resistor R301; The 14th, 15th, 18th, 19th, 23rd, 42nd, 48th, 58th and 63rd pins of the network interface chip are connected with an analog ground AGND; The 21st and 22nd pins of the network interface chip are connected with a quartz oscillator X301, the two ends of the quartz oscillator X301 are connected with a ground GND via a resonance capacitor C313 and a resonance capacitor C314 respectively, the 26th pin of the network interface chip is connected with the analog ground AGND via a resistor R307, and the 27th, 28th and 35th pins of the network interface chip are connected with an analog power supply AVCC; The 33rd, 34th, 29th and 30th pins of the network interface chip are connected with the 1st, 3rd, 6th and 8th pins of the network transformer chip respectively. The eighth pin of the network transformer chip is connected with one end of the resistance R305, and the sixth pin is connected with one end of the resistance R306. The other end of the resistance R306 and the resistance R305 is connected with one end of the capacitor C304, and the other end of the capacitor C304 is connected with the analog ground AGND. The seventh pin of the network transformer chip is connected with the analog ground AGND through the capacitor C305. The first pin of the network transformer chip HR601680 is connected with one end of the resistance R304, and the third pin is connected with one end of the resistance R303. The other end of the resistance R304 and the resistance R303 is connected with the analog voltage AVCC. The second pin of the network transformer chip is connected with one end of the matching impedance L302 and the capacitor C303. The other end of the impedance L302 is connected with the analog power supply AVCC, and the other end of the capacitor C303 is connected with the ground GND. The eleventh pin of the network transformer chip is connected with the RX+ pin of the RJ45 connector U301. The ninth pin of the network transformer chip is connected with the RX- pin of the RJ45 connector U301. The sixteenth pin of the network transformer chip is connected with the TX+ pin of the RJ45 connector U301. The fourteenth pin of the network transformer chip is connected with the TX- pin of the RJ45 connector U301. The tenth pin of the network transformer chip is connected with one end of the resistance R308. The fifteenth pin of the network transformer chip is connected with one end of the resistance R309. The other end of the resistance R308 and the resistance R309 is connected with the analog ground AGND through the high-voltage capacitor C312. The sixtieth pin of the network interface chip is connected with the eleventh pin of the RJ45 connector U301, and the sixty-second pin is connected with the ninth pin of the RJ45 connector U301. The eleventh pin of the RJ45 connector U301 is the speed indicator pin, and the ninth pin is the Active indicator pin.

3. An interface circuit based on eNTP client synchronization technology as claimed in claim 2, wherein, The eighty-second pin, the eighty-third pin, the eighty-fourth pin, the eighty-fifth pin, the eighty-sixth pin, the eighty-seventh pin, the eighty-eighth pin, the eighty-ninth pin, the sixth pin, the seventh pin, the eighth pin, the ninth pin, the tenth pin, the eleventh pin, the twelfth pin, the thirteenth pin, the eightieth pin, the one hundredth pin, the ninety-second pin, the first pin, the second pin, the third pin, the fourth pin, the twenty-fourth pin, the thirty-seventh pin, the thirty-eighth pin, the thirty-ninth pin, the fortieth pin, the forty-first pin, the forty-third pin, the forty-fourth pin, the forty-fifth pin, the forty-sixth pin, the forty-seventh pin, the forty-ninth pin, the fiftieth pin, the fifty-first pin, the fifty-second pin, the fifty-third pin, the fifty-fourth pin, the fifty-sixth pin, the fifty-seventh pin, the fifty-ninth pin, the sixty-first pin, the sixty-fourth pin, the sixty-fifth pin, the sixty-sixth pin, the sixty-eighth pin, the sixty-ninth pin, the seventieth pin, the seventy-first pin, the seventy-fourth pin, and the seventy-fifth pin of the network interface chip DM9000E are empty pins.

4. The interface circuit based on eNTP client synchronization technique as claimed in claim 2, wherein, The FPGA processing module adopts an FPGA processing chip with the model EP4CE10E22I7N: The one hundred and tenth pin, the one hundred and eleventh pin, the one hundred and thirteenth pin, the one hundred and twentieth pin, the one hundred and twenty-fourth pin, the one hundred and twenty-sixth pin, the one hundred and twenty-eighth pin, the one hundred and thirty-second pin, the one hundred and thirty-fifth pin, the one hundred and thirty-sixth pin, the one hundred and thirty-seventh pin, the one hundred and thirty-eighth pin, the one hundred and forty-first pin, the one hundred and forty-second pin, and the one hundred and forty-third pin of the FPGA processing chip are connected with the sixteen-bit address bus of the CPU processing module. The 112th pin, the 114th pin, the 119th pin, the 125th pin, the 127th pin, the 129th pin and the 133th pin of the FPGA processing chip are connected with the 8-bit data bus of the CPU processing module; The 144th pin of the FPGA processing chip is connected with an interrupt pin of the CPU processing module; and the 90th pin of the FPGA processing chip is a clock input pin of the CPU processing module; The 55th pin, the 54th pin, the 53th pin and the 52th pin of the FPGA processing chip are connected with the receiving data lines of the network chip; and the 72th pin, the 71th pin, the 70th pin and the 69th pin of the FPGA processing chip are connected with the sending data lines of the network chip; The 50th pin of the FPGA processing chip is connected with the receiving validity indication of the network chip DM9000E; the 51th pin of the FPGA processing chip is connected with the receiving clock of the network chip; the 68th pin of the FPGA processing chip is connected with the sending clock of the network chip; the 59th pin of the FPGA processing chip is connected with the network chip as a bidirectional configuration data line; the 58th pin of the FPGA processing chip is connected with the network chip as a configuration data clock; and the 60th pin of the FPGA processing chip is connected with the network chip as a hardware network chip reset pin.

Images