Load current source module for reading image sensor, reading system and imaging equipment
By introducing a negative impedance transformation circuit and a charge/discharge acceleration circuit into the load current source module in the CMOS image sensor, the power consumption and design difficulty caused by the increase of the load current source bias current are solved, and the VSL signal is established quickly.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-11
- Publication Date
- 2026-03-27
AI Technical Summary
In existing CMOS image sensors, an increase in the bias current of the load current source leads to increased power consumption and design complexity, which in turn affects the VSL signal settling time.
The load current source module incorporates a negative impedance transformation circuit and a charge/discharge acceleration circuit. The negative impedance transformation circuit cancels out parasitic resistance and capacitance, while the charge/discharge acceleration circuit provides transient current, enabling rapid establishment of the VSL signal.
It effectively accelerates the VSL signal settling time, avoids the problems of increased power consumption and design difficulty, and keeps the operating point design of the current mirror circuit unchanged.
Smart Images
Figure CN224054357U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to image sensor technical field especially relates to a kind of load current source module for image sensor reading, reading system and imaging equipment. BACKGROUND
[0002] The existing CMOS image sensor ADC (A / DConverter) is composed of load current source array, comparator array and counter array. Among them, the load current source array is responsible for providing constant current for the source follower of the pixel array;During the signal reading process of the pixel array, the charge in the PD (Photon Diode) needs to be transferred to the FD (Floating Diffusion), so that the FD voltage drops;Further, the pixel array output signal VSL (Vertical Signal Line) is lowered by the pixel SF (Source Follower).
[0003] During the above reading process, due to the influence of metal wiring parasitic resistance, parasitic capacitance and SF equivalent output impedance on the VSL drop process, the VSL drop process will be slow, so that the whole image sensor needs to spend time waiting for VSL to drop to a stable level during the reading process. The time consumed in this process is called VSL setup time.
[0004] At present, for the traditional image sensor structure, if you want to speed up the VSL setup time, you often increase the bias current of the load current source: on the one hand, the transconductance of the SF of the pixel array is increased to reduce its equivalent output impedance, on the other hand, during the large signal setup, increasing the bias current of the load current source can speed up the establishment of the large signal.
[0005] However, the above method has the problem that increasing the bias current of the load current source often causes the power consumption of the whole analog circuit to increase and the DC operating point design of the load current source to be difficult. SUMMARY
[0006] The utility model aims at solving the shortcoming that increasing the bias current of the load current source in the prior art easily leads to increased power consumption, and provides a load current source module for image sensor reading, a reading system and an imaging device.
[0007] In order to achieve the above purpose, the utility model adopts the following technical scheme:
[0008] The utility model provides a load current source module for image sensor reading in the first aspect, and the load current source module is electrically connected with the pixel matrix in the pixel driving module, comprising:
[0009] A current mirror circuit electrically connected to the pixel driving module, the current mirror circuit being configured to provide a bias current;
[0010] A negative impedance conversion circuit configured to generate a negative resistance or a negative capacitance to offset the parasitic resistance or the parasitic capacitance of the VSL itself;
[0011] The negative impedance conversion circuit comprises an amplifier in a negative feedback state.
[0012] A charge and discharge acceleration circuit configured to provide a charge and discharge current during establishment of the VSL.
[0013] In some possible solutions, the current mirror circuit further comprises:
[0014] Two N-channel field effect transistors are connected in a common source and common gate manner, the gate of the N-channel field effect transistor connected in the common source and common gate manner is connected to a bias voltage, and the source of the N-channel field effect transistor connected in the common source and common gate manner is electrically connected to the pixel driving module, the negative impedance conversion circuit and the charge and discharge acceleration circuit respectively.
[0015] In some possible solutions, the charge and discharge acceleration circuit comprises:
[0016] A voltage-current conversion circuit having one end connected to a drain source voltage, the voltage-current conversion circuit being configured to perform voltage-current conversion;
[0017] A current amplification circuit electrically connected to the voltage-current conversion circuit, the current amplification circuit being configured to amplify the voltage-current conversion current.
[0018] In some possible solutions, the voltage-current conversion circuit comprises:
[0019] A first P-channel field effect transistor having one end connected to a drain source voltage, the first P-channel field effect transistor being configured to provide a current source;
[0020] A second P-channel field effect transistor also having one end connected to the drain source voltage, the second P-channel field effect transistor being configured to provide a bias current;
[0021] A capacitor arranged on one side of the second P-channel field effect transistor, the capacitor being electrically connected to the second P-channel field effect transistor, and the capacitor being a bypass capacitor of the second P-channel field effect transistor.
[0022] A third P-channel field effect transistor, a gate of the third P-channel field effect transistor being connected with a vertical signal line signal output node, a source of the third P-channel field effect transistor being connected with the second P-channel field effect transistor;
[0023] A first N-channel field effect transistor, the first N-channel field effect transistor being connected with the second P-channel field effect transistor, the first N-channel field effect transistor being connected with a drain of the third P-channel field effect transistor;
[0024] A second N-channel field effect transistor, the second N-channel field effect transistor and the first N-channel field effect transistor constituting a current mirror.
[0025] In some possible solutions, the amplifier is an operational amplifier, and the negative impedance conversion circuit further comprises:
[0026] A first resistor, the first resistor being electrically connected with a non-inverting input terminal of the amplifier;
[0027] A second resistor, the second resistor being electrically connected with an inverting input terminal of the amplifier;
[0028] A third resistor, the third resistor being electrically connected with the inverting input terminal of the amplifier, and the third resistor being connected with the second resistor in parallel.
[0029] In some possible solutions, the negative impedance conversion circuit further comprises:
[0030] A first capacitor, the first capacitor replacing the first resistor, the first capacitor being electrically connected with the non-inverting input terminal of the amplifier.
[0031] In some possible solutions, the amplifier is a common-gate amplifier, and the negative impedance conversion circuit further comprises:
[0032] A first capacitor, one end of the first capacitor being electrically connected with the pixel driving module;
[0033] A fourth P-channel field effect transistor, a source of the fourth P-channel field effect transistor being electrically connected with the pixel driving module, and the fourth P-channel field effect transistor being electrically connected with the first capacitor, a gate of the fourth P-channel field effect transistor being connected with a bias voltage;
[0034] A third N-channel field effect transistor, a gate of the third N-channel field effect transistor being electrically connected with the bias voltage, a source of the third N-channel field effect transistor being electrically connected with a drain of the fourth P-channel field effect transistor.
[0035] In some possible solutions, the common-gate amplifier is replaced with a source follower, and the negative impedance conversion circuit further comprises:
[0036] A fourth N-channel field effect transistor replaces the fourth P-channel field effect transistor, the fourth N-channel field effect transistor gate is electrically connected with the pixel driving module, the fourth N-channel field effect transistor drain is connected with a power supply, and the fourth N-channel field effect transistor source is electrically connected with the third N-channel field effect transistor drain.
[0037] One end of the first capacitor is electrically connected with the fourth N-channel field effect transistor source, and the other end of the first capacitor is electrically connected with the current mirror circuit.
[0038] The utility model provides a kind of image sensor readout system in the second aspect, using the load current source module of any one described in the first aspect, the readout system further includes:
[0039] Pixel noise detection module, the pixel noise detection module is electrically connected with the pixel driving module, and the pixel noise detection module is used to detect pixel matrix in pixel driving module;
[0040] Reference slope generation module, the reference slope generation module is electrically connected with the pixel driving module;
[0041] Comparator, the comparator is electrically connected with the load current source module and reference slope generation module respectively;
[0042] Counter, the counter is electrically connected with the comparator;
[0043] Data transmission module, the data transmission module is electrically connected with the counter.
[0044] The utility model provides a kind of imaging equipment in the third aspect, using the load current source module of any one described in the first aspect or using the image sensor readout system described in the second aspect.
[0045] The utility model has the advantages that:
[0046] The load current source module is internally constructed with negative impedance conversion circuit and charge-discharge acceleration circuit, on the one hand, the negative impedance conversion circuit generates negative impedance to offset the parasitic capacitance and parasitic resistance existing between VSL signal to realize the acceleration of small signal establishment speed, on the other hand, the charge-discharge acceleration circuit provides larger transient current to realize the acceleration of large signal establishment speed. BRIEF DESCRIPTION OF DRAWINGS
[0047] Figure 1 It is the working connection schematic view of the load current source module for reading out the image sensor provided in the embodiment of the utility model;
[0048] Figure 2 It is the pixel matrix part structure schematic view of the pixel driving module provided in the embodiment of the utility model;
[0049] Figure 3 It is the vertical signal line node VSL reduction process schematic view provided in the embodiment of the utility model;
[0050] Figure 4 It is the pixel matrix connection schematic view of the load current source module for reading out the image sensor and the pixel driving module provided in the embodiment of the utility model;
[0051] Figure 5 It is the current mirror circuit connection schematic view of the load current source module for reading out the image sensor provided in the embodiment of the utility model;
[0052] Figure 6 It is the negative impedance transformation circuit connection schematic view of the load current source module for reading out the image sensor provided in the embodiment of the utility model, which generates negative resistance;
[0053] Figure 7 It is the negative impedance transformation circuit connection schematic view of the load current source module for reading out the image sensor provided in the embodiment of the utility model, which generates negative capacitance;
[0054] Figure 8 It is the negative impedance transformation circuit connection schematic view of the load current source module for reading out the image sensor provided in the embodiment of the utility model, which contains common gate amplifier;
[0055] Figure 9 It is the negative impedance transformation circuit connection schematic view of the load current source module for reading out the image sensor provided in the embodiment of the utility model, which contains source follower. DETAILED DESCRIPTION
[0056] The technical scheme in the embodiments of the utility model will be described clearly and completely below with the drawings in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by the person skilled in the art without creative labor belong to the protection scope of the utility model.
[0057] It should be noted that all directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative positional relationship, movement condition, etc. between components in a certain specific posture (as shown in the drawings), and if the specific posture changes, the directionality indications will also change accordingly.
[0058] In the present application, unless otherwise explicitly specified and limited, the terms "connection", "fixing" and the like should be understood in a broad sense, for example, "fixing" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship of two elements, unless otherwise explicitly limited. For ordinary skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0059] In addition, if the present application embodiments involve "first", "second" and the like, the "first", "second" and the like are only for description purposes, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features with "first" and "second" can explicitly or implicitly include at least one of the features. In addition, the meaning of "and / or" appearing throughout the text includes three parallel solutions, for example, "A and / or B" includes A solution, or B solution, or A and B solution. In addition, the technical solutions of each embodiment can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, and is not within the protection scope required by the present application.
[0060] Referring to Figures 1 to 9 The purpose of the present application is to solve the problem of increasing the bias current of the load current source in the prior art, which easily leads to increased power consumption, and to provide a load current source module for image sensor reading. The load current source module is internally provided with a negative impedance conversion circuit 1062 and a charge and discharge acceleration circuit 1063. On the one hand, the negative impedance conversion circuit 1062 generates negative impedance to offset the parasitic capacitance and parasitic resistance affecting the VSL establishment speed, so as to accelerate the small signal establishment speed. On the other hand, the charge and discharge acceleration circuit 1063 provides a larger transient current to accelerate the large signal establishment speed. That is, the load current source module in the present application does not change the action point design of the main current mirror circuit, and can effectively accelerate the VSL establishment time.
[0061] Referring to Figure 1 , Figure 2 , Figure 3 andFigure 4 As shown in the figure, a load current source module 106 is electrically connected to the pixel matrix 100 in the pixel driving module 101, and is used to cooperate with the pixel array in the pixel driving module 101 to establish a large signal and a small signal. The pixel array in the pixel driving module 101 is composed of a plurality of pixel units 100, and each pixel unit 100 includes a photodiode 1001, an N-channel field effect transistor 1002, an N-channel field effect transistor 1003, an N-channel field effect transistor 1004, and an N-channel field effect transistor 1005. When exposed to light, the photodiode 1001 completes photoelectric conversion and generates photo-generated electrons. When resetting, the N-channel field effect transistor 1003 is connected to the signal RST at the gate, the N-channel field effect transistor 1003 is turned on, the potential of the floating diffusion point FD 1006 is reset to a level slightly lower than the power supply VDD, and then the RST signal is lowered to end the reset operation. When reading a signal, the N-channel field effect transistor 1002 is connected to the signal TX at the gate, and the N-channel field effect transistor 1002 is turned on at this time. Because the potential of the floating diffusion point FD 1006 is higher than the positive terminal of the photodiode 1001 at this time, the photo-generated electrons generated by the photodiode 1001 move to the floating diffusion point FD 1006 through the N-channel field effect transistor 1002, so that the voltage decreases. At this time, if the pixel row where the pixel unit 1000 is located is in a readout state, the N-channel field effect transistor 1005 is connected to the signal SEL at the gate, and the N-channel field effect transistor 1004 is in a source follower working state when the N-channel field effect transistor 1005 is turned on. When the potential of the floating diffusion point FD 1006 decreases, it makes the vertical signal line node VSL 1007 also decrease by a voltage slightly smaller than the voltage change amount of the floating diffusion point FD 1006. At this time, the voltage change amount of the vertical signal line node VSL 1007 corresponds to the signal amount brought by the photo-generated electrons. Therefore, in the pixel unit readout process shown in the figure, the action timing diagram of the N-channel field effect transistor 1002 gate connected signal TX and the vertical signal line node VSL 1007 is as follows: Figure 2 As shown in the figure, a load current source module 106 is electrically connected to the pixel matrix 100 in the pixel driving module 101, and is used to cooperate with the pixel array in the pixel driving module 101 to establish a large signal and a small signal. The pixel array in the pixel driving module 101 is composed of a plurality of pixel units 100, and each pixel unit 100 includes a photodiode 1001, an N-channel field effect transistor 1002, an N-channel field effect transistor 1003, an N-channel field effect transistor 1004, and an N-channel field effect transistor 1005. When exposed to light, the photodiode 1001 completes photoelectric conversion and generates photo-generated electrons. When resetting, the N-channel field effect transistor 1003 is connected to the signal RST at the gate, the N-channel field effect transistor 1003 is turned on, the potential of the floating diffusion point FD 1006 is reset to a level slightly lower than the power supply VDD, and then the RST signal is lowered to end the reset operation. When reading a signal, the N-channel field effect transistor 1002 is connected to the signal TX at the gate, and the N-channel field effect transistor 1002 is turned on at this time. Because the potential of the floating diffusion point FD 1006 is higher than the positive terminal of the photodiode 1001 at this time, the photo-generated electrons generated by the photodiode 1001 move to the floating diffusion point FD 1006 through the N-channel field effect transistor 1002, so that the voltage decreases. At this time, if the pixel row where the pixel unit 1000 is located is in a readout state, the N-channel field effect transistor 1005 is connected to the signal SEL at the gate, and the N-channel field effect transistor 1004 is in a source follower working state when the N-channel field effect transistor 1005 is turned on. When the potential of the floating diffusion point FD 1006 decreases, it makes the vertical signal line node VSL 1007 also decrease by a voltage slightly smaller than the voltage change amount of the floating diffusion point FD 1006. At this time, the voltage change amount of the vertical signal line node VSL 1007 corresponds to the signal amount brought by the photo-generated electrons. Therefore, in the pixel unit readout process shown in the figure, the action timing diagram of the N-channel field effect transistor 1002 gate connected signal TX and the vertical signal line node VSL 1007 is as follows: Figure 3As shown in the figure. That is, when the TX is high, the N-channel field effect transistor 1002 is turned on, and the vertical signal line node VSL1007 begins to drop. The drop of the VSL1007 can be divided into two parts: a large signal setup period and a small signal setup period. Here, in order to facilitate the circuit connection of the load current source module and the pixel unit in the pixel driving module in the present application, a group of pixel units are connected as an example. In addition, the metal trace parasitic resistance 1101 of the vertical signal line node VSL1007 can be represented by a resistance R0, the metal trace parasitic capacitance 1102 can be represented by a capacitance C0, the load current source can be represented by an ideal current source 1104, and the vertical signal line node connected to the load current source 1104 is VSL_OUT1103.
[0062] Referring to Figures 5 to 6 As shown in the figure, specifically, the load current source module includes a current mirror circuit 1061, a negative impedance conversion circuit 1062, and a charge and discharge acceleration circuit 1063. The current mirror circuit 1061 is electrically connected to the pixel driving module 101, and is used to provide a bias current. Specifically, the current mirror circuit 1061 includes a common-source common-gate current mirror or two N-channel field effect transistors. Specifically, the current mirror circuit can be connected by two N-channel field effect transistors (i.e., can include N-channel field effect transistor 10611 and N-channel field effect transistor 10612) through common-source common-gate connection. The gate of the common-source common-gate connected N-channel field effect transistor is connected with a bias voltage, and the source of the common-source common-gate connected N-channel field effect transistor is electrically connected with the pixel driving module 101, the negative impedance conversion circuit 1062, and the charge and discharge acceleration circuit 1063, respectively. That is, the gates of the two common-source common-gate connected N-channel field effect transistors are connected with VB2 and VB1, respectively, as the bias voltage of the common-source common-gate current mirror. Then, the vertical signal line output node VSL_OUT1103 is connected with the negative impedance conversion circuit 1062 and the charge and discharge acceleration circuit 1063. It should be noted that the negative impedance conversion circuit 1062 and the charge and discharge acceleration circuit 1063 can be connected to the vertical signal line output node VSL_OUT1103 at the same time, or only one of them can be connected to the vertical signal line output node VSL_OUT1103. The negative impedance conversion circuit 1062 is used to generate a negative resistance or a negative capacitance, which offsets the parasitic resistance 1101 or the parasitic capacitance 1102 of the VSL itself. The charge and discharge acceleration circuit 1063 is used to provide a charge and discharge current during the VSL setup period. In order to offset the parasitic capacitance 1101 and the parasitic resistance 1102 existing in the signal setup of the VSL, so as to accelerate the small signal setup speed; the charge and discharge acceleration circuit 1063 provides a larger transient current, so as to accelerate the large signal setup speed.
[0063] Referring toFigure 6 As shown, when the negative impedance transformation circuit 1062 offsets the parasitic resistance established when the negative resistance is generated, the negative impedance transformation circuit 1062 includes a first resistor 10621, a second resistor 10623, a third resistor 10624, and an operational amplifier 10622. The first resistor 10621 is electrically connected to the non-inverting input terminal of the operational amplifier 10622; the second resistor 10623 is electrically connected to the inverting input terminal of the operational amplifier 10622; the third resistor 10624 is electrically connected to the inverting input terminal of the operational amplifier 10622, and the third resistor 10624 is in parallel with the second resistor 10623. That is, in the negative impedance transformation circuit 1062 of this embodiment, the operational amplifier 10622, the second resistor 10623, and the third resistor 10624 form a negative feedback connection, and the closed-loop gain thereof is (R1+R2) / R2, where R1 is the second resistor 10623 and R2 is the third resistor 10624. Therefore, when the variation of the voltage at the non-inverting input terminal of the operational amplifier 10622 is Vin=V1, the variation of the voltage at the output terminal thereof is Vout=(R1+R2) / R2*V1; at this time, the input current flowing through the first resistor 10621 is:
[0064] Iin=(Vin-Vout) / R_NI=-R1 / R2*V1 / R_NI, R_NI is the first resistor 10621;
[0065] Therefore, in this embodiment, the negative impedance transformation circuit 1062 has an equivalent input resistance of -R2 / R1*R_NI, and when the value of R2 / R1*R_NI is equal to the parasitic resistance 1101 of the vertical signal line node VSL1007, the equivalent input impedance of the negative impedance transformation circuit 1062 offsets the parasitic resistance 1101.
[0066] In order to facilitate the understanding of the above, examples are given, for example: when the parasitic resistance R0=20KΩ, R2=10KΩ, R1=500Ω, and R_NI=1KΩ, the equivalent input impedance of the negative impedance transformation circuit 1062 is Zin=-20KΩ, thereby effectively reducing the load of the vertical signal line node VSL1007 and accelerating the speed of small signal establishment. It should be noted that when R2 / R1>1, the equivalent input impedance of the negative impedance transformation circuit 1062 behaves as a negative resistance; and when R2 / R1<1, the equivalent input impedance of the negative impedance transformation circuit 1062 behaves as a positive resistance.
[0067] Reference Figure 6In the charging and discharging acceleration circuit 1063 of this embodiment, all field effect transistors work in saturation state. Specifically, the charging and discharging acceleration circuit 1063 includes a voltage-current conversion circuit and a current amplification circuit, one end of the voltage-current conversion circuit is connected with a drain source voltage, and the voltage-current conversion circuit is used for voltage-current conversion; the current amplification circuit is electrically connected with the voltage-current conversion circuit, and the current amplification circuit is used for amplifying the voltage-current conversion current. In this embodiment, the voltage-current conversion circuit includes a first P-channel field effect transistor 10636, a second P-channel field effect transistor 10631, a capacitor 10632, a third P-channel field effect transistor 10633, a first N-channel field effect transistor 10634 and a second N-channel field effect transistor 10635. One end of the first P-channel field effect transistor 10636 is connected with a drain source voltage, and the first P-channel field effect transistor 10636 is used for providing a current source; one end of the second P-channel field effect transistor 10631 is also connected with a drain source voltage, and the second P-channel field effect transistor 10631 is used for providing a bias current; the capacitor 10632 is arranged on one side of the second P-channel field effect transistor 10631, and the capacitor 10632 is electrically connected with the second P-channel field effect transistor 10631, and the capacitor 10632 is a bypass capacitor of the second P-channel field effect transistor 10631 (i.e. reducing the noise and voltage fluctuation generated by the second P-channel field effect transistor 10631); the gate of the third P-channel field effect transistor 10633 is connected with a vertical signal line signal output node VSL_OUT 1103, and the source of the third P-channel field effect transistor 10633 is connected with the second P-channel field effect transistor 10631; the first N-channel field effect transistor 10634 is connected with the second P-channel field effect transistor 10631, and the first N-channel field effect transistor 10634 is connected with the drain of the third P-channel field effect transistor 10633; the second N-channel field effect transistor 10635 and the first N-channel field effect transistor 10634 constitute a current mirror. In this embodiment, the first P-channel field effect transistor 10636 and the second P-channel field effect transistor 10631 can act as a current source, and the capacitor 10632 can act as a bypass capacitor of the second P-channel field effect transistor 10631. The second P-channel field effect transistor 10631 is the third P-channel field effect transistor 10633 and the first N-channel field effect transistor 10634.The gate of the third P-channel field effect transistor 10633 is connected to the vertical signal line output node VSL_OUT 1103, and the drain of the third P-channel field effect transistor 10633 is connected to the first N-channel field effect transistor 10634, and the first N-channel field effect transistor 10634 and the second N-channel field effect transistor 10635 form a current mirror, and the current mirror ratio is determined by the ratio of the width-length ratio of the second N-channel field effect transistor 10635 to the width-length ratio of the first N-channel field effect transistor 10634. The current of the first P-channel field effect transistor 10636 as a current source is set to be slightly equal to the saturation current of the second N-channel field effect transistor 10635. During the falling process of the vertical signal line output node VSL_OUT 1103, the gate voltage of the third P-channel field effect transistor 10633 decreases by ΔV, at this time, the third P-channel field effect transistor 10633 acts as a source follower, and the source voltage will decrease, at this time, the capacitor 10632 as a bypass capacitor acts as a current source to provide a transient current ΔI=C1*dΔV / dt to the second P-channel field effect transistor 10631, and the transient current is amplified by the current mirror composed of the first N-channel field effect transistor 10634 and the second N-channel field effect transistor 10635, and the amplification factor is the ratio of the width-length ratio of the second N-channel field effect transistor 10635 to the width-length ratio of the first N-channel field effect transistor 10634 as mentioned above.
[0068] K=(W / L)_10635 / (W / L)_10634.
[0069] Therefore, it can be known that the transient output current generated by the drain of the second N-channel field effect transistor 10635 is K*ΔI. Since the first P-channel field effect transistor 10636 is set to be in a constant current working state, the transient current K*ΔI will be provided by the load capacitor through the vertical signal line output node VSL_OUT 1103; if the current of the current source is set to I, then in this embodiment, the current flowing out of the load capacitor during the large signal establishment can be represented as I+K*ΔI, and the size adjustment can be realized by adjusting the capacitance value of the capacitor and the current mirror ratio K. Therefore, in this embodiment, the charge and discharge acceleration circuit 1063 accelerates the large signal establishment speed of the vertical signal line output node VSL_OUT 1103 by increasing the transient current flowing out of the load capacitor during the large signal establishment.
[0070] Referring to Figure 7As shown, when the negative impedance conversion circuit 1062 is used to offset the parasitic resistance established when VSL, the introduction of the first resistance 10621 can increase the thermal noise on the vertical signal line input node VSL on the one hand, and the negative resistance of the first resistance 10621 can cause the circuit to oscillate on the other hand. Therefore, in some feasible solutions, the negative impedance conversion circuit further includes: a first capacitor 10625, the first capacitor 10625 is connected to the non-inverting input terminal of the operational amplifier 10622. That is, in this embodiment, the first capacitor 10625 is arranged in the negative impedance conversion circuit 1062, and the first capacitor 10625 is used to offset the parasitic capacitance established when VSL, so as to accelerate the establishment of VSL. Wherein, the remaining structure is consistent with that shown in the first embodiment, and will not be described in detail herein. Figure 6 In this embodiment, during the establishment of the drop of the vertical signal line node VSL1007, when the voltage variation of the non-inverting input terminal of the operational amplifier 10622 is Vin=V1, the output terminal Vout=(R1+R2) / R2*V1. As known from the first embodiment, at this time, the equivalent input current flowing through the first capacitor 10625 is:
[0071] Iin=(Vin-Vout)*s*C_NI=-R1 / R2*V1*s*C_NI;
[0072] Wherein, s represents a complex variable, and its unit is rad / s, and C_NI is the first capacitor 10625.
[0073] Therefore, it can be calculated that the equivalent input impedance of the negative impedance conversion circuit 1062 at this time is
[0074] Zin=Vin / Iin=-R2 / R1*(1 / (s*C_NI));
[0075] As can be seen from the above formula, in this embodiment, the negative impedance conversion circuit 1062 has an equivalent input capacitance of -R2 / R1 times the first capacitor 10625. When the value of R2 / R1*C_NI is equal to the parasitic capacitance 1102 of the vertical signal line node VSL1007, the equivalent input impedance of the negative impedance conversion circuit 1062 is offset with the parasitic capacitance 1102.
[0076] For the convenience of understanding the above content, examples are given, for example: when the parasitic capacitance C0=2pF, R2=10KΩ, R1=500Ω, C_NI=100fF, the equivalent input impedance of the negative impedance conversion circuit 1062 is: Zin=-(1 / s*2p)Ω, and the impedance of the parasitic capacitance 1102 is Zc0=(1 / s*2p)Ω; by canceling Zin and Zc0, the load of the vertical signal line node VSL1007 is effectively reduced, and the speed of small signal establishment is accelerated. It should be noted that when R2 / R1>1, the equivalent input impedance of the negative impedance conversion circuit 1062 behaves as a negative capacitance; when R2 / R1<1, the equivalent input impedance of the negative impedance conversion circuit 1062 behaves as a positive capacitance. In this embodiment, by replacing the negative resistance in the negative impedance conversion circuit 1062 with a negative capacitance, the same small signal establishment process is achieved, but the risk of picture quality deterioration caused by the thermal noise of the resistor is avoided.
[0077] With reference to Figure 8 In Figure 6 and Figure 7 , the operational amplifier 10622 using negative feedback achieves the cancellation of the negative resistance or negative capacitance of the negative impedance conversion circuit 1062 with the parasitic resistance 1101 or the parasitic capacitance 1102; however, in actual use, the operational amplifier 10622 itself may introduce noise, and also increase the circuit area and power consumption. In some feasible schemes, the amplifier can be a common-gate amplifier. Specifically, in this embodiment, the negative impedance conversion circuit 1062 can be composed of a first capacitor 10625, a fourth P-channel field effect transistor 10626, and a third N-channel field effect transistor 10627. One end of the first capacitor 10625 is electrically connected to the pixel driving module 101. The source of the fourth P-channel field effect transistor 10626 is electrically connected to the pixel driving module 101 and is electrically connected to the first capacitor 10625. The gate of the fourth P-channel field effect transistor 10626 is connected to a bias voltage. The gate of the third N-channel field effect transistor 10627 is electrically connected to a bias voltage. The source of the third N-channel field effect transistor 10627 is electrically connected to the drain of the fourth P-channel field effect transistor 10626. In this embodiment, the negative impedance conversion circuit 1062 can be composed of the first capacitor 10625, the fourth P-channel field effect transistor 10626, and the third N-channel field effect transistor 10627. The charge and discharge acceleration circuit 1063 can be connected to the pixel driving module 101 through the negative impedance conversion circuit 1062. Figure 6 and Figure 7The same, here will not be too much elaboration. Specifically, in the negative impedance conversion circuit 1062, the source of the fourth P-channel field effect transistor 10626 is connected to the vertical signal line output node VSL_OUT 1103 and one end of the first capacitor 10625, the gate is connected to the bias voltage VB5, and the drain is connected to the third N-channel field effect transistor 10627 and the other end of the first capacitor 10625. The gate of the third N-channel field effect transistor 10627 is connected to the bias voltage VB6 and is used as a current source. The direct current of the fourth P-channel field effect transistor 10626 is set to be slightly equal to the third N-channel field effect transistor 10627. At this time, the fourth P-channel field effect transistor 10626 is used as a current source load common-gate amplifier. At this time, when the vertical signal line output node VSL_OUT 1103 drops Vin=V1, the transconductance of the fourth P-channel field effect transistor 10626 is gm1, ignoring its body effect, and the small-signal resistance of the third N-channel field effect transistor 10627 is ro2, so that the drain voltage of the fourth P-channel field effect transistor 10626 will also drop due to the drop of the source voltage: Vout=gm1*ro2*V1; and then the input current flowing through the first capacitor is:
[0078] Iin=(Vin-Vout)*s*C_NI=(1-gm1*ro2)*V1*s*C_NI;
[0079] At this time, the equivalent input impedance of the negative impedance conversion circuit 1062 is:
[0080] Zin=Vin / Iin=1 / (1-gm1*ro2)*(1 / (s*C_NI));
[0081] When 1<gm1*ro2, the negative impedance conversion circuit 1062 has (1-gm1*ro2) times the equivalent input capacitance of the first capacitor 10625 at this time, and the first capacitor 10625 behaves as a negative capacitance. Through reasonable design of gm1 and ro2, the negative impedance conversion circuit 1062 can have a negative capacitance that can offset the parasitic capacitance 1102, thereby achieving accelerated small-signal establishment speed.
[0082] Referring to Figure 9 , in Figure 8In some embodiments, the negative impedance transformation circuit 1062 uses a common-gate amplifier with an active load to generate a negative capacitance to cancel the load parasitic capacitance 1102 of the vertical signal line node VSL 1007, thus speeding up the small signal settling speed. However, when using a common-gate amplifier, the drain swing of the fourth P-channel field effect transistor 10626 limits the operating point of the negative impedance transformation circuit 1062. For example, when the falling voltage amplitude of the vertical signal line output node VSL_OUT 1103 is large, it forces the fourth P-channel field effect transistor 10626 to turn off, thus disabling the negative impedance transformation circuit 1062. Therefore, in some embodiments, the common-gate amplifier can be replaced with a source follower, and other circuit structures can be used to achieve the same function. Figure 8Consistent, here will not be too much elaboration. In this embodiment, the negative impedance conversion circuit 1062 also includes: a fourth N-channel field effect transistor 10628, the fourth N-channel field effect transistor 10628 replaces the fourth P-channel field effect transistor 10626, the fourth N-channel field effect transistor 10628 gate is electrically connected with the pixel driving module 101, the fourth N-channel field effect transistor 10628 drain is connected with a power supply, and the fourth N-channel field effect transistor 10628 source is electrically connected with the third N-channel field effect transistor 10627 drain. One end of the first capacitor 10625 is electrically connected with the fourth N-channel field effect transistor 10628 source, and the other end of the first capacitor 10625 is electrically connected with the current mirror circuit 1061. That is, in the negative impedance conversion circuit 1062 in this embodiment, the third N-channel field effect transistor 10627 is used as a bias current source of the fourth N-channel field effect transistor 10628; the fourth N-channel field effect transistor 10628 is used as a source follower, the fourth N-channel field effect transistor 10628 gate is connected to the vertical signal line output node VSL_OUT 1103, the fourth N-channel field effect transistor 10628 drain is connected to the power supply, and the fourth N-channel field effect transistor 10628 source is connected to the drain of the third N-channel field effect transistor 10627 and one end of the first capacitor 10625. The other end of the first capacitor 10625 is connected to the source of one N-channel field effect transistor 10611 in the common-source common-gate current mirror circuit 1061. Therefore, in this embodiment, when the vertical signal line output node VSL_OUT 1103 drops Vin=V1, assuming that the input current is Iin and the body effect of the fourth N-channel field effect transistor 10628 is ignored (for example, the substrate is connected to the source), it can be considered that the transfer gain of the source follower at this time is approximately equal to 1. At this time, for the negative impedance conversion circuit 1062 in this embodiment, the transconductance of one N-channel field effect transistor 10611 in the common-source common-gate current mirror circuit 1061 is gm1, the source voltage variation of the N-channel field effect transistor 10611 is Vx, the source voltage variation of the fourth N-channel field effect transistor 10628 is Vy, the output impedance of the third N-channel field effect transistor 10627 is Ro, and the transconductance of the fourth N-channel field effect transistor 10628 is gm2. Then, according to Kirchhoff's current and voltage theorem, the following equation is obtained:
[0083] gm2*(Vin-Vy)+(Vx-Vy) / (1 / (s*C_NI))=Vy / Ro;
[0084] Iin=-gm1*Vx=(Vx-Vy) / (1 / (s*C_NI);
[0085] After transformation and simplification of the above equation set, the following approximate equation is obtained:
[0086] Zin=Vin / Iin=[gm1+gm1*gm2*Ro+s*C_NI*(gm2*Ro+gm1*Ro)] / gm1*gm2*Ro*s*C_NI;
[0087] From the above formula, at this time, the equivalent input impedance of the negative impedance conversion circuit 1062 at low frequency is a negative resistance and a negative capacitance, and the equivalent input impedance at high frequency is a negative resistance, but the resistance value is small; therefore, gm2 and Ro can be reasonably designed according to the actual situation, so that the negative impedance conversion circuit 1062 has a negative capacitance that can offset the parasitic capacitance 1102, thereby realizing the speed of accelerating the establishment of a small signal.
[0088] Referring Figure 1 , the utility model discloses a kind of image sensor readout systems in the second aspect, using the load current source module of any one described in the first aspect, the readout system further include: pixel noise detection module 102, reference ramp generation module 103, comparator 107, counter 108, data transmission module 109, the pixel noise detection module 102 with the pixel drive module 101 is electrically connected, and the pixel noise detection module 102 is used to detect pixel matrix 100 in pixel drive module 101;The reference ramp generation module 103 is electrically connected with the pixel drive module 101 by signal input end 104;The comparator 107 is electrically connected with load current source module 106 and reference ramp generation module by signal output end 105 respectively;The counter 108 is electrically connected with the comparator 107;The data transmission module 109 is electrically connected with the counter 108.The readout system can effectively accelerate the small signal of VSL and the establishment of the large signal of VSL by using the load current source module 106 in the first aspect.
[0089] It should be noted that, in the present readout system, readout work can be carried out by using the negative impedance conversion circuit in the load current source module in Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 That is, in the readout system, the negative impedance conversion circuit in the load current source module in Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 Can be used in combination to realize the offset of the parasitic capacitance or resistance of VSL itself.
[0090] In some embodiments, the readout system can communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol), and can be interconnected with digital data communications (e.g., a communications network) of any form or medium (e.g., wire or wireless, and combinations thereof). Examples of communications networks include local area networks ("LANs"), wide area networks ("WANs"), internetworks (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future developed networks. The functionality described above herein can be performed, at least in part, by one or more hardware logic components. For example, and without limitation, example types of hardware logic components that can be used include field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SOCs), complex programmable logic devices (CPLDs), and the like.
[0091] The utility model discloses still provide a kind of imaging equipment in third aspect, using the load current source module 106 of a kind of image sensor readout described in any one of first aspect or using the image sensor readout system described in second aspect.
[0092] The flow and block diagrams in the drawings illustrate the architecture, functionality, and operations of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flow and block diagrams can represent a module, a segment, or a portion of code, which comprises one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may
[0093] The above description is merely exemplary of some of the many possible embodiments of the present disclosure and of the principles thereof. It is to be understood that those skilled in the art will be able to devise various embodiments of the present disclosure without departing from the scope of the present disclosure as disclosed in the above description and claims. For example, the technical features of the above-described embodiments and the technical features of the embodiments disclosed in the above description (but not limited to) can be combined with each other to form other technical solutions.
Claims
1. An image sensor readout load current source module electrically connected to a pixel matrix in a pixel drive module, characterized by, The application relates to a pixel driving circuit, which comprises the following parts: a current mirror circuit, which is electrically connected with a pixel driving module and is used for providing a bias current; a negative impedance conversion circuit, which is used for generating a negative resistance or a negative capacitance and offsetting a parasitic resistance or a parasitic capacitance of the VSL itself; wherein the negative impedance conversion circuit comprises an amplifier in a negative feedback state; a charge and discharge acceleration circuit, which is used for providing a charge and discharge current during VSL establishment.
2. The load current source module for readout of an image sensor according to claim 1, characterized in that, The current mirror circuit further comprises: two N-channel field effect transistors which are connected through a common source and a common gate, the gate of the N-channel field effect transistor connected through the common source and the common gate is connected with a bias voltage, and the source of the N-channel field effect transistor connected through the common source and the common gate is electrically connected with the pixel driving module, the negative impedance conversion circuit and the charge and discharge acceleration circuit respectively.
3. The load current source module for readout of an image sensor according to claim 1, wherein The charge and discharge acceleration circuit comprises: a voltage-current conversion circuit, one end of which is connected with a drain source voltage, and the voltage-current conversion circuit is used for voltage-current conversion; a current amplification circuit, which is electrically connected with the voltage-current conversion circuit and is used for amplifying the voltage-current conversion current.
4. The load current source module for readout of an image sensor according to claim 3, wherein The voltage-current conversion circuit comprises: a first P-channel field effect transistor, one end of which is connected with a drain source voltage, and the first P-channel field effect transistor is used for providing a current source; a second P-channel field effect transistor, one end of which is also connected with a drain source voltage, and the second P-channel field effect transistor is used for providing a bias current; a capacitor, which is arranged on one side of the second P-channel field effect transistor, is electrically connected with the second P-channel field effect transistor and is a bypass capacitor of the second P-channel field effect transistor; a third P-channel field effect transistor, the gate of which is connected with a vertical signal line signal output node, and the source of the third P-channel field effect transistor is connected with the second P-channel field effect transistor; a first N-channel field effect transistor, which is connected with the second P-channel field effect transistor and is connected with the drain of the third P-channel field effect transistor; a second N-channel field effect transistor, which forms a current mirror with the first N-channel field effect transistor.
5. The load current source module for readout of an image sensor according to claim 4, wherein The amplifier is an operational amplifier, and the negative impedance conversion circuit further comprises: a first resistor, which is electrically connected with the non-inverting input terminal of the amplifier; a second resistor, which is electrically connected with the inverting input terminal of the amplifier; a third resistor, which is electrically connected with the inverting input terminal of the amplifier and is connected with the second resistor in parallel.
6. The load current source module for readout of an image sensor according to claim 5, wherein The negative impedance conversion circuit further comprises: a first capacitor, which replaces the first resistor and is electrically connected with the non-inverting input terminal of the amplifier.
7. The load current source module for readout of an image sensor according to claim 4, wherein The amplifier is a common gate amplifier, and the negative impedance conversion circuit further comprises: a first capacitor, one end of the first capacitor being electrically connected to the pixel driving module; a fourth P-channel field effect transistor, a source of the fourth P-channel field effect transistor being electrically connected to the pixel driving module and electrically connected to the first capacitor, a gate of the fourth P-channel field effect transistor being connected with a bias voltage; a third N-channel field effect transistor, a gate of the third N-channel field effect transistor being electrically connected with a bias voltage, a source of the third N-channel field effect transistor being electrically connected to a drain of the fourth P-channel field effect transistor.
8. The load current source module for readout of an image sensor according to claim 7, wherein, The common-gate amplifier is replaced by a source follower, and the negative impedance conversion circuit further comprises: a fourth N-channel field effect transistor, the fourth N-channel field effect transistor replacing the fourth P-channel field effect transistor, a gate of the fourth N-channel field effect transistor being electrically connected to the pixel driving module, a drain of the fourth N-channel field effect transistor being connected with a power supply, a source of the fourth N-channel field effect transistor being electrically connected to a drain of the third N-channel field effect transistor; wherein one end of the first capacitor is electrically connected to the source of the fourth N-channel field effect transistor, and the other end of the first capacitor is electrically connected to the current mirror circuit.
9. An image sensor readout system, characterized by, An image sensor readout system is provided, and the readout system comprises: a pixel noise detection module, the pixel noise detection module being electrically connected to the pixel driving module, the pixel noise detection module being configured to detect a pixel matrix in the pixel driving module; a reference ramp generation module, the reference ramp generation module being electrically connected to the pixel driving module; a comparator, the comparator being electrically connected to the load current source module and the reference ramp generation module respectively; a counter, the counter being electrically connected to the comparator; a data transmission module, the data transmission module being electrically connected to the counter.
10. An image forming apparatus characterized by comprising: An image sensor readout system is provided, and the readout system comprises: a pixel noise detection module, the pixel noise detection module being electrically connected to the pixel driving module, the pixel noise detection module being configured to detect a pixel matrix in the pixel driving module; a reference ramp generation module, the reference ramp generation module being electrically connected to the pixel driving module; a comparator, the comparator being electrically connected to the load current source module and the reference ramp generation module respectively; a counter, the counter being electrically connected to the comparator; a data transmission module, the data transmission module being electrically connected to the counter. An image sensor readout system is provided, and the readout system comprises: a pixel noise detection module, the pixel noise detection module being electrically connected to the pixel driving module, the pixel noise detection module being configured to detect a pixel matrix in the pixel driving module; a reference ramp generation module, the reference ramp generation module being electrically connected to the pixel driving module; a comparator, the comparator being electrically connected to the load current source module and the reference ramp generation module respectively; a counter, the counter being electrically connected to the comparator; a data transmission module, the data transmission module being electrically connected to the counter.