Nested heat dissipation network structure based on TSV with thick inside and thin outside
By using a nested heat dissipation network structure with coarse inner and fine outer TSVs, the radius and density of TSVs are optimized. Combined with silicon dioxide dielectric and copper heat sink, the heat dissipation problem in three-dimensional integrated circuits is solved, improving integration and thermal stability, and reducing manufacturing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-02
- Publication Date
- 2026-03-27
AI Technical Summary
There are serious heat dissipation problems in existing three-dimensional integrated circuits, which limit their development, especially the thermal stability problem after the system power density increases has not been effectively solved.
A nested heat dissipation network structure with coarse inner and fine outer TSVs is adopted. By setting multiple TSVs on the three-layer power chip and using silicon dioxide dielectric and copper heat sink for heat dissipation, the radius and density of TSVs are optimized to improve heat dissipation efficiency.
This technology enables rapid heat dissipation in 3D integrated circuits, improves system integration and the performance of each functional module, solves the problems of long interconnect lines and high manufacturing costs in planar integration processes, and enhances thermal stability.
Smart Images
Figure CN224054773U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a nested heat dissipation network structure based on inner thick and outer thin TSV. BACKGROUND
[0002] Three-dimensional integration is an important technology to break through the limit of Moore's law, and silicon through hole (TSV) as a conductive channel connecting upper and lower devices is a key component to realize three-dimensional integrated circuit, and its characteristics have a decisive role on the overall performance of three-dimensional integrated circuit.
[0003] TSV mainly functions in two aspects: one is to significantly shorten the interconnection line length, improve the integration degree and performance of the system, and the other is to realize the integration of heterogeneous elements and systems. Another important function of TSV is to serve as a heat dissipation channel to enhance the heat load capacity of three-dimensional integrated system. When using TSV array to dissipate heat inside the chip, appropriate TSV radius, density and spacing need to be set to reduce the influence of thermal stress on carrier mobility, thereby improving the reliability of the chip. The integration of three-dimensional system is beneficial to improve the signal transmission efficiency, but the power density of the system also increases sharply, which will lead to serious heat dissipation problems and become the bottleneck of the development of three-dimensional integrated circuit. Therefore, how to quickly dissipate the temperature of the chip in three-dimensional integrated circuit and realize effective heat transfer has become the key to the development of three-dimensional integrated circuit.
[0004] Therefore, a nested heat dissipation network structure based on inner thick and outer thin TSV is provided. UTILITY MODEL CONTENTS
[0005] The utility model aims at overcoming the defects of the prior art and provides a nested heat dissipation network structure based on inner thick and outer thin TSV, which improves the integration degree of the system and the performance of each functional module, and solves the technical problems of long interconnection line, large layout area and high manufacturing cost in planar integration process.
[0006] The technical scheme for achieving the above-mentioned purpose is:
[0007] A nested heat dissipation network structure based on inner thick and outer thin TSV, comprising: a plurality of power chips and a plurality of TSVs in three layers of upper, middle and lower, each layer of power chip and TSV is bonded with a layer of silicon dioxide medium, and the lowermost layer of silicon dioxide medium is installed on the copper heat sink.
[0008] Preferably, each power chip is embedded with a power cell, each layer contains 5 rows and 5 columns, i.e. 25 power cells, and the upper, middle and lower three layers contain 75 power cells in total.
[0009] Preferably, the TSV is cylindrical.
[0010] Preferably, three circles of the TSVs are arranged around the power chip from the periphery to the center, and the radius of the TSVs gradually increases from the periphery to the center.
[0011] Preferably, the outermost circle has 20 TSVs, the middle circle has 12 TSVs, and the innermost circle has 4 TSVs.
[0012] The utility model discloses a three-dimensional integrated power system based on the nested heat dissipation network structure of the inner thick and outer thin TSV. BRIEF DESCRIPTION OF DRAWINGS
[0013] Figure 1 is a schematic diagram of the utility model of a nested heat dissipation network structure based on the inner thick and outer thin TSV;
[0014] Figure 2 is the top view of the utility model of a nested heat dissipation network structure based on the inner thick and outer thin TSV;
[0015] Figure 3 is the thermal resistance circuit diagram of the power chip and TSV in the utility model.
[0016] In the drawing: 1, power chip;2, TSV;3, silicon dioxide medium;4, copper heat sink;5, power cell. DETAILED DESCRIPTION
[0017] The technical scheme of the utility model will be described clearly and completely below in combination with the drawings. In the description of the utility model, it needs to be explained that the orientation or position relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like is the orientation or position relationship shown in the drawings, and is only for the convenience of describing the utility model and simplifying the description, and cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the utility model. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying the importance of the opposite.
[0018] The utility model will be further described below in combination with the drawings.
[0019] As Figure 1 , 2 shown, a nested heat dissipation network structure based on inner thick and outer thin TSVs, characterized in that it comprises: a plurality of power chips 1 and a plurality of TSVs 2 in three layers of upper, middle and lower, each layer of power chips 1 and TSVs 2 is bonded with a layer of silicon dioxide medium 3, and the lowermost layer of silicon dioxide medium 3 is installed on a copper heat sink 4.
[0020] In the embodiment, each power chip 1 is embedded with a power cell 5, each layer contains 5 rows and 5 columns, a total of 25 power cells 5, and the upper, middle and lower three layers contain a total of 75 power cells 5, each power cell 5 has a power of 1.6W, and the total power is 120W.
[0021] In the embodiment, the TSV 2 is cylindrical.
[0022] In the embodiment, three circles of TSVs 2 are arranged around the power chip 1 from the periphery to the center, and the radius of the TSV 2 gradually thickens from the periphery to the center.
[0023] In the embodiment, there are a total of 20 TSVs 2 in the outermost circle, 12 TSVs 2 in the middle circle, and 4 TSVs 2 in the innermost circle.
[0024] As Figure 2 can be seen, there are four TSVs 2 around each power chip 1, and the spacing of each power chip 1 is adjusted according to the size of the TSV diameter and the safety distance, the heat source is a volume heat source, and the actual heat path of the heat source will be shortened, and the heat path is approximately considered to be shortened to half the longitudinal thickness of the heat source; as Figure 3 shown, RSi1e, RSi2e, RSi3e, and RSi4e are the oblique thermal resistance of the silicon substrate, also known as the segmented equivalent thermal resistance of the power chip 1; RTSV1, RTSV2, RTSV3, RTSV4, and RTSV5 are the TSV thermal resistances after five equal divisions of the TSV 2.
[0025] In the embodiment, firstly, the uniform TSV 2 is optimized, that is, the radii of the TSV 2 of the three layers of power chips 1 in the inner-thick-outer-thin TSV heat dissipation model are set to be the same, and for the 3D power IC (integrated circuit) with the uniform TSV 2, the radius, density and pitch of the TSV 2 are changed respectively, and the simulation is performed respectively, the temperature curves of the three layers of power chips 1 in the 3D power IC with the change of the radius, density and pitch of the TSV 2 are obtained, the three curves are analyzed, and the radius, pitch and density of the TSV 2 with better heat dissipation are obtained, the radius of the TSV 2 is taken as the radius of the outermost TSV in each layer of power chips 1 in the inner-thick-outer-thin TSV model, the pitch and density of the TSV 2 in the inner-thick-outer-thin TSV model are consistent with the pitch and density of the optimized uniform TSV 2, and the radius of the TSV 2 in each layer of power chips 1 is increased from the outer periphery to the inner periphery, that is, the radius of the outermost TSV 2 is the thinnest, and the radius of the central (inner periphery) TSV 2 is the thickest.
[0026] Secondly, the inner-thick-outer-thin TSV heat dissipation model is optimized and designed. The optimization and design of the uniform TSV 2 obtain the radius of the uniform TSV 2, the radius of the TSV 2 is selected as the radius of the outermost TSV 2 in each layer of power chips 1 in the three-dimensional power IC, the radius of the TSV 2 in each layer of chips is increased from the outer periphery to the inner periphery, and the simulation optimization is performed respectively, the temperature curves of the three layers of power chips 1 in the 3D power IC with the change of the radius of the TSV 2 in each layer of power chips 1 in the inner-thick-outer-thin TSV heat dissipation model are obtained, the two curves are analyzed, and the radius of the TSV 2 of each layer of power chips 1 with better heat dissipation is obtained.
[0027] After the optimization of the TSV 2 in each layer of power chips 1 is completed, the copper heat sink 4 is further optimized, according to the optimization of the radius of the uniform TSV 2 and the inner-thick-outer-thin TSV 2, the radius of the TSV 2 in the three layers of power chips 1 in the 3D power IC is set to be: the radius of the outermost TSV 2 in each layer of chips is the radius of the optimized uniform TSV 2, the radius of the TSV 2 from the outer periphery to the inner periphery is increased from the outer periphery to the inner periphery, and the radius of the TSV 2 with the best heat dissipation effect obtained by the simulation optimization is obtained. This model is set as a nested heat dissipation model based on the inner-thick-outer-thin TSV 2, and then the copper heat sink 4 under the lower layer of power chips 1 is optimized and designed. The optimization and design of the copper heat sink 4 mainly increase the cross-sectional area of the copper heat sink 4, that is, the number of fins of the copper heat sink 4 is increased, and the heat dissipation effect is improved.
[0028] The above embodiments are only used to illustrate the technical solutions of the present application, and are not limited thereto; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A nested heat dissipation network structure based on inner thick and outer thin TSVs, characterized in that, Comprise: Multiple power chips (1) and multiple TSVs (2) in three layers, each layer of the power chip (1) and TSV (2) is bonded with a layer of silicon dioxide medium (3), the lowermost layer of the silicon dioxide medium (3) is installed on the copper heat sink (4); Each of the power chips (1) is embedded with a power cell (5), each layer contains 5 rows and 5 columns, a total of 25 power cells (5), and a total of 75 power cells (5) in the upper, middle and lower three layers.
2. The nested heat dissipation network structure based on the inner coarse and outer fine TSV according to claim 1, characterized in that, The TSV (2) is cylindrical.
3. The nested heat dissipation network structure based on TSVs with thick inner and thin outer according to claim 1, characterized in that, Three circles of TSVs (2) are arranged around the power chip (1) from the periphery to the center, and the radius of the TSV (2) gradually thickens from the periphery to the center.
4. The nested heat dissipation network structure based on TSVs with thick inner and thin outer according to claim 1, characterized in that, There are a total of 20 TSVs (2) in the outermost circle, 12 TSVs (2) in the middle circle, and 4 TSVs (2) in the innermost circle.