Multi-layer chip stacking packaging structure

Abstract

The utility model relates to the field of semiconductor packaging, in particular to a multi-layer chip stacking packaging structure. Comprising a supporting frame and an electric protruding block, the positioning protruding block is used for ensuring that chips can be accurately aligned during stacking, the supporting frame is used for supporting during stacking of the chips, poor electric connection caused by deformation and collapse of the electric protruding block due to excessive extrusion is prevented, and chip displacement caused by external force or vibration is also prevented. According to the packaging structure, the supporting frame and the positioning protruding block are matched, on one hand, the stacking precision is improved, the electrical connection problem caused by inaccurate alignment is reduced, on the other hand, chip displacement caused by external force or vibration in the stacking process of the packaging structure is prevented, supporting and alignment in the chip stacking process are considered, and the packaging quality is improved. Therefore, poor electrical connection caused by deformation and collapse of the electrical bumps due to excessive extrusion is prevented, displacement of the chips in the stacking process is also prevented, and the stability of the packaging structure is ensured.

Description

TECHNICAL FIELD

[0001] The utility model relates to the field of semiconductor packaging, especially to a multilayer chip stack packaging structure. BACKGROUND

[0002] With the development of electronic equipment to miniaturization and high performance, higher requirements are put forward for chip packaging technology. However, in the existing chip stacking process, too small pressure will lead to poor welding, such as tin ball falling off, interface peeling and other problems, which seriously affect the electrical connection and structural stability between chips; too large pressure will also lead to excessive deformation of tin ball extrusion, affecting the welding quality, and even possibly damaging the chip. Moreover, when performing multilayer chip stacking welding, there are differences in the size of the welding bumps between different layers of chips, and the temperature at which each layer of chips is located is also different, making the pressure size control problem more complex. Therefore, how to reasonably and accurately realize the stability of the packaging structure during the chip stacking process is a very challenging problem. SUMMARY

[0003] To solve the above technical problems, the utility model provides a multilayer chip stack packaging structure.

[0004] The multilayer chip stack packaging structure provided by the present application comprises:

[0005] A multilayer chip packaging structure composed of a substrate and a plurality of chip structures;

[0006] The multilayer chip packaging structure is located on the first surface of the substrate;

[0007] The chip structure comprises a chip, a support frame, an electrical bump and a positioning bump;

[0008] The first surface of the chip comprises a positioning support area and an electrical connection area, the positioning support area is located on the edges of the opposite sides of the first surface of the chip, and the electrical connection area is located on the area of the first surface of the chip except the positioning support area; the electrical bump is located in the electrical connection area of the first surface of the chip and is used for electrically connecting the first surface of the substrate or the second surface of the chip in the next layer of chip structure; the positioning bump is located in the positioning support area of the first surface of the chip; the support frame comprises a first part and a second part of the support frame, the first part of the support frame is located in the positioning support area of the first surface of the chip and the chip is arranged on the surface of the first part of the support frame, the second part of the support frame is located on the outer edge of the chip, the first part of the support frame comprises a through hole of the support frame, the positioning bump is located in the through hole of the support frame, and the positioning bump and the support frame cooperate to support and align each layer of the chip structure.

[0009] Optionally, the second part of the support frame is in a whole structure or a hollow structure.

[0010] Optionally, the hollow structure is in a comb shape.

[0011] Optionally, the support frame corresponding to the chip structure in the same layer is arranged in an axial symmetry or in a staggered manner.

[0012] Optionally, the second part of the support frame in adjacent layers is arranged in contact or not in contact.

[0013] Optionally, the support frame comprises one of a metal support frame, a ceramic support frame.

[0014] Optionally, the support frame is in an L shape.

[0015] Optionally, the chip comprises a through silicon via, the substrate comprises a conductive circuit, the through silicon via of the chip is used for electrically connecting with the electric bump, and the conductive circuit of the substrate is used for electrically connecting with the multilayer chip package structure.

[0016] Optionally, the substrate comprises a heat dissipation channel, the heat dissipation channel is located directly below the support frame, and the support frame is cooled.

[0017] Optionally, the multilayer chip stack package structure further comprises a plastic encapsulation material layer, the plastic encapsulation material layer is located between the chips, between the chip and the substrate, and on the surface of the multilayer chip package structure.

[0018] Optionally, the second surface of the substrate is provided with an electric bump for electrically connecting the multilayer chip stack package structure with an external device.

[0019] In conclusion, the advantages and beneficial effects of the utility model are as follows:

[0020] The application provides a multi-layer chip stack packaging structure, comprising a substrate, a multi-layer chip packaging structure composed of a plurality of chip structures; the multi-layer chip packaging structure is located on a first surface of the substrate; the chip structure comprises a chip, a support frame, an electrical bump and a positioning bump; a first surface of the chip comprises a positioning support area and an electrical connection area, the positioning support area is located on edges of opposite sides of the first surface of the chip, and the electrical connection area is located on an area other than the positioning support area on the first surface of the chip; the electrical bump is located on the electrical connection area of the first surface of the chip and is used for electrically connecting a first surface of the substrate or a second surface of a chip in a next layer of chip structure; the positioning bump is located on the positioning support area of the first surface of the chip; the support frame comprises a first part and a second part of the support frame, a surface of the first part of the support frame is located on the positioning support area of the first surface of the chip, and the chip is arranged on the surface of the first part of the support frame; the second part of the support frame is located on an outer edge of the chip; the first part of the support frame comprises a support frame through hole, the positioning bump is located in the support frame through hole, and the positioning bump and the support frame are matched to support and align each layer of the chip structure.

[0021] The positioning bump is used for ensuring that the chip can be accurately aligned when being stacked, the support frame is used for supporting the chip when being stacked, prevents the electrical bump from being excessively extruded and deformed and collapsed, causes poor electrical connection, and also prevents the chip from being displaced due to external force or vibration. By matching the support frame and the positioning bump, on the one hand, the stacking accuracy is improved, and the electrical connection problem caused by inaccurate alignment is reduced. On the other hand, the chip is prevented from being displaced due to external force or vibration in the stacking process of the packaging structure, the support and alignment in the stacking process of the chip are realized, the electrical bump is prevented from being excessively extruded and deformed and collapsed, causes poor electrical connection, the chip is prevented from being displaced in the stacking process, and the stability of the packaging structure is ensured.

[0022] In addition, the support frame and the positioning bump are arranged on edges of opposite sides of the chip, so that the chip can be stably supported, the flowability of plastic sealing material between subsequent chips is not affected, and the reliability and yield of the packaging structure are improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 A cross-sectional schematic view of a multi-layer chip stack packaging structure provided by the embodiment of the application is shown in the figure;

[0024] Figures 2-5 A top view schematic view of a multi-layer chip stack packaging structure provided by the embodiment of the application is shown in the figure;

[0025] Figures 6-8A schematic diagram of a multilayer chip stack packaging structure is provided for another embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical scheme and advantages of the present application clearer, the technical scheme of the present application will be described clearly and completely in combination with the specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0027] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present application, and cannot be understood as a limitation on the present application.

[0028] The present application provides a multilayer chip stack packaging structure, as shown in the drawings, comprising: Figure 1

[0029] A multilayer chip packaging structure 200 composed of a substrate 100 and a plurality of chip structures;

[0030] The multilayer chip packaging structure 200 is located on the first surface of the substrate 100;

[0031] The chip structure comprises a chip 10, a support frame 20, an electrical bump 30 and a positioning bump 40;

[0032] ​The first surface of the chip includes a positioning support area 12 and an electrical connection area 11. The positioning support area 12 is located at the edges of the opposite sides of the first surface of the chip. The electrical connection area 11 is located at the area of the first surface of the chip other than the positioning support area. The electrical bump 30 is located at the electrical connection area 11 of the first surface of the chip, and is used to electrically connect the first surface of the substrate 100 or the second surface of the chip in the chip structure of the next layer. The positioning bump 40 is located at the positioning support area 12 of the first surface of the chip. The support frame 20 includes a first support frame part 21 and a second support frame part 22. The first support frame part 21 is located at the positioning support area 12 of the first surface of the chip, and the chip 10 is arranged on the surface of the first support frame part 21. The second support frame part 22 is located at the outer side edge of the chip 10. The first support frame part 21 includes a support frame through hole. The positioning bump 40 is located in the support frame through hole. The positioning bump 40 and the support frame 20 are matched to support and align each layer of the chip structure.

[0033] Specifically, in the embodiment, the substrate 100 is a silicon substrate, a silicon carbide substrate, a sapphire substrate, a copper-clad laminate, a redistribution layer, or other suitable packaging substrate. The substrate 100 includes a first surface and a second surface. The multilayer chip package structure 200 is located on the first surface of the substrate 100. The second surface of the substrate 100 has conductive bumps for electrically connecting the multilayer chip stack package structure 200 with external devices.

[0034] In the embodiment, there is a bonding layer (not shown) between the positioning bump and the first surface of the substrate or the second surface of the chip, so that the positioning bump is bonded to the first surface of the substrate or the second surface of the chip. The positioning bump is used to ensure accurate alignment between different layers of the chip when the chip is stacked.

[0035] In the embodiment, the thickness of the positioning bump 40 is the same as the thickness of the first support frame part 21.

[0036] In other embodiments, the thickness of the positioning bump is smaller than the thickness of the first support frame part.

[0037] In the embodiment, one side opposite to the surface of the first support frame part is the first surface of the chip, and the other side opposite to it is the second surface of the chip. The first surface of the chip includes a positioning support area 12 and an electrical connection area 11. The positioning support area 12 is located at the edges of the opposite sides of the first surface of the chip. The electrical connection area 11 is located at the area of the first surface of the chip other than the positioning support area.

[0038] In the embodiment, the chip 10 in the chip structure is directly placed on the surface of the support frame first part 21 and in contact with the inner side of the support frame second part 22, so that the chip 10 is just placed between the support frames on both sides of the same layer.

[0039] The support frame 20 is used for support when the chips are stacked, preventing the electrical bumps from being excessively pressed and deformed, collapsed, resulting in poor electrical connection, and preventing the chips from being displaced due to external force or vibration. The support frame 20 includes a support frame first part 21 and a support frame second part 22, which are in L-shaped structure. The support frame first part 21 is located in the positioning support area 12 of the first surface of the chip, and the chip 10 is arranged on the surface of the support frame first part 21. The support frame second part 22 is located at the outer side edge of the chip 10. The support frame first part includes a support frame through hole, and the positioning bump 40 is located in the support frame through hole. The positioning bump 40 and the support frame 20 cooperate to support and align each layer of the chip structure.

[0040] In the embodiment, the surface of the support frame first part 21 opposite to the first surface of the chip serves as the first surface of the support frame 20, and the opposite surface serves as the other surface of the support frame 20. The other surface of the support frame 20 has a bonding layer between the first surface of the substrate 100 or the second surface of the chip in the next layer of chip structure, so that the support frame and the first surface of the substrate 100 or the second surface of the chip in the next layer of chip structure are bonded, the support frame is fixed, and further displacement of the chips during stacking is prevented.

[0041] In one embodiment, when the multilayer chip package structure includes two layers of chip structures, the electrical bumps on the first surface of the chip on the surface layer are electrically connected to the second surface of the chip on the next layer, and the electrical bumps on the first surface of the chip on the next layer are electrically connected to the first surface of the substrate.

[0042] In other embodiments, the other surface of the support frame and the first surface of the substrate or the second surface of the chip in the next layer of chip structure are not bonded, and the support frame is directly placed on the first surface of the substrate or the second surface of the chip in the next layer of chip structure.

[0043] Figure 2 The cross-sectional view along the AA' direction is Figure 3 The cross-sectional view along the BB' direction is the embodiment.

[0044] In one embodiment, as Figure 2As shown, the second part 22 of the support frame is a comb-shaped hollow structure, so that the area of the second part 22 of the support frame is relatively small, to disperse the stress generated in the stacking process, to avoid the chip damage, and to save the material of the support frame and reduce the packaging cost.

[0045] In another embodiment, as shown in Figures 3-4 the second part of the support frame is a whole structure.

[0046] In other embodiments, the second part of the support frame is designed as other suitable structures according to needs.

[0047] In an embodiment, as shown in Figure 2 the support frame corresponding to the chip structure of the same layer is arranged in axial symmetry.

[0048] In another embodiment, as shown in Figure 5 the support frame corresponding to the chip structure of the same layer is arranged in misalignment.

[0049] In the present embodiment, as shown in Figure 1 the second parts 22 of the support frames of adjacent layers are arranged in contact, so that another surface of the second part of the support frame is in contact with the surface of the second part of the support frame in the chip structure of the next layer.

[0050] In another embodiment, as shown in Figure 7 the second parts of the support frames of adjacent layers are not in contact, so that there is a gap between the second parts of the support frames of adjacent layers.

[0051] In the present embodiment, the support frame 20 is a metal support frame, which is helpful to improve the heat dissipation capacity of the packaging structure and improve the reliability of welding due to the good heat conduction performance of metal.

[0052] In another embodiment, the support frame is a ceramic support frame or other suitable material for support.

[0053] The present application sets the positioning bump 40 in the through hole of the support frame, so that the support frame 20 and the positioning bump 40 cooperate, on the one hand, to improve the stacking accuracy and reduce the problem of poor electrical connection caused by inaccurate alignment, on the other hand, to prevent the positioning bump 40 from being excessively extruded and deformed or collapsed during stacking, to cause poor electrical connection and displacement of the chip during stacking, to ensure the stability of the packaging structure, and to achieve the support and alignment during the chip stacking process.

[0054] In addition, the support frame 20 and the positioning bump 40 are arranged at the edges of the opposite sides of the chip, which can stably support the chip and can not affect the flowability of the plastic encapsulating material between the chips, to improve the reliability of the packaging structure.

[0055] In this embodiment, the electrical bumps 30 are located on the first surface of the chip, and the electrical connection between chips is achieved through the electrical bumps 40.

[0056] In this embodiment, the material of the electrical bumps 30 is tin, gold or other suitable conductive material.

[0057] In this embodiment, the electrical bumps 30 are tin balls.

[0058] In other embodiments, the electrical bumps are gold bumps or other suitable conductive bumps.

[0059] In this embodiment, the chip 10 includes a through-silicon via 60 and the substrate 100 includes a conductive circuit, the through-silicon via of the chip 10 and the electrical bumps on the first surface of the chip are electrically connected, and the conductive circuit of the substrate is used to electrically connect the multi-layer chip package structure 200.

[0060] In this embodiment, as shown in Figure 6 , the substrate 100 is provided with a heat dissipation channel 50, which is located below the support frame 20, and the support frame 20 is cooled through the heat dissipation channel 50.

[0061] In another embodiment, the heat dissipation channel is a conductive column structure.

[0062] In another embodiment, the material of the heat dissipation channel and the material of the conductive circuit of the substrate are the same and are formed in the same preparation process.

[0063] In other embodiments, the materials and preparation processes of the heat dissipation channel and the conductive circuit of the substrate can also be different.

[0064] In this embodiment, as shown in Figure 6 , when the substrate has a heat dissipation channel, the second surface of the substrate and the position of the heat dissipation channel have conductive bumps, which are used to connect with external heat dissipation structures, and are used to cool the chips through the heat conduction of the support frame chips.

[0065] In this embodiment, as shown in Figure 1 , Figure 6 , Figure 7 , the second surface of the substrate 100 is provided with conductive bumps, which are used to electrically connect the multi-layer chip stack package structure and external devices.

[0066] In this embodiment, as shown in Figure 8As shown, the multilayer chip stack package structure further comprises a plastic encapsulation material layer 300, which is located between the chips, between the chips and the substrate, and on the surface of the multilayer chip package structure.

[0067] When the chips are stacked and encapsulated by the plastic encapsulation material to form the multilayer chip stack package structure, the support frame and the positioning bump are located on the opposite sides of the chips, the plastic encapsulation material is injected from the other two sides of the chips, and the flowability of the plastic encapsulation material between the chips and between the chips and the substrate is not affected, thereby ensuring the reliability of encapsulation.

[0068] The multilayer chip stack package structure improves the precise positioning and support between the chips in each layer of the multilayer chip package structure through cooperation of the support frame and the positioning bump, improves the performance and integration of the package structure, meets the demand of modern electronic equipment for miniaturization and high performance, and at the same time, through different designs of the support frame, the heat dissipation capacity and reliability of encapsulation are enhanced, thereby meeting the demand of modern electronic equipment for high performance and high reliability.

[0069] The utility model also provides a kind of preparation method of multilayer chip stack package structure, comprising:

[0070] Step S10, provide substrate, a plurality of chips formed with electrical bump, positioning bump, support frame, the first surface of the chip includes positioning support area and electrical connection area, the positioning support area is located on the edge of the opposite side of the first surface of the chip, the electrical connection area is located in the area except the positioning support area on the first surface of the chip, the electrical bump is located in the electrical connection area of the chip, the support frame has support frame first part and support frame second part, the support frame first part has support frame through hole;

[0071] In the embodiment, the positioning support area is arranged on the edge of the opposite side of the chip, so that the subsequent elastic support frame and the positioning bump are located on the edge of the opposite side of the chip, which can stably support the chip and does not affect the flowability of the plastic encapsulation material between the subsequent chips and between the chip and the substrate, thereby improving the reliability of the package structure.

[0072] Step S20, form positioning bump in the positioning support area of the first surface of the substrate, and the positioning bump is used for precise alignment of the chip.

[0073] In the embodiment, the positioning bump is formed on the first surface of the substrate in a pasting manner, and the positioning bump is used to ensure the precise alignment between the chips when the chips are stacked.

[0074] Step S30, the support frame through hole is matched with the positioning boss, and the support frame is arranged on the surface of the substrate, the first part of the support frame corresponding to the chip structure of the same layer is arranged oppositely, and the second part of the support frame is arranged away;

[0075] In the embodiment, the support frame through hole is sleeved on the positioning boss, and the positioning boss and the support frame are matched.

[0076] In the embodiment, the support frame and the substrate are formed with a sticking layer, and the support frame is stuck.

[0077] In other embodiments, the support frame is directly sleeved on the positioning boss and placed on the surface of the substrate.

[0078] In the embodiment, the support frame is used for supporting the chip stacking, prevents the electrical bump from being excessively extruded and deformed and collapsed, causes the electrical connection to be poor, and also prevents the chip from being displaced due to external force or vibration.

[0079] In the embodiment, the support frame and the positioning boss are located on the opposite side edges of the first surface of the subsequent chip, can stably support the chip, can not affect the flowability of the plastic sealing material between the subsequent chips, and improves the reliability of the packaging structure.

[0080] Step S40, the positioning and supporting area of the first surface of the chip is placed on the surface of the first part of the support frame, the chip and the inner side of the second part of the support frame are in contact, and the electrical bump of the first surface of the chip is located on the first surface of the substrate.

[0081] Step S50, the substrate with the support frame, the positioning boss and the chip formed on the surface is fixed and welded to form a first layer of chip structure.

[0082] In the embodiment, after welding, the chip and the substrate are fixed and electrically connected to form a first layer of chip structure.

[0083] By arranging the positioning boss in the support frame through hole, the support frame and the positioning boss are matched, on the one hand, the stacking accuracy is improved, and the problem of poor electrical connection caused by inaccurate alignment is reduced, on the other hand, the electrical bump is prevented from being excessively extruded and deformed and collapsed, causes the electrical connection to be poor, also prevents the chip from being displaced during the stacking process, ensures the stability of the packaging structure, and realizes the support and alignment during the chip stacking process.

[0084] Step S60, the above steps are repeated to complete the stacking of a plurality of layers of chip structures to form a multi-layer chip packaging structure.

[0085] Step S70, injecting plastic sealing material between the chips, between the chip and the substrate, around the multi-layer chip packaging structure to form a multi-layer chip stack packaging structure.

[0086] When the chips are stacked and encapsulated by the plastic sealing material to form the multi-layer chip stack packaging structure, the support frame and the positioning bump are located on the opposite sides of the chips, the plastic sealing material is injected from the other two sides of the chips, and the flowability of the plastic sealing material between the chips is not affected, thereby ensuring the reliability of the plastic sealing.

[0087] Finally, it should be noted that any modification or equivalent replacement of part or all of the technical features of the technical solutions of the device structure and the embodiments described above, as long as the essence does not deviate from the corresponding technical solutions of the device structure and the embodiments described above, belongs to the patent range of the device structure and the embodiments described above.

Claims

1. A multi-chip package-on-package structure, comprising: The application relates to a multi-layer chip package structure, comprising: a substrate and a plurality of chip structures; the multi-layer chip package structure is located on a first surface of the substrate; the chip structure comprises a chip, a support frame, an electrical bump and a positioning bump; a first surface of the chip comprises a positioning support area and an electrical connection area, the positioning support area is located on the edges of the opposite sides of the first surface of the chip, and the electrical connection area is located on the area of the first surface of the chip except the positioning support area; the electrical bump is located on the electrical connection area of the first surface of the chip and is used for electrically connecting the first surface of the substrate or the second surface of the chip in the next layer chip structure; the positioning bump is located on the positioning support area of the first surface of the chip; the support frame comprises a first part and a second part, the first part is located on the positioning support area of the first surface of the chip and the chip is arranged on the surface of the first part, the second part is located on the outer edge of the chip, the first part comprises a support frame through hole, the positioning bump is located in the support frame through hole, and the positioning bump and the support frame are matched to support and align each chip structure.

2. The multi-chip stacked package structure of claim 1, wherein, The second part of the support frame is in an integral structure or a hollow structure.

3. The multi-chip stacked package structure of claim 2, wherein, The hollow structure is in a comb shape.

4. The multi-chip stacked package structure of claim 1, wherein, The support frame corresponding to the chip structure in the same layer is arranged in axial symmetry or misalignment.

5. The multi-chip stacked package structure of claim 1, wherein, The second parts of the support frames of adjacent layers are arranged in contact or not in contact.

6. The multi-chip stacked package structure of claim 1, wherein, The support frame comprises one of a metal support frame and a ceramic support frame.

7. The multi-chip stacked package structure of claim 1, wherein, The support frame is in an L-shaped structure.

8. The multi-chip stacked package structure of claim 1, wherein, The chip comprises a through silicon via, and the substrate comprises a conductive circuit, the through silicon via of the chip is used for electrically connecting the electrical bump, and the conductive circuit of the substrate is used for electrically connecting the multi-layer chip package structure.

9. The multi-chip stacked package structure of claim 8, wherein, The substrate further comprises a heat dissipation channel, the heat dissipation channel is located directly below the support frame and dissipates heat for the support frame.

10. The multi-chip stacked package structure of claim 9, wherein, The heat dissipation channel is in a conductive column structure.

11. The multi-chip stacked package structure of claim 1, wherein, The application further comprises a plastic sealing material layer, the plastic sealing material layer is located between the chips, between the chip and the substrate and on the surface of the multi-layer chip package structure.

12. The multi-chip stacked package structure of claim 1, wherein, A second surface of the substrate is provided with a conductive bump and is used for electrically connecting the multi-layer chip package structure and external devices.

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