Deposition mask and electronic device

Abstract

The utility model relates to a deposition mask and an electronic device. The deposition mask includes: a mask frame having cell openings and including rib regions defining the cell openings; the diaphragm comprises a unit area located above the unit opening and a grid area located on the rib area; and a plurality of first scale patterns overlapping the rib region in a thickness direction of the mask frame, the plurality of first scale patterns being located at the mesh region and spaced apart from each other by a first gap along a first direction traversing the diaphragm.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0070882, filed on May 30, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to deposition masks and electronic devices manufactured using deposition masks. Background Technology

[0004] Wearable devices that focus at a distance close to the user's eyes have been developed in the form of glasses or helmets. For example, wearable devices can be head-mounted displays (HMDs) and / or augmented reality (AR) glasses. Wearable devices can provide users with augmented reality (hereinafter referred to as "AR") or virtual reality (hereinafter referred to as "VR") visuals.

[0005] For wearable devices such as HMDs or AR glasses, display specifications of approximately 3000 PPI (pixels per inch) or higher are required to allow users to use the wearable device for extended periods without experiencing dizziness. For this purpose, organic light-emitting diodes on silicon (OLEDoS) technology, used in high-resolution, small organic light-emitting display devices, is emerging. OLEDoS is a technology that places organic light-emitting diodes (OLEDs) on a semiconductor wafer substrate on which complementary metal-oxide-semiconductor (CMOS) elements are disposed.

[0006] To manufacture display panels with a high resolution of approximately 3000 PPI or higher, a high-resolution deposition mask is required. For example, a deposition mask can be manufactured by forming a diaphragm (also known as a "mask film") with multiple pixel openings on a substrate and partially etching the substrate to form cell openings that expose the multiple pixel openings. However, after manufacturing the aforementioned deposition mask, warping or deformation may occur due to residual stress within the diaphragm and / or differences in the coefficient of thermal expansion between the substrate and the diaphragm. Utility Model Content

[0007] Aspects and features of embodiments of this disclosure provide an improved deposition mask that allows for the measurement of warpage or deformation, and electronic devices manufactured using said deposition mask.

[0008] However, this disclosure is not limited to the embodiments set forth herein. The above and other embodiments of this disclosure will become more apparent to those skilled in the art from the detailed description of this disclosure that follows.

[0009] According to one or more embodiments of the present disclosure, a deposition mask includes: a mask frame having a cell opening and including a rib region defining the cell opening; a diaphragm including a cell region located above the cell opening and a grid region on the rib region; and a plurality of first scale patterns overlapping the rib region in the thickness direction of the mask frame, the plurality of first scale patterns being located at the grid region and spaced apart from each other by a first gap along a first direction traversing the diaphragm.

[0010] A first direction extends through the central portion of the diaphragm, and each of the plurality of first scale patterns extends in a second direction intersecting the first direction.

[0011] The deposition mask also includes a plurality of third scale patterns that overlap with the rib region in the thickness direction of the mask frame and are located between a plurality of first scale patterns along a first direction with a second gap smaller than the first gap.

[0012] The deposition mask also includes a plurality of second scale patterns that overlap with the rib region in the thickness direction of the mask frame. The plurality of second scale patterns are located in the grid region and are spaced apart from each other with a first gap along a second direction that intersects the first direction.

[0013] The second direction extends through the central portion of the diaphragm, and each of the plurality of second scale patterns extends in the first direction.

[0014] The deposition mask also includes a plurality of fourth scale patterns that overlap with the rib region in the thickness direction of the mask frame and are located between a plurality of second scale patterns along the second direction with a second gap smaller than the first gap.

[0015] The diaphragm comprises inorganic materials, and multiple first-scale patterns comprise metallic materials.

[0016] When multiple first ruler patterns are in the grid area, the multiple first ruler patterns have a thickness equal to the thickness of the grid area.

[0017] When multiple first ruler patterns are on the grid area, the multiple first ruler patterns have a thickness equal to or less than the thickness of the grid area.

[0018] When the mask frame includes a substrate and an inorganic film on the substrate, the cell openings expose the cell regions through the substrate and the inorganic film, respectively, and the cell regions have multiple pixel openings communicating with the cell openings.

[0019] The deposition mask also includes a first reinforcing pattern that overlaps with the rib region in the thickness direction of the mask frame, extends along the first direction, and is located in the grid region.

[0020] Each of the plurality of first scale patterns extends from the first reinforcing pattern in a second direction intersecting the first direction.

[0021] Multiple first scale patterns and first reinforcing patterns are made of the same material.

[0022] In one or more embodiments, the deposition mask includes: a mask frame having cell openings and including rib regions defining the cell openings; a diaphragm including cell regions located above the cell openings and grid regions on the rib regions; a plurality of first scale patterns overlapping the rib regions in the thickness direction of the mask frame and located at first intervals in the grid regions along a first direction traversing the central portion of the diaphragm; and a plurality of second scale patterns overlapping the rib regions in the thickness direction of the mask frame and located at first intervals in the grid regions along a second direction intersecting the first direction and traversing the central portion of the diaphragm.

[0023] Each of the plurality of first ruler patterns extends in the second direction, and each of the plurality of second ruler patterns extends in the first direction.

[0024] The deposition mask further includes: a plurality of third scale patterns that overlap with the rib region in the thickness direction of the mask frame and are located between the plurality of first scale patterns with a second gap smaller than the first gap along the first direction; and a plurality of fourth scale patterns that overlap with the rib region in the thickness direction of the mask frame and are located between the plurality of second scale patterns with a second gap along the second direction.

[0025] Multiple first-scale patterns and multiple second-scale patterns have a thickness equal to the thickness of the grid area.

[0026] The deposition mask further includes: a first reinforcing pattern that overlaps with the rib region in the thickness direction of the mask frame, extends along a first direction and is located in the grid region; and a second reinforcing pattern that overlaps with the rib region in the thickness direction of the mask frame, extends along a second direction and is located in the grid region.

[0027] Each of the plurality of first scale patterns extends from the first reinforcing pattern in a second direction, and each of the plurality of second scale patterns extends from the second reinforcing pattern in a first direction.

[0028] Multiple first scale patterns and first reinforcing patterns are made of the same material, and multiple second scale patterns and second reinforcing patterns are made of the same material.

[0029] In one or more embodiments, an electronic device includes a display panel comprising a substrate and a plurality of light-emitting layers formed on the substrate using a deposition mask. The deposition mask includes a mask frame having cell openings and including rib regions defining the cell openings, a diaphragm including grid regions located above the cell openings and on the rib regions, respectively, and a plurality of first scale patterns overlapping the rib regions in the thickness direction of the mask frame, the plurality of first scale patterns being located at the grid regions and spaced apart from each other by a first gap along a first direction traversing the diaphragm.

[0030] According to the above embodiments, multiple scale patterns can be arranged in or on the grid area of ​​the diaphragm, and therefore, the warpage and / or deformation of the deposition mask can be accurately measured using a simple vision camera without the need for a separate measuring device.

[0031] Other features and embodiments may be apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0032] The above and other aspects and features of this disclosure will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 This is an exploded perspective view of the display device;

[0034] Figure 2 It is used for explanation Figure 1 Block diagram of the display device shown;

[0035] Figure 3 It is used for explanation Figure 2 The equivalent circuit diagram of the example of the first sub-pixel shown;

[0036] Figure 4 It is shown Figure 1 A schematic floor plan of an example of a display panel shown;

[0037] Figure 5 It is shown Figure 4 A schematic floor plan of an example of the display area shown;

[0038] Figure 6 It is shown Figure 4 A schematic floor plan of another example of the display area shown;

[0039] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I-I';

[0040] Figure 8 This is a schematic perspective view showing an example of a head-mounted display;

[0041] Figure 9 It is shown Figure 8 A schematic exploded perspective view of an example of a head-mounted display shown;

[0042] Figure 10 This is a schematic perspective view showing another example of a head-mounted display;

[0043] Figure 11 This is a schematic plan view illustrating a deposition mask according to one or more embodiments of the present disclosure;

[0044] Figure 12 It is shown Figure 11 A schematic enlarged plan view of the unit area and scale pattern shown;

[0045] Figure 13 It is along Figure 12 A schematic cross-sectional view taken by line II-II' shown in the figure;

[0046] Figure 14 It is along Figure 12 A schematic cross-sectional view taken by line III-III' shown in the figure;

[0047] Figure 15 This is a cross-sectional view showing a deposition mask according to one or more embodiments of the present disclosure;

[0048] Figure 16 This is a plan view showing a deposition mask according to yet another embodiment of the present disclosure; and

[0049] Figure 17 It is shown Figure 16 A schematic enlarged plan view of the cell area and scale pattern shown. Detailed Implementation

[0050] Embodiments will now be described more fully below with reference to the accompanying drawings. However, these embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals refer to the same components. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0051] In order to describe embodiments of this disclosure, some components that are not related to this description may not be provided.

[0052] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, the layer or substrate can be directly on the other layer or substrate, or an intermediary layer may also be present. Conversely, when an element (such as a layer or substrate) is referred to as being "directly on" another element, an intermediary element may not be present.

[0053] Furthermore, the phrase "in a plan view" means when viewing the target portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section obtained by vertically cutting the target portion from the side. The terms "overlapping" or "overlapping" mean that the first object may be above or below the second object or on the side of the second object, and vice versa. Furthermore, the term "overlapping" can include layering, stacking, facing or oriented, extending / covering over, covering or partially covering, or any other suitable term understood and mastered by one of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "separated from," or "offset from," and any other suitable equivalent meaning understood and mastered by one of ordinary skill in the art. The terms "facing" and "oriented" can mean that the first object may be directly or indirectly opposite the second object. In the case of a third object between the first and second objects, although they still face each other, the first and second objects can be understood as indirectly opposite each other.

[0054] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” or “upper” are used herein to describe the relationship between one element or component shown in the figures and another. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, in the case where the device shown in the figures is flipped, a device positioned “below” or “under” another device can be placed “above” another device. Therefore, the descriptive term “below” can include both “below” and “above” positions. The device may also be oriented in other directions, and therefore spatial relative terms can be interpreted differently depending on orientation.

[0055] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element, or “electrically connected” or “electrically coupled” to the other element, and one or more intermediary elements may be present between the element and the other element. It will also be understood that when the terms “comprising,” “including,” “having,” “possessing,” “containing,” and / or “comprise” are used, they may indicate the presence of the stated features, integrals, steps, operations, elements, components, and / or any combination thereof, but do not exclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0056] It will be understood that although the terms “first,” “second,” or “third,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or for convenience in their description and interpretation. For example, without departing from the teachings of this document, when discussing a “first element” in a description, the “first element” may be referred to as a “second element” or a “third element,” and “second element” and “third element” may be named in a similar manner.

[0057] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0058] In this specification, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunction or disjunction and can be understood as equivalent to "and / or". In this specification, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one of the group consisting of...". For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0059] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having meanings consistent with their meanings in the context of the relevant field and will not be interpreted in an idealized or overly formalized sense.

[0060] Those skilled in the art will understand that, in view of the entirety of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with one another, and may be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in any suitable combination with one another.

[0061] Figure 1 This is an exploded perspective view showing the display device. Figure 2 It is used for explanation Figure 1Block diagram of the display device shown.

[0062] Reference Figure 1 and Figure 2 The display device 10 can be a device for displaying moving images and / or still images. The display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation systems, and / or ultra-mobile PCs (UMPCs). For example, the display device 10 can be used as a display unit for electronic devices such as televisions, laptops, monitors, billboards, and / or Internet of Things (IoT) devices. Alternatively, the display device 10 can be applied to electronic devices such as smartwatches, smartwatch phones, and / or head-mounted displays (HMDs) for realizing virtual and augmented reality.

[0063] The display device 10 may include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (i.e., a timing controller) 400, and a power supply circuit (i.e., a power supply unit) 500.

[0064] The display panel 100 may have a planar shape similar to a quadrilateral. For example, the display panel 100 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, the angle where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be a right angle or a rounded corner with a suitable curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, but may be a planar shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may conform to the planar shape of the display panel 100, but this disclosure is not limited thereto.

[0065] The display panel 100 may include multiple pixels PX, multiple scan lines SL, multiple emission control lines EL, multiple data lines DL, a scan driver 610, an emission driver 620, and a data driver 700. For example... Figure 2 As shown, the display panel 100 can be divided into a display area DAA for displaying images and a non-display area NDA for not displaying images.

[0066] Multiple pixels (PX) can be set in the display area (DAA). The multiple pixels (PX) can be arranged in a matrix along a first direction (DR1) and a second direction (DR2). For example, the multiple pixels (PX) can be arranged along rows and columns of a matrix along the first direction (DR1) and the second direction (DR2). While arranged along the second direction (DR2), multiple scan lines (SL) and multiple emission control lines (EL) can extend along the first direction (DR1). While arranged along the first direction (DR1), multiple data lines (DL) can extend along the second direction (DR2).

[0067] Multiple scan lines SL can include multiple write scan lines GWL, multiple control scan lines GCL, and multiple bias scan lines GBL. Multiple emit control lines EL can include multiple first emit control lines EL1 and multiple second emit control lines EL2.

[0068] Multiple pixels PX may include multiple sub-pixels SP1, SP2, and SP3. Multiple sub-pixels SP1, SP2, and SP3 may include multiple pixel transistors (see, for example, [link to relevant documentation]). Figure 3 Multiple pixel transistors can be formed using semiconductor processes and can be disposed on a semiconductor substrate SSUB (see, for example). Figure 7 For example, multiple pixel transistors of multiple sub-pixels SP1, SP2 and SP3 can be formed by complementary metal-oxide-semiconductor (CMOS) processes, but this disclosure is not limited thereto.

[0069] Each of the multiple sub-pixels SP1, SP2, and SP3 can be connected to a corresponding write scan line GWL, a corresponding control scan line GCL, a corresponding bias scan line GBL, a corresponding first emission control line EL1, a corresponding second emission control line EL2, and a corresponding data line DL. Each of the multiple sub-pixels SP1, SP2, and SP3 can receive the data voltage of the data line DL in response to the write scan signal of the write scan line GWL, and emit light from the light-emitting element according to the data voltage.

[0070] The scan driver 610, transmit driver 620, and data driver 700 can be located in the non-display area NDA.

[0071] Scan driver 610 may include multiple scan transistors, and emitter driver 620 may include multiple light-emitting transistors. The multiple scan transistors and multiple light-emitting transistors can be formed on a semiconductor substrate SSUB using semiconductor processes (e.g., see [reference]). Figure 7For example, multiple scanning transistors and multiple light-emitting transistors can be formed using CMOS processes, but this disclosure is not limited thereto.

[0072] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from a timing control circuit (i.e., a timing controller) 400. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS from the timing control circuit (i.e., the timing controller) 400, and sequentially output these write scan signals to the write scan line GWL. The control scan signal output unit 612 may generate control scan signals in response to the scan timing control signal SCS, and sequentially output these control scan signals to the control scan line GCL. The bias scan signal output unit 613 may generate bias scan signals according to the scan timing control signal SCS, and sequentially output these bias scan signals to the bias scan line GBL.

[0073] The transmit driver 620 includes a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 can receive transmit timing control signals ECS from the timing control circuit (i.e., timing controller) 400. The first transmit control driver 621 can generate first transmit control signals according to the transmit timing control signals ECS and sequentially outputs these first transmit control signals to the first transmit control line EL1. The second transmit control driver 622 can generate second transmit control signals according to the transmit timing control signals ECS and sequentially outputs these second transmit control signals to the second transmit control line EL2.

[0074] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed by semiconductor processes and formed on a semiconductor substrate SSUB (e.g., see...). Figure 7 For example, the plurality of data transistors can be formed using a CMOS process, but this disclosure is not limited thereto.

[0075] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit (i.e., timing controller) 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS and outputs the analog data voltage to the data line DL. In this case, sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the analog data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0076] The heat dissipation layer 200 may overlap with the display panel 100 on a third direction DR3, which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be disposed on one surface of the display panel 100, for example, on the rear surface of the display panel 100. The heat dissipation layer 200 is used to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include graphite with high thermal conductivity or metals such as silver (Ag), copper (Cu) and / or aluminum (Al).

[0077] Circuit board 300 can be electrically connected to the first pad portion of display panel 100 PDA1 using conductive adhesive components such as anisotropic conductive film (see, for example, see...). Figure 4 Multiple first pads PD1 (e.g., see...) Figure 4 Circuit board 300 can be a flexible printed circuit board (FPCB) or a flexible film made of flexible material. Although circuit board 300 is in Figure 1 The circuit board 300 is shown unfolded, but it can be bent. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The other end of the circuit board 300 can be attached to the first pad portion PDA1 of the display panel 100 using conductive adhesive components (see, for example, [link to relevant documentation]). Figure 4 Multiple first pads PD1 (e.g., see...) Figure 4 One end of circuit board 300 may be the opposite end of the other end of circuit board 300.

[0078] The timing control circuit (i.e., timing controller) 400 can receive digital video data DATA and timing signals input from an external source. The timing control circuit (i.e., timing controller) 400 can generate a scan timing control signal SCS, a transmit timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signals. The timing control circuit (i.e., timing controller) 400 can output the scan timing control signal SCS to the scan driver 610 and the transmit timing control signal ECS to the transmit driver 620. The timing control circuit (i.e., timing controller) 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0079] The power supply circuit (i.e., power supply unit) 500 can generate multiple panel driving voltages based on the power supply voltage from an external source. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply these voltages to the display panel 100. This will be discussed later. Figure 3 Describe the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT.

[0080] Each of the timing control circuit (i.e., timing controller) 400 and the power supply circuit (i.e., power supply unit) 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. In this case, the scan timing control signal SCS, transmit timing control signal ECS, digital video data DATA, and data timing control signal DCS of the timing control circuit (i.e., timing controller) 400 can be supplied to the display panel 100 through the circuit board 300. Furthermore, the first drive voltage VSS, the second drive voltage VDD, and the third drive voltage VINT of the power supply circuit (i.e., power supply unit) 500 can be supplied to the display panel 100 through the circuit board 300.

[0081] As another example, each of the timing control circuit (i.e., timing controller) 400 and the power supply circuit (i.e., power supply unit) 500 can be arranged in the non-display area NDA of the display panel 100, similar to the scan driver 610, transmit driver 620, and data driver 700. In this case, the timing control circuit (i.e., timing controller) 400 may include multiple timing transistors, and each power supply circuit (i.e., power supply unit) 500 may include multiple power transistors. The multiple timing transistors and the multiple power transistors can be formed by semiconductor processes and are formed on a semiconductor substrate SSUB (e.g., see...). Figure 7In, for example, multiple timing transistors and multiple power transistors can be formed using CMOS technology, but this disclosure is not limited thereto. Each of the timing control circuitry 400 and the power supply circuitry 500 can be disposed in the data driver 700 and the first pad portion of PDA1 (see, for example, see...). Figure 4 )between.

[0082] Figure 3 It is used for explanation Figure 2 The equivalent circuit diagram of the example of the first sub-pixel shown.

[0083] Reference Figure 3 The first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emit control line EL1, the second emit control line EL2, and the data line DL. Furthermore, the first sub-pixel SP1 can also be connected to a first drive voltage VSS corresponding to a low potential voltage (see, for example, [link to relevant documentation]). Figure 2 The first driving voltage line VSL applied, and the second driving voltage VDD corresponding to the high potential voltage (for example, see...). Figure 2 The second drive voltage line VDL and the third drive voltage VINT corresponding to the initialization voltage are applied (see, for example, see...). Figure 2 The third driving voltage line VIL is applied. That is, the first driving voltage line VSL can be a low-potential voltage line, the second driving voltage line VDL can be a high-potential voltage line, and the third driving voltage line VIL can be the initialization voltage line. In this case, the first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0084] The first sub-pixel SP1 may include multiple transistors T1 to T6, a light-emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0085] The light-emitting element LE emits light in response to a drive current flowing through the channel of the first transistor T1. The emission amount of the light-emitting element LE can be proportional to the drive current. The light-emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. The first electrode of the light-emitting element LE can be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light-emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light-emitting element LE can be an anode electrode, and the second electrode of the light-emitting element LE can be a cathode electrode.

[0086] The first transistor T1 may be a driving transistor that controls the source-drain current (also called "drive current") flowing between the source and drain electrodes of the first transistor T1 according to the voltage applied to the gate electrode of the first transistor T1. The first transistor T1 may include a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0087] A second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Therefore, the data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1. The second transistor T2 may include a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0088] A third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal from the control scan line GCL to connect the first node N1 to the second node N2. Therefore, when the gate and drain electrodes of the first transistor T1 are connected, the first transistor T1 can operate like a diode (e.g., the first transistor T1 can be diode-connected). The third transistor T3 may include a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0089] A fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by a first emitter control signal on the first emitter control line EL1 to connect the second node N2 to the third node N3. Therefore, the drive current of the first transistor T1 can be supplied to the light-emitting element LE. The fourth transistor T4 may include a gate electrode connected to the first emitter control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0090] A fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light-emitting element LE. The fifth transistor T5 may include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0091] A sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by a second emitter control signal via the second emitter control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 may include a gate electrode connected to the second emitter control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0092] A first capacitor CP1 may be disposed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 may include one electrode connected to the drain electrode of the second transistor T2 and another electrode connected to the first node N1.

[0093] A second capacitor CP2 is formed between the gate electrode (or first node N1) of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 may include one electrode connected to the gate electrode (or first node N1) of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0094] The first node N1 is the node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 is the node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is the node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light-emitting element LE.

[0095] Each of the first transistors T1 through T6 can be a metal-oxide-semiconductor field-effect transistor (MOSFET). For example, each of the first transistors T1 through T6 can be a P-type MOSFET, but this disclosure is not limited thereto. Each of the first transistors T1 through T6 can be an N-type MOSFET. Alternatively, some of the first transistors T1 through T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0096] although Figure 3 The diagram shows that the first sub-pixel SP1 includes six transistors T1 to T6 and two capacitors CP1 and CP2. However, it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to this. Figure 3The circuit diagram shown. For example, the number of transistors and capacitors in the first sub-pixel SP1 is not limited to... Figure 3 The quantities shown.

[0097] In addition, the second sub-pixel SP2 (see, for example, see...) Figure 2 The equivalent circuit diagram of ) and the third sub-pixel SP3 (see, for example, see...) Figure 2 The equivalent circuit diagram of ) can be combined with Figure 3 The equivalent circuit diagram of the first sub-pixel SP1 is substantially the same. Therefore, the description of the equivalent circuit diagrams of the second sub-pixel SP2 and the third sub-pixel SP3 will be omitted in this disclosure.

[0098] Figure 4 It is shown Figure 1 A schematic floor plan of an example of a display panel shown.

[0099] Reference Figure 4 The display area DAA of the display panel 100 may include a plurality of pixels PX arranged in a matrix. The non-display area NDA of the display panel 100 may include a scan driver 610, a transmit driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0100] The scan driver 610 can be disposed on a first side of the display area DAA, and the transmit driver 620 can be disposed on a second side of the display area DAA. For example, the scan driver 610 can be disposed on one side of the display area DAA in the first direction DR1, and the transmit driver 620 can be disposed on the other side of the display area DAA in the first direction DR1. That is, as... Figure 4 As shown, the scan driver 610 can be disposed on the left side of the display area DAA, and the transmit driver 620 can be disposed on the right side of the display area DAA. However, this disclosure is not limited thereto, and the scan driver 610 and the transmit driver 620 together can be disposed on the first side or the second side of the display area DAA.

[0101] The first pad portion of PDA1 may include a connection to the circuit board 300 via a conductive adhesive component (see, for example, see...). Figure 1 Multiple first pads PD1 of the pads or bumps of the display area DAA. The first pad portion PDA1 can be located on the third side of the display area DAA. For example, the first pad portion PDA1 can be located on one side of the display area DAA in the second direction DR2. The first pad portion PDA1 can be located outside the data driver 700 on the second direction DR2. That is, as... Figure 4As shown, the first pad portion of PDA1 can be configured to be closer to the edge of the display panel 100 than the data driver 700.

[0102] The second pad portion PDA2 may include multiple second pads PAD2 corresponding to inspection pads for testing whether the display panel 100 is operating normally. During the inspection process, the multiple second pads PD2 may be connected to a fixture or probe, or may be connected to a circuit board used for inspection. The circuit board used for inspection may be a printed circuit board (PCB) made of a rigid material or a flexible printed circuit board (FPCB) made of a flexible material.

[0103] The second pad portion of PDA2 can be located on the fourth side of the display area DAA. For example, the second pad portion of PDA2 can be located on the other side of the display area DAA in the second direction DR2. The second pad portion of PDA2 can be located outside the second distribution circuit 720 on the second direction DR2. That is, as... Figure 4 As shown, the second pad portion PDA2 can be configured to be closer to the edge of the display panel 100 than the second distribution circuit 720.

[0104] The first distribution circuit 710 distributes the data voltage applied through the first pad portion of PDA1 to multiple data lines DL (e.g., see...). Figure 2 For example, the first distribution circuit 710 can distribute the data voltage applied through a first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or greater) data lines DL, and therefore, the number of multiple first pads PD1 can be reduced. The first distribution circuit 710 can be disposed on the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed on one side of the display area DAA in the second direction DR2. That is, as Figure 4 As shown, the first distribution circuit 710 can be disposed on the lower side of the display area DAA.

[0105] The second distribution circuit 720 distributes the signal applied through the second pad portion PDA2 to the scan driver 610 and the transmit driver 620. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be disposed on the fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed on the other side of the display area DAA in the second direction DR2. That is, as... Figure 4 As shown, the second distribution circuit 720 can be disposed on the upper side of the display area DAA.

[0106] Figure 5 It is shown Figure 4A schematic floor plan of an example of the display area shown. Figure 6 It is shown Figure 4 A schematic floor plan of another example of the display area shown.

[0107] Reference Figure 5 Each of the plurality of pixels PX may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may each include an emission region EA1, EA2, and EA3, respectively. For example, the first sub-pixel SP1 may include a first emission region EA1, the second sub-pixel SP2 may include a second emission region EA2, and the third sub-pixel SP3 may include a third emission region EA3.

[0108] Each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be a pixel-defined film PDL (e.g., see...). Figure 7 The region defined by the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be a film PDL1 defined by the first pixel (see, for example, see...). Figure 7 (The area defined by the region)

[0109] The length of the third transmission region EA3 in the first direction DR1 can be less than the length of the first transmission region EA1 in the first direction DR1 and the length of the second transmission region EA2 in the first direction DR1. The lengths of the first transmission region EA1 and the second transmission region EA2 in the first direction DR1 can be substantially the same.

[0110] The length of the third transmission region EA3 in the second direction DR2 can be greater than the length of the first transmission region EA1 in the second direction DR2 and the length of the second transmission region EA2 in the second direction DR2. The length of the first transmission region EA1 in the second direction DR2 can be greater than the length of the second transmission region EA2 in the second direction DR2.

[0111] In each of the plurality of pixels PX, a first emission region EA1 and a second emission region EA2 may be adjacent to each other in a second direction DR2. Furthermore, a first emission region EA1 and a third emission region EA3 may be adjacent to each other in a first direction DR1. The areas of the first emission region EA1, the second emission region EA2, and the third emission region EA3 may be different from each other.

[0112] The first emission region EA1 can emit light of a first color, the second emission region EA2 can emit light of a second color, and the third emission region EA3 can emit light of a third color. Here, the first color light can be light in the red wavelength band, the second color light can be light in the green wavelength band, and the third color light can be light in the blue wavelength band. For example, the blue wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 370 nm to about 460 nm, the green wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 480 nm to about 560 nm, and the red wavelength band can be the wavelength band of light whose main peak wavelength is in the range of about 600 nm to about 750 nm.

[0113] As another example, such as Figure 6 As shown, the first emission region EA1, the second emission region EA2, and the third emission region EA3 can be configured as a hexagonal structure with a hexagonal shape in the plan view. In this case, the first emission region EA1 and the second emission region EA2 can be adjacent to each other in the first direction DR1, but the second emission region EA2 and the third emission region EA3 can be adjacent to each other in the first diagonal direction DD1, and the first emission region EA1 and the third emission region EA3 can be adjacent to each other in the second diagonal direction DD2.

[0114] Despite Figure 5 and Figure 6 The diagram shows each of a plurality of pixels PX comprising three emission regions EA1, EA2, and EA3, but this disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission regions. Furthermore, with Figure 5 and Figure 6 The shapes shown are different; each of the emission regions EA1, EA2, and EA3 can have a polygonal shape other than a quadrilateral or hexagonal, a circular shape, an elliptical shape, or an atypical shape in the plan view.

[0115] The arrangement of the emission regions EA1, EA2, and EA3 of multiple pixel PXs is not limited to Figure 5 and Figure 6 The arrangement shown is illustrated. For example, the emission regions of multiple pixels PX can be configured as a stripe structure in which the emission regions are arranged along a first direction DR1 and / or in which the emission regions are arranged in a diamond shape. Structure, etc. It is a registered trademark of Samsung Display Co., Ltd. of the Republic of Korea.

[0116] Figure 7 It shows along Figure 5 A cross-sectional view of an example display panel taken by line I-I'.

[0117] Reference Figure 7 The display panel 100 may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an adhesive layer (APL), a cover layer (CVL), and a polarizing plate (POL).

[0118] The semiconductor backplane (SBP) includes a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films (SINS1, SINS2, and SINS3) covering the multiple pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the multiple pixel transistors (PTRs). The multiple pixel transistors (PTRs) can be referenced... Figure 3 The first transistor T1 to the sixth transistor T6 are described.

[0119] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, and / or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a type I impurity. Multiple well regions WA can be disposed on the top surface portion of the semiconductor substrate SSUB. The multiple well regions WA can be regions doped with a type II impurity. The type II impurity can be different from the aforementioned type I impurity. For example, when the type I impurity is a P-type impurity, the type II impurity can be an N-type impurity. Alternatively, when the type I impurity is an N-type impurity, the type II impurity can be a P-type impurity.

[0120] Each of the multiple well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0121] A lower insulating film (BINS) can be disposed between the gate electrode GE and the well region WA. A side insulating film (SINS) can be disposed on the side surface of the gate electrode GE. A side insulating film (SINS) can be disposed on the lower insulating film (BINS).

[0122] Each of the source region SA and drain region DA can be a region doped with a type I impurity. The gate electrode GE of the pixel transistor PTR can overlap with the well region WA on the third-direction DR3. The channel region CH can overlap with the gate electrode GE on the third-direction DR3. The source region SA can be located on one side of the gate electrode GE, and the drain region DA can be located on the other side of the gate electrode GE.

[0123] Each of the multiple well regions WA may further include a first low-concentration impurity region LDD1 disposed between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 disposed between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may have an impurity concentration lower than that of the source region SA. The second low-concentration impurity region LDD2 may have an impurity concentration lower than that of the drain region DA. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, the distance between the source region SA and the drain region DA can be increased. Therefore, the length of the channel region CH of each of the multiple pixel transistors PTR can be increased, thereby reducing or preventing breakdown and hot carrier phenomena that may be caused by short channels.

[0124] The first semiconductor insulating film SINS1 can be disposed on the semiconductor substrate SSUB and the gate electrode GE of the pixel transistor PTR. The first semiconductor insulating film SINS1 can be made of silicon carbide (SiCN) and / or silicon oxide (SiO2). x Inorganic membranes of various types can be formed, but this disclosure is not limited thereto.

[0125] The second semiconductor insulating film SINS2 can be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be made of silicon oxide (SiO2). x Inorganic membranes of various types can be formed, but this disclosure is not limited thereto.

[0126] Multiple contact terminals (CTEs) can be arranged on the second semiconductor insulating film (SINS2). Each of the multiple contact terminals (CTEs) can be connected to one of the gate electrode (GE), source region (SA), and drain region (DA) of each of the multiple pixel transistors (PTRs) via a contact plug penetrating the first semiconductor insulating film (SINS1) and the second semiconductor insulating film (SINS2). The multiple contact terminals (CTEs) can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of these.

[0127] A third semiconductor insulating film (SINS3) can be disposed on the side surfaces of multiple contact terminals (CTEs). The top surface of each of the multiple contact terminals (CTEs) can be exposed and not covered by the third semiconductor insulating film (SINS3). The third semiconductor insulating film (SINS3) can be made of silicon oxide (SiO2). x Inorganic membranes of various types can be formed, but this disclosure is not limited thereto.

[0128] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate such as a polyimide substrate. In this case, thin-film transistors (e.g., pixel transistors PTRs) can be disposed on the glass substrate and / or the polymer resin substrate. The glass substrate can be a rigid substrate that cannot be bent, and the polymer resin substrate can be a flexible substrate that can be bent and / or flexed.

[0129] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. The multiple insulating films INS1 to INS9 can be used for electrical insulation between the multiple conductive layers ML1 to ML8 and between the eighth conductive layer ML8 and the reflective electrode layer RL.

[0130] The first conductive layers ML1 to the eighth conductive layers ML8 are connected to a plurality of contact terminals CTE exposed from the semiconductor backplane SBP, and are used to implement Figure 3 The circuitry for the first sub-pixel SP1 is shown. For example, the first transistor T1 (see, for example, [reference needed]). Figure 3 ) to the sixth transistor T6 (for example, see Figure 3 ) are formed only in the semiconductor backplane SBP, and the first transistor T1 to the sixth transistor T6 are connected to the first capacitor CP1 (for example, see Figure 3 ) and the second capacitor CP2 (for example, see Figure 3 The connection can be achieved through the first conductive layer ML1 to the eighth conductive layer ML8. Furthermore, corresponding to the fourth transistor T4 (see, for example, [link to documentation]). Figure 3 The drain region of the drain electrode of the fifth transistor T5 (see, for example, see...) Figure 3 The source region of the source electrode and the light-emitting element (LE) (see, for example, see source region of source electrode ... Figure 3 The connection between the first electrode AND (also known as the anode electrode AND) can also be achieved by the first conductive layer ML1 to the eighth conductive layer ML8.

[0131] A first insulating film INS1 may be disposed on a semiconductor backplane SBP. Each of a plurality of first vias VA1 may penetrate the first insulating film INS1 and connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of a plurality of first conductive layers ML1 may be disposed on the first insulating film INS1 and may connect to the first via VA1.

[0132] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the plurality of second through holes VA2 can penetrate the second insulating film INS2 and can be connected to the first conductive layer ML1. Each of the plurality of second conductive layers ML2 can be disposed on the second insulating film INS2 and can be connected to the second through hole VA2.

[0133] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the plurality of third through-holes VA3 can penetrate the third insulating film INS3 and can be connected to the second conductive layer ML2. Each of the plurality of third conductive layers ML3 can be disposed on the third insulating film INS3 and can be connected to the third through-hole VA3.

[0134] A fourth insulating film INS4 can be disposed on the third insulating film INS3 and the third conductive layer ML3. Each of the plurality of fourth through-holes VA4 can penetrate the fourth insulating film INS4 and can be connected to the third conductive layer ML3. Each of the plurality of fourth conductive layers ML4 can be disposed on the fourth insulating film INS4 and can be connected to the fourth through-hole VA4.

[0135] A fifth insulating film INS5 can be disposed on the fourth insulating film INS4 and the fourth conductive layer ML4. Each of the plurality of fifth through-holes VA5 can penetrate the fifth insulating film INS5 and can be connected to the fourth conductive layer ML4. Each of the plurality of fifth conductive layers ML5 can be disposed on the fifth insulating film INS5 and can be connected to the fifth through-hole VA5.

[0136] A sixth insulating film INS6 can be disposed on the fifth insulating film INS5 and the fifth conductive layer ML5. Each of the plurality of sixth vias VA6 can penetrate the sixth insulating film INS6 and can be connected to the fifth conductive layer ML5. Each of the plurality of sixth conductive layers ML6 can be disposed on the sixth insulating film INS6 and can be connected to the sixth via VA6.

[0137] A seventh insulating film INS7 can be disposed on the sixth insulating film INS6 and the sixth conductive layer ML6. Each of the plurality of seventh vias VA7 can penetrate the seventh insulating film INS7 and can be connected to the sixth conductive layer ML6. Each of the plurality of seventh conductive layers ML7 can be disposed on the seventh insulating film INS7 and can be connected to the seventh via VA7.

[0138] An eighth insulating film INS8 can be disposed on the seventh insulating film INS7 and the seventh conductive layer ML7. Each of the plurality of eighth through-holes VA8 can penetrate the eighth insulating film INS8 and can be connected to the seventh conductive layer ML7. Each of the plurality of eighth conductive layers ML8 can be disposed on the eighth insulating film INS8 and can be connected to the eighth through-hole VA8.

[0139] The first conductive layer ML1 to the eighth conductive layer ML8 can be made of substantially the same material. The first conductive layer ML1 to the eighth conductive layer ML8 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of these. The first through-hole VA1 to the eighth through-hole VA8 can be made of substantially the same material. The first through-hole VA1 to the eighth through-hole VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or alloys including any one of these. The first insulating film INS1 to the eighth insulating film INS8 can be made of silicon oxide (SiO2). x Inorganic membranes of various types can be formed, but this disclosure is not limited thereto.

[0140] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first through-hole VA1, the second through-hole VA2, the third through-hole VA3, the fourth through-hole VA4, the fifth through-hole VA5, and the sixth through-hole VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately...

[0141] The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately [missing information]. The thickness of each of the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, and the sixth through hole VA6 can be approximately

[0142] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately... The thickness of each of the seventh through hole VA7 and the eighth through hole VA8 can be approximately

[0143] The ninth insulating film INS9 can be disposed on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be made of silicon oxide (SiO2). x Inorganic membranes of various types can be formed, but this disclosure is not limited thereto.

[0144] Each of the plurality of ninth vias VA9 can penetrate the ninth insulating film INS9 and can be connected to the eighth conductive layer ML8. The ninth vias VA9 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of these. The thickness of the ninth via VA9 can be approximately [missing information].

[0145]

[0146] The display element layer (EML) can be disposed on the light-emitting element backplane (EBP). The display element layer (EML) may include a reflective electrode layer (RL), a tenth insulating film (INS10), a tenth via (VA10), light-emitting elements (LE), and a pixel defining film (PDL). Each of the plurality of light-emitting elements (LE) may include a first electrode (AND), a light-emitting stack (ES), and a second electrode (CAT).

[0147] A reflective electrode layer RL can be disposed on the ninth insulating film INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, and RL4, a first step layer STPL1, and a second step layer STPL2. For example, as... Figure 7 As shown, the reflective electrode layer RL may include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0148] Each of the plurality of first reflective electrodes RL1 may be disposed on the ninth insulating film INS9 and may be connected to the ninth through-hole VA9. The first reflective electrodes RL1 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys or nitrides including one or more of these. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0149] Each of a plurality of second reflective electrodes RL2 may be disposed on a first reflective electrode RL1. The second reflective electrodes RL2 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys comprising one or more of these. For example, the second reflective electrode RL2 may comprise aluminum (Al).

[0150] The first step layer STPL1 can be set on the second reflective electrode RL2 in the second sub-pixel SP2 and the third sub-pixel SP3. The first step layer STPL1 can also be not set on the second reflective electrode RL2 in the first sub-pixel SP1.

[0151] The second step layer STPL2 can be disposed on the first step layer STPL1 in the third sub-pixel SP3. The second step layer STPL2 may not be disposed on the second reflective electrode RL2 in the first sub-pixel SP1. Furthermore, the second step layer STPL2 may not be disposed on the first step layer STPL1 in the second sub-pixel SP2.

[0152] The thickness of the first step layer STPL1 can be set taking into account the wavelength of the second color light and the distance from the light-emitting stack ES2 of the second sub-pixel SP2 to the fourth reflective electrode RL4 to reflect (e.g., advantageously reflect) the second color light emitted from the light-emitting stack ES2. The thickness of the second step layer STPL2 can be set taking into account the wavelength of the third color light and the distance from the light-emitting stack ES3 of the third sub-pixel SP3 to the fourth reflective electrode RL4 to reflect (e.g., advantageously reflect) the third color light emitted from the light-emitting stack ES3.

[0153] The first step layer STPL1 and the second step layer STPL2 can be made of silicon carbide (SiCN) and / or silicon oxide (SiO2). x Inorganic membranes of various types can be formed, but this disclosure is not limited thereto.

[0154] In the first sub-pixel SP1, the third reflective electrode RL3 can be disposed on the second reflective electrode RL2. In the second sub-pixel SP2, the third reflective electrode RL3 can be disposed on the first step layer STPL1 and the second reflective electrode RL2. In the third sub-pixel SP3, the third reflective electrode RL3 can be disposed on the second step layer STPL2 and the second reflective electrode RL2. The third reflective electrode RL3 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or an alloy or nitride comprising one or more of these. For example, the third reflective electrode RL3 may comprise titanium nitride (TiN).

[0155] At least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 can be omitted.

[0156] Each of a plurality of fourth reflective electrodes RL4 may be disposed on the third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the light-emitting stack ES. The fourth reflective electrode RL4 may comprise a metal with high reflectivity to reflect (e.g., advantageously reflect) light. Furthermore, since the fourth reflective electrode RL4 is an electrode that substantially reflects light from the light-emitting element LE, the thickness of the fourth reflective electrode RL4 may be greater than the thickness of each of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3. The fourth reflective electrode RL4 may be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and / or neodymium (Nd) and / or alloys including one or more of these. For example, the fourth reflective electrode RL4 may comprise aluminum (Al) and / or titanium (Ti). However, in one or more embodiments, the thickness of the fourth reflective electrode RL4 may be substantially the same as the thickness of each of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3.

[0157] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9 and the fourth reflective electrode RL4. The tenth insulating film INS10 can be an optical auxiliary layer that reflects light emitted by the light-emitting element LE through the reflective electrode layer RL. The tenth insulating film INS10 can be made of silicon oxide (SiO2). x Inorganic membranes of various types can be formed, but this disclosure is not limited thereto.

[0158] Each of the plurality of tenth through-holes VA10 can penetrate the tenth insulating film INS10 and can be connected to the reflective electrode layer RL. The tenth through-hole VA10 can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys including one or more of them.

[0159] To adjust the resonant distance of the light emitted by the light-emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the thickness of the tenth via VA10 can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the thickness of the tenth via VA10 in the third sub-pixel SP3 can be less than the thickness of the tenth via VA10 in each of the first sub-pixel SP1 and the second sub-pixel SP2. Furthermore, the thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the first sub-pixel SP1. That is, the distance between the light-emitting stack ES and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0160] In summary, in order to adjust the distance between the light-emitting stack ES and the reflective electrode layer RL according to the dominant wavelength of the light emitted by the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3, the presence or absence of the first step layer STPL1 and the second step layer STPL2, as well as the thickness of each of the first step layer STPL1 and the second step layer STPL2 in the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3, can be set.

[0161] The first electrode AND of each of the plurality of light-emitting elements LE can be disposed on the tenth insulating film INS10 and connected to the tenth through-hole VA10. The first electrode AND of each of the plurality of light-emitting elements LE can be connected to the drain region DA or source region SA of the pixel transistor PTR through the tenth through-hole VA10, the first reflective electrodes RL1 to the fourth reflective electrodes RL4, the first through-hole VA1 to the ninth through-hole VA9, the first conductive layer ML1 to the eighth conductive layer ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light-emitting elements LE can be formed of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and / or neodymium (Nd) and / or alloys or nitrides including one or more of them. For example, the first electrode AND of each of the plurality of light-emitting elements LE can be titanium nitride (TiN).

[0162] A pixel-defining film (PDL) can be disposed on a portion of the tenth insulating film (INS10) and the first electrode AND of each of the plurality of light-emitting elements (LEs). The pixel-defining film (PDL) can cover the edge of the first electrode AND of each of the plurality of light-emitting elements (LEs). The pixel-defining film (PDL) can be used to separate a first emitting region (EA1), a second emitting region (EA2), and a third emitting region (EA3). That is, the pixel-defining film (PDL) can have an opening that partially exposes the first electrode AND of each of the plurality of light-emitting elements (LEs).

[0163] The first emitting region EA1 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emitting region EA2 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emitting region EA3 can be defined as the region in which the first electrode AND, the light-emitting stack ES, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0164] The pixel-defining film (PDL) may include a first pixel-defining film (PDL1), a second pixel-defining film (PDL2), and a third pixel-defining film (PDL3). The first pixel-defining film (PDL1) may be disposed on the tenth insulating film (INS10) and the first electrode (AND) of each of the plurality of light-emitting elements (LEs). The second pixel-defining film (PDL2) may be disposed on the first pixel-defining film (PDL1), and the third pixel-defining film (PDL3) may be disposed on the second pixel-defining film (PDL2). The first pixel-defining film (PDL1), the second pixel-defining film (PDL2), and the third pixel-defining film (PDL3) may be made of silicon oxide (SiO2). x The formation of inorganic films is not limited to this. The first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 may each have approximately The thickness.

[0165] When the first pixel-defining film PDL1, the second pixel-defining film PDL2, and the third pixel-defining film PDL3 form a single pixel-defining film, the height of the single pixel-defining film increases, making the first encapsulating inorganic film TFE1 potentially cut due to step coverage. Step coverage refers to the ratio of the film thickness coated on the inclined portion to the film thickness coated on the flat portion. The lower the step coverage, the more likely the film is to be cut at the inclined portion.

[0166] Therefore, in order to reduce or prevent the possibility of the first encapsulated inorganic film TFE1 being cut due to step coverage, the first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 may have a cross-sectional structure with a stepped portion. For example, the width of the opening of the first pixel defining film PDL1 may be smaller than the width of the opening of the second pixel defining film PDL2, and the width of the opening of the second pixel defining film PDL2 may be smaller than the width of the opening of the third pixel defining film PDL3.

[0167] The light-emitting stack ES may include a first light-emitting stack ES1 disposed in a first emission region EA1, a second light-emitting stack ES2 disposed in a second emission region EA2, and a third light-emitting stack ES3 disposed in a third emission region EA3. In one or more embodiments, the first light-emitting stack ES1 may include a hole injection layer, a hole transport layer, a first light-emitting layer, an electron transport layer, and an electron injection layer; the second light-emitting stack ES2 may include a hole injection layer, a hole transport layer, a second light-emitting layer, an electron transport layer, and an electron injection layer; and the third light-emitting stack ES3 may include a hole injection layer, a hole transport layer, a third light-emitting layer, an electron transport layer, and an electron injection layer.

[0168] For example, a hole injection layer can be disposed on the first electrode AND exposed by the opening of the pixel-defining film PDL, the inner surface of the opening of the pixel-defining film PDL, and the top surface of the pixel-defining film PDL. A hole transport layer can be disposed on the hole injection layer.

[0169] The first to third light-emitting layers can be disposed on the hole transport layer within openings in the pixel-defining film (PDL). The first light-emitting layer can be disposed in the opening in the first emission region EA1 of the PDL and can emit light of a first color, such as red light. The second light-emitting layer can be disposed in the opening in the second emission region EA2 of the PDL and can emit light of a second color, such as green light. The third light-emitting layer can be disposed in the opening in the third emission region EA3 of the PDL and can emit light of a third color, such as blue light.

[0170] An electron transport layer can be disposed on the first to third light-emitting layers and the hole transport layer, and an electron injection layer can be disposed on the electron transport layer.

[0171] In another example, in one or more embodiments, a plurality of trenches may be formed between the first emitter region EA1, the second emitter region EA2, and the third emitter region EA3. The trenches may have annular shapes surrounding the first emitter region EA1, the second emitter region EA2, and the third emitter region EA3, respectively, and may be formed to penetrate the pixel-defining film (PDL). The hole injection layer and the hole transport layer formed on the first electrode AND of the first emitter region EA1, the second emitter region EA2, and the third emitter region EA3 may be disconnected from each other through the trenches.

[0172] In another example, the first light-emitting stack ES1, the second light-emitting stack ES2, and the third light-emitting stack ES3 can be disposed in the openings of the pixel-defining film PDL, or they can be disposed outside the pixel-defining film PDL. In this case, the first light-emitting stack ES1, the second light-emitting stack ES2, and the third light-emitting stack ES3 can be disconnected from each other through the pixel-defining film PDL.

[0173] The second electrode CAT can be disposed on the first light-emitting stack ES1, the second light-emitting stack ES2, and the third light-emitting stack ES3, as well as the pixel-defining film PDL. The second electrode CAT can be formed of a transparent conductive oxide (TCO) capable of transmitting light, such as ITO and / or IZO, or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), and / or an alloy of magnesium and silver. When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency can be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to the microcavity effect.

[0174] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE may include at least one encapsulation inorganic film TFE1 and TFE2 to reduce and / or prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0175] The first encapsulating inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulating inorganic film TFE1 can be formed in which silicon nitride (SiN) is selected. x ) layer, silicon oxynitride (SiON) layer and / or silicon oxide (SiO) layer x A multilayer consisting of two or more inorganic films stacked alternately. The first encapsulating inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0176] The second encapsulating inorganic film TFE2 can be disposed on the first encapsulating inorganic film TFE1. The second encapsulating inorganic film TFE2 can be made of titanium oxide (TiO2). x ) and / or alumina (AlO) xThe second encapsulation inorganic film TFE2 can be formed by atomic layer deposition (ALD). The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0177] The adhesive layer APL can be a layer used to increase the interfacial adhesion between the encapsulation layer TFE and the cover layer CVL. The adhesive layer APL can be an organic film including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin.

[0178] A cover layer CVL can be disposed on an adhesive layer APL. The cover layer CVL can be a glass substrate and / or a polymer resin substrate. When the cover layer CVL is a glass substrate, it can be attached to the adhesive layer APL and can be used as an encapsulation substrate. When the cover layer CVL is a polymer resin substrate, it can be directly applied to the adhesive layer APL.

[0179] The polarizing plate (POL) can be disposed on the CVL (container layer). The polarizing plate (POL) can be a structure used to reduce or prevent visibility reduction caused by reflection of external light. The polarizing plate (POL) can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter-wave plate), but this disclosure is not limited thereto.

[0180] Figure 8 This is a schematic perspective view showing an example of a head-mounted display. Figure 9 It is shown Figure 8 A schematic exploded perspective view of an example of a head-mounted display shown.

[0181] Reference Figure 8 and Figure 9 The head-mounted display 1000 according to one or more embodiments may include a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a headband 1300, a middle frame 1400, a first optical component 1510, a second optical component 1520, and a control circuit board 1600.

[0182] The first display device 10_1 can provide an image to the user's left eye, and the second display device 10_2 provides an image to the user's right eye. Because each of the first display device 10_1 and the second display device 10_2 is combined with... Figure 1 and Figure 2 The display devices 10 described are substantially the same, so the description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0183] The first optical component 1510 may be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical component 1520 may be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical component 1510 and the second optical component 1520 may include at least one convex lens.

[0184] The intermediate frame 1400 can be disposed between the first display device 10_1, the second display device 10_2, and the control circuit board 1600. The intermediate frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0185] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 via connectors. The control circuit board 1600 can convert externally input image sources into digital video data (DATA, e.g., see...). Figure 2 ), and transmits digital video data DATA to the first display device 10_1 and the second display device 10_2 via a connector.

[0186] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to both the first display device 10_1 and the second display device 10_2.

[0187] The display device housing 1100 is used to house the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical component 1510, the second optical component 1520, and the control circuit board 1600. The housing cover 1200 is configured to cover an open surface of the display device housing 1100. The housing cover 1200 may include a first eyepiece 1210 for the user's left eye and a second eyepiece 1220 for the user's right eye. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are shown to be disposed separately, but this disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be combined into one unit.

[0188] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical component 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical component 1520. Therefore, the user can view the image of the first display device 10_1 magnified into a virtual image by the first optical component 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified into a virtual image by the second optical component 1520 through the second eyepiece 1220.

[0189] The headband 1300 is used to secure the display device housing 1100 to the user's head such that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are positioned over the user's left and right eyes, respectively. When the display device housing 1100 is made lightweight and compact, the head-mounted display 1000 can be as follows: Figure 10 The glasses shown are provided in the form of eyeglasses.

[0190] In addition, the head-mounted display 1000 may also include a battery for power supply, an external memory slot for accommodating external memory, and an external connection port and a wireless communication module for receiving image sources. The external connection port may be a Universal Serial Bus (USB) terminal, a display port, or a High Definition Multimedia Interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0191] Figure 10 This is a schematic perspective view showing another example of a head-mounted display.

[0192] Reference Figure 10 The head-mounted display 1000_1 can be an eyeglass-type display device, wherein the display device housing 1200_1 is implemented in a lightweight and compact manner. The head-mounted display 1000_1 may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical component 1060, an optical path conversion component 1070, and a display device housing 1200_1.

[0193] The display device housing 1200_1 can accommodate the display device 10_3, the optical component 1060, and the optical path conversion component 1070. The image displayed on the display device 10_3 can be magnified by the optical component 1060 and, after the optical path of the image is changed by the optical path conversion component 1070, can be provided to the user's right eye through the right eye lens 1020. Therefore, the user can view an augmented reality image combining the virtual image displayed on the display device 10_3 and the real image seen through the right eye lens 1020 through their right eye.

[0194] Figure 10 The display device housing 1200_1 is shown positioned at the right end of the support frame 1030, but this disclosure is not limited thereto. For example, the display device housing 1200_1 may be positioned at the left end of the support frame 1030, in which case the image displayed on the display device 10_3 can be provided to the user's left eye. As another example, the display device housing 1200_1 may be positioned at both the left and right ends of the support frame 1030, in which case the user can view the image displayed on the display device 10_3 through both their left and right eyes.

[0195] Figure 11 This is a schematic plan view illustrating a deposition mask according to one or more embodiments of the present disclosure. Figure 12 It is shown Figure 11 A schematic enlarged plan view of the cell area and scale pattern shown. Figure 13 It is along Figure 12 The schematic cross-sectional view taken by line II-II' shown. Figure 14 It is along Figure 12 The schematic cross-sectional view taken by line III-III' shown.

[0196] Reference Figures 11 to 14 The deposition mask 2000 according to one or more embodiments of this disclosure can be used to form a light-emitting stack ES on a display substrate (or backplane substrate) (e.g., see...). Figure 7 The light-emitting layer is used as a shadow mask in the deposition process of the light-emitting layer to manufacture the display panel 100 (see, for example, see...). Figure 1 For example, such as Figure 7 As shown, a semiconductor backplane SBP and a light-emitting element backplane EBP can be disposed on a display substrate, and a reflective electrode layer RL and a tenth insulating film INS10 can be disposed on the light-emitting element backplane EBP. An electrode pattern (e.g., an anode electrode AND) can be disposed on the tenth insulating film INS10, and the anode electrode AND can be electrically connected to the reflective electrode layer RL through a tenth via VA10. As an example, a deposition mask 2000 can be used to form a first light-emitting layer for emitting light of a first color having a red wavelength band on the electrode pattern of a first emission region EA1. As another example, a deposition mask 2000 can be used to form a second light-emitting layer for emitting light of a second color having a green wavelength band on the electrode pattern of a second emission region EA2. As yet another example, a deposition mask 2000 can be used to form a third light-emitting layer for emitting light of a third color having a blue wavelength band on the electrode pattern of a third emission region EA3.

[0197] The deposition mask 2000 may include a mask frame 2010 and a diaphragm 2100 disposed on the mask frame 2010. The mask frame 2010 may have a plurality of cell openings 2012 and may include rib regions 2014 defining the cell openings 2012. The diaphragm 2100 may include a plurality of cell regions 2110 disposed above the cell openings 2012 and a grid region 2120 disposed on the rib regions 2014 of the mask frame 2010.

[0198] like Figure 11 As shown, the cell regions 2110 can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. For example, the cell regions 2110 can be arranged in a matrix along a first horizontal direction and a second horizontal direction perpendicular to the first horizontal direction. However, since the number and arrangement direction of the cell regions 2110 can be varied, the scope of this disclosure is not limited thereto.

[0199] The mask frame 2010 may have a plurality of cell openings 2012 corresponding to the cell regions 2110 of the diaphragm 2100. For example, the cell openings 2012 may be formed by dry and / or wet etching processes to penetrate the mask frame 2010 so that the cell regions 2110 of the diaphragm 2100 may be exposed through the cell openings 2012.

[0200] Furthermore, the mask frame 2010 may include a substrate 2020 and an inorganic film 2030 disposed on the substrate 2020. In this case, the cell opening 2012 may be formed to penetrate the substrate 2020 and the inorganic film 2030. For example, a silicon substrate may be used as the substrate 2020, and a silicon oxide film may be used as the inorganic film 2030. For example, a silicon oxide film formed by a thermal oxidation process or a chemical vapor deposition process may be used as the inorganic film 2030. However, the inorganic film 2030 may be made of a material different from the materials described above, and therefore, the scope of this disclosure is not limited to the silicon oxide film.

[0201] The separator 2100 can be made of a material different from that of the inorganic membrane 2030. For example, a silicon nitride film formed by a chemical vapor deposition process can be used as the separator 2100. In this case, the inorganic membrane 2030 can serve as an adhesive film between the substrate 2020 and the separator 2100. However, the separator 2100 can be made of a material different from the aforementioned material, and therefore, the scope of this disclosure is not limited to the silicon nitride film.

[0202] Furthermore, each of the plurality of unit regions 2110 of the diaphragm 2100 may have a plurality of pixel openings 2112. The pixel openings 2112 can serve as pathways for providing luminescent material during the deposition process of the luminescent layer used to form the luminescent stack ES. For example, as Figure 12As shown, pixel openings 2112 can be arranged in a matrix along a first direction DR1 and a second direction DR2, and cell regions 2110 can be formed through an anisotropic etching process after a diaphragm 2100 is formed on the inorganic film 2030. In this case, the inorganic film 2030 can be used as an etching stop film during anisotropic etching. After forming pixel openings 2112, cell openings 2012 can be formed to expose cell regions 2110, thereby enabling communication between pixel openings 2112 and cell openings 2012.

[0203] In one or more embodiments, the deposition mask 2000 may warp or deform due to residual stress generated during the manufacturing process described above, and in such cases, the deposition mask 2000 may not be in sufficient close contact with the backplane substrate during the deposition process for forming the light-emitting layer. In particular, the warping or deformation of the deposition mask 2000 may occur primarily during the etching process for forming the cell opening 2012, and therefore, the warping and / or deformation of the deposition mask 2000 must be measured after the formation of the cell opening 2012.

[0204] According to one or more embodiments of this disclosure, the deposition mask 2000 may include scale patterns 2210, 2220, 2230, and 2240 for measuring warpage and / or deformation. For example, the deposition mask 2000 may include a plurality of first scale patterns 2210 arranged in a direction traversing the diaphragm 2100. Specifically, the first scale patterns 2210 may overlap with the rib regions 2014 of the mask frame 2010 in the thickness direction (e.g., a third direction DR3) and may be disposed in the grid regions 2120 of the diaphragm 2100. In particular, the first scale patterns 2210 may be arranged along a first direction DR1 traversing the diaphragm 2100 with a suitable first gap (e.g., a predetermined first gap). In this case, the first direction DR1 may extend through the central portion of the diaphragm 2100, and each of the plurality of first scale patterns 2210 may extend in a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 can be perpendicular to the first direction DR1, and the thickness direction can be a third direction DR3 that is perpendicular to the first direction DR1 and the second direction DR2.

[0205] The deposition mask 2000 may include a second scale pattern 2220 disposed in the grid region 2120 along a second direction DR2 intersecting the first direction DR1 with a first gap. Specifically, the second scale pattern 2220 may overlap with the rib region 2014 of the mask frame 2010 in the thickness direction of the mask frame 2010. In this case, the second direction DR2 may extend through the central portion of the diaphragm 2100, and each of the plurality of second scale patterns 2220 may extend along the first direction DR1. Furthermore, each of the plurality of second scale patterns 2220 may have the same length and width as the first scale pattern 2210.

[0206] In one or more embodiments, when the cell region (hereinafter referred to as the “central cell region”) is arranged on the central portion of the mask frame 2010, the first scale pattern 2210 may be disposed in the grid region 2120 in a fourth direction parallel to the first direction DR1 to be adjacent to the central cell region, and the second scale pattern 2220 may be disposed in the grid region 2120 in a fifth direction parallel to the second direction DR2 to be adjacent to the central cell region.

[0207] like Figure 12 As shown and combined Figure 11 and Figure 13 The deposition mask 2000 may further include third scale patterns 2230 disposed between the first scale patterns 2210. For example, the third scale patterns 2230 may overlap with the rib region 2014 of the mask frame 2010 in the thickness direction (e.g., third direction DR3) and may be disposed in the grid region 2120 of the diaphragm 2100 along the first direction DR1. In this case, the third scale patterns 2230 may be arranged with a second gap smaller than the first gap. Furthermore, each of the plurality of third scale patterns 2230 may have a length and width smaller than the length and width of the first scale patterns 2210 and may extend in the second direction DR2.

[0208] like Figure 12 As shown and combined Figure 11 and Figure 13The deposition mask 2000 may further include a fourth scale pattern 2240 disposed between the second scale patterns 2220. For example, the fourth scale pattern 2240 may overlap with the rib region 2014 of the mask frame 2010 in the thickness direction (e.g., the third direction DR3) and may be disposed in the grid region 2120 of the diaphragm 2100 along the second direction DR2. In this case, the fourth scale pattern 2240 may be arranged with a second gap. Furthermore, each of the plurality of fourth scale patterns 2240 may have a length and width smaller than that of the second scale pattern 2220 and may extend in the first direction DR1. For example, each of the plurality of fourth scale patterns 2240 may have the same length and width as the third scale pattern 2230.

[0209] The first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 may include metallic materials. For example, the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 may be made of metallic materials such as tungsten (W), molybdenum (Mo), chromium (Cr), titanium (Ti), iron (Fe), nickel (Ni), tungsten nitride (WN), titanium nitride (TiN), and / or invar alloys, and may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, and / or electroforming processes.

[0210] For example, after forming a second inorganic film for forming the diaphragm 2100 on the inorganic film 2030, a photoresist pattern can be formed on the second inorganic film to expose portions where the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 will be formed. The photoresist pattern can be used as an etching mask to perform an anisotropic etching process to form multiple recesses that penetrate the second inorganic film and expose the inorganic film 2030. In this case, the inorganic film 2030 can be used as an etching stop film in the anisotropic etching process. Subsequently, a metal film made of the aforementioned metallic material can be formed on the second inorganic film to bury the recesses, and then a planarization process such as chemical mechanical polishing is performed to form the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 in the recesses. In this case, a planarization process can be performed until the second inorganic membrane is exposed such that the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 have the same thickness as the second inorganic membrane. Therefore, the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 can be exposed through the top surface of the second inorganic membrane (i.e., diaphragm 2100) so that they can be observed from the outside.

[0211] As described above, after forming the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240, a photoresist pattern can be formed on the second inorganic film to expose the portion where the pixel opening 2112 will be formed. The photoresist pattern can be used as an etching mask to perform an anisotropic etching process to form the pixel opening 2112 that penetrates the second inorganic film and exposes the inorganic film 2030. Therefore, the diaphragm 2100 having the pixel opening 2112 can be formed from the second inorganic film.

[0212] Simultaneously, the cell opening 2012 can be formed by partially removing the mask frame 2010. For example, the cell opening 2012 can be formed by forming a photoresist pattern or a hard mask pattern on the back side of the substrate 2020 to expose the portion where the cell opening 2012 will be formed, and then using the photoresist pattern or hard mask pattern as an etching mask to perform a dry and / or wet etching process to form the cell opening 2012. In this case, the substrate 2020 and the inorganic film 2030 can be partially removed by a dry and / or wet etching process, thereby forming the cell opening 2012 that exposes the cell region 2110 of the diaphragm 2100.

[0213] According to this embodiment, since the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 can be exposed through the top surface of the diaphragm 2100, they can be identified from the top of the deposition mask 2000. Therefore, the warpage or deformation of the deposition mask 2000 can be accurately measured using a simple vision camera without the need for a separate measuring device equipped with a laser displacement sensor.

[0214] For example, after fabricating the deposition mask 2000, a vision camera can be positioned above the deposition mask 2000. The vision camera can be used to detect the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240, and can measure the gaps between the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240. When warping or deformation occurs during the fabrication process of the deposition mask 2000, the gaps between the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 may change, and the measured gaps between the first scale pattern 2210, the second scale pattern 2220, the third scale pattern 2230, and the fourth scale pattern 2240 can be compared with suitable gaps (e.g., predetermined gaps) to determine the degree of warping and / or deformation of the deposition mask 2000.

[0215] Figure 15 This is a cross-sectional view showing a deposition mask according to one or more embodiments of the present disclosure.

[0216] Reference Figure 15 In (A) and (B) of this disclosure, a deposition mask 2000 according to one or more embodiments of the present disclosure may include a mask frame 2010, a diaphragm 2100 disposed on the mask frame 2010, and a first scale pattern 2212 disposed on the diaphragm 2100. Furthermore, the deposition mask 2000 may include a second scale pattern 2222, a third scale pattern 2232, and a fourth scale pattern 2242 disposed on the diaphragm 2100. The mask frame 2010 may have a plurality of cell openings 2012 (e.g., see...). Figure 13 ), and may include a rib region 2014 defining the unit opening 2012 (e.g., see Figure 13 The diaphragm 2100 may include cell regions 2110 respectively disposed above the cell opening 2012 (see, for example, see...). Figure 13 ) and the grid area 2120 disposed on the rib area 2014 of the mask frame 2010 (see, for example, see Figure 13 ).

[0217] The first scale pattern 2212 may overlap with the rib region 2014 in the thickness direction (e.g., the third direction DR3) of the mask frame 2010, and may be disposed on the grid region 2120 of the diaphragm 2100 with a suitable first gap (e.g., a predetermined first gap) along the first direction DR1 that traverses the diaphragm 2100. The second scale pattern 2222 may overlap with the rib region 2014 in the thickness direction (e.g., the third direction DR3) of the mask frame 2010, and may be disposed on the grid region 2120 of the diaphragm 2100 with a first gap along the second direction DR2 that intersects the first direction DR1.

[0218] The third scale pattern 2232 may overlap with the rib region 2014 in the thickness direction (e.g., third direction DR3) of the mask frame 2010, and may be disposed between the first scale patterns 2212 on the grid region 2120 of the diaphragm 2100 with a second gap smaller than the first gap along the first direction DR1. The fourth scale pattern 2242 may overlap with the rib region 2014 in the thickness direction (e.g., third direction DR3) of the mask frame 2010, and may be disposed between the second scale patterns 2222 on the grid region 2120 of the diaphragm 2100 with a second gap along the second direction DR2.

[0219] According to this embodiment, when the first scale pattern 2212 is disposed on the grid area 2120 of the diaphragm 2100, the first scale pattern 2212 can be formed to have a thickness equal to or less than the thickness of the grid area 2120, and the third scale pattern 2232 can be formed to have the same thickness as the first scale pattern 2212. Furthermore, the second scale pattern 2222 and the fourth scale pattern 2242 can be formed to have the same thickness as the first scale pattern 2212.

[0220] The first scale pattern 2212, the second scale pattern 2222, the third scale pattern 2232, and the fourth scale pattern 2242 may include metallic materials. For example, the first scale pattern 2212, the second scale pattern 2222, the third scale pattern 2232, and the fourth scale pattern 2242 may be made of metallic materials such as tungsten (W), molybdenum (Mo), chromium (Cr), titanium (Ti), iron (Fe), nickel (Ni), tungsten nitride (WN), titanium nitride (TiN), and / or Invar alloys, and may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, and / or electroforming processes. Specifically, after forming a second inorganic film for forming the diaphragm 2100 on the inorganic film 2030, a metallic film including metallic materials may be formed on the second inorganic film, and then patterned to form the first scale pattern 2212, the second scale pattern 2222, the third scale pattern 2232, and the fourth scale pattern 2242.

[0221] In this embodiment, the mask frame 2010 and the diaphragm 2100 are the same as those described above. Figures 11 to 14 The descriptions are essentially the same, and therefore their detailed descriptions will be omitted.

[0222] According to this embodiment, the first scale pattern 2212, the second scale pattern 2222, the third scale pattern 2232, and the fourth scale pattern 2242 can be disposed on the diaphragm 2100, and therefore, the first scale pattern 2212, the second scale pattern 2222, the third scale pattern 2232, and the fourth scale pattern 2242 can be identified from the top of the deposition mask 2000. Therefore, the warpage or deformation of the deposition mask 2000 can be accurately measured using a simple vision camera without the need for a separate measuring device.

[0223] Figure 16 This is a plan view showing a deposition mask according to yet another embodiment of the present disclosure. Figure 17 It is shown Figure 16 A schematic enlarged plan view of the cell area and scale pattern shown.

[0224] Reference Figure 16 and Figure 17 According to another embodiment of the present disclosure, the deposition mask 2000 may include a mask frame 2010 (see, for example, see...). Figure 13 The diaphragm 2100 disposed on the mask frame 2010 and the first scale pattern 2310, the second scale pattern 2320, the third scale pattern 2330 and the fourth scale pattern 2340 disposed in the diaphragm 2100. In addition, the deposition mask 2000 may include a first reinforcing pattern 2350 and a second reinforcing pattern 2360 disposed in the diaphragm 2100.

[0225] The mask frame 2010 may include a plurality of unit openings 2012 (see, for example, see...) Figure 13 ) and the rib region 2014 defining the opening 2012 of the unit (see, for example, see Figure 13 The diaphragm 2100 may include a cell region 2110 disposed above the cell opening 2012 and a mesh region 2120 disposed on the rib region 2014 of the mask frame 2010. In this embodiment, the mask frame 2010 and the diaphragm 2100 are as described above. Figures 11 to 14 The descriptions are essentially the same, so their detailed descriptions will be omitted.

[0226] According to this embodiment, the deposition mask 2000 may include scale patterns 2310, 2320, 2330, and 2340 for measuring warpage or deformation. For example, the deposition mask 2000 may include a plurality of first scale patterns 2310 arranged in a direction traversing the diaphragm 2100. Specifically, the first scale patterns 2310 may overlap with the rib regions 2014 of the mask frame 2010 in the thickness direction of the mask frame 2010 and may be disposed in the grid regions 2120 of the diaphragm 2100. In particular, the first scale patterns 2310 may be arranged along a first direction DR1 traversing the diaphragm 2100 with a suitable first gap (e.g., a predetermined first gap). In this case, the first direction DR1 may extend through the central portion of the diaphragm 2100, and each of the plurality of first scale patterns 2310 may extend in a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 can be perpendicular to the first direction DR1, and the thickness direction can be a third direction DR3 that is perpendicular to the first direction DR1 and the second direction DR2.

[0227] The deposition mask 2000 may include a second scale pattern 2320 disposed in a grid region 2120 of the diaphragm 2100 along a second direction DR2 intersecting the first direction DR1 with a first gap. Specifically, the second scale pattern 2320 may overlap with the rib region 2014 of the mask frame 2010 in the thickness direction. In this case, the second direction DR2 may extend through the central portion of the diaphragm 2100, and each of the plurality of second scale patterns 2320 may extend along the first direction DR1. Furthermore, each of the plurality of second scale patterns 2320 may have the same length and width as the first scale pattern 2310.

[0228] In one or more embodiments, when the cell region (hereinafter referred to as the “central cell region”) is disposed on the central portion of the mask frame 2010, the first scale pattern 2310 may be disposed in the grid region 2120 of the diaphragm 2100 in a fourth direction parallel to the first direction DR1 to be adjacent to the central cell region, and the second scale pattern 2220 may be disposed in the grid region 2120 of the diaphragm 2100 in a fifth direction parallel to the second direction DR2 to be adjacent to the central cell region.

[0229] like Figure 17 As shown and combined Figure 16 and Figure 13The deposition mask 2000 may also include third scale patterns 2330 disposed between the first scale patterns 2310. For example, the third scale patterns 2330 may overlap with the rib region 2014 of the mask frame 2010 in the thickness direction (e.g., third direction DR3) and may be disposed in the grid region 2120 of the diaphragm 2100 along the first direction DR1. In this case, the third scale patterns 2330 may be disposed at a second interval smaller than the first interval. Furthermore, each of the plurality of third scale patterns 2330 may have a length and width smaller than the length and width of the first scale patterns 2310 and may extend in the second direction DR2.

[0230] like Figure 17 As shown and combined Figure 16 and Figure 13 The deposition mask 2000 may also include a fourth scale pattern 2340 disposed between the second scale patterns 2320. For example, the fourth scale pattern 2340 may overlap with the rib region 2014 of the mask frame 2010 in the thickness direction and may be disposed in the grid region 2120 of the diaphragm 2100 along the second direction DR2. In this case, the fourth scale pattern 2340 may be arranged with a second gap. Furthermore, each of the plurality of fourth scale patterns 2340 may have a length and width smaller than that of the second scale pattern 2320 and may extend in the first direction DR1. For example, each of the plurality of fourth scale patterns 2340 may have the same length and width as the third scale pattern 2330.

[0231] The first scale pattern 2310, the second scale pattern 2320, the third scale pattern 2330, and the fourth scale pattern 2340 may include metallic materials. For example, the first scale pattern 2310, the second scale pattern 2320, the third scale pattern 2330, and the fourth scale pattern 2340 may be made of metallic materials such as tungsten (W), molybdenum (Mo), chromium (Cr), titanium (Ti), iron (Fe), nickel (Ni), tungsten nitride (WN), titanium nitride (TiN), and / or Invar alloys, and may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, and / or electroforming processes.

[0232] According to this embodiment, the first reinforcing pattern 2350 and the second reinforcing pattern 2360 can be used to reduce warpage and / or deformation of the deposition mask 2000. For example, as... Figure 16 and Figure 17As shown, the first reinforcing pattern 2350 may overlap with the rib region 2014 of the mask frame 2010 in the thickness direction (e.g., the third direction DR3) and may be disposed in the grid region 2120 of the diaphragm 2100. In particular, the first reinforcing pattern 2350 may extend along the first direction DR1, and each of the first scale pattern 2310 and the third scale pattern 2330 may extend from the first reinforcing pattern 2350 in the second direction DR2.

[0233] Specifically, the second reinforcing pattern 2360 may overlap with the rib region 2014 of the mask frame 2010 in the thickness direction (e.g., the third direction DR3) and may be disposed in the grid region 2120 of the diaphragm 2100. In particular, the second reinforcing pattern 2360 may extend along the second direction DR2, and each of the second scale pattern 2320 and the fourth scale pattern 2340 may extend from the second reinforcing pattern 2360 in the first direction DR1.

[0234] The first reinforcing pattern 2350 and the second reinforcing pattern 2360 may include metallic materials. For example, the first reinforcing pattern 2350 and the second reinforcing pattern 2360 may be made of metallic materials such as tungsten (W), molybdenum (Mo), chromium (Cr), titanium (Ti), iron (Fe), nickel (Ni), tungsten nitride (WN), titanium nitride (TiN), and / or Invar alloys, and may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, and / or electroforming processes.

[0235] The first scale pattern 2310, the second scale pattern 2320, the third scale pattern 2330, and the fourth scale pattern 2340, as well as the first reinforcing pattern 2350 and the second reinforcing pattern 2360, can be formed concurrently (e.g., simultaneously) using the same material. For example, in the inorganic membrane 2030 (e.g., see...), Figure 13After forming the second inorganic film for forming the diaphragm 2100, a photoresist pattern can be formed on the second inorganic film to expose portions where the first scale pattern 2310, the second scale pattern 2320, the third scale pattern 2330, and the fourth scale pattern 2340, as well as the first reinforcing pattern 2350 and the second reinforcing pattern 2360 will be formed. The photoresist pattern can be used as an etching mask to perform an anisotropic etching process to form multiple recesses that penetrate the second inorganic film and expose the inorganic film 2030. In this case, the inorganic film 2030 can be used as an etching stop film in the anisotropic etching process. Subsequently, a metal film made of the aforementioned metallic material can be formed on the second inorganic film to bury the recess, and then a planarization process, such as chemical mechanical polishing, is performed to form a first scale pattern 2310, a second scale pattern 2320, a third scale pattern 2330, and a fourth scale pattern 2340, as well as a first reinforcing pattern 2350 and a second reinforcing pattern 2360 in the recess. In this case, the planarization process can be performed until the second inorganic film (i.e., diaphragm 2100) is exposed such that the first scale pattern 2310, the second scale pattern 2320, the third scale pattern 2330, and the fourth scale pattern 2340, as well as the first reinforcing pattern 2350 and the second reinforcing pattern 2360 have the same thickness as the second inorganic film. Therefore, the first scale pattern 2310, the second scale pattern 2320, the third scale pattern 2330 and the fourth scale pattern 2340, as well as the first reinforcing pattern 2350 and the second reinforcing pattern 2360 can have the same thickness as the diaphragm 2100 and can be exposed through the top surface of the diaphragm 2100 so that they can be observed from the outside.

[0236] According to this embodiment, the first scale pattern 2310, the second scale pattern 2320, the third scale pattern 2330, and the fourth scale pattern 2340 can be detected using a simple vision camera without the need for a separate measuring device, thereby accurately measuring the warpage or deformation of the deposition mask 2000. Furthermore, according to this embodiment, the stiffness of the deposition mask 2000 can be increased by the first reinforcing pattern 2350 and the second reinforcing pattern 2360, and therefore, the warpage or deformation of the deposition mask 2000 can be reduced.

[0237] The above description is an example of the technical features of this disclosure, and those skilled in the art to which this disclosure pertains will be able to make various modifications and variations. Therefore, the embodiments of this disclosure described above can be implemented individually or in combination with each other.

[0238] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles and spirit and scope of this disclosure. Therefore, the embodiments are used only in a general and descriptive sense and are not intended to be limiting.

Claims

1. A deposition mask, characterized in that, The deposition mask includes: a mask frame having a cell opening and including a rib region defining the cell opening; a membrane including a cell region located above the cell opening and a mesh region on the rib region, respectively; and a plurality of first scale patterns overlapping the rib region in a thickness direction of the mask frame, the plurality of first scale patterns being located at the mesh region and spaced apart from each other at a first gap along a first direction crossing the membrane.

2. The deposition mask of claim 1, wherein, The first direction extends through a central portion of the membrane, and wherein each of the plurality of first scale patterns extends in a second direction intersecting the first direction.

3. The deposition mask of claim 1, wherein, The deposition mask further includes a plurality of second scale patterns overlapping the rib region in the thickness direction of the mask frame, the plurality of second scale patterns being located at the mesh region and spaced apart from each other at the first gap along a second direction intersecting the first direction.

4. The deposition mask of claim 1, wherein, The membrane is an inorganic membrane, and the plurality of first scale patterns are metal scale patterns.

5. The deposition mask of claim 1, wherein, When the plurality of first scale patterns are in the mesh region, the plurality of first scale patterns have a thickness equal to a thickness of the mesh region.

6. The deposition mask of claim 1, wherein, When the plurality of first scale patterns are on the mesh region, the plurality of first scale patterns have a thickness equal to or less than a thickness of the mesh region.

7. The deposition mask of claim 1, wherein, The deposition mask further includes a first reinforcement pattern overlapping the rib region in the thickness direction of the mask frame, extending along the first direction, and located in the mesh region.

8. A deposition mask, characterized by, The deposition mask includes: a mask frame having a cell opening and including a rib region defining the cell opening; a membrane including a cell region located above the cell opening and a mesh region on the rib region, respectively; a plurality of first scale patterns overlapping the rib region in a thickness direction of the mask frame and located in the rib region at a first gap along a first direction crossing a central portion of the membrane; and a plurality of second scale patterns overlapping the rib region in the thickness direction of the mask frame and located in the rib region at the first gap along a second direction intersecting the first direction while crossing the central portion of the membrane.

9. The deposition mask of claim 8, wherein, The deposition mask further includes a first reinforcement pattern overlapping the rib region in the thickness direction of the mask frame, extending along the first direction, and located in the rib region; and a second reinforcement pattern overlapping the rib region in the thickness direction of the mask frame, extending along the second direction, and located in the rib region.

10. An electronic device, comprising: The electronic device includes a display panel including a substrate and a plurality of light emitting layers formed on the substrate by using a deposition mask, the deposition mask including: a mask frame having a cell opening and including a rib region defining the cell opening; a membrane including a cell region located above the cell opening and a mesh region on the rib region, respectively; A plurality of first scale patterns overlapping the rib region in a thickness direction of the mask frame, the plurality of first scale patterns being located at the rib region and spaced apart from each other at a first gap along a first direction crossing the diaphragm.

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