Resource board card and testing machine
By designing resource boards and testers, the motherboard receives multiple clock signals of different frequencies and selects them through the multiplexer on the sub-board, solving the problem of low testing efficiency in traditional testers, realizing parallel testing of semiconductor devices, and improving testing efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2026-03-31
AI Technical Summary
Traditional semiconductor testing machines require generating clock signals of different frequencies for each functional module during testing, resulting in low testing efficiency.
The system employs a resource board and tester design. It receives multiple clock signals of different frequencies through the motherboard and selects them through the multiplexer and control module in the sub-board, thereby enabling parallel testing of the device under test.
It improves testing efficiency, reduces the serial process of clock signal generation, and enhances testing speed and efficiency.
Smart Images
Figure CN224066933U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing technology, and in particular to a resource board and a testing machine. Background Technology
[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of the device under test (DUT), eliminating defective products to control the quality of semiconductors leaving the factory. With the continuous development of technology, SOC (System on Chip) and DDR memory chips integrate more independent functional modules, and different functional modules have different clock requirements. In traditional testing machines, different clocks are generated sequentially within the board to meet these different clock requirements. After generating a clock signal of one frequency to test one functional module, a different clock signal of another frequency is generated to test the next functional module. This serial testing method requires more time and has the disadvantage of low testing efficiency. Utility Model Content
[0003] Therefore, it is necessary to provide a resource board and test machine that can improve testing efficiency to address the above problems.
[0004] The first aspect of this application provides a resource board, including:
[0005] The motherboard connects to the communication board, receives multiple clock signals of different frequencies output by the communication board, and transmits them to the daughter board.
[0006] At least one of the sub-boards includes a multiplexer and a control module. The multiplexer connects the motherboard and the control module, and selects and transmits clock signals of different frequencies received to the control module. The clock signals are used by the control module to test the device under test.
[0007] In one embodiment, the sub-board further includes a local clock unit, which is connected to the multiplexer and outputs a local clock signal, which is selected and output to the control module by the multiplexer; the frequency of the local clock signal is different from the frequency of the multiple clock signals transmitted by the motherboard.
[0008] In one embodiment, the local clock unit includes a first crystal oscillator and a first phase-locked loop (PLL), the first PLL being connected to the first crystal oscillator and the multiplexer.
[0009] In one embodiment, the control module connects to each functional unit in the device under test and performs parallel tests on the corresponding functional units according to the received clock signals of different frequencies.
[0010] In one embodiment, the control module includes a controller and a PE chip. The controller is connected to the multiplexer and the PE chip, and the PE chip is connected to each functional unit in the device under test through corresponding channels.
[0011] In one embodiment, the motherboard is a board that receives multiple clock signals of different frequencies originating from the same source.
[0012] A second aspect of this application provides a test machine, including a communication board and at least one of the aforementioned resource boards.
[0013] In one embodiment, the test machine further includes a backplane, through which the communication board is connected to the motherboard of any of the resource boards.
[0014] In one embodiment, the communication board includes a second crystal oscillator, a second phase-locked loop (PLL), a first clock fan-out, and a second clock fan-out. There are two or more second PLLs, each outputting clock signals of different frequencies. Each second PLL is connected to the second crystal oscillator via a first clock fan-out, and each second PLL is also connected to the backplane via a corresponding second clock fan-out.
[0015] In one embodiment, both the backplane and the motherboard are provided with a third clock fan-out corresponding to clock signals of different frequencies.
[0016] The aforementioned resource board and test machine have a motherboard that receives multiple clock signals of different frequencies output from the communication board and transmits them to a daughter board. The daughter board includes a multiplexer and a control module. The multiplexer connects the motherboard and the control module, selecting the received clock signals of different frequencies and sending them to the control module. These clock signals are used by the control module to test the device under test (DUT). By transmitting multiple clock signals of different frequencies from the motherboard to the daughter board, the daughter board can select the appropriate clock signal according to testing needs using the multiplexer. The control module uses the selected clock signal to test the DUT, eliminating the need to generate clock signals one by one for serial testing, thus improving testing efficiency. Attached Figure Description
[0017] Figure 1 This is a structural block diagram of a resource board in one embodiment;
[0018] Figure 2 This is a schematic diagram of the structure of a resource board in one embodiment;
[0019] Figure 3This is a schematic diagram of the test machine in one embodiment. Detailed Implementation
[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0022] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.
[0023] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts, or combinations thereof.
[0024] In one embodiment, such as Figure 1 As shown, a resource board is provided, including a motherboard 110 and at least one daughter board 120. The motherboard 110 is connected to a communication board, receives multiple clock signals of different frequencies output by the communication board, and transmits them to the daughter board 120. The daughter board 120 includes a multiplexer (MUX) and a control module 122. The multiplexer (MUX) is connected to the motherboard 110 and the control module 122, and selects the received clock signals of different frequencies to transmit to the control module 122. The clock signals are used by the control module 122 to test the device under test (DUT). The motherboard 110 receives multiple clock signals of different frequencies from the same source. The motherboard 110 transmits these clock signals to the daughter board 120 for testing, resulting in relatively small errors in jitter and offset, thus reducing problems caused by clock asynchrony. Furthermore, the control module 122 is connected to each functional unit in the DUT and performs parallel testing on the corresponding functional units based on the received clock signals of different frequencies. Resource boards include, but are not limited to, digital I / O boards, power supply I / O boards, radio frequency (RF) boards, or mixed analog-to-digital (A / D) boards.
[0025] The motherboard 110 can be directly or indirectly connected to the communication board, transmitting multiple clock signals of different frequencies output by the communication board to the daughter board 120. There can be one or more daughter boards 120. The device under test (DUT) can be a SOC chip or other type of memory semiconductor chip. The daughter board 120 connects to the corresponding DUT for parameter testing. The DUT contains multiple functional units that need to be tested, and the frequency of the clock signal required for testing each functional unit will be different. According to actual testing needs, the communication board can be controlled to output multiple frequency clock signals, which are then transmitted from the motherboard 110 to the daughter board 120. The multiplexer (MUX) in the daughter board 120 selects and sends the clock signals of different frequencies to the control module 122, allowing the control module 122 to use different frequency clock signals to test the corresponding functional units in the DUT.
[0026] Specifically, such as Figure 2 As shown, the control module 122 includes a controller and a PE (Pin Electronics Driver / Comparator) chip. The controller is connected to the multiplexer MUX and the PE chip, and the PE chip is connected to each functional unit in the device under test through corresponding channels. The controller can be an FPGA, CPU, MCU, etc. In this embodiment, the controller uses an FPGA. The motherboard 110 can be connected to the communication board through the backplane 300, and receives multiple clock signals of the same source but different frequencies output by the communication board, such as clock signal CLK_A, clock signal CLK_B, etc. The motherboard 110 transmits the received multiple clock signals to the multiplexer MUX in the daughter board 120.
[0027] Furthermore, the daughterboard 120 also includes a local clock unit 124, which is connected to a multiplexer (MUX) and outputs a local clock signal. This local clock signal is selected and output to the control module 122 via the multiplexer. The frequency of the local clock signal is different from the frequencies of the multiple clock signals transmitted by the motherboard 110. The local clock unit 124 may include a first crystal oscillator (OSC1) and a first phase-locked loop (PLL1), which is connected to the OSC1 and the multiplexer (MUX). The multiplexer (MUX) can be selected and controlled by the motherboard 110 or other control devices to send either the clock signal sent by the motherboard 110 or the local clock signal generated by the local clock unit 124 to the controller. The controller then tests the corresponding functional units in the device under test through the channels of the PE chip based on the received clock signal.
[0028] In one embodiment, such as Figure 2 and Figure 3As shown, a test machine is also provided, including a communication board 200 and at least one of the aforementioned resource boards. The test machine may also include a backplane 300, through which the communication board 200 is connected to the motherboard 110 of any of the resource boards. The test machine may include multiple resource boards, each containing a motherboard 110 and multiple sub-boards 120. Each sub-board 120 has multiple output channels, which can be configured into test ports to test the device under test as needed.
[0029] Specifically, such as Figure 3 As shown, the communication board 200 may include a second crystal oscillator OSC2, a second phase-locked loop (PLL) 2, a first clock fan-out BUFFER 1, and a second clock fan-out BUFFER 2. There are two or more second PLLs, each outputting clock signals of different frequencies. Each second PLL 2 is connected to the second crystal oscillator OSC2 via the first clock fan-out BUFFER 1, and each second PLL 2 is also connected to the backplane 300 via its corresponding second clock fan-out BUFFER 2, outputting clock signals of the same origin but different frequencies to the backplane 300. Furthermore, both the backplane 300 and the motherboard 110 are equipped with third clock fan-out BUFFERs corresponding to different frequency clock signals, transmitting clock signals of the corresponding frequencies.
[0030] like Figure 2As shown, taking the resource board DIO as an example, the mainboard 110 is connected to multiple sub-boards 120, such as sub-boards DIO_Fe0 to DIO_Fe7, for a total of 8 sub-boards 120. Each sub-board 120 is equipped with a multiplexer (MUX), a control module 122, and a local clock unit 124. The control module 122 includes an FPGA and a PE chip. The channel of the PE chip is connected to the interface of the device under test. The local clock unit 124 includes a first crystal oscillator (OSC1) and a first phase-locked loop (PLL1). After receiving the clock signals CLK_A and CLK_B provided by the backplane 300, the mainboard 110 outputs the same clock signal to the 8 sub-boards 120 through the internal third clock fan-out (CLOCK BUFFER). Each sub-board 120 is equipped with a first crystal oscillator (OSC1), which can generate a local clock signal CLK_C through the first phase-locked loop (PLL1). The eight sub-boards 120 receive the same clock signal CLK_A and the same clock signal CLK_B. The local clock signal CLK_C of the eight sub-boards 120 can be the same or different to accommodate the different testing requirements of each sub-board 120. Each sub-board 120 corresponds to a group of 32 channels. The 32 channels in the same group share the same clock signal CLK_A, clock signal CLK_B, and local clock signal CLK_C. A multiplexer (MUX) selects which clock signal to connect to the FPGA. The FPGA controls the 32 channels of the PE chip to operate according to the received clock signal to test the device under test (DUT). Alternatively, the channels of the PE chip can be divided into one or more groups, with each group connected to a corresponding functional unit in the DUT. The FPGA performs different functional tests through the different groups of channels of the PE chip, enabling testing based on different clock frequencies according to the different interface operating frequencies of the DUT.
[0031] The test machine provided in this application can achieve parallel testing of different functional units of the device under test (DUT) by setting clock signals of different frequencies. The internal resources can be combined with test ports according to requirements, enabling simultaneous testing of functional components such as the DUT's core, FLASH, and RAM. Both synchronous and asynchronous clocks are available to meet the needs of scenarios requiring simultaneous or asynchronous testing.
[0032] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0033] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A resource board card, characterized by, The application relates to a communication board and a resource board. The main board card is connected with the communication board card, receives a plurality of clock signals of different frequencies output by the communication board card and transmits the clock signals to the sub-board card. At least one of the sub-board cards comprises a multiplexer and a control module, the multiplexer is connected with the main board card and the control module, and the multiplexer selects and transmits the received clock signals of different frequencies to the control module; the clock signals are used for testing the device under test by the control module.
2. The resource board card of claim 1, wherein, The sub-board card further comprises a local clock unit, the local clock unit is connected with the multiplexer, outputs a local clock signal and transmits the local clock signal to the control module through the multiplexer. The frequency of the local clock signal is different from the frequency of the clock signals transmitted by the main board card.
3. The resource board card of claim 2, wherein, The local clock unit comprises a first crystal oscillator and a first phase-locked loop, the first phase-locked loop is connected with the first crystal oscillator and the multiplexer.
4. The resource board card of claim 1, wherein, The control module is connected with each functional unit in the device under test, and the control module tests the corresponding functional units in parallel according to the received clock signals of different frequencies.
5. The resource board card according to any one of claims 1-4, wherein, The control module comprises a controller and a PE chip, the controller is connected with the multiplexer and the PE chip, and the PE chip is connected with each functional unit in the device under test through a corresponding channel.
6. The resource board card of claim 5, wherein, The main board card is a board card for receiving a plurality of clock signals of different frequencies.
7. A testing machine characterized by, The application further relates to a communication board and at least one resource board.
8. The testing machine of claim 7, wherein, The communication board is connected with the main board card in any of the resource boards through a backboard.
9. The testing machine of claim 8, wherein, The communication board comprises a second crystal oscillator, a second phase-locked loop, a first clock fan-out device and a second clock fan-out device, the number of the second phase-locked loops is more than two, and the second phase-locked loops output clock signals of different frequencies; each second phase-locked loop is connected with the second crystal oscillator through the first clock fan-out device, and each second phase-locked loop is connected with the backboard through a corresponding second clock fan-out device.
10. The testing machine of claim 8, wherein, The backboard and the main board card are provided with third clock fan-out devices corresponding to the clock signals of different frequencies.