Integrated circuit device

Abstract

The utility model provides an integrated circuit device which comprises a substrate. A photodetector includes a substrate including a first surface and a second surface, a first dielectric layer disposed on the second surface of the substrate, a light detector and an optical edge coupler disposed in the first dielectric layer, at least one dielectric layer disposed on the first dielectric layer, a conductive structure disposed in the at least one dielectric layer, a conductive pad disposed on the surface of the integrated circuit device, and a trench extending from the surface of the integrated circuit device toward the substrate. The conductive pad is electrically coupled to the light detector through the conductive structure. An optical edge coupler is optically coupled to the light detector and is configured to receive light from a sidewall of the trench.

Description

Technical Field

[0001] This utility model relates to an integrated circuit device that facilitates same-side electrical and optical testing at multiple stages of manufacturing. Background Technology

[0002] The continued development of integrated circuit (IC) technology has resulted in the integration of electrical and optical functions into a single IC device. To support this integration, yield testing of the device's electrical functions (e.g., using circuit probes (CP)) and optical functions (e.g., using lasers for optical test inputs) is performed before customer delivery to reduce or eliminate the delivery of IC devices that are non-functional or have poor performance. Utility Model Content

[0003] This utility model provides an embodiment relating to an integrated circuit (IC) device. The device includes a substrate having a first surface and a second surface; a first dielectric layer disposed on the second surface of the substrate; a photodetector and an optical edge coupler disposed in the first dielectric layer, the optical edge coupler being optically coupled to the photodetector; at least one dielectric layer disposed on the first dielectric layer; a conductive structure disposed in the at least one dielectric layer; a conductive pad disposed on the surface of the IC device, the conductive pad being electrically coupled to the photodetector through the conductive structure; and a trench extending from the surface of the IC device toward the substrate, the optical edge coupler being configured to receive light from the sidewalls of the trench.

[0004] This utility model provides an integrated circuit device. The integrated circuit device includes an electrical integrated circuit structure and a photonic integrated circuit structure. The electrical integrated circuit structure includes: an electrical integrated circuit die; and a first conductive pad disposed on the surface of the electrical integrated circuit structure and electrically coupled to the electrical integrated circuit die. The photonic integrated circuit structure is disposed adjacent to the surface of the electrical integrated circuit structure, and the photonic integrated circuit structure includes: a substrate including a first surface and a second surface; a first dielectric layer disposed on the second surface of the substrate; a photodetector and an optical edge coupler disposed in the first dielectric layer, the optical edge coupler being optically coupled to the photodetector; at least one dielectric layer disposed on the first dielectric layer; a conductive structure disposed in the at least one dielectric layer; a second conductive pad disposed on the surface of the photonic integrated circuit structure and contacting the first conductive pad, the second conductive pad being electrically coupled to the photodetector through the conductive structure; a third conductive pad disposed on the first surface of the substrate and electrically coupled to the conductive structure; and a trench extending from the first surface of the substrate to the electrical integrated circuit structure, the optical edge coupler being configured to receive light from the sidewalls of the trench. Attached Figure Description

[0005] The present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the sizes of the various features may be arbitrarily increased or decreased.

[0006] Figure 1A and Figure 1B Schematic perspective views and plan views are shown respectively of some embodiments of the manufacture of integrated circuit (IC) devices according to the present disclosure, which facilitate on-side electrical and optical testing at multiple stages of manufacture.

[0007] Figure 1C and Figure 1D Schematic side views of several embodiments of the photonic IC (P-IC) structure and subsequent combined structure according to this disclosure are shown, which facilitate on-side electrical and optical testing at different stages of manufacturing.

[0008] Figure 2A and Figure 2B Structural side views and plan views of some embodiments of the P-IC structure according to this disclosure are shown, which facilitate on-side electrical and optical testing during the respective manufacturing stages.

[0009] Figure 3A and Figure 3B Structural side views and plan views of some embodiments of the combined P-IC / E-IC (E-IC) structure according to this disclosure are shown respectively, which facilitates same-side electrical and optical testing at the respective manufacturing stages.

[0010] Figure 4A and Figure 4B Structural plan and side views of some embodiments of an optical edge coupler for an IC device according to this disclosure are shown, which facilitates same-side electrical and optical testing at multiple stages of manufacturing.

[0011] Figures 5A to 5K Cross-sectional views of some embodiments of a semiconductor structure according to this disclosure are shown, the semiconductor structure including an optical edge coupler for an IC device, the optical edge coupler facilitating same-side electrical and optical testing at multiple stages of manufacturing.

[0012] Figure 6A and Figure 6B The formation according to some embodiments is shown. Figures 5A to 5K Methods for developing semiconductor structures. Detailed Implementation

[0013] The following utility model description provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the utility model description. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature is formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the utility model description. This repetition is for simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and similar terms may be used to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of components in use or operation. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0015] As optical and associated electrical functions continue to be further integrated into single IC devices, simultaneous testing of both types of functions within a device is considered important from the perspectives of photonics wafer acceptance testing (oWAT) and chip probe (CP) testing. However, such simultaneous testing can be challenging because accessible electrical input / output (I / O) points may be located on the side of the device opposite the optical I / O location, and some test equipment and processes may be incompatible with simultaneous access to both sides of the IC device. Providing test optical I / O paths on the opposite side of the device from the optical I / O paths used during normal operation is possible. However, these test paths may suffer significant optical signal loss due to undesirable diffraction and scattering effects, resulting in lower efficiency for the associated optical tests.

[0016] Furthermore, providing such testing at a single stage of device manufacturing (e.g., after integrating these functions at or near the end of device manufacturing) can lead to a significant increase in the percentage of devices ultimately rejected because parts of the device cannot be tested at multiple (e.g., earlier) manufacturing stages.

[0017] To address these issues, this disclosure provides embodiments of IC devices that facilitate on-side electrical and optical testing at multiple stages of manufacturing. In some embodiments, a photonic IC (P-IC) structure (e.g., prior to integration with an E-IC structure) may have conductive pads electrically coupled to a photodetector and trenches on the upper surface of the P-IC structure, with the trenches facilitating optical access from the upper surface of the P-IC to an optical edge detector optically coupled to the photodetector. Therefore, the conductive pads and optical edge detectors can be accessed from the upper surface of the P-IC structure to perform electro-optical testing.

[0018] Furthermore, in some embodiments, the combined structure including the P-IC structure and the E-IC structure bonded to the upper surface of the P-IC structure may include another conductive pad located on the lower surface of the P-IC structure and a trench facilitating optical access from the lower surface of the P-IC structure to an optical edge detector. Therefore, the other conductive pad and the optical edge detector can be accessed from the (opposite) lower surface of the P-IC structure to perform electro-optical testing of the E-IC die incorporating the E-IC structure.

[0019] Therefore, some embodiments using IC devices can provide more accurate and therefore more useful simultaneous electrical and optical testing capabilities on the same side, which can be performed at multiple stages of device manufacturing using currently available test systems. In some embodiments, this testing capability can more accurately and effectively ensure die yield and more precisely monitor IC process health.

[0020] Figure 1A and Figure 1B Schematic perspective views and plan views are shown respectively of some embodiments of the fabrication of an integrated circuit (IC) device 112 according to the present disclosure, which facilitates same-side electrical and optical testing at multiple stages of fabrication. As described in more detail below, in some embodiments, an E-IC wafer 101 (e.g., a semiconductor wafer including one or more circuits) and a P-IC structure 106 (e.g., an optical wafer including one or more photonic structures and associated circuits) can be fabricated or provided. As described in more detail below, the P-IC structure 106 may include first edge coupling (EC) trenches 121 extending from the upper surface of the P-IC structure 106 into the P-IC structure 106. Each first EC trench 121 facilitates access to a corresponding optical edge coupler (in Figure 1A and Figure 1B (Not explicitly shown in the text), the optical edge coupler is optically coupled to the photodetector (in... Figure 1A and Figure 1B(Not explicitly shown in the text). Therefore, each first EC trench 121 and located in the P-IC structure 106 ( Figure 1A and Figure 1B The corresponding first conductive pad on the upper surface (not shown) can facilitate combined electrical-optical testing 110 of the P-IC structure 106 in the early manufacturing stages of the IC device 112.

[0021] Subsequently, after the E-IC wafer 101 is monomerized into a plurality of E-IC dies 103, the E-IC dies 103 may be bonded or otherwise attached to the P-IC structure 106, further supplementing it to form an E-IC structure 104, which, together with the P-IC structure 106, constitutes a combined structure 108. In some embodiments, the P-IC structure 106 may include a second EC trench 122 extending from the lower surface of the P-IC structure 106. As described above, each second EC trench 122 facilitates access to a corresponding optical edge coupler optically coupled to a photodetector. In some embodiments, each second EC trench 122 may be substantially perpendicularly aligned with a corresponding first EC trench 121. Therefore, each second EC trench 122 and a corresponding second conductive pad at the lower surface of the P-IC structure 106 can facilitate combined electro-optic testing 110 of the combined structure 108 in later stages of IC device 112 manufacturing.

[0022] Furthermore, in some embodiments, after the combined structure 108 is individualized into a single IC device 112, each IC device 112 can be electro-optically tested 110 via the optical edge coupler discussed above.

[0023] Figure 1C and Figure 1D Schematic side views of some embodiments of the P-IC structure 106 and subsequent combined structure 108 according to this disclosure are shown, which facilitate same-side electrical and optical testing at different stages of manufacturing. Figure 1C The P-IC structure 106 (e.g., prior to its integration with the E-IC die 103) may include an optical edge coupler 124 optically coupled to a photodetector (PD) 126 (e.g., a photodiode). The P-IC structure 106 may also include at least one conductive pad 130 at a first surface (e.g., the upper surface) of the P-IC structure 106, the conductive pad 130 being coupled to the PD 126 through a conductive structure 123. Furthermore, the P-IC structure 106 may include a first EC trench 121 extending from the upper surface of the P-IC structure 106 to facilitate optical access to the optical EC 124, thereby allowing combined electrical detection and edge-coupled optical testing via the first surface.

[0024] Subsequently, as described above, the E-IC die 103, as part of the E-IC structure 104, can be bonded to the upper surface of the P-IC structure 106 (e.g., thus covering the opening of the first EC trench 121). In some embodiments, when the E-IC die 103 is bonded to the P-IC structure 106, the conductive pad 130 electrically connected to the E-IC die 103 can contact the conductive pad 130 on the first surface of the P-IC structure 106, thereby electrically coupling the E-IC die 103 to the PD 126 through the conductive structure 123. Furthermore, another conductive pad 130 at the second (e.g., lower) surface of the P-IC structure 106 can be electrically coupled to the conductive structure 123, thereby electrically coupling to the E-IC die 103. Furthermore, the P-IC structure 106 may include a second EC trench 122 extending from the second surface of the P-IC structure 106 (e.g., sharing at least some volume with the first EC trench 121) to facilitate optical access to the optical EC 124, thereby allowing combined electrical detection and edge-coupled optical testing via the second surface, such as... Figure 1D As shown.

[0025] Figure 2A and Figure 2B Structural side views and plan views of some embodiments of the P-IC structure 106 according to this disclosure are shown, which facilitates same-side electrical and optical testing during the respective manufacturing stages. Figure 2B Compared to Figure 2A The possible length (L) of the first trench 121 relative to its width (W) is shown at a smaller scale, and will be discussed in more detail below. In some embodiments, the P-IC structure 106 (e.g., before being combined with the E-IC structure 104) may include a substrate 202. Examples of materials used in the substrate 202 may include, but are not limited to, silicon (Si), silicon dioxide (SiO2), boron (B), phosphorus (P), etc. Furthermore, a buried oxide layer 204 may be disposed on the substrate 202. In some embodiments, the buried oxide layer 204 may be formed by using an oxygen ion beam implantation process on the substrate 202 to form an oxygen-rich layer, which may then be annealed to produce the buried oxide layer 204.

[0026] In some embodiments, a dielectric layer (e.g., oxide layer 214) may be disposed on the oxide layer 204. Examples of materials in the oxide layer 214 may include, but are not limited to, silicon oxide (SiO2). x (e.g., SiO2) or another oxide or dielectric layer. Within the oxide layer 214, an optical edge coupler (EC) 124 and a photodetector (PD) 126 can be configured and optically coupled together, for example, through a waveguide ( Figure 2A(Not explicitly shown in the text). In some embodiments, PD 126 may also be coupled to a grating coupler ( Figure 2A (not shown in the image), so as to receive light via the upper or lower surface of the P-IC structure 106.

[0027] In some embodiments, the optical EC 124 may include an upper portion 208 and a lower portion 206 to facilitate the transfer of light received by the optical EC 124 into a waveguide for transmission to the PD 126. (The following is in conjunction with...) Figure 4A and Figure 4B Discuss examples of optical EC 124.

[0028] In some embodiments, such as Figure 2A As shown, PD 126 can include germanium structure 207 on silicon structure 205 forming a photodiode. However, other types of photodetectors, including other forms of photodiodes, can be used as PD 126.

[0029] At least one dielectric layer 210 may be disposed on the oxide layer 214, PD 126, and optical EC 124. In some embodiments, the at least one dielectric layer 210 may comprise one or more dielectric materials, including but not limited to silicon oxide (SiO2). x (For example, silicon dioxide (SiO2)), tantalum nitride (TaN), etc.

[0030] Conductive structure 212 may be configured within at least one dielectric layer 210. In some embodiments, conductive structure 212 may include vertically oriented vias and interconnecting metal wiring layers to electrically couple components within P-IC structure 106. Conductive structure 212 may include n (e.g., 6) metal layers and n-1 (e.g., 5) intermediate vias, although in other embodiments there may be more or fewer layers and vias. In some embodiments, conductive structure 212 may provide one or more separate electrical connections between components, such as PD 126. Conductive structure 212 may include, but is not limited to, copper (Cu), tantalum (Ta), manganese (Mn), aluminum (Al), silicon (Si), titanium (Ti), tungsten (W), other metals or alloys, or other conductive materials.

[0031] A via 216 (e.g., a through-dielectric via, TDV) may be configured on the upper surface of at least one dielectric layer 210 and may be electrically connected to the conductive structure 212. In some embodiments, the via 216 may be a conductive material, such as one or more conductive materials listed above for the conductive structure 212.

[0032] Another dielectric structure (e.g., oxide layer 214) may be disposed on at least one dielectric layer 210 to form the upper surface of the P-IC structure 106. In some embodiments, oxide layer 214 may comprise the same dielectric material as oxide layer 214 disposed beneath at least one dielectric layer 210, or may comprise a different dielectric material.

[0033] The first conductive pad 130 may be disposed on the upper surface of the P-IC structure 106 (e.g., in the oxide layer 214). The first conductive pad 130 may contact the via 216, thereby providing an electrical connection to the PD 126 through the conductive structure 212. In some embodiments, the first conductive pad 130 may comprise one or more conductive materials, such as those discussed above in conjunction with the conductive structure 212 and / or the via 216. Thus, as Figure 2A As shown, the first conductive pad 130 can be easily engaged with the electrical test probe 260 (e.g., the test probe of a circuit test probe (CP) tester) from above the P-IC structure 106.

[0034] The P-IC structure 106 may also include a first trench 121 extending from the upper surface of the P-IC structure 106 toward the substrate 202. In some embodiments, the first trench 121 may extend to the upper surface of the substrate 202, possibly to a point above the substrate 202, or possibly into the substrate 202. Furthermore, in some embodiments, the first trench 121 may be configured to facilitate optical access to the optical EC 124 (e.g., by exposing a portion of the optical EC 124 to the first trench 121). In some embodiments, the first trench 121 may have dimensions that allow the first trench 121 to receive an optical test probe 250 from above the P-IC structure 106, the optical test probe 250 emitting light as an optical signal to the optical EC 124, which then forwards the signal to the PD 126 (e.g., via a waveguide). For example, as... Figure 2A and Figure 2B As shown, the width (W) of the first trench 121 is at least 10 micrometers, the depth (D) is at least 50 micrometers, and the length (L) is at least 200 micrometers. In some embodiments, the width (W) of the first trench 121 is approximately 60 micrometers, the depth (D) is approximately 95 micrometers, and the length (L) is approximately 1500 micrometers. In some embodiments, the sidewalls of the first trench 121, where the upper portion 208 of the optical EC 124 is located, can be substantially vertical (e.g., perpendicular to the substrate 202, such as...). Figure 2A (as shown), while in other embodiments, the sidewalls may be more inclined relative to the vertical direction.

[0035] Therefore, in Figure 2A and Figure 2BIn embodiments of the P-IC structure 106, combined electrical and optical tests 110 of the P-IC structure 106 (e.g., before the E-IC structure is incorporated thereon) can therefore be performed via an electrical test probe 260 in contact with the first conductive pad 130 and an optical test probe 250 providing an optical signal through an optical EC 124 in the first trench 121. This combined electrical and optical testing can be performed from above the upper surface of the P-IC structure 106.

[0036] Figure 3A and Figure 3B Structural side views and plan views of some embodiments of the combined P-IC / E-IC structure 108 according to the present disclosure are shown respectively, which facilitates same-side electrical and optical testing at the respective manufacturing stages. Figure 3B In relation to Figure 3A The smaller scale is used to depict the possible length (L) of the width (W) of the second groove 121 relative to the second groove 122, which will be discussed in more detail below.

[0037] like Figure 3A and 3B As shown, the P-IC structure 106 of the combined structure 108 includes the above-mentioned... Figure 2A and Figure 2B The P-IC structure 106 discusses many or all of the components. The differences will be discussed in more detail below.

[0038] exist Figure 3A and Figure 3B The manufacturing stages shown include bonding the E-IC structure 104 of the E-IC die 103 to the upper surface of the P-IC structure 106. In some embodiments, the E-IC die 103 may include logic circuitry for controlling the PD 126, capturing data therefrom, and / or processing such data. Furthermore, in some embodiments, the E-IC die 103 may include a conductive structure 322 electrically connected to a second conductive pad 130 surrounded by an oxide layer 214. Therefore, the E-IC structure 104 can be bonded to the P-IC structure 106 through the second conductive pad 130 of the E-IC structure 104 bonded to the first conductive pad 130 of the E-IC die 103 and / or through the oxide layer 214 surrounding the second conductive pad 130 bonded to the oxide layer 214 at the upper surface of the P-IC structure 106. In some embodiments, this bonding can be performed using a heat-based bonding process. In some embodiments, this bonding can close the opening end of the first trench 121.

[0039] In some embodiments, a carrier 324 (e.g., a silicon (Si) carrier) may be configured on the E-IC die 103 to facilitate processing of the combined structure 108 during subsequent manufacturing stages of the IC device 112. Figure 3A As shown, a carrier 324 can be provided to prepare for narrowing or "thinning" the substrate 202 of the P-IC structure 106. The E-IC die 103, the carrier 324, the second conductive pad 130, and the associated oxide layer 214 are referred to herein as the E-IC structure 104.

[0040] like Figure 3A As shown, in addition to the thinned substrate 202, the P-IC structure 106 may include a newly formed via 326 that extends through the buried oxide layer 204 and the adjacent oxide layer 214 and contacts the conductive structure 212 (e.g., at its underlying metal layer). A third conductive pad 130 is disposed in the substrate 202 and contacts the via 326. In some embodiments, the via 326 may be a TDV, similar to the via 216 described above. In some embodiments, the third conductive pad 130 may include one or more conductive materials, such as those discussed above in conjunction with the first and second conductive pads 130. Thus, as Figure 3A As shown, the third conductive pad 130 can be easily coupled to the electrical test probe 260 from below the P-IC structure 106.

[0041] The P-IC structure 106 also includes a second trench 122 extending from the lower surface of the P-IC structure 106 at the substrate 202 toward the E-IC structure 104. In some embodiments, the second trench 122 may extend to the lower surface of the E-IC structure 104, possibly to a point below the E-IC structure 104, or possibly into the E-IC structure 104. Furthermore, in some embodiments, the second trench 122 may be configured to facilitate optical access to the optical EC 124 (e.g., by exposing a portion of the optical EC 124 to the second trench 122). In some embodiments, like the first trench 121, the second trench 122 may have dimensions that allow the second trench 122 to receive an optical test probe 250 from below the P-IC structure 106, the optical test probe 250 emitting light as an optical signal to the optical EC 124, which then forwards the signal to the PD 126 (e.g., via a waveguide). For example, as... Figure 3A and Figure 3BAs shown, the second trench 122 has a width (W) of at least 10 micrometers, a depth (D) of at least 50 micrometers, and a length (L) of at least 200 micrometers. In some embodiments, the second trench 122 may have a width (W) of approximately 60 micrometers, a depth (D) of approximately 95 micrometers, and a length (L) of approximately 1500 micrometers. Furthermore, in some embodiments, the second trench 122 may have a length that matches or exceeds the width or length of the E-IC die 103, such as... Figure 3B As shown. Furthermore, in some embodiments, the second trench 122 is substantially vertically aligned with the preceding first trench 121 and may be at least as wide as, or wider than, the first trench 121. Additionally, in some embodiments, the sidewalls of the second trench 122, where the upper portion 208 of the optical EC 124 is located, may be substantially vertical (e.g., perpendicular to the substrate 202, as shown). Figure 3A (as shown), while in other embodiments, the sidewalls may be more inclined relative to the vertical direction.

[0042] Therefore, in Figure 3A and 3B In embodiments of the combined structure 108, combined electrical and optical testing 110 of the combined structure 108 (e.g., including testing of the E-IC die 103 after the E-IC die 103 is bonded to the P-IC structure 106) can therefore be performed via an electrical test probe 260 contacting the third conductive pad 130 and an optical test probe 250 providing an optical signal through an optical EC 124 in the second trench 122. This combined electrical and optical testing can be performed through the lower surface of the P-IC structure 106, opposite the upper surface, through which combined electrical and optical testing 110 can be performed before the E-IC structure 104 is bonded to the P-IC structure 106. In some embodiments, the combined structure 108 can be relative to... Figure 3A The structure shown is flipped or inverted so that all combined electrical and optical tests can be performed from above.

[0043] Figure 4A and Figure 4B Structural plan views and side views of several embodiments of an optical EC 124 for an IC device 112 according to this disclosure are shown, facilitating same-side electrical and optical testing at multiple stages of manufacturing. As described above, the optical EC 124 may include an upper portion 208 and a lower portion 206 disposed within an oxide layer 214. In some embodiments, such as Figure 4AAs shown in the plan view, the upper portion 208 may have a first rectangular portion 208A and a laterally tapered portion 208B, while the lower portion 206 may have a second rectangular portion 206A and a laterally reverse tapered portion 206B. In some embodiments, the upper portion 208 may include silicon mononitride (SiN), and the lower portion 206 may include silicon (Si). However, other optically transmitting materials may also be used for the upper portion 208 and the lower portion 206. In some embodiments, the upper portion 208 receives light 230 of a first spot size (e.g., from an optical fiber or an optical test probe 250, such as...). Figure 2A and Figure 3A As shown), and forwards the light to the lower part 206 to reduce the spot size so that it can be transmitted to PD126 through the waveguide.

[0044] like Figure 4A and Figure 4B As shown, the transverse tapered portion 208B at least partially overlaps with the transverse reverse tapered portion 206B, and may completely overlap. Furthermore, in some embodiments, the upper portion 208 may be perpendicularly separated from the lower portion 206 within the oxide layer 214, and its thickness may be less than the thickness of one or both of the upper portion 208 and the lower portion 206. Furthermore, in some embodiments, regarding... Figure 3A and Figure 3B Various dimensions A through H are shown, where A can be approximately 800 nanometers (nm), B can be approximately 370 nanometers, C can be approximately 200 nanometers, D can be approximately 30 micrometers, E can be approximately 400 nanometers, F can be approximately 100 nanometers, G can be approximately 270 nanometers, and H can be approximately 2000 nanometers. However, in other embodiments, other dimensions may be employed in the similarly configured optical EC 124. Furthermore, in other embodiments, other types or configurations of optical edge ECs may be employed to couple received light into a waveguide for transmission within the oxide layer 214 to the PD 126.

[0045] Figures 5A to 5K Cross-sectional views of some embodiments of a semiconductor structure according to this disclosure are shown, the semiconductor structure including optical edge couplers (e.g., optical EC 124) for multiple manufacturing stages of an IC device (e.g., IC device 112), which facilitate on-side electrical and optical testing. Although Figures 5A to 5K The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted, in whole or in part.

[0046] Figure 5A A P-IC structure 106 is shown, on which subsequent operations can be performed to facilitate combined electrical and optical testing. As described above... Figure 2A As described, the P-IC structure 106 may include a substrate 202 (e.g., a silicon substrate) on which a buried oxide layer 204 may be disposed. An oxide layer 214 or another dielectric material layer may be disposed on the buried oxide layer 204. Within the oxide layer 214, optical EC 124 and PD 126 may be configured and optically coupled together, for example, through a waveguide ( Figure 5A (Not explicitly shown). In some embodiments, as described above, the optical EC 124 may include an upper portion 208 and a lower portion 206 to facilitate the transfer of light received by the optical EC 124 into a waveguide for transmission to the PD 126. Furthermore, in some embodiments, the PD 126 may include a germanium structure 207 on the silicon structure 205 forming the photodiode. However, other types of photodetectors, including other forms of photodiodes, may be used as the PD 126. The P-IC structure 106 may also include a conductive structure 212 disposed within at least one dielectric layer 210 on the oxide layer 214, wherein the conductive structure 212 may be electrically coupled to the PD 126. Additionally, an additional oxide layer 214 may be disposed on at least one dielectric layer 210. Various possible materials included in each of these components may be combined as described above. Figure 2A The subject of discussion.

[0047] In some embodiments, Figure 5A The formation of each component of the P-IC structure 106 shown can begin with providing a substrate 202 and continue through a series of formation (e.g., deposition) and etching operations to form various layers (e.g., starting with a buried oxide layer 204) and encapsulated components (e.g., optical EC couplers 124 and PD 126) to end with the deposition of an additional oxide layer 214 on at least one dielectric layer 210.

[0048] Figure 5B The formation (e.g., etching and deposition) of additional features of the P-IC structure 106 is illustrated to facilitate combined electrical and optical testing of the P-IC structure 106, as described above. Figure 2A More specifically, the additional oxide layer 214 and at least one underlying dielectric layer 210 may be etched, and the upper surface of the P-IC structure 106 may subsequently be filled with a conductive material to form a via 216 (e.g., TDV) and a first conductive pad 130, thereby creating an electrical connection between the first conductive pad 130 and the PD 126 through the via 216 and the conductive structure 212. In some embodiments, the dimensions of the first conductive pad 130 are determined to align with an electrical test probe (e.g., electrical test probe 260), as described above. Figure 2A The subject of discussion.

[0049] Figure 5BIt is also shown that a first EC trench 121 is formed (e.g., etched) towards the substrate 202 through an additional oxide layer 214 on the upper surface of the P-IC structure 106. This etching may end at the substrate 202, before reaching the substrate 202, or within the substrate 202. As described above, the size of the first EC trench 121 can be adapted to insert an optical test probe (e.g., optical test probe 250) into the first EC trench 121 to emit light into an optical EC 124 for transmission to the PD 126.

[0050] Figure 5C An optical test probe 250 and an electrical test probe 260 are shown engaging with a first conductive pad 130 in a first EC trench 121 to perform combined electrical and optical testing of a P-IC structure 106 including a PD 126 and an optical EC 124. In some embodiments, such as Figure 1A and Figure 1B As shown, the P-IC structure 106 can include multiple PDs 126, optical ECs 124, and associated first conductive pads 130, first EC trenches 121, etc., within a single P-IC chip.

[0051] In some embodiments, Figures 5D to 5J Depicting what can be described from Figure 2A P-IC structure 106 to Figure 3A The manufacturing stage of the conversion process of the combined structure 108. For example, Figure 5D The formation (e.g., deposition) of a filler material (e.g., conductive material 502, such as copper (Cu) or another metal, alloy or other conductive material) in the first EC trench 121 is shown. In some embodiments, the conductive material 502 is formed to prevent damage to the optical EC 124 or other portions of the P-IC structure 106 in subsequent manufacturing steps discussed below.

[0052] Figure 5E The connection (e.g., bonding) between the E-IC die 103 and the upper surface of the P-IC structure 106 is illustrated. In some embodiments, another oxide layer 214 may be formed (e.g., deposited) on the lower surface of the E-IC die 103, subsequently etched and filled with a conductive material to form a second conductive pad 130 in contact with the conductive structure 322 of the E-IC die 103. Thereafter, the E-IC die 103 may be bonded to the upper surface of the P-IC structure 106 (e.g., through thermal bonding) to bond the first and second conductive pads 130 and the associated oxide layer 214, thereby creating an electrical connection between the E-IC die 103 and the PD 126 through the conductive structure 212 and the via 216.

[0053] Figure 5FThe diagram shows the filling (e.g., deposition) of additional dielectric material (e.g., additional oxide layer 214 material) and the carrier 324 (e.g., silicon carrier, as described above). Figure 3A The connection (e.g., bonding) is made to the E-IC die 103 and the P-IC structure 106 to produce the combined structure 108. In some embodiments, an additional oxide layer 214 material and a carrier 324 may provide mechanical stability to the combined structure 108 during subsequent processing steps described below.

[0054] For example, Figure 5G The substrate 202 is shown to be thinned or narrowed (e.g., by chemical mechanical planarization (CMP)) (e.g., to facilitate access to the conductive structure 212 through the lower surface of the P-IC structure 106).

[0055] Figure 5H The via 326 and the corresponding third conductive pad 130 are shown through the formation (e.g., etching and filling or deposition) of the substrate 202, the buried oxide layer 204 and the oxide layer 214, such that the third conductive pad 130 can be electrically coupled to the E-IC die 103 and / or the PD 126.

[0056] Figure 5I The formation (e.g., etching) of a second EC trench 122 is illustrated. This second EC trench 122 extends from the lower surface of the P-IC structure 106 toward the oxide layer 214 of the E-IC structure 104, and may extend upwards or into the oxide layer 214 of the E-IC structure 104. As shown, the formation of the second EC trench 122 can completely remove the conductive material 502 previously disposed in the first EC trench 121. Therefore, the width of the second EC trench 122 can be equal to or greater than the width of the previous first EC trench 121 (e.g., to facilitate access to the optical EC 124 again through the optical test probe 250).

[0057] Figure 5J An example is shown where an optical test probe 250 and an electrical test probe 260 are engaged with a third conductive pad 130 in a second EC trench 122 to perform combined electrical and optical testing of a composite structure 108 comprising an E-IC die 103, a PD 126, and an optical EC 124. In some embodiments, such as Figure 1A and Figure 1B As shown, the combined structure 108 can combine a single P-IC chip including multiple E-IC dice 103, PD 126, optical EC 124, and associated third conductive pad 130, second EC trench 122, etc.

[0058] Figure 5K This illustrates the separation (e.g., isomorphism or dicing) of the individual IC device 112 from the combined structure 108, such as... Figure 1Aand Figure 1B As shown above. In some embodiments, additional combined electrical and optical tests (e.g., such as...) are performed on the IC device 112. Figure 1A (As shown) This can be achieved through a third conductive pad 130 located on the bottom surface of the IC device 112 and an optical EC 124 located on the side surface of the IC device 112. Furthermore, in some embodiments, several such IC devices 112 can be fabricated from a single P-IC wafer, such as... Figure 1A and Figure 1B As shown.

[0059] Figure 6A and Figure 6B The formation according to this disclosure is shown Figures 5A to 5K Some embodiments of the method 600 for semiconductor structures are described herein. Although the methods and other methods shown and / or described herein are illustrated as a series of actions or events, it should be understood that this disclosure is not limited to the order or actions shown. Therefore, in some embodiments, actions may be performed in a different order than illustrated, and / or may be performed simultaneously. Furthermore, in some embodiments, the illustrated actions or events may be subdivided into multiple actions or events that may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some illustrated actions or events may be omitted, and other actions or events not illustrated may be included.

[0060] In some embodiments, Figure 6A Actions 602 to 614 can correspond to tests associated with the P-IC structure 106. Figure 1C , Figure 2A and Figure 2B as well as Figures 5A to 5C Actions 616 to 636 can correspond to Figure 1D , Figure 3A and Figure 3B as well as Figures 5D to 5J .exist Figure 6A Action 602, for example, can provide a photonic IC structure (e.g., Figure 2A The P-IC structure 106). In some embodiments, the photonic IC structure may include a substrate having a lower surface and a upper surface (e.g., Figure 2A Substrate 202); oxide layer (e.g., Figure 2A The oxide layer 204); a photodetector (e.g., ) configured in the oxide layer. Figure 2A PD 126) and optical edge couplers (e.g., Figure 2A The optical EC 124), an optical edge coupler, is optically coupled to a photodetector; at least one dielectric layer (e.g.,) is disposed on an oxide layer. Figure 2AAt least one dielectric layer 210); and a conductive structure disposed in at least one dielectric layer and electrically coupled to the photodetector (e.g., Figure 2A Conductive structure 212). Figure 5A Cross-sectional views corresponding to some embodiments of action 602 are shown.

[0061] In action 604, a first via (e.g., via 216) can be formed in at least one dielectric layer through the upper surface of the photonic IC structure, and the first via is electrically coupled to a conductive structure. In action 606, a first conductive pad (e.g., Figure 2A The first conductive pad 130 can be formed on the first via on the upper surface of the photonic IC structure. In operation 608, a first trench extending from the upper surface of the photonic IC structure toward the substrate can be formed (e.g., ...). Figure 2A The first EC trench 121) is configured to receive light through the sidewalls of the first trench. Figure 5B Cross-sectional views corresponding to some embodiments of actions 604, 606 and 608 are shown.

[0062] In action 610, the first electrical test probe (e.g., Figure 2A The electrical test probe 260 can be connected to the first conductive pad. In action 612, the first optical test probe (e.g., Figure 2A The optical test probe 250 can be inserted into the first trench through the upper surface of the photonic IC structure to optically couple with the optical edge coupler. In action 614, the first electrical test probe and the first optical test probe can be used to perform first optical and electrical tests on the photonic IC structure. Figure 5C Cross-sectional views corresponding to some embodiments of actions 610, 612 and 614 are shown.

[0063] continue Figure 6B In action 616, the first trench may be filled with a conductive material (e.g., Figure 3A Conductive material 502). Figure 5D Cross-sectional views corresponding to some embodiments of action 616 are shown.

[0064] In action 618, the electrical IC die (e.g., Figure 3A The E-IC die 103 is bonded to the upper surface of the photonic IC structure to electrically couple the E-IC die to the first conductive pad of the photonic IC structure. Figure 5E Cross-sectional views corresponding to some embodiments of action 618 are shown.

[0065] In action 620, a supplementary oxide layer can be formed on the electrical IC die and the photonic IC structure (e.g., Figure 3AThe oxide layer 214). Furthermore, in action 622, the carrier structure (e.g., Figure 3A The carrier 324) can be bonded to the supplementary oxide layer to form an electrical IC structure (e.g., Figure 3A The E-IC structure 104). Figure 5F Cross-sectional views corresponding to some embodiments of actions 620 and 622 are shown.

[0066] In action 624, the substrate can be thinned (e.g., narrowed or thinned) at the lower surface of the substrate. Figure 5G Cross-sectional views corresponding to some embodiments of action 624 are shown.

[0067] In action 626, the second through hole (e.g., Figure 3A The via 326 can be formed in at least one dielectric layer through the lower surface of the substrate to electrically connect to the conductive structure. In action 628, the second conductive pad (e.g., Figure 3A The second conductive pad 130 can be formed on the lower surface of the substrate to be electrically connected to the second via. Figure 5H Cross-sectional views corresponding to some embodiments of actions 626 and 628 are shown.

[0068] In action 630, a second trench extending from the lower surface of the substrate toward the electrical IC structure can be formed (e.g., Figure 3A The second EC trench 122) is configured to receive light through the sidewalls of the second trench. Figure 5I Cross-sectional views corresponding to some embodiments of action 630 are shown.

[0069] In action 632, the second electrical test probe (e.g., Figure 3A The electrical test probe 260 can be connected to the second conductive pad. In action 634, the second optical test probe (e.g., Figure 3A The optical test probe 250 can be inserted into the second trench through the lower surface of the substrate to optically couple with the optical edge coupler. In action 636, the second electrical test probe and the second optical test probe can be used to perform second optical and electrical tests on the photonic IC structure and the electrical IC die. Figure 5J Cross-sectional views corresponding to some embodiments of actions 632, 634 and 636 are shown.

[0070] Some embodiments relate to an integrated circuit (IC) device. The device includes a substrate having a first surface and a second surface; a first dielectric layer disposed on the second surface of the substrate; a photodetector and an optical edge coupler disposed in the first dielectric layer, the optical edge coupler being optically coupled to the photodetector; at least one dielectric layer disposed on the first dielectric layer; a conductive structure disposed in the at least one dielectric layer; a conductive pad disposed on the surface of the IC device, the conductive pad being electrically coupled to the photodetector through the conductive structure; and a trench extending from the surface of the IC device toward the substrate, the optical edge coupler being configured to receive light from the sidewalls of the trench. In some embodiments, the trench extends to the second surface of the substrate. In some embodiments, the integrated circuit device further includes a buried oxide layer disposed on the second surface of the substrate. In some embodiments, the optical edge coupler includes: a first layer including a first light-transmitting material, the first layer including a first rectangular portion and a laterally tapered portion contacting the first rectangular portion; and a second layer including a second light-transmitting material, the second layer including a laterally reversed tapered portion and a second rectangular portion, the laterally reversed tapered portion being configured to at least partially overlap the laterally tapered portion of the first layer in a plan view. In some embodiments, the first layer is perpendicularly separated from the second layer within the first dielectric layer. In some embodiments, the first light-transmitting material comprises silicon mononitride, and the second light-transmitting material comprises silicon. In some embodiments, the photodetector comprises a photodiode laterally disposed from the optical edge coupler. In some embodiments, the trench has a width greater than or equal to 50 micrometers, a length greater than or equal to 200 micrometers, and a depth greater than or equal to 10 micrometers.

[0071] Some embodiments relate to another integrated circuit device. The integrated circuit device includes an electrical integrated circuit structure and a photonic integrated circuit structure. The electrical integrated circuit structure includes: an electrical integrated circuit die; and a first conductive pad disposed on the surface of the electrical integrated circuit structure and electrically coupled to the electrical integrated circuit die. The photonic integrated circuit structure is disposed adjacent to the surface of the electrical integrated circuit structure, the photonic integrated circuit structure including: a substrate including a first surface and a second surface; a first dielectric layer disposed on the second surface of the substrate; a photodetector and an optical edge coupler disposed in the first dielectric layer, the optical edge coupler being optically coupled to the photodetector; at least one dielectric layer disposed on the first dielectric layer; a conductive structure disposed in the at least one dielectric layer; a second conductive pad disposed on the surface of the photonic integrated circuit structure and contacting the first conductive pad, the second conductive pad being electrically coupled to the photodetector through the conductive structure; a third conductive pad disposed on the first surface of the substrate and electrically coupled to the conductive structure; and a trench extending from the first surface of the substrate toward the electrical integrated circuit structure, the optical edge coupler being configured to receive light from the sidewalls of the trench. In some embodiments, the trench extends to the surface of the electrical integrated circuit structure. In some embodiments, the electrical integrated circuit structure further includes a carrier structure disposed on the electrical integrated circuit die. In some embodiments, the optical edge coupler includes: a first layer including a first light-transmitting material, the first layer including a first rectangular portion and a laterally tapered portion contacting the first rectangular portion; and a second layer including a second light-transmitting material, the second layer including a laterally reversed tapered portion and a second rectangular portion, the laterally reversed tapered portion being configured to at least partially overlap the laterally tapered portion of the first layer in a planar view. In some embodiments, the first layer is perpendicularly separated from the second layer within the first dielectric layer. In some embodiments, the photonic integrated circuit structure further includes a via electrically connecting the third conductive pad to the conductive structure. In some embodiments, the trench has a width greater than or equal to 50 micrometers, a length greater than or equal to 200 micrometers, and a depth greater than or equal to 10 micrometers.

[0072] Some embodiments relate to a method. The method includes providing a photonic IC structure comprising: a substrate including a first surface and a second surface; a first dielectric layer disposed on the second surface of the substrate; a photodetector and an optical edge coupler disposed in the first dielectric layer, the optical edge coupler being optically coupled to the photodetector; at least one dielectric layer disposed on the first dielectric layer; and a conductive structure disposed in the at least one dielectric layer and electrically coupled to the photodetector; a first via formed through a surface of the photonic IC structure in the at least one dielectric layer, the first via electrically coupled to the conductive structure; a first conductive pad formed on the first via on the surface of the photonic IC structure; and forming a first trench extending from the surface of the photonic IC structure toward the substrate, such that the optical edge coupler is configured to receive light from the sidewalls of the first trench. In some embodiments, the method further includes: connecting a first electrical test probe to a first conductive pad; inserting a first optical test probe into the first trench via the surface of the photonic integrated circuit structure optically coupled to the optical edge coupler; and performing first optical and electrical tests on the photonic integrated circuit structure using the first electrical test probe and the first optical test probe. In some embodiments, the method further includes: filling the first trench with a conductive material; bonding an electrical integrated circuit die to the surface of the photonic integrated circuit structure to electrically couple the electrical integrated circuit die to the first conductive pad of the photonic integrated circuit structure; forming a supplementary dielectric layer on the electrical integrated circuit die and the photonic integrated circuit structure; bonding a carrier structure to the supplementary dielectric layer to form the electrical integrated circuit structure; thinning the substrate at the first surface of the substrate; forming a second via through the first surface of the substrate in the at least one dielectric layer to electrically connect to the conductive structure; forming a second conductive pad on the first surface of the substrate to electrically connect to the second via; and forming a second trench extending from the first surface of the substrate toward the electrical integrated circuit structure, such that the optical edge coupler is configured to receive light from the sidewalls of the second trench. In some embodiments, the formation of the second trench involves removing the conductive material from the first trench. In some embodiments, the method further includes: attaching a second electrical test probe to the second conductive pad; inserting a second optical test probe into the second trench via the first surface of the substrate to be optically coupled to the optical edge coupler; and performing second optical and electrical tests on the photonic integrated circuit structure and the electrical integrated circuit die using the second electrical test probe and the second optical test probe.

[0073] It should be understood that in this written description and the following claims, the terms "first," "second," "third," etc., are merely general identifiers used to facilitate description and distinguish different elements of a graphic or series of graphics. In themselves, these terms do not imply any temporal order or structural proximity of these elements and are not intended to describe corresponding elements in different illustrated embodiments and / or unillustrated embodiments. For example, "first dielectric layer" described in conjunction with the first figure does not necessarily correspond to "first dielectric layer" described in conjunction with another figure, and does not necessarily correspond to "first dielectric layer" in embodiments not shown.

[0074] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this invention. Those skilled in the art should understand that this invention can be used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this invention.

Claims

1. An integrated circuit device, characterized by comprising: comprising: a substrate comprising a first surface and a second surface; a first dielectric layer disposed on the second surface of the substrate; a photodetector and an optical edge coupler disposed in the first dielectric layer, the optical edge coupler optically coupled with the photodetector; at least one dielectric layer disposed on the first dielectric layer; a conductive structure disposed in the at least one dielectric layer; a conductive pad disposed on a surface of the integrated circuit device, the conductive pad electrically coupled to the photodetector through the conductive structure; and a trench extending from a surface of the integrated circuit device toward the substrate, the optical edge coupler configured to receive light from a sidewall of the trench. The trench extends to the second surface of the substrate.

2. The integrated circuit device of claim 1, wherein, Further comprising a buried oxide layer disposed on the second surface of the substrate.

3. The integrated circuit device of claim 1, wherein, The optical edge coupler comprises:

4. The integrated circuit device of claim 1, wherein, a first layer comprising a first light transmissive material, the first layer comprising a first rectangular portion and a lateral taper portion contacting the first rectangular portion; and a second layer comprising a second light transmissive material, the second layer comprising a lateral reverse taper portion and a second rectangular portion, the lateral reverse taper portion configured to at least partially overlap the lateral taper portion of the first layer in plan view. The photodetector comprises a photodiode laterally disposed from the optical edge coupler.

5. The integrated circuit device of claim 1, wherein, comprising:

6. An integrated circuit device, characterized by an electrical integrated circuit structure comprising: an electrical integrated circuit die; and a first conductive pad disposed on a surface of the electrical integrated circuit structure and electrically coupled to the electrical integrated circuit die; and a photonic integrated circuit structure disposed adjacent to a surface of the electrical integrated circuit structure, the photonic integrated circuit structure comprising: a substrate comprising a first surface and a second surface; a first dielectric layer disposed on the second surface of the substrate; a photodetector and an optical edge coupler disposed in the first dielectric layer, the optical edge coupler optically coupled with the photodetector; at least one dielectric layer disposed on the first dielectric layer; a conductive structure disposed in the at least one dielectric layer; a second conductive pad disposed on a surface of the photonic integrated circuit structure and contacting the first conductive pad, the second conductive pad electrically coupled to the photodetector through the conductive structure; a third conductive pad disposed on the first surface of the substrate and electrically coupled to the conductive structure; and a trench extending from the first surface of the substrate toward the electrical integrated circuit structure, the optical edge coupler configured to receive light from a sidewall of the trench. The trench extends to a surface of the electrical integrated circuit structure.

7. The integrated circuit device of claim 6, wherein, The electrical integrated circuit structure further comprises a carrier structure disposed on the electrical integrated circuit die.

8. The integrated circuit device of claim 6, wherein, The optical edge coupler comprises:

9. The integrated circuit device of claim 6, wherein, a first layer comprising a first light transmissive material, the first layer comprising a first rectangular portion and a lateral taper portion contacting the first rectangular portion; and a second layer comprising a second light transmissive material, the second layer comprising a lateral reverse taper portion and a second rectangular portion, the lateral reverse taper portion configured to at least partially overlap the lateral taper portion of the first layer in plan view. ​ 10. The integrated circuit device of claim 6, wherein, The photonic integrated circuit structure further comprises a via electrically connecting the third conductive pad to the conductive structure.

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