Test system for single-chip voltage inspection device of flow battery

Abstract

The utility model relates to the technical field of flow batteries, and particularly provides a test system for a single-chip voltage inspection device of a flow battery. The test system comprises a single-chip CVM test unit and a test power supply, wherein the single-chip CVM test unit comprises a cardinal number path detection channel parallel interface used for connecting each cardinal number detection channel in a CVM to be tested, and an even number path detection channel parallel interface used for connecting each even number detection channel in the CVM to be tested; and the cardinal detection channel parallel interface and the even detection channel parallel interface are respectively connected with the positive electrode and the negative electrode of the test power supply. As the cardinal number detection channel parallel interface can be connected with each cardinal number detection channel in the CVM to be tested, and the even number detection channel parallel interface can be connected with each even number detection channel in the CVM to be tested, a plurality of detection channels can be tested at one time for the CVM to be tested, and the test efficiency is improved.

Description

Technical Field

[0001] This utility model relates to the field of flow battery technology, specifically to a flow battery single-cell voltage inspection system. Background Technology

[0002] Flow batteries are a new type of battery that utilizes electrochemical energy storage technology. A flow battery typically consists of a stack unit, electrolytes for positive and negative electrodes, electrolyte storage and supply units for both electrodes, and a management and control unit. Its working principle involves separating the positive and negative electrolytes and allowing them to circulate independently for charging and discharging. Flow batteries are characterized by high capacity, wide applicability (in various environments), and long cycle life; therefore, countries worldwide are actively developing flow battery technology. Currently, single-cell voltage monitors (CVMs) have become an essential device for the condition diagnosis of flow battery stacks.

[0003] Single-cell voltage monitors can accurately detect the voltage of each individual cell in a flow battery stack unit in real time. They can also analyze and process the detected voltage of each individual cell in real time, thereby enabling comprehensive and rapid fault diagnosis. This allows for the detection, diagnosis, storage, and retrieval of the status and performance of individual cells. Therefore, single-cell voltage monitors can improve the stability of the flow battery stack unit during operation, which is why they are widely used in voltage detection of flow batteries.

[0004] It should be noted that because a flow battery stack unit contains multiple individual cells, a single-cell voltage monitor (CVM) is also equipped with multiple detection channels to accurately detect the voltage of these individual cells. Typically, the number of detection channels in a CVM may reach several hundred or more. For example... Figure 1 The diagram shown is a schematic of the specific structure of the current monolithic voltage detector 10. This monolithic voltage detector 10 includes multiple detection channels 11, namely C0, C1, C2, C3, ... C1. 2n-1 C 2n These detection channels 11 can be used to detect the voltage of the corresponding single cell in the stack unit of the flow battery. Of course, the voltage detected by each detection channel 11 can be transmitted to the voltage signal processing unit 12 in the single-cell voltage inspector 10 for processing.

[0005] In practical applications, to improve the accuracy of single-chip voltage detectors, it is often necessary to test the single-chip voltage detector. Since a single-chip voltage detector includes multiple detection channels 11, the current testing method typically involves testing each detection channel 11 separately. For example, a test power supply can be connected to the first detection channel, a reference voltage Vref can be input, and the actual detection voltage of the first detection channel can be obtained. Then, the difference between the reference voltage Vref and the actual detection voltage is compared to test the accuracy of the first detection channel's detection result. Then, based on the same principle, the second and other detection channels are tested separately. Clearly, this current method of testing single-chip voltage detectors is inefficient. Utility Model Content

[0006] In view of the deficiencies in the existing technology, the purpose of this utility model is to provide a fuel cell system and electrical equipment, which aims to solve the technical problems in the related technology to a certain extent.

[0007] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0008] This application provides a single-cell voltage monitor (CVM) testing system for flow batteries, comprising: a single-cell CVM testing unit and a test power supply, wherein:

[0009] The single-chip CVM test unit includes a radix-path detection channel parallel interface for connecting each radix-path detection channel in the CVM under test, and an even-path detection channel parallel interface for connecting each even-path detection channel in the CVM under test.

[0010] The parallel interface of the base-number detection channel and the parallel interface of the even-number detection channel are respectively connected to the positive and negative terminals of the test power supply.

[0011] Preferably, the testing system further includes a host computer, which is communicatively connected to the test power supply.

[0012] Preferably, the host computer is equipped with a communication module that can communicate with the CVM under test.

[0013] Preferably, the test power supply specifically includes a high-precision controllable DC voltage source.

[0014] Preferably, the test system includes multiple parallel-connected single-chip CVM test units.

[0015] Preferably, the parallel interface of the base detection channel specifically includes multiple wiring ports for connecting the base detection channels, and a parallel circuit for connecting the various wiring ports in parallel.

[0016] Preferably, the even-numbered detection channel parallel interface specifically includes multiple second wiring ports for connecting even-numbered detection channels, and a second parallel circuit that connects the various wiring ports in parallel.

[0017] Compared with the prior art, the advantages of this utility model are:

[0018] The present application implements a single-cell voltage monitor (CVM) testing system for flow batteries. This system includes a single-cell CVM testing unit and a test power supply. The single-cell CVM testing unit includes a parallel interface for connecting the basic detection channels of the CVM under test (CVM) and a parallel interface for connecting the even-numbered detection channels of the CVM under test (CVM). The basic and even-numbered detection channel parallel interfaces are connected to the positive and negative terminals of the test power supply, respectively. This allows the test power supply to input corresponding test voltages to the basic and even-numbered detection channel parallel interfaces. Since the basic detection channel parallel interface can connect to the basic detection channels of the CVM under test, and the even-numbered detection channel parallel interface can connect to the even-numbered detection channels of the CVM under test, multiple detection channels can be tested simultaneously for the CVM under test, thereby improving testing efficiency. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the specific structure of a single-chip voltage detector provided in one embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the specific structure of a flow battery single-cell voltage inspector testing system provided in one embodiment of this application.

[0021] Figure 3 This is a schematic diagram of the specific structure of a flow battery single-cell voltage inspector testing system provided in another embodiment of this application.

[0022] In the above figures: 10-Single-chip voltage detector; 11-Detection channel; 12-Voltage signal processing unit; 20-Test system; 21-Single-chip CVM test unit; 22-Test power supply; 23-Host computer; 211-Parallel interface for basic detection channels; 212-Parallel interface for even detection channels. Detailed Implementation

[0023] The embodiments of this utility model will be further described in detail below with reference to the accompanying drawings.

[0024] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0025] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] As mentioned earlier, since a single-chip voltage monitor includes multiple detection channels, current testing methods test each channel separately. For example, the test power supply is first connected to the first detection channel, then a reference voltage Vref is input, and the actual detection voltage of the first detection channel is obtained. The difference between the reference voltage Vref and the actual detection voltage is then compared to test the accuracy of the first detection channel's detection result. Then, based on the same principle, the second and other detection channels are tested separately. Clearly, this current method of testing a single-chip voltage monitor is inefficient.

[0027] In view of this, this application provides a test system for a single-cell voltage detector of a flow battery, which can be used to test single-cell voltage detectors more efficiently. Figure 2 The diagram shows the specific structure of the test system 20. The test system 20 includes a single-chip CVM test unit 21 and a test power supply 22. The test power supply 22 can be used to provide the voltage required for the test. For example, the test power supply 22 can be a high-precision controllable DC voltage source to output a high-precision DC voltage.

[0028] It is important to note that the CVM test unit 21 includes a radix-number detection channel parallel interface 211 and an even-number detection channel parallel interface 212. The radix-number detection channel parallel interface 211 can be used to connect each radix-number detection channel in the CVM under test. Specifically, for example, each radix-number detection channel in the CVM under test includes C1, C3, ... C 2n-1 These cardinality detection channels can be connected to the cardinality detection channel parallel interface 211, thereby connecting these cardinality detection channels in parallel through the cardinality detection channel parallel interface 211. Here, the CVM under test can be any CVM to be tested; there are no restrictions on the type or other technical parameters of the CVM under test.

[0029] Similarly, for the even-numbered detection channel parallel interface 212, each even-numbered detection channel in the CVM under test specifically includes C0, C2, ... C 2n These even-numbered detection channels can be connected to the even-numbered detection channel parallel interface 212, thereby connecting these even-numbered detection channels in parallel through the even-numbered detection channel parallel interface 212.

[0030] In addition, the parallel interface 211 of the base number detection channels and the parallel interface 212 of the even number detection channels are respectively connected to the positive and negative terminals of the test power supply 22.

[0031] Therefore, the test system 20 provided in this application embodiment is adopted. The test system 20 includes a single-chip CVM test unit 21 and a test power supply 22. The single-chip CVM test unit 21 includes a radix detection channel parallel interface 211 for connecting each radix detection channel in the CVM under test, and an even-number detection channel parallel interface 212 for connecting each even-number detection channel in the CVM under test. The radix detection channel parallel interface 211 and the even-number detection channel parallel interface 212 are respectively connected to the positive and negative terminals of the test power supply 20. This allows the test power supply 20 to input corresponding test voltages to the parallel interface 211 for the base number detection channels and the parallel interface 212 for the even number detection channels. Since the parallel interface 211 for the base number detection channels can connect to each base number detection channel in the CVM under test, and the parallel interface 212 for the even number detection channels can connect to each even number detection channel in the CVM under test, multiple detection channels can be tested at once for the CVM under test, thereby improving test efficiency.

[0032] The implementation principle of this application mainly focuses on the various detection channels C0, C1, C2, C3, ... C in the CVM under test. 2n-1 C 2nThese detection channels are divided into two groups based on the number of radix and even-radix paths, namely radix detection channels C1, C3, ... C 2n-1 And even-numbered detection channels C0, C2, ... C 2n And through the parallel interface 211 of the base detection channels, the base detection channels C1, C3, ... C 2n-1 Parallel connection is achieved by using the even-numbered detection channel parallel interface 212 to connect the even-numbered detection channels C0, C2, ... C 2n By connecting them in parallel, the test voltage can be input through the test power supply 20, allowing multiple test channels to be tested at once.

[0033] In order to realize the cardinality detection channels C1, C3, ... C 2n-1 The parallel connection of the base detection channels, specifically the structure of the parallel interface 211, can include multiple wiring ports for connecting the base detection channels, and a parallel circuit connecting these wiring ports in parallel. Thus, these base detection channels C1, C3, ... C 2n-1 A connection can be made to the terminal block via a connecting wire, and then parallel connection can be achieved through this parallel circuit.

[0034] Similarly, in order to achieve an even number of detection channels C0, C2, ... C 2n For the parallel connection of the even-numbered detection channels, the structure of the parallel interface 212 can specifically include multiple second terminals for connecting the even-numbered detection channels, and a second parallel circuit that connects the terminals in parallel. Thus, these even-numbered detection channels C0, C2, ... C 2n The second terminal can be connected via a connecting wire, and then parallel connection can be achieved through the second parallel circuit.

[0035] In this application, to facilitate the control of the test voltage input to the test power supply 22, the test system 20 may further include a host computer 23, which is communicatively connected to the test power supply 22. This allows the host computer 23 to input corresponding control signals to control the test power supply 22 to output the corresponding test voltage. The host computer 23 may have a user interface for user operation.

[0036] Of course, the host computer 23 may be equipped with a communication module, which can communicate with the CVM under test and the test power supply 22. The communication module may be a network communication module, a CAN communication module or other types of communication module.

[0037] It needs to be further explained that, such as Figure 3As shown, the number of single-chip CVM test units 21 in the test system 20 can be multiple, that is, it can include multiple single-chip CVM test units 21 connected in parallel. Specifically, the parallel interface 211 for the number of detection channels and the parallel interface 212 for the even number of detection channels in these single-chip CVM test units 21 are connected to the positive and negative terminals of the test power supply 20, respectively. This allows the parallel interface 211 for the number of detection channels and the parallel interface 212 for the even number of detection channels of different CVMs under test, enabling simultaneous testing of multiple different CVMs and further improving the testing efficiency of the CVMs. The multiple different CVMs under test are specifically... Figure 3 CVM1, CVM2, ..., CVMm.

[0038] This utility model is not limited to the above-described embodiments. For those skilled in the art, various improvements and modifications can be made without departing from the principle of this utility model, and these improvements and modifications are also considered to be within the protection scope of this utility model. Contents not described in detail in this specification are prior art known to those skilled in the art.

Claims

1. A flow battery monolithic voltage sentry test system, characterized by, The application relates to a test system for a single-chip CVM (Counting Value Module), which comprises a single-chip CVM test unit and a test power supply, wherein the single-chip CVM test unit comprises a radix path detection channel parallel connection interface for connecting various radix detection channels in a CVM to be tested and an even path detection channel parallel connection interface for connecting various even detection channels in the CVM to be tested; the radix path detection channel parallel connection interface and the even path detection channel parallel connection interface are respectively connected to the positive and negative poles of the test power supply. The test system further comprises a host computer which is in communication connection with the test power supply. The host computer is provided with a communication module which can communicate with the CVM to be tested. The test power supply specifically comprises a high-precision controllable direct-current voltage source.

2. The test system of claim 1, wherein, The test system comprises a plurality of parallel single-chip CVM test units.

3. The test system of claim 2, wherein, The radix path detection channel parallel connection interface specifically comprises a plurality of connection ports for connecting the radix detection channels and a parallel circuit for connecting the various connection ports in parallel.

4. The test system of claim 1, wherein, The even path detection channel parallel connection interface specifically comprises a plurality of second connection ports for connecting the even detection channels and a second parallel circuit for connecting the various connection ports in parallel.

5. The test system of claim 1, wherein, ​ 6. The test system of claim 1, wherein, ​ 7. The test system of claim 1, wherein, ​

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