5M-2.5 G bit error rate test equipment

Abstract

The utility model provides a 5M-2.5 G bit error rate test device. The 5M-2.5 G bit error rate test device comprises an MCU controller, a clock source circuit and a signal shaping circuit. The signal shaping circuit is composed of a chip U13, a resistor R122, a resistor R123, a capacitor C148, a capacitor C149, a capacitor C150, a connector J12 and a connector J13. And a plurality of pins of the chip U13 are respectively connected with the capacitor, the resistor, the clock source circuit and the connector. In a wide frequency range of 5M-2.5 G, the signal is susceptible to interference and distortion. The chip U13 is matched with the resistor and the capacitor to form a network, input signals can be shaped and filtered, high-frequency noise and clutter are removed, and signal waveforms are more regular. Through equalization and filtering, the signal distortion degree is reduced, and the amplitude and phase stability is improved. Therefore, high-quality signals are provided for subsequent bit error rate testing, testing errors caused by poor signal quality are reduced, and the accuracy and reliability of bit error rate testing are improved.

Description

Technical Field

[0001] This utility model belongs to the technical field of signal testing equipment, specifically a 5M-2.5G bit error rate testing device. Background Technology

[0002] As communication technology continues to evolve from 1G to 5G and even 6G in the future, data transmission rates are getting higher and higher, and the requirements for transmission quality are becoming increasingly stringent. For example, 5G networks require higher spectrum efficiency and lower latency, and bit error rate testing can ensure that the network meets these performance indicators, guaranteeing the normal operation of services such as high-definition video and autonomous driving, which have extremely high requirements for data accuracy.

[0003] In existing technologies, a bit error rate (BER) tester is used to test the bit error rate. This tester generates a standard test bitstream and sends it to the system under test. At the receiving end, the BER tester compares the received bitstream with the original transmitted bitstream, and calculates the BER by determining the ratio of the number of erroneous bits to the total number of bits.

[0004] In existing technologies, accurate sampling and comparison of signals can result in significant sampling errors due to clock jitter or instability. Utility Model Content

[0005] The purpose of this invention is to provide a 5M-2.5G bit error rate testing device to solve the problem in the background art that bit error rate testing requires accurate sampling and comparison of signals, and that the existing technology has a large sampling error due to clock jitter or instability.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows:

[0007] A bit error rate testing device for 5M-2.5G includes an MCU controller, a clock source circuit, and a signal shaping circuit; wherein, the MCU controller is used to control the clock source circuit and the signal shaping circuit;

[0008] The clock extraction circuit is used to extract the clock signal from the high-speed data signal, and the signal shaping circuit is used to amplify, filter and perform other preprocessing on the signal to improve the signal quality and make it suitable for subsequent processing.

[0009] The signal shaping circuit includes chip U13, resistor R122, resistor R123, capacitor C148, capacitor C149, capacitor C150, connector J12, and connector J13.

[0010] Specifically, pins 7 and 14 of chip U13 are both connected to one end of capacitor C148, and the other end of capacitor C148 is grounded; pins 13 and 17 of chip U13 are both grounded; pin 15 of chip U13 is connected to one end of resistor R122 and capacitor C149 respectively; the other end of resistor R122 is grounded, and the other end of capacitor C149 is connected to one end of connector J12; the other end of connector J12 is grounded.

[0011] Pins 9 and 12 of chip U13 are connected to the clock source circuit, respectively.

[0012] Pin 16 of chip U13 is connected to one end of resistor R123 and capacitor C150 respectively; the other end of resistor R123 is grounded, and the other end of capacitor C50 is connected to one end of connector J13; the other end of connector J13 is grounded.

[0013] According to the above technical solution, the clock source circuit is used to extract the clock signal from the input 5M-2.5G signal; the clock source circuit includes recovery module A and recovery module B.

[0014] According to the above technical solution, recovery module A includes chip U11A, capacitors C151, C152, C153, and C154, connectors J14, J15, J16, and J17; pin M8 of chip U11A is connected to one end of capacitor C151, the other end of capacitor C151 is connected to one end of connector J14, and the other end of connector J14 is grounded; pin L8 of chip U11A is connected to one end of capacitor C152, the other end of capacitor C152 is connected to one end of connector J15, and the other end of connector J15 is grounded; pin M7 of chip U11A is connected to one end of capacitor C153, the other end of capacitor C153 is connected to one end of connector J16, and the other end of connector J16 is grounded; pin L7 of chip U11A is connected to one end of capacitor C154, the other end of capacitor C154 is connected to one end of connector J17, and the other end of connector J17 is grounded.

[0015] Pin A12 of chip U11A is connected to pin 9 of chip U13; pin B12 of chip U11A is connected to pin 12 of chip U13.

[0016] Pins G1, G2, H1, H2, J4, J5, J1, J2, K3, K4, K2, K1, L1, L2, L3, and L4 of chip U11A are connected to the MCU controller.

[0017] According to the above technical solution, the recovery module B includes chip U11 B, capacitors C131, C132, and C133, connector J10, connector J11, and resistor R120; wherein, pin K5 of chip U11 B is connected to one end of capacitor C131, and the other end of capacitor C131 is grounded; pin M5 of chip U11 B is connected to one end of capacitor C132, and the other end of capacitor C132 is connected to one end of connector J10, and the other end of connector J10 is grounded;

[0018] Pin L5 of chip U11 B is connected to one end of capacitor C133, the other end of capacitor C133 is connected to one end of connector J11, and the other end of connector J11 is grounded.

[0019] Pins D1, D2, D8, and C8 of chip U11 B are connected to the MCU controller respectively.

[0020] Pins C6, C7, A6, A7, B5, B6, A4, A5, C4, C5, A3, A2, B3, B4, C1, and C2 of chip U11 B are connected to the MCU controller.

[0021] According to the above technical solution, the MCU controller includes a first chip module, a second chip module, a third chip module, and a fourth chip module; the MCU controller is used to receive input instructions and set test parameters.

[0022] According to the above technical solution, the first chip module includes chip U6D, chip U12, inductor L13, resistor R121, capacitor C140, capacitor C141, capacitor C144 and capacitor C145; wherein, pin D13 of chip U6D is connected to pin 4 of chip U12, and pin D14 of chip U6D is connected to pin 5 of chip U12.

[0023] Pins D15 and E15 of chip U6D are connected to the fourth chip module respectively;

[0024] Pins E14 and D17 of chip U6D are both connected to one end of capacitors C144 and C145, and the other ends of capacitors C144 and C145 are grounded.

[0025] Pin 1 of chip U12 is connected to one end of resistor R121, and the other end of resistor R121 is connected to the power supply; pin 3 of chip U12 is grounded; pin 6 of chip U12 is connected to one end of capacitor C140, capacitor C141 and inductor L13 respectively, and the other ends of capacitors C140 and C141 are both grounded; the other end of inductor L13 is connected to the power supply.

[0026] According to the above technical solution, the second chip module includes chip U6E, capacitor C146 and capacitor C147.

[0027] Pins AD8 and AC7 of chip U6E are connected to the third chip module respectively; pins AC10 and AB13 of chip U6E are connected to one end of capacitor C146 and capacitor C147 respectively, and the other end of capacitor C146 and capacitor C147 are grounded.

[0028] According to the above technical solution, the third chip module includes chip U6 I, and pins E2 and E1 of chip U6 I are connected to pins C6 and C7 of chip U11 B, respectively.

[0029] Pins F3 and E3 of chip U6I are connected to pins C4 and C5 of U11 B, respectively; pins G1 and H1 of chip U6I are connected to pins B3 and B4 of U11 B, respectively; pins F2 and G2 of chip U6I are connected to pins A3 and A2 of U11 B, respectively; pins K3 and K2 of chip U6I are connected to pins C6 and C7 of U11 B, respectively; pins H3 and J3 of chip U6I are connected to pins A4 and A5 of U11 B, respectively; pins L2 and K1 of chip U6I are connected to pins A6 and A7 of U11 B, respectively; pins J1 and H2 of chip U6I are connected to pins B5 and B6 of U11 B, respectively.

[0030] Pins T2 and R2 of chip U6 I are connected to pins D1 and D2 of chip U11 B, respectively. Pins M2 and N2 of chip U6 I are connected to pins D8 and C8 of chip U11 B, respectively. Pins V2 and V1 of chip U6 I are connected to pins AD8 and AC7 of chip U6E, respectively.

[0031] According to the above technical solution, the fourth chip module includes chip U6K, pin A4 of chip U6K is connected to pin L1 of chip U11A; pin A5 of chip U6K is connected to pin L2 of chip U11A.

[0032] Pin B5 of chip U6K is connected to pin K3 of chip U11A; pin B6 of chip U6K is connected to pin K4 of chip U11A.

[0033] Pin D3 of chip U6K is connected to pin E1 of chip U11A; pin D4 of chip U6K is connected to pin E2 of chip U11A.

[0034] Pin C4 of chip U6K is connected to pin K1 of chip U11A; pin B4 of chip U6K is connected to pin K2 of chip U11A.

[0035] Pin A2 of chip U6K is connected to pin G1 of chip U11A; pin A3 of chip U6K is connected to pin G2 of chip U11A.

[0036] Pin D1 of chip U6K is connected to pin C1 of chip U11A; pin A4 of chip U6K is connected to pin J3 of chip U11A.

[0037] Pin A4 of chip U6K is connected to pin J5 of chip U11A; pin A4 of chip U6K is connected to pin J4 of chip U11A.

[0038] Pin B1 of chip U6K is connected to pin H1 of chip U11A; pin B2 of chip U6K is connected to pin H2 of chip U11A.

[0039] Pin C6 of chip U6K is connected to pin D9 of chip U11A; pin C7 of chip U6K is connected to pin C9 of chip U11A.

[0040] Both pins D7 and G8 of chip U6K are grounded.

[0041] Compared with the prior art, the present invention has the following advantages:

[0042] In this invention, chip U13, combined with a network of resistors (R122, R123) and capacitors (C148, C149, C150), can perform shaping and filtering of the input signal. In a wide frequency range of 5MHz-2.5GHz, signals are easily affected by various interferences and distortions. This circuit can remove high-frequency noise and spurious signals, making the signal waveform more regular. Through signal equalization and filtering, signal distortion is reduced, and the amplitude and phase stability of the signal are improved. This allows subsequent bit error rate (BER) testing to be based on high-quality signals, reducing test errors caused by poor signal quality, thereby improving the accuracy and reliability of BER testing. Attached Figure Description

[0043] Figure 1 This is a circuit diagram of the signal shaping circuit of this utility model;

[0044] Figure 2 This is a circuit diagram of the recovery module A of the clock source circuit of this utility model;

[0045] Figure 3 This is a circuit diagram of the recovery module B of the clock source circuit of this utility model;

[0046] Figure 4 This is the circuit diagram of the first chip module of this utility model;

[0047] Figure 5 This is the circuit diagram of the second chip module of this utility model;

[0048] Figure 6 This is the circuit diagram of the third chip module of this utility model;

[0049] Figure 7 This is the circuit diagram of the fourth chip module of this utility model. Detailed Implementation

[0050] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0051] Example 1

[0052] like Figure 1 As shown, a 5M-2.5G bit error rate testing device specifically relates to a 5M-2.5G bit error rate testing circuit, including an MCU controller, a clock source circuit, and a signal shaping circuit.

[0053] The signal shaping circuit includes chip U13, resistor R122, resistor R123, capacitor C148, capacitor C149, capacitor C150, connector J12, and connector J13.

[0054] Specifically, pins 7 and 14 of chip U13 are both connected to one end of capacitor C148, and the other end of capacitor C148 is grounded; pins 13 and 17 of chip U13 are both grounded; pin 15 of chip U13 is connected to one end of resistor R122 and capacitor C149 respectively; the other end of resistor R122 is grounded, and the other end of capacitor C149 is connected to one end of connector J12; the other end of connector J12 is grounded.

[0055] Pins 9 and 12 of chip U13 are connected to the clock source circuit, respectively.

[0056] Pin 16 of chip U13 is connected to one end of resistor R123 and capacitor C150 respectively; the other end of resistor R123 is grounded, and the other end of capacitor C50 is connected to one end of connector J13; the other end of connector J13 is grounded.

[0057] In existing technologies, when testing the bit error rate of 5M-2 and 5G, the test signal cannot be effectively processed, resulting in poor test signal quality and inconvenience for subsequent processing.

[0058] In this invention, chip U13, combined with a network of resistors (R122, R123) and capacitors (C148, C149, C150), can perform shaping and filtering of the input signal. In a wide frequency range of 5MHz-2.5GHz, signals are easily affected by various interferences and distortions. This circuit can remove high-frequency noise and spurious signals, making the signal waveform more regular. Through signal equalization and filtering, signal distortion is reduced, and the amplitude and phase stability of the signal are improved. This allows subsequent bit error rate (BER) testing to be based on high-quality signals, reducing test errors caused by poor signal quality, thereby improving the accuracy and reliability of BER testing.

[0059] The technical solution of this utility model improves signal quality and reduces interference and noise during signal transmission by processing signals transmitted in the 5M-2.5G range, thereby enabling the signal to meet the signal quality requirements of bit error rate testing and improving the accuracy and reliability of bit error rate testing.

[0060] Example 2

[0061] This embodiment is a further refinement of Embodiment 1.

[0062] The clock source circuit is used to extract the clock signal from the input 5M-2.5G signal; the clock source circuit includes recovery module A and recovery module B.

[0063] like Figure 2 As shown, recovery module A includes chip U11A, capacitors C151, C152, C153, and C154, connectors J14, J15, J16, and J17. Pin M8 of chip U11A is connected to one end of capacitor C151, and the other end of capacitor C151 is connected to one end of connector J14, with the other end of connector J14 grounded. Pin L8 of chip U11A is connected to one end of capacitor C152, and the other end of capacitor C152 is connected to one end of connector J15, with the other end of connector J15 grounded. Pin M7 of chip U11A is connected to one end of capacitor C153, and the other end of capacitor C153 is connected to one end of connector J16, with the other end of connector J16 grounded. Pin L7 of chip U11A is connected to one end of capacitor C154, and the other end of capacitor C154 is connected to one end of connector J17, with the other end of connector J17 grounded.

[0064] Pin A12 of chip U11A is connected to pin 9 of chip U13; pin B12 of chip U11A is connected to pin 12 of chip U13.

[0065] Pins G1, G2, H1, H2, J4, J5, J1, J2, K3, K4, K2, K1, L1, L2, L3, and L4 of chip U11A are connected to the MCU controller.

[0066] like Figure 3 As shown, recovery module B includes chip U11 B, capacitors C131, C132, and C133, connector J10, connector J11, and resistor R120. Pin K5 of chip U11 B is connected to one end of capacitor C131, and the other end of capacitor C131 is grounded. Pin M5 of chip U11 B is connected to one end of capacitor C132, and the other end of capacitor C132 is connected to one end of connector J10, and the other end of connector J10 is grounded.

[0067] Pin L5 of chip U11 B is connected to one end of capacitor C133, the other end of capacitor C133 is connected to one end of connector J11, and the other end of connector J11 is grounded.

[0068] Pins D1, D2, D8, and C8 of chip U11 B are connected to the MCU controller respectively.

[0069] Pins C6, C7, A6, A7, B5, B6, A4, A5, C4, C5, A3, A2, B3, B4, C1, and C2 of chip U11 B are connected to the MCU controller.

[0070] The MCU controller includes a first chip module, a second chip module, a third chip module, and a fourth chip module; the MCU controller is used to receive input instructions and set test parameters.

[0071] like Figure 4 As shown, the first chip module includes chip U6D, chip U12, inductor L13, resistor R121, capacitor C140, capacitor C141, capacitor C144 and capacitor C145; wherein, pin D13 of chip U6D is connected to pin 4 of chip U12, and pin D14 of chip U6D is connected to pin 5 of chip U12.

[0072] Pins D15 and E15 of chip U6D are connected to the fourth chip module respectively;

[0073] Pins E14 and D17 of chip U6D are both connected to one end of capacitors C144 and C145, and the other ends of capacitors C144 and C145 are grounded.

[0074] Pin 1 of chip U12 is connected to one end of resistor R121, and the other end of resistor R121 is connected to the power supply; pin 3 of chip U12 is grounded; pin 6 of chip U12 is connected to one end of capacitor C140, capacitor C141 and inductor L13 respectively, and the other ends of capacitors C140 and C141 are both grounded; the other end of inductor L13 is connected to the power supply.

[0075] like Figure 5 As shown, the second chip module includes chip U6E, capacitor C146, and capacitor C147.

[0076] Pins AD8 and AC7 of chip U6E are connected to the third chip module respectively; pins AC10 and AB13 of chip U6E are connected to one end of capacitor C146 and capacitor C147 respectively, and the other end of capacitor C146 and capacitor C147 are grounded.

[0077] like Figure 6 As shown, the third chip module includes chip U6I, and pins E2 and E1 of chip U6I are connected to pins C6 and C7 of chip U11B, respectively.

[0078] Pins F3 and E3 of chip U6I are connected to pins C4 and C5 of U11 B, respectively; pins G1 and H1 of chip U6I are connected to pins B3 and B4 of U11 B, respectively; pins F2 and G2 of chip U6I are connected to pins A3 and A2 of U11 B, respectively; pins K3 and K2 of chip U6I are connected to pins C6 and C7 of U11 B, respectively; pins H3 and J3 of chip U6I are connected to pins A4 and A5 of U11 B, respectively; pins L2 and K1 of chip U6I are connected to pins A6 and A7 of U11 B, respectively; pins J1 and H2 of chip U6I are connected to pins B5 and B6 of U11 B, respectively.

[0079] Pins T2 and R2 of chip U6 I are connected to pins D1 and D2 of chip U11 B, respectively. Pins M2 and N2 of chip U6 I are connected to pins D8 and C8 of chip U11 B, respectively. Pins V2 and V1 of chip U6 I are connected to pins AD8 and AC7 of chip U6E, respectively.

[0080] like Figure 7 As shown, the fourth chip module includes chip U6K, pin A4 of chip U6K is connected to pin L1 of chip U11A; pin A5 of chip U6K is connected to pin L2 of chip U11A.

[0081] Pin B5 of chip U6K is connected to pin K3 of chip U11A; pin B6 of chip U6K is connected to pin K4 of chip U11A.

[0082] Pin D3 of chip U6K is connected to pin E1 of chip U11A; pin D4 of chip U6K is connected to pin E2 of chip U11A.

[0083] Pin C4 of chip U6K is connected to pin K1 of chip U11A; pin B4 of chip U6K is connected to pin K2 of chip U11A.

[0084] Pin A2 of chip U6K is connected to pin G1 of chip U11A; pin A3 of chip U6K is connected to pin G2 of chip U11A.

[0085] Pin D1 of chip U6K is connected to pin C1 of chip U11A; pin A4 of chip U6K is connected to pin J3 of chip U11A.

[0086] Pin A4 of chip U6K is connected to pin J5 of chip U11A; pin A4 of chip U6K is connected to pin J4 of chip U11A.

[0087] Pin B1 of chip U6K is connected to pin H1 of chip U11A; pin B2 of chip U6K is connected to pin H2 of chip U11A.

[0088] Pin C6 of chip U6K is connected to pin D9 of chip U11A; pin C7 of chip U6K is connected to pin C9 of chip U11A.

[0089] Both pins D7 and G8 of chip U6K are grounded.

[0090] Furthermore, all electronic components involved in this utility model are existing technologies. For example, chip U13 uses the SY89831 U-type chip; U11A and U11B use the S4882 type chip; and U6D, U6E, U6I and U6K use the XC5VLX30-2FFG676C type chip.

[0091] The working principle of this invention is as follows: After the input 5M-2.5G high-speed data signal enters the device, recovery modules A and B in the clock source circuit extract the clock signal from the high-speed data signal. The chips (U11A, U11B) in recovery modules A and B, in conjunction with their respective connected capacitors, connectors, and other components, complete the relevant signal processing to provide a stable clock signal for subsequent circuits.

[0092] The signal shaping circuit amplifies and filters the input signal. Chip U13, with the cooperation of resistors (R122, R123), capacitors (C148-C150) and connectors (J12, J13), processes the signal, improves the signal quality, and makes it suitable for subsequent processing. At the same time, it is connected to the clock source circuit to receive clock signals to achieve synchronization and other functions.

[0093] The MCU controller receives input instructions and sets test parameters. It contains multiple chip modules. The first chip module connects to other modules and performs specific control functions through chips U6D and U12, as well as related inductors, resistors, capacitors, and other components. The second chip module (chip U6E) participates in the entire control process through connections with capacitors and the third chip module. The third chip module (chip U6I) has multiple pin connections to chip U11B of recovery module B, enabling control and signal interaction with recovery module B. The fourth chip module (chip U6K) has numerous pin connections to chip U11A of recovery module A, enabling control and signal transmission of recovery module A. All chip modules work together to comprehensively control the clock source circuit and signal shaping circuit, thereby realizing the various functions of the bit error rate testing equipment.

[0094] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0095] Finally, it should be noted that the above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A 5M-2.5G BER test equipment, characterized in that: The clock extraction circuit is used for extracting a clock signal from a high-speed data signal, and the signal shaping circuit is used for amplifying and filtering a signal to improve the signal quality and make it suitable for subsequent processing. The signal shaping circuit comprises a chip U13, a resistor R122, a resistor R123, a capacitor C148, a capacitor C149, a capacitor C150, a joint J12, and a joint J13. The 7th pin and the 14th pin of the chip U13 are connected with one end of the capacitor C148, and the other end of the capacitor C148 is grounded. The 9th pin and the 12th pin of the chip U13 are connected with the clock source circuit. The 16th pin of the chip U13 is connected with one end of the resistor R123 and one end of the capacitor C150. The clock source circuit is used for extracting a clock signal from an input 5M-2.5G signal.

2. The 5M-2.5G BER test equipment according to claim 1, characterized in that: The clock source circuit comprises a recovery module A and a recovery module B.

3. The 5M-2.5G BER test equipment according to claim 2, characterized in that: The recovery module A comprises a chip U11A, a capacitor C151, a capacitor C152, a capacitor C153, a capacitor C154, a joint J14, a joint J15, a joint J16, and a joint J17. The 12th pin of the chip U11A is connected with the 12th pin of the chip U13. The G1, G2, H1, H2, J4, J5, J1, J2, K3, K4, K2, K1, L1, L2, L3, and L4 pins of the chip U11A are connected with the MCU controller.

4. The 5M-2.5G BER test equipment according to claim 3, characterized in that: The recovery module B comprises a chip U11B, a capacitor C131, a capacitor C132, a capacitor C133, a joint J10, a joint J11 and a resistor R120; wherein a K5 pin of the chip U11B is connected with one end of the capacitor C131, and the other end of the capacitor C131 is grounded; a M5 pin of the chip U11B is connected with one end of the capacitor C132, and the other end of the capacitor C132 is connected with one end of the joint J10, and the other end of the joint J10 is grounded; a L5 pin of the chip U11B is connected with one end of the capacitor C133, and the other end of the capacitor C133 is connected with one end of the joint J11, and the other end of the joint J11 is grounded; D1, D2, D8 and C8 pins of the chip U11B are respectively connected with the MCU controller; C6, C7, A6, A7, B5, B6, A4, A5, C4, C5, A3, A2, B3, B4, C1 and C2 pins of the chip U11B are respectively connected with the MCU controller.

5. The 5M-2.5G BER test equipment according to claim 4, characterized in that: The MCU controller comprises a first chip module, a second chip module, a third chip module and a fourth chip module; the MCU controller is used for receiving an input instruction and setting a test parameter.

6. The 5M-2.5G BER test equipment according to claim 5, characterized in that: The first chip module comprises a chip U6D, a chip U12, an inductor L13, a resistor R121, a capacitor C140, a capacitor C141, a capacitor C144 and a capacitor C145; wherein a D13 pin of the chip U6D is connected with a 4 pin of the chip U12, and a D14 pin of the chip U6D is connected with a 5 pin of the chip U12; D15 and E15 pins of the chip U6D are respectively connected with the fourth chip module; E14 and D17 pins of the chip U6D are both connected with one end of the capacitor C144 and the capacitor C145, and the other ends of the capacitor C144 and the capacitor C145 are both grounded; a 1 pin of the chip U12 is connected with one end of the resistor R121, and the other end of the resistor R121 is connected with a power supply; a 3 pin of the chip U12 is grounded; a 6 pin of the chip U12 is respectively connected with one end of the capacitor C140, the capacitor C141 and the inductor L13, and the other ends of the capacitor C140 and the capacitor C141 are both grounded; the other end of the inductor L13 is connected with the power supply.

7. The 5M-2.5G BER test equipment according to claim 6, characterized in that: The second chip module comprises a chip U6E, a capacitor C146 and a capacitor C147; AD8 and AC7 pins of the chip U6E are respectively connected with the third chip module; AC10 and AB13 pins of the chip U6E are both connected with one end of the capacitor C146 and the capacitor C147, and the other ends of the capacitor C146 and the capacitor C147 are both grounded.

8. The 5M-2.5G BER test equipment according to claim 7, characterized in that: The third chip module comprises a chip U6I, and E2 and E1 pins of the chip U6I are respectively connected with C6 and C7 pins of the chip U11B; The pin F3 of the chip U6I is connected with the pin C4 of the chip U11B, the pin E3 of the chip U6I is connected with the pin C5 of the chip U11B, the pin G1 of the chip U6I is connected with the pin B3 of the chip U11B, the pin H1 of the chip U6I is connected with the pin B4 of the chip U11B, the pin F2 of the chip U6I is connected with the pin A3 of the chip U11B, the pin G2 of the chip U6I is connected with the pin A2 of the chip U11B, the pin K3 of the chip U6I is connected with the pin C6 of the chip U11B, the pin K2 of the chip U6I is connected with the pin C7 of the chip U11B, the pin H3 of the chip U6I is connected with the pin A4 of the chip U11B, the pin J3 of the chip U6I is connected with the pin A5 of the chip U11B, the pin L2 of the chip U6I is connected with the pin A6 of the chip U11B, the pin K1 of the chip U6I is connected with the pin A7 of the chip U11B, the pin J1 of the chip U6I is connected with the pin B5 of the chip U11B, and the pin H2 of the chip U6I is connected with the pin B6 of the chip U11B. The pin T2 of the chip U6I is connected with the pin D1 of the chip U11B, the pin R2 of the chip U6I is connected with the pin D2 of the chip U11B, the pin M2 of the chip U6I is connected with the pin D8 of the chip U11B, the pin N2 of the chip U6I is connected with the pin C8 of the chip U11B, the pin V2 of the chip U6I is connected with the pin AD8 of the chip U6E, and the pin V1 of the chip U6I is connected with the pin AC7 of the chip U6E.

9. The 5M-2.5G BER test equipment of claim 8, wherein: The fourth chip module comprises a chip U6K, the pin A4 of the chip U6K is connected with the pin L1 of the chip U11A, the pin A5 of the chip U6K is connected with the pin L2 of the chip U11A, the pin B5 of the chip U6K is connected with the pin K3 of the chip U11A, the pin B6 of the chip U6K is connected with the pin K4 of the chip U11A, the pin D3 of the chip U6K is connected with the pin E1 of the chip U11A, the pin D4 of the chip U6K is connected with the pin E2 of the chip U11A, the pin C4 of the chip U6K is connected with the pin K1 of the chip U11A, the pin B4 of the chip U6K is connected with the pin K2 of the chip U11A, the pin A2 of the chip U6K is connected with the pin G1 of the chip U11A, the pin A3 of the chip U6K is connected with the pin G2 of the chip U11A, the pin D1 of the chip U6K is connected with the pin C1 of the chip U11A, the pin A4 of the chip U6K is connected with the pin J3 of the chip U11A, the pin A4 of the chip U6K is connected with the pin J5 of the chip U11A, the pin A4 of the chip U6K is connected with the pin J4 of the chip U11A, the pin B1 of the chip U6K is connected with the pin H1 of the chip U11A, the pin B2 of the chip U6K is connected with the pin H2 of the chip U11A, the pin C6 of the chip U6K is connected with the pin D9 of the chip U11A, the pin C7 of the chip U6K is connected with the pin C9 of the chip U11A, and the pins D7 and G8 of the chip U6K are grounded. The fourth chip module comprises a chip U6K, the pin A4 of the chip U6K is connected with the pin L1 of the chip U11A, the pin A5 of the chip U6K is connected with the pin L2 of the chip U11A, the pin B5 of the chip U6K is connected with the pin K3 of the chip U11A, the pin B6 of the chip U6K is connected with the pin K4 of the chip U11A, the pin D3 of the chip U6K is connected with the pin E1 of the chip U11A, the pin D4 of the chip U6K is connected with the pin E2 of the chip U11A, the pin C4 of the chip U6K is connected with the pin K1 of the chip U11A, the pin B4 of the chip U6K is connected with the pin K2 of the chip U11A, the pin A2 of the chip U6K is connected with the pin G1 of the chip U11A, the pin A3 of the chip U6K is connected with the pin G2 of the chip U11A, the pin D1 of the chip U6K is connected with the pin C1 of the chip U11A, the pin A4 of the chip U6K is connected with the pin J3 of the chip U11A, the pin A4 of the chip U6K is connected with the pin J5 of the chip U11A, the pin A4 of the chip U6K is connected with the pin J4 of the chip U11A, the pin B1 of the chip U6K is connected with the pin H1 of the chip U11A, the pin B2 of the chip U6K is connected with the pin H2 of the chip U11A, the pin C6 of the chip U6K is connected with the pin D9 of the chip U11A, the pin C7 of the chip U6K is connected with the pin C9 of the chip U11A, and the pins D7 and G8 of the chip U6K are grounded. ​ ​ ​ ​ ​ ​ ​ ​

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