Multi-camera video signal acquisition and return processing system

Abstract

The utility model provides a multi-camera video signal acquisition and return processing system, and belongs to the technical field of signal acquisition and return. Comprising a plurality of cameras, the plurality of cameras are independently connected with a signal acquisition and processing node and used for processing image information acquired by the cameras, and the plurality of signal acquisition and processing nodes are jointly connected to a switch to form a regional network. According to the utility model, a plurality of cameras are respectively connected with independent signal acquisition and processing nodes, and the nodes are gathered in the same switch to form a regional network, so that clear construction and efficient integration of a network topology structure are realized, and the network topology structure is more compact through close cooperation of the video encoder, the video compressor and the network interface module. When the number of the cameras is increased, the bandwidth occupation of data transmission is effectively reduced under limited bandwidth resources, the network congestion is avoided, and the transmission delay is obviously reduced.

Description

Technical Field

[0001] This utility model relates to the field of signal acquisition and transmission technology, and in particular to a multi-camera video signal acquisition and transmission processing system. Background Technology

[0002] In today's era of rapid digital and intelligent development, video surveillance technology has been widely applied in numerous fields, such as urban security monitoring, transportation hub management, industrial production monitoring, and security for large commercial venues. With the increasing demand for monitoring, the requirements for monitoring range and accuracy are also constantly rising, prompting multi-camera monitoring systems to become the mainstream monitoring solution.

[0003] Traditional surveillance systems often lack unified and flexible network planning, resulting in cluttered connections between cameras, transmission equipment, and backend processing systems. Multiple cameras may converge on a single transmission line or device, leading to uneven line load. If a camera experiences excessive data traffic or malfunctions, it can easily impact the stability of the entire network and the normal operation of other cameras. Furthermore, traditional architectures have poor scalability when adjusting for changes in the number of cameras. They struggle to easily integrate new camera equipment or reconfigure the network, potentially requiring large-scale network topology modifications involving complex cabling and equipment replacement, which is not only costly but also causes prolonged system downtime. In addition, traditional network architectures are rather crude in their data traffic management, failing to effectively isolate and fine-tune traffic control for data from cameras in different areas or of different types. This can easily lead to situations where some cameras excessively consume network bandwidth while other cameras experience data transmission bottlenecks, ultimately affecting the overall performance of the surveillance system and the real-time and smoothness of video transmission. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a multi-camera video signal acquisition and transmission processing system, which solves the technical problems of chaotic network architecture, poor scalability, and inefficient video signal encoding and compression leading to bandwidth congestion and large transmission delay in traditional monitoring systems.

[0005] Technical Solution: To achieve the above objectives, this utility model provides the following technical solution: A multi-camera video signal acquisition and transmission processing system, comprising: multiple cameras, each camera being individually connected to a signal acquisition and processing node for processing image information acquired by the cameras; and multiple signal acquisition and processing nodes being connected to a single switch to form a local area network. The connection lines between the signal acquisition and processing nodes and the cameras utilize well-shielded cables to reduce the impact of electromagnetic interference on video signal transmission. The switch is an industrial-grade gigabit Ethernet switch with an operating temperature range of -40℃ to 75℃ to adapt to different environmental conditions. The switch port speed is adaptive, and each port has traffic shaping capabilities to effectively control data traffic and prevent excessive data traffic on a single port from affecting overall network performance. The switch has a port density of at least 24 ports to meet the access requirements of a certain scale of signal acquisition and processing nodes.

[0006] In a further embodiment, the switch is connected to a router, a monitoring terminal, and a central server to achieve multi-path distribution and interaction of video signals. The router connects the local area network (LAN) to an external wide area network (WAN), extending the remote transmission range of video signals. The monitoring terminal displays video footage in real time and provides interactive operation functions. The central server centrally manages, stores, and processes video data resources from multiple signal acquisition and processing nodes. The router is an enterprise-grade router that supports multiple line accesses (such as 4G / 5G backup lines) to ensure network connection stability and redundancy. The router has intelligent routing strategies that automatically select the optimal transmission path based on network conditions. The monitoring terminal software interface is simple and intuitive, easy to operate, and supports multiple operating systems (such as Windows, Linux, Android, and iOS). The central server uses a stable and reliable server-specific operating system, such as Windows Server or a Linux distribution, with comprehensive user permission management and log recording functions.

[0007] In a further embodiment, the signal acquisition and processing node includes a video encoder, a video compressor, and a network interface module. The video encoder is used to convert the acquired raw video signal into an encoding format according to a specific encoding standard. The video compressor is used to compress the encoded video signal. The network interface module is used to transmit the compressed video signal to the switch. The video encoder supports multiple mainstream encoding standards (such as H.264, H.265, MPEG-4, etc.) and can dynamically switch according to network bandwidth and video quality requirements. The video compressor adopts advanced lossless or near-lossless compression algorithms, which can maintain the detail and clarity of the video even at high compression ratios. The network interface module has a network link detection function, which can monitor the connection status with the switch in real time and provide timely feedback to the microcontroller.

[0008] In a further embodiment, the image sensor interface chip in the signal acquisition and processing node has a data output pin (DOUT), which is directly connected to the data input pin (DATA_IN) of the encoding chip to realize the transmission of video signals. The data transmission line between the image sensor interface chip and the encoding chip adopts differential signal transmission to improve anti-interference capability. The impedance matching of the data transmission line needs to be precisely designed to ensure the integrity of signal transmission. Signal buffers are set at the data output pin (DOUT) and the data input pin (DATA_IN) to enhance driving capability and prevent signal distortion; the common-mode rejection ratio (CMRR) of the differential signal transmission line is not less than 60dB to effectively suppress common-mode noise. The delay time of the signal buffer does not exceed 10 nanoseconds and has overvoltage protection, capable of withstanding ±5V overvoltage surges.

[0009] In a further embodiment, the encoding chip in the video encoder has power supply pins (VCC and GND), a clock pin (CLK), a data input pin (DATA_IN), and a data output pin (DATA_OUT). The clock pin (CLK) is connected in series with an external crystal oscillator. One pin of the external crystal oscillator is connected to the clock pin (CLK) of the encoding chip, and the other pin is grounded. The data output pin (DATA_OUT) is connected to the input pin (COMP_IN) of the video compressor. The external crystal oscillator is a high-precision, low-jitter crystal oscillator with a frequency stability within ±10ppm. The driving capability of the clock pin (CLK) must meet the operating frequency requirements of the encoding chip, and the clock frequency must be within ±10ppm. The duty cycle of the clock signal should be controlled between 45% and 55%; the data output pin (DATA_OUT) of the encoding chip and the input pin (COMP_IN) of the video compressor should use a high-speed data transmission interface standard, such as LVDS (Low Voltage Differential Signaling) or MIPI (Mobile Industrial Processor Interface); the load capacitance of the crystal oscillator should be precisely matched according to the requirements of the encoding chip, with an error not exceeding ±5%; the output current capability of the data output pin (DATA_OUT) should not be less than 10mA to ensure stable driving of the input pin of the video compressor; the transmission rate of the LVDS interface should not be less than 1Gbps, and the MIPI interface should conform to the corresponding version specification (such as MIPICSI-2).

[0010] In another embodiment, the video compressor includes a compression chip and a buffer chip. The compression chip has power supply pins (VDD and VSS), an input pin (COMP_IN), an output pin (COMP_OUT), data pins (DATA0-DATA3), and address output pins (ADDR_OUT0-ADDR_OUT1). The buffer chip has address pins (ADDR1-ADDR2), data input / output pins (DATA_IO1-DATA_IO2), a chip select pin (CS), and a read / write control pin (R / W). The data output pin (DATA_OUT) of the encoding chip is connected to the input pin (COMP_IN) of the compression chip, and the data input / output pins (DATA_IO1-DATA_IO2) of the buffer chip are connected to the data pins (DATA0-DATA3) of the compression chip. The address pins (ADDR1-ADDR2) of the cache chip are connected to the address output pins (ADDR_OUT0-ADDR_OUT1) of the compression chip. The chip select pin (CS) and read / write control pin (R / W) of the cache chip are connected to the corresponding control pins of the compression chip. The compression chip uses a multi-core architecture to process video data in parallel, improving compression speed. The cache chip uses high-speed static random access memory (SRAM) with a read / write speed of no less than 100MHz. The connection lines between the compression chip and the cache chip should be as short and of equal length as possible to reduce signal transmission delay and skew. The compression chip has at least four cores, and each core has a processing capacity of no less than 100M pixels / second. The SRAM capacity is determined based on the video data flow and compression algorithm requirements, generally between 1MB and 16MB. The length difference of the connection lines should be controlled within ±5mm, and the signal transmission delay should not exceed 5 nanoseconds.

[0011] In a further embodiment, the network interface module includes a network interface chip, a network transformer, and an RJ-45 interface socket. The network interface chip has power supply pins (VDD and GND), data input / output pins (DATA_IN_OUT), and pins connected to the RJ-45 interface (TX+, TX-, RX+, RX-). The network transformer has primary coil pins (P1-P4) and secondary coil pins (S1-S4). The RJ-45 interface socket has a pair of differential signal pins (TX+, TX-) for transmitting data, a pair of differential signal pins (RX+, RX-) for receiving data, and a ground pin (GND). The output pin (COMP_OUT) of the video compressor is connected to the data input pin (DATA_IN_OUT) of the network interface chip. The TX+ and TX- pins of the network interface chip are connected to the primary coil pins of the network transformer. P1 and P2 are connected to the secondary coil pins (S1 and S2), and then to the TX+ and TX- pins of the RJ-45 interface socket. The RX+ and RX- pins of the network interface chip are connected to the secondary coil pins (S3 and S4) of the network transformer via the primary coil pins (P3 and P4), and then to the RX+ and RX- pins of the RJ-45 interface socket. The network interface chip supports multiple network protocols (such as TCP / IP, UDP, ICMP, etc.) and has hardware acceleration capabilities to improve network data processing efficiency. The network transformer uses high-quality magnetic materials, providing excellent isolation performance and high-frequency characteristics. The RJ-45 interface socket conforms to relevant international standards (such as Cat5e, Cat6, etc.), featuring anti-misinsertion design and good contact reliability. The network protocol stack of the network interface chip conforms to RFC standards, and hardware acceleration can improve network data processing speed by at least 50%. The isolation voltage of the network transformer is not less than 1500V, and the high-frequency response bandwidth is not less than 100MHz. The RJ-45 interface socket has a mating and extraction life of not less than 1000 cycles, and the contact resistance does not exceed 20 milliohms.

[0012] In a further embodiment, the signal acquisition and processing node also includes a microcontroller. The microcontroller communicates with the encoding chip via an SPI or I2C bus. The microcontroller has power supply pins (VCC and GND), a reset pin (RST), and communication pins connected to the encoding chip. During SPI communication, the microcontroller's MOSI pin is connected to the encoding chip's control data input pin, the MISO pin is connected to the encoding chip's status data output pin, the SCK pin is connected to the encoding chip's clock pin for synchronous communication, and the CS pin is used for chip select, so as to realize parameter configuration and status monitoring and control operations of the encoding chip. The microcontroller is selected from low-power, high-performance microprocessors, such as the ARM Cortex-M series. The SPI or I2C bus communication rate can be adjusted according to system requirements, up to a maximum of 10MHz; the microcontroller integrates abundant peripheral resources, such as timers, interrupt controllers, and general purpose input / output interfaces (GPIO), to connect and control other external devices (such as sensors, indicator lights, etc.); the microcontroller operates at a frequency between 100MHz and 200MHz, and the SPI bus communication bit error rate is no higher than 10^-6; the microcontroller has no fewer than 30 GPIO pins, and each pin has a drive capability of no less than 20mA, which can directly drive some small external devices; at the same time, the microcontroller has a power-down detection function, which can save critical data and enter a low-power sleep state in time when the power supply is abnormal.

[0013] Beneficial effects: 1. The design of connecting multiple cameras to independent signal acquisition and processing nodes and then aggregating these nodes to form a local area network (LAN) achieves clear construction and efficient integration of the network topology; the layered architecture allows the system to easily expand when the number of cameras increases without requiring large-scale reconstruction of the overall network architecture; at the same time, the switch, as the core hub of the LAN, can centrally manage the data traffic of each signal acquisition and processing node, facilitating traffic monitoring, load balancing, and other operations, effectively improving the efficiency of network resource allocation and management convenience.

[0014] 2. Through the close cooperation of the video encoder, video compressor and network interface module, the system effectively reduces the bandwidth consumption of data transmission under limited bandwidth resources when the number of cameras increases, avoids network congestion and significantly reduces transmission latency, thus achieving smooth video signal acquisition, transmission and processing, and ensuring the efficient and stable operation of the multi-camera monitoring system. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a system framework diagram of the present invention.

[0017] Figure 2 This is a schematic diagram of the internal circuitry of the signal acquisition and processing node. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this utility model clearer, the technical solutions in this utility model are described clearly and completely. Obviously, the described embodiments are only some, not all, of the embodiments in this utility model. All other embodiments obtained by those skilled in the art based on the embodiments in this utility model without creative effort are within the scope of protection of this utility model.

[0019] This application provides a multi-camera video signal acquisition and transmission processing system, which solves the technical problems of chaotic network architecture, poor scalability, and inefficient video signal encoding and compression leading to bandwidth congestion and high transmission latency in traditional monitoring systems. In practical use, it achieves the construction of a clear, orderly, and easily scalable network architecture, realizes efficient management and allocation of network resources, and effectively reduces bandwidth consumption, avoids congestion, and reduces transmission latency when multiple cameras are running, ensuring smooth, stable, and real-time acquisition, transmission, and processing of video signals.

[0020] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0021] Reference Figure 1-2 A multi-camera video signal acquisition and transmission processing system includes: multiple cameras, each of which is individually connected to a signal acquisition and processing node for processing image information acquired by the cameras, and the multiple signal acquisition and processing nodes are connected to a switch to form a local area network.

[0022] It achieves the effect of building a standardized and scalable basic network architecture; multiple cameras are connected to independent signal acquisition and processing nodes, and then form a local area network through switches, making the access and management of cameras more orderly, the data transmission path within the local area network clear, and facilitating the flexible addition or removal of cameras and the overall allocation of data traffic.

[0023] The switches are connected to routers, monitoring terminals, and central servers to enable multi-path distribution and interaction of video signals. Routers connect the local area network to external wide area networks to extend the remote transmission range of video signals. Monitoring terminals display video images in real time and have interactive operation functions. Central servers centrally manage, store, and process video data resources from multiple signal acquisition and processing nodes.

[0024] It achieves the effects of all-round distribution of video signals, remote interaction and centralized management; the connection between the switch, router, monitoring terminal and central server allows video signals to break through regional restrictions and be remotely transmitted to different terminals for users to view and interact with. At the same time, the central server can centrally process and store video data, realizing efficient integration and in-depth utilization of multi-camera data resources.

[0025] The signal acquisition and processing node includes a video encoder, a video compressor, and a network interface module. The video encoder is used to convert the acquired raw video signal into an encoding format according to a specific encoding standard. The video compressor is used to compress the encoded video signal. The network interface module is used to transmit the compressed video signal to the switch.

[0026] It achieves efficient preprocessing of video signals to adapt to network transmission; the video encoder converts the original video into an encoding format, reducing data redundancy; the video compressor further compresses the encoded data, significantly reducing the amount of video signal data; and the network interface module ensures that the compressed signal is stably transmitted to the switch. Together, they reduce the bandwidth occupation of the video signal during transmission and avoid network congestion and transmission delay caused by excessive data volume.

[0027] The image sensor interface chip in the signal acquisition and processing node is equipped with a data output pin (DOUT), which is directly connected to the data input pin (DATA_IN) of the encoding chip to realize the transmission of video signals.

[0028] It achieves fast, stable and low-interference transmission of video signals from the image sensor to the encoding chip; the direct connection between the data output pin of the image sensor interface chip and the data input pin of the encoding chip constructs a short and efficient signal transmission link, reduces signal transfer links and line loss, and ensures that the video signal can accurately and timely enter the encoding process at the beginning stage, reducing the risk of signal quality degradation and transmission delay caused by the complexity of the transmission line.

[0029] The encoding chip in the video encoder has power supply pins (VCC and GND), clock pin (CLK), data input pin (DATA_IN), and data output pin (DATA_OUT). The clock pin (CLK) is connected in series with an external crystal oscillator. One pin of the external crystal oscillator is connected to the clock pin (CLK) of the encoding chip, and the other pin is grounded. The data output pin (DATA_OUT) is connected to the input pin (COMP_IN) of the video compressor.

[0030] It achieves the effect of providing a stable clock signal and an orderly data transmission channel for the video encoder; the clock pin of the encoding chip is connected to an external crystal oscillator to ensure precise timing control of the encoding operation, the power pin ensures a stable power supply, and the data input and output pins regulate the inflow of the original video signal and the outflow of the encoded signal, enabling the video encoder to efficiently encode and convert video signals according to the set standards in a stable and reliable electrical and signal environment.

[0031] The video compressor includes a compression chip and a buffer chip. The compression chip has power pins (VDD and VSS), input pins (COMP_IN), output pins (COMP_OUT), data pins (DATA0-DATA3), and address output pins (ADDR_OUT0-ADDR_OUT1). The buffer chip has address pins (ADDR1-ADDR2), data input / output pins (DATA_IO1-DATA_IO2), chip select pin (CS), and read / write control pins (R / W). The data output pin (DATA_OUT) of the encoding chip is connected to the input pin (COMP_IN) of the compression chip. The data input / output pins (DATA_IO1-DATA_IO2) of the buffer chip are connected to the data pins (DATA0-DATA3) of the compression chip. The address pins (ADDR1-ADDR2) of the buffer chip are connected to the address output pins (ADDR_OUT0-ADDR_OUT1) of the compression chip. The chip select pin (CS) and read / write control pin (R / W) of the buffer chip are connected to the corresponding control pins of the compression chip.

[0032] It achieves high-speed caching and precise interaction of data during video compression; the pin connection design between the compression chip and the cache chip enables the cache chip to store and provide the data required by the compression chip in a timely manner during video compression. Through the coordinated work of address pins, data pins and control pins, high-speed reading and writing of data and precise interaction are achieved, ensuring that the video compressor can compress the encoded video signal in an efficient and stable state, thereby improving compression efficiency and quality.

[0033] The network interface module includes a network interface chip, a network transformer, and an RJ-45 interface socket. The network interface chip has power supply pins (VDD and GND), data input / output pins (DATA_IN_OUT), and pins for connecting to the RJ-45 interface (TX+, TX-, RX+, RX-). The network transformer has primary coil pins (P1-P4) and secondary coil pins (S1-S4). The RJ-45 interface socket has a pair of differential signal pins (TX+, TX-) for transmitting data, a pair of differential signal pins (RX+, RX-) for receiving data, and a ground pin. (GND), the output pin (COMP_OUT) of the video compressor is connected to the data input pin (DATA_IN_OUT) of the network interface chip. The TX+ and TX- pins of the network interface chip are connected to the secondary coil pins (S1 and S2) through the primary coil pins (P1 and P2) of the network transformer, and then connected to the TX+ and TX- pins of the RJ-45 interface socket. The RX+ and RX- pins of the network interface chip are connected to the secondary coil pins (S3 and S4) through the primary coil pins (P3 and P4) of the network transformer, and then connected to the RX+ and RX- pins of the RJ-45 interface socket.

[0034] It achieves the effect of adapting and connecting the compressed video signal to the network and ensuring stable transmission. The connection design of the chip, transformer and RJ-45 interface socket in the network interface module converts the signal output by the video compressor into a format and level standard suitable for network transmission. The network transformer isolates common-mode interference, ensuring stable signal transmission at the physical layer. Finally, the signal is accurately sent to the switch through the RJ-45 interface socket, ensuring that the video signal enters the network transmission link smoothly.

[0035] The signal acquisition and processing node also includes a microcontroller. The microcontroller communicates with the encoding chip via SPI or I2C bus. The microcontroller has power supply pins (VCC and GND), a reset pin (RST), and communication pins connected to the encoding chip. During SPI communication, the microcontroller's MOSI pin is connected to the encoding chip's control data input pin, the MISO pin is connected to the encoding chip's status data output pin, the SCK pin is connected to the encoding chip's clock pin for synchronous communication, and the CS pin is used for chip select, so as to realize control operations such as parameter configuration and status monitoring of the encoding chip.

[0036] This system achieves intelligent control and real-time status monitoring of key parameters of the video encoder. The microcontroller communicates with the encoding chip via SPI or I2C bus, and through specific pin connections, it enables flexible configuration of the encoding chip parameters, such as frame rate and bit rate. Simultaneously, it can acquire the encoding chip's operating status information in real time, adjusting encoding parameters promptly based on network conditions and monitoring needs. This ensures the video encoder is always in optimal working condition, improving the adaptability and stability of the entire video signal acquisition and processing system.

[0037] During operation, multiple cameras begin acquiring raw video signals. These signals are first transmitted directly to the data input pin (DATA_IN) of the encoding chip via the data output pin (DOUT) of the image sensor interface chip in their respective connected signal acquisition and processing nodes. Driven by a stable clock signal provided by a series connection between its clock pin (CLK) and an external crystal oscillator, the encoding chip converts the raw video signals into an encoded format according to a specific encoding standard and transmits the encoded signal to the input pin (COMP_IN) of the video compressor via the data output pin (DATA_OUT). After receiving the signal, the compression chip in the video compressor, with the cooperation of the buffer chip, performs data compression processing on the encoded signal based on the efficient data interaction mechanism constructed by the connection of the address pins (ADDR1-ADDR2), data input / output pins (DATA_IO1-DATA_IO2), chip select pin (CS), and read / write control pin (R / W) with the corresponding pins of the compression chip. Then, the compressed signal is transmitted to the data input pin (DATA_IN_OUT) of the network interface chip in the network interface module via the output pin (COMP_OUT) of the compression chip. The network interface chip then processes the data and transmits it through the TX+ and TX- pins via the network. The primary coil pins (P3-P4) of the network transformer are connected to the secondary coil pins (S3-S4), which in turn are connected to the TX+ and TX- pins of the RJ-45 interface socket to transmit signals. The RX+ and RX- pins of the network interface chip are connected to the secondary coil pins (S1 and S2) of the network transformer via the primary coil pins (P1 and P2), which are then connected to the RX+ and RX- pins of the RJ-45 interface socket to receive data. Finally, the signal is transmitted to the switch through the RJ-45 interface socket. The switch then transmits the signal to the router, monitoring terminal, and central server. The router connects the local area network (LAN) to the external wide area network (WAN), extending the field of view. The system extends the remote transmission range of frequency signals, and the monitoring terminal displays video images in real time with interactive operation functions. The central server centrally manages, stores, and processes video data resources from multiple signal acquisition and processing nodes. Meanwhile, the microcontrollers in the signal acquisition and processing nodes communicate with the encoding chip via SPI or I2C bus. The MOSI pin is connected to the control data input pin of the encoding chip, the MISO pin is connected to the status data output pin of the encoding chip, the SCK pin is connected to the clock pin of the encoding chip for synchronous communication, and the CS pin is used for chip select. This enables parameter configuration, status monitoring, and control operations of the encoding chip, thereby ensuring the stable and efficient operation of the entire system.

[0038] The figures shown in the accompanying drawings are illustrative and are intended only to more intuitively demonstrate the key structure and connection relationships of the multi-camera video signal acquisition and transmission processing system of this utility model. In practical applications, the appearance and size of the device can be adjusted and optimized according to specific needs.

[0039] This utility model encompasses any substitutions, modifications, equivalent methods, and solutions made within the spirit and scope of this utility model. To provide the public with a thorough understanding of this utility model, specific details have been described in detail in the above preferred embodiments; however, those skilled in the art can fully understand this utility model even without these detailed descriptions. Furthermore, to avoid unnecessary confusion regarding the essence of this utility model, well-known methods, processes, procedures, components, and circuits have not been described in detail.

[0040] The above description is only a preferred embodiment of the present utility model. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present utility model, and these improvements and modifications should also be considered within the protection scope of the present utility model.

Claims

1. A multi-camera video signal acquisition backhaul processing system, characterized by, The application relates to a video signal acquisition and processing system. The switch is connected with a router, a monitoring terminal and a central server respectively to realize multi-path distribution and interaction of the video signal, wherein the router is used for connecting the area network with an external wide area network to expand the remote transmission range of the video signal, the monitoring terminal is used for presenting the video picture in real time and has an interactive operation function, and the central server is used for centrally managing, storing and processing the video data resource from the multiple signal acquisition and processing nodes.

2. The multi-camera video signal acquisition, backhaul and processing system of claim 1, wherein: The signal acquisition and processing node comprises a video encoder, a video compressor and a network interface module, the video encoder is used for converting the original video signal into an encoding format according to a specific encoding standard, the video compressor is used for compressing the encoded video signal, and the network interface module is used for transmitting the compressed video signal to the switch.

3. The multi-camera video signal acquisition, backhaul and processing system of claim 1, wherein: The image sensor interface chip in the signal acquisition and processing node is provided with a data output pin (DOUT) which is directly connected to a data input pin (DATA_IN) of the encoding chip to realize transmission of the video signal.

4. The multi-camera video signal acquisition, backhaul and processing system of claim 1, wherein: The encoding chip in the video encoder has a power pin (VCC and GND), a clock pin (CLK), a data input pin (DATA_IN), a data output pin (DATA_OUT), the clock pin (CLK) is connected in series with an external crystal oscillator, one pin of the external crystal oscillator is connected to the clock pin (CLK) of the encoding chip, and the other pin is grounded, and the data output pin (DATA_OUT) is connected to an input pin (COMP_IN) of the video compressor.

5. The multi-camera video signal acquisition, backhaul and processing system of claim 3, wherein: The video compressor comprises a compression chip and a cache chip, the compression chip has a power pin (VDD and VSS), an input pin (COMP_IN), an output pin (COMP_OUT), a data pin (DATA0-DATA3) and an address output pin (ADDR_OUT0-ADDR_OUT1), the cache chip has an address pin (ADDR1-ADDR2), a data input / output pin (DATA_IO1-DATA_IO2), a chip select pin (CS) and a read / write control pin (R / W), the data output pin (DATA_OUT) of the encoding chip is connected to the input pin (COMP_IN) of the compression chip, the data input / output pin (DATA_IO1-DATA_IO2) of the cache chip is connected to the data pin (DATA0-DATA3) of the compression chip, the address pin (ADDR1-ADDR2) of the cache chip is connected to the address output pin (ADDR_OUT0-ADDR_OUT1) of the compression chip, and the chip select pin (CS) and the read / write control pin (R / W) of the cache chip are connected to the corresponding control pins of the compression chip.

6. The multi-camera video signal acquisition, backhaul and processing system of claim 3, wherein: ​ 7. The multi-camera video signal acquisition, backhaul and processing system of claim 3, wherein: The network interface module includes a network interface chip, a network transformer and an RJ-45 interface socket, the network interface chip has power supply pins (VDD and GND), data input / output pins (DATA_IN_OUT), pins connected with the RJ-45 interface (TX+, TX-, RX+, RX-), the network transformer has primary coil pins (P1-P4) and secondary coil pins (S1-S4), the RJ-45 interface socket has a pair of differential signal pins (TX+, TX-) for transmitting data, a pair of differential signal pins (RX+, RX-) for receiving data and a ground pin (GND), the output pin (COMP_OUT) of the video compressor is connected with the data input pin (DATA_IN_OUT) of the network interface chip, the TX+ and TX- pins of the network interface chip are connected with the secondary coil pins (S1 and S2) through the primary coil pins (P1 and P2) of the network transformer, and then connected with the TX+ and TX- pins of the RJ-45 interface socket, and the RX+ and RX- pins of the network interface chip are connected with the secondary coil pins (S3 and S4) through the primary coil pins (P3 and P4) of the network transformer, and then connected with the RX+ and RX- pins of the RJ-45 interface socket.

8. The multi-camera video signal acquisition, backhaul and processing system of claim 1, wherein: The signal acquisition processing node further includes a microcontroller, which communicates with the encoding chip through an SPI or I2C bus, the microcontroller has power supply pins (VCC and GND), a reset pin (RST) and communication pins connected with the encoding chip, in SPI communication, the MOSI pin of the microcontroller is connected with the control data input pin of the encoding chip, the MISO pin is connected with the state data output pin of the encoding chip, the SCK pin is connected with the clock pin of the encoding chip for synchronous communication, and the CS pin is used for chip selection, so as to realize parameter configuration, state monitoring and control operation of the encoding chip.

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