Novel power semiconductor module packaging substrate

Abstract

The utility model relates to the field of semiconductor module packaging substrates, and discloses a novel power semiconductor module packaging substrate, which comprises a bottom plate, a mounting hole is arranged on the outer side of the bottom plate in a penetrating manner, a copper coating is arranged on the upper part of the bottom plate, a double-sided copper-clad ceramic plate is arranged on the upper part of the copper coating, and the double-sided copper-clad ceramic plate comprises a ceramic dielectric layer. The ceramic dielectric layer is arranged on the upper portion of the copper coating, and the metal copper layer is arranged on the upper portion of the ceramic dielectric layer. According to the utility model, no gap exists between the coating and the base material, no gap exists on the interface, the coating and the base material are tightly combined, and the copper surface can support copper sintering very reliably, so that the double-sided copper-clad ceramic plate and the packaging substrate are creatively sintered together by using a copper sintering process, and high-strength all-copper combination of the double-sided copper-clad ceramic plate and the aluminum silicon carbide substrate is realized; and the thermal resistance between the two is greatly reduced, and the problems of large soldering thermal resistance and low bonding strength are solved.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor module packaging substrates, and in particular to a novel power semiconductor module packaging substrate. Background Technology

[0002] In today's electronic technology field, semiconductor power devices such as IGBTs (Insulated Gate Bipolar Transistors) are widely used in many key areas, such as new energy vehicles, industrial automation, smart grids, and aerospace. These semiconductor power devices generate a lot of heat during operation, and efficient heat dissipation is crucial to ensuring device performance, stability, and extending their service life.

[0003] Currently, the biggest bottleneck in heat dissipation of existing semiconductor power device systems such as IGBTs is the interface thermal resistance. Interface thermal resistance refers to the resistance encountered when heat is transferred at the interface between different materials, which seriously affects the efficiency of heat transfer from the heat source to the heat dissipation device.

[0004] In traditional packaging structures, nickel-plated aluminum silicon carbide (ALSIC) substrates are soldered to DBC / AMB double-sided copper-clad ceramic substrates using solder paste. However, the solder paste has low thermal conductivity and bonding strength, making it difficult to meet the packaging requirements for higher power densities. These problems can be solved by sintering nano-copper between the DBC / AMB double-sided copper-clad ceramic substrate and the ALSIC substrate. However, the nickel-plated surface of the ALSIC substrate does not support copper sintering. Therefore, a novel power semiconductor module packaging substrate is proposed to solve the above problems. Utility Model Content

[0005] To overcome the above shortcomings, this utility model provides a novel power semiconductor module packaging substrate, which aims to improve the problem in the prior art that "the thermal conductivity and bonding strength of solder paste are low, making it difficult to meet the packaging requirements of higher power density".

[0006] To achieve the above objectives, the present invention adopts the following technical solution: a novel power semiconductor module packaging substrate, comprising a base plate, wherein a mounting hole is provided through the outer side of the base plate, a copper coating is provided on the upper part of the base plate, a double-sided copper-clad ceramic plate is provided on the upper part of the copper coating, the double-sided copper-clad ceramic plate comprises a ceramic dielectric layer, the ceramic dielectric layer is provided on the upper part of the copper coating, and a metallic copper layer is provided on the upper part of the ceramic dielectric layer.

[0007] As a further description of the above technical solution:

[0008] The copper coating and the base plate are integrally formed by cold spraying.

[0009] As a further description of the above technical solution:

[0010] The thickness of the copper coating is 0.1-1mm, and the thickness of the base plate is 1.5mm-10mm.

[0011] As a further description of the above technical solution:

[0012] The copper coating includes a pure copper coating.

[0013] As a further description of the above technical solution:

[0014] The copper coating is provided in one or more groups.

[0015] As a further description of the above technical solution:

[0016] The double-sided copper-clad ceramic substrate is configured as a direct copper-clad ceramic substrate (DBC) or an active metal brazing ceramic substrate (AMB).

[0017] As a further description of the above technical solution:

[0018] The base plate is made of aluminum silicon carbide (ALSIC).

[0019] As a further description of the above technical solution:

[0020] The base plate includes square, rectangular, and circular flat plate structures.

[0021] As a further description of the above technical solution:

[0022] The bottom of the base plate is either flat or has heat dissipation columns fixedly installed.

[0023] This utility model has the following beneficial effects:

[0024] 1. In this utility model, the coating and the substrate material are seamless, the interface is seamless, and the bonding is tight. The copper surface can reliably support copper sintering. Therefore, it is possible to creatively sinter the double-sided copper-clad ceramic plate and the packaging substrate together using the copper sintering process. This achieves a high-strength all-copper bond between the double-sided copper-clad ceramic plate and the aluminum silicon carbide substrate, and significantly reduces the thermal resistance between the two, solving the problems of high thermal resistance and low bonding strength in soldering.

[0025] 2. In this utility model, by setting the material of the base plate to aluminum silicon carbide (ALSIC) for forming, under the same working conditions, the thermal conductivity of the copper sintered structure of this device is increased by 30% and the bonding strength is increased by 50% compared with the traditional solder paste welding structure, ensuring the long-term reliable operation of the power device. Attached Figure Description

[0026] Figure 1 This is a three-dimensional structural diagram of the overall device in this utility model;

[0027] Figure 2 This is a three-dimensional structural diagram showing the disassembled double-sided copper-clad ceramic plate and the substrate in this utility model;

[0028] Figure 3 This is a three-dimensional structural diagram of Embodiment 2 of this utility model.

[0029] Legend:

[0030] 1. Base plate; 2. Mounting holes; 3. Copper coating; 4. Double-sided copper-clad ceramic plate; 41. Metallic copper layer; 42. Ceramic dielectric layer; 5. Heat dissipation column. Detailed Implementation

[0031] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0032] Example 1:

[0033] Reference Figure 1 and Figure 2 This utility model provides an embodiment of a novel power semiconductor module packaging substrate, including a base plate 1, which serves as the basic structure of the entire packaging substrate, providing a stable support platform for other components and ensuring that each component maintains a stable relative position during operation. Mounting holes 2 are provided through the outer side of the base plate 1 for mounting the packaging substrate onto other equipment or heat sinks, facilitating the integration and fixation of the entire power semiconductor module and ensuring its accurate installation and stable operation within the system. A copper coating 3 is provided on the upper part of the base plate 1. The copper coating 3 has good thermal conductivity, effectively improving the heat transfer from the power semiconductor device to the double-sided copper-clad ceramic plate 4. Compared to traditional thermal grease, this material can conduct heat away more quickly, reduce interfacial thermal resistance, and improve overall heat dissipation. A double-sided copper-clad ceramic plate 4 is provided on the top of the copper coating 3. The double-sided copper-clad ceramic plate 4 includes a ceramic dielectric layer 42, which serves as the main thermal and electrical conductive layer. The ceramic dielectric layer 42 has excellent thermal and electrical conductivity. The thermal conductivity of the copper coating 3 and the ceramic dielectric layer 42 can reach 317 W / MK. The ceramic dielectric layer 42 is located on the top of the copper coating 3, and a metallic copper layer 41 is provided on the top of the ceramic dielectric layer 42. The metallic copper layer 41 can evenly dissipate the heat transferred from the ceramic dielectric layer 42 into the surrounding environment, further improving heat dissipation efficiency.

[0034] Reference Figure 1 and Figure 2The copper coating 3 and the base plate 1 are integrally formed by cold spraying. The integral forming method of cold spraying makes the copper coating 3 and the base plate 1 gapless and tightly bonded, which greatly improves the heat conduction efficiency. The thickness of the copper coating 3 is 0.1-0.5mm, and the thickness of the base plate 1 is 1.5mm-10mm. The copper coating 3 is a pure copper coating. The copper coating 3 is provided with one or more sets. The copper surface can reliably support soldering. This allows power semiconductor devices or chips to be connected to the heat sink by soldering, realizing "low-temperature integral soldering" and "DOH packaging". This soldering method not only does not damage the device by the soldering temperature, but also avoids the problem of corrosion caused by electrochemical reaction, improving the reliability and stability of the connection.

[0035] Reference Figure 1 - Figure 3 The double-sided copper-clad ceramic plate 4 is configured as either a direct copper-clad ceramic substrate (DBC) or an active metal brazed ceramic substrate (AMB). Both types of ceramic plates possess excellent heat dissipation and insulation properties, meeting the performance requirements of different application scenarios. The base plate 1 is made of pure aluminum, aluminum alloy, or aluminum silicon carbide (ALSIC) material, exhibiting good mechanical strength and low density. This ensures structural strength while reducing overall weight. It also possesses good thermal conductivity, aiding in dissipating heat generated by power semiconductor devices and transferring heat to the surrounding environment, thus improving overall heat dissipation efficiency. The base plate 1 includes square, rectangular, and circular flat plate structures, allowing for the collection of materials according to actual needs and meeting the performance requirements of different application scenarios.

[0036] Example 2:

[0037] Reference Figure 1 - Figure 3 The difference between this second embodiment and the first embodiment is that in the second embodiment, multiple sets of heat dissipation columns 5 are fixedly connected to the lower part of the base plate 1. The heat dissipation columns 5 can increase the heat dissipation area, accelerate the dissipation of heat to the surrounding environment, further improve the heat dissipation capacity of the entire packaging substrate, ensure that the power semiconductor device operates stably at a lower temperature, and improve its performance and service life.

[0038] Working principle: During use, the power semiconductor device generates heat, which is first transferred to the ceramic dielectric layer 42 connected to it. The ceramic dielectric layer 42 has a thermal conductivity of up to 317W / MK, which can efficiently collect heat. The heat is then transferred to the guiding copper metal layer 41. At the same time, thanks to the tight bond between the copper coating layer 3 and the base plate 1, which is integrally formed by cold spraying, the heat is quickly conducted to the base plate 1. The base plate 1 is made of pure aluminum, aluminum alloy, or aluminum silicon carbide (ALSIC) material, which has a certain thermal conductivity and helps to diffuse the heat, achieving efficient heat dissipation. In the second embodiment, the multiple sets of heat dissipation columns 5 fixed at the bottom of the base plate 1 increase the heat dissipation area, accelerate the heat dissipation speed, and further enhance the heat dissipation effect. At the same time, the base plate 1 serves as a basic structure, and the mounting holes 2 on it are used to install the packaged substrate onto other devices or heat sinks, further enhancing the structural stability and installation accuracy.

[0039] Finally, it should be noted that the above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A novel power semiconductor module package substrate comprising a base plate (1), characterized in that: The bottom plate (1) is provided with mounting holes (2) on the outer side, the upper part of the bottom plate (1) is provided with a copper coating (3), the upper part of the copper coating (3) is provided with a double-sided copper-clad ceramic plate (4), the double-sided copper-clad ceramic plate (4) comprises a ceramic dielectric layer (42), the ceramic dielectric layer (42) is arranged on the upper part of the copper coating (3), and the upper part of the ceramic dielectric layer (42) is provided with a copper layer (41).

2. The novel power semiconductor module package substrate according to claim 1, characterized by: The copper coating (3) and the bottom plate (1) are integrally formed by cold spraying.

3. The novel power semiconductor module package substrate according to claim 1, characterized by: The thickness of the copper coating (3) is 0.1-1mm, and the thickness of the bottom plate (1) is 1.5mm-10mm.

4. The novel power semiconductor module package substrate according to claim 1, characterized by: The copper coating (3) is a pure copper material coating.

5. The novel power semiconductor module package substrate according to claim 1, characterized by: The copper coating (3) is provided with one or more groups.

6. The novel power semiconductor module package substrate according to claim 1, characterized by: The double-sided copper-clad ceramic plate (4) is arranged as a direct copper-clad ceramic substrate (DBC) or an active metal brazing ceramic substrate (AMB).

7. The novel power semiconductor module package substrate according to claim 1, characterized by: The material of the bottom plate (1) is aluminum silicon carbide (ALSIC) formed.

8. The novel power semiconductor module package substrate according to claim 1, characterized by: The bottom plate (1) comprises a square, rectangular or circular flat plate structure.

9. The novel power semiconductor module package substrate according to claim 1, characterized by: The bottom plate (1) is provided with a heat dissipation column (5) on the bottom.

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