Ceramic tube shell and packaging structure

Abstract

The utility model discloses a ceramic tube shell and a packaging structure. The ceramic tube shell comprises a ceramic base body and a working assembly. The ceramic base body comprises a base and an enclosure part, the enclosure part is installed on one side of the base, an installation space is defined by the enclosure part and the base, the installation space is used for containing a chip, and the base is provided with a step located in the installation space; the working assembly comprises a power supply layer, a bonding layer, a signal layer and a back PAD layer, the power supply layer is arranged in the enclosure part, the bonding layer is arranged on the surface of the step, the signal layer is arranged in the base and located on the side, away from the power supply layer, of the bonding layer, and the back PAD layer is located on the side, away from the enclosure part, of the base. According to the scheme, the adverse effect of electromagnetic interference of the power supply layer on signal transmission can be effectively reduced, and the small size of the ceramic tube shell can be conveniently realized.

Description

Technical Field

[0001] This utility model relates to the field of ceramic packaging technology, specifically to a ceramic tube shell and packaging structure. Background Technology

[0002] The ceramic encapsulation shell uses high-temperature sintered ceramic materials such as alumina and aluminum nitride, and is formed through processes such as punching, printing, stacking and cutting.

[0003] Publication number CN218730876U discloses a ceramic package shell for a power management module. Long electrodes and short electrodes are respectively installed at the bottom of the circuit board support and the chip support slot, both extending beyond the lower end of the ceramic base. A bonding layer is processed on the chip support slot. The bonding layers for the chip and its internal leads are also processed on the base. A circuit board can be placed on the steps, and the circuit board and chip can be connected via vertical leads. The top space of the ceramic base cavity is utilized, further reducing the volume of the ceramic base.

[0004] However, in existing ceramic packages, the bonding layer, power layer, and signal layer are typically located at the bottom of the chip carrier groove and arranged sequentially away from the chip carrier groove. To reduce electromagnetic interference from the power layer to the signal layer, the spacing between them is usually increased. However, due to the trend towards miniaturization of ceramic packages, their relatively small size limits the range of adjustment for the spacing between the power layer and the signal layer, resulting in limited effectiveness in reducing electromagnetic interference by increasing the distance. Utility Model Content

[0005] The purpose of this invention is to overcome the above-mentioned technical deficiencies and propose a ceramic shell that solves the problem that in the prior art, the bonding layer, power layer and signal layer are usually located at the bottom of the chip carrier groove and arranged sequentially in a direction away from the chip carrier groove. In order to reduce the electromagnetic interference of the power layer to the signal layer, the distance between the two is usually increased. However, since ceramic shells tend to be miniaturized, their size is relatively small, which limits the range of adjustment of the distance between the power layer and the signal layer, resulting in a limited effect of reducing electromagnetic interference by increasing the distance.

[0006] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, this utility model provides a ceramic tube shell, comprising:

[0008] A ceramic substrate includes a base and a surrounding portion, the surrounding portion being mounted on one side of the base and enclosing a mounting space for accommodating a chip, the base having a step located within the mounting space; and

[0009] The working component includes a power layer, a bonding layer, a signal layer, and a back PAD layer. The power layer is disposed inside the enclosure portion, the bonding layer is disposed on the surface of the step, the signal layer is disposed inside the base and located on the side of the bonding layer away from the power layer, and the back PAD layer is located on the side of the base away from the enclosure portion.

[0010] In one embodiment, the working component further includes an isolation ground layer disposed within the base or the enclosure and located between the power layer and the signal layer.

[0011] In one embodiment, the isolation layer is located between the power layer and the bonding layer, and is disposed within the enclosure portion.

[0012] In one embodiment, the mounting space is provided with an opening on the side away from the base.

[0013] In one embodiment, the enclosure includes a panel that is mounted on one side of the base and encloses the installation space.

[0014] The power supply layer is located inside the enclosure.

[0015] In one embodiment, the enclosure is integrally formed with the base.

[0016] In one embodiment, multiple signal layers are provided, and the multiple signal layers are arranged sequentially in a direction away from the power layer.

[0017] In one embodiment, the working component further includes a pin lead layer mounted on the base and located on the side of the base away from the enclosure portion, and connected to the signal layer.

[0018] In one embodiment, the bonding layer is at least partially located within the mounting space for connecting the chip.

[0019] Secondly, this utility model also provides a packaging structure, which includes a ceramic tube shell as described in any of the above claims.

[0020] Compared with existing technologies, the ceramic housing provided by this invention, because the bonding layer is located between the power layer and the signal layer, eliminates the need for signal layer traces to pass through the power layer, effectively reducing electromagnetic interference from the power layer to the signal leads. Simultaneously, the bonding layer also isolates electromagnetic interference from the power layer to the signal layer to a certain extent, thus effectively mitigating the adverse effects of power layer electromagnetic interference on signal transmission. Furthermore, the enclosure serves both as a protective structure for chip mounting and as a mounting carrier for the power layer, thereby increasing the distance between the power layer and the signal layer without requiring additional enlargement of the ceramic substrate. This further reduces electromagnetic interference from the power layer to the signal layer and facilitates miniaturization of the ceramic housing. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the ceramic tube shell provided in an embodiment of the present utility model;

[0022] Figure 2 yes Figure 1 A partial schematic diagram of the ceramic tube shell;

[0023] Figure 3 yes Figure 1 Schematic diagram of the ceramic matrix;

[0024] Figure 4 yes Figure 3 Cross-sectional view of the ceramic matrix;

[0025] Figure 5 yes Figure 1 A schematic diagram of the working components;

[0026] Figure 6 yes Figure 5 A partial schematic diagram of the working components;

[0027] Figure 7 This is a schematic diagram of the framework of the working components in another embodiment;

[0028] Figure 8 yes Figure 5 Schematic diagram of the middle power layer;

[0029] Figure 9 yes Figure 5 Schematic diagram of the intermediate isolation strata;

[0030] Figure 10 yes Figure 5 Schematic diagram of the intermediate bonding layer;

[0031] Figure 11 yes Figure 5 A schematic diagram of the middle signal layer.

[0032] Explanation of reference numerals in the attached figures:

[0033] 1. Ceramic substrate; 1a. Mounting space; 11. Base; 12. Enclosure; 121. Enclosure panel; 13. Step; 2. Working component; 21. Power layer; 22. Bonding layer; 23. Signal layer; 24. Ground isolation layer; 25. Pin and lead layer. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0035] To address the problem that existing ceramic housings typically place the bonding layer, power layer, and signal layer at the bottom of the chip carrier groove and arrange them sequentially away from the chip carrier groove, and to reduce electromagnetic interference from the power layer to the signal layer, the spacing between them is usually increased. However, due to the trend towards miniaturization of ceramic housings, their relatively small size limits the range of adjustment for the spacing between the power layer and the signal layer, resulting in limited effectiveness in reducing electromagnetic interference by increasing the distance. This invention provides a ceramic housing that can effectively reduce the adverse effects of electromagnetic interference from the power layer on signal transmission and facilitates the miniaturization of the ceramic housing.

[0036] It should be noted that the ceramic tube shell described in this utility model is used in, but not limited to, packaging structures, etc. For ease of explanation, this utility model only uses the application of the ceramic tube shell in packaging structures as an example for explanation. The principle of applying the ceramic tube shell in other types of equipment is essentially the same as the principle of applying it in packaging structures, and will not be described in detail here.

[0037] Please see Figures 1 to 6 , Figures 1 to 6 This is a schematic diagram of the structure of a ceramic tube shell in one embodiment of the present invention. The ceramic tube shell includes a ceramic substrate 1 and a working component 2. The ceramic substrate 1 includes a base 11 and a enclosure portion 12. The enclosure portion 12 is installed on one side of the base 11 and encloses an installation space 1a with the base 11. The installation space 1a is used to accommodate the chip. The base has a step 13 located within the installation space 1a. The working component 2 includes a power layer 21, a bonding layer 22, a signal layer 23, and a back PAD layer (not shown). The power layer 21 is disposed inside the enclosure portion 12. The bonding layer 22 is disposed on the surface of the step 13. The signal layer 23 is disposed inside the base 11 and is located on the side of the bonding layer 22 away from the power layer 21. The back PAD layer is located on the side of the base 11 away from the enclosure portion 12.

[0038] In the ceramic housing provided by this utility model, since the bonding layer 22 is located between the power layer 21 and the signal layer 23, the traces of the signal layer 23 no longer need to pass through the power layer 21, effectively reducing the electromagnetic interference of the power layer 21 on the signal leads. At the same time, the bonding layer 22 can also isolate the electromagnetic interference of the power layer 21 on the signal layer 23 to a certain extent, thereby effectively reducing the adverse effects of the electromagnetic interference of the power layer 21 on signal transmission. On the other hand, the enclosure portion 12 serves as both a protective structure for chip mounting and a mounting carrier for the power layer 21. Thus, while increasing the distance between the power layer 21 and the signal layer 23, it is not necessary to additionally increase the size of the ceramic substrate 1. This further reduces the electromagnetic interference of the power layer 21 on the signal layer 23 and facilitates the miniaturization of the ceramic housing.

[0039] It should be noted that the enclosure portion 12 typically serves as a sidewall enclosure for the chip and is relatively thin. That is, the portion of the mounting space 1a corresponding to the enclosure portion 12 has a thin-walled structure. Therefore, the relatively small power layer 21 can be placed in the enclosure portion 12; that is, the power layer 21 is placed within the thin sidewall of the mounting space 1a, making full use of the thin-walled structure of the chip mounting space 1a; while the relatively large bonding layer 22 and signal layer 23 are placed within the base 11 and arranged sequentially in a direction away from the power layer 21.

[0040] Thus, on the one hand, since the bonding layer 22 is located between the power layer 21 and the signal layer 23, the leads of the signal layer 23 no longer need to pass through the power layer 21, effectively reducing the electromagnetic interference of the power layer 21 on the signal leads. At the same time, the bonding layer 22 can also isolate the electromagnetic interference of the power layer 21 on the signal layer 23 to a certain extent, thereby effectively reducing the adverse effects of the electromagnetic interference of the power layer 21 on signal transmission. On the other hand, based on the thin-walled structure of the mounting space 1a, the power layer 21 can be accommodated, increasing the spacing between the power layer 21 and the signal layer 23, and without needing to further increase the size of the ceramic substrate 1. While further reducing the electromagnetic interference of the power layer 21 on the signal layer 23, it also facilitates the miniaturization of the ceramic tube shell.

[0041] It should be understood that PAD refers to the solder pad, the bonding layer 22 is the physical interface between the chip and the package, and the signal layer 23 usually needs to lead the chip's I / O signals (input / output signals) to the external circuit through the bonding layer 22. It is the core link to realize electrical functions and needs to be realized through wire bonding, flip-chip bonding or RDL technology (redistribution layer technology), taking into account the requirements of materials, processes and signal integrity.

[0042] Furthermore, signal layer 23 and power layer 21 do not require direct electrical connection; they perform different functions within the package. Signal layer 23 is typically dedicated to transmitting high-speed / high-frequency signals and requires impedance matching and a low-noise environment. Power layer 21, on the other hand, is responsible for stable power supply and requires a low-impedance loop to suppress voltage fluctuations. In one embodiment, they are arranged independently to reduce power supply noise interference with signals and avoid common-mode noise coupling.

[0043] In one embodiment, the working component 2 further includes an isolation layer 24, which is disposed within the base 11 or the enclosure portion 12 and is located between the power layer 21 and the signal layer 23.

[0044] In this embodiment, an isolation ground layer 24 is also provided between the power layer 21 and the signal layer 23 to further isolate the electromagnetic interference effect of the power layer 21 on the signal layer 23. Since the size of the isolation ground layer 24 can also be set relatively small, in this case, the isolation ground layer 24 is set between the bonding layer 22 and the power layer 21. Specifically, the isolation ground layer 24 is also placed inside the enclosure portion 12. That is, the isolation ground layer 24 is also set in the thin wall of the mounting space 1a, making full use of the thin-walled structure of the chip mounting space 1a, thereby further improving the electromagnetic interference resistance while avoiding increasing the volume of the ceramic package.

[0045] In one embodiment, the mounting space 1a is provided with an opening on the side away from the base 11.

[0046] In this embodiment, the chip mounting space 1a is set as an open slot to facilitate chip installation, simplify the structure of the ceramic housing, and improve assembly convenience.

[0047] It should be noted that the arrangement of the enclosure 12 is not limited, as long as it can be used together with the base 11 to form the installation space 1a. Specifically, the enclosure 12 can be configured as an enclosure seat or enclosure cover, or other forms.

[0048] In one embodiment, the enclosure 12 includes a enclosure 121, which is installed on one side of the base 11 and encloses an installation space 1a; the power supply layer 21 is disposed within the enclosure 121.

[0049] In this embodiment, the mounting space 1a with the above opening is formed by the enclosure 121, and the power supply layer 21 is placed in the enclosure 121, resulting in a simple and reliable structure. Specifically, to improve the connection strength between the enclosure 121 and the base 11, in one embodiment, the enclosure 121 and the base 11 are integrally formed.

[0050] In one embodiment, please refer to Figure 7 Multiple signal layers 23 are provided, and the multiple signal layers 23 are arranged sequentially in a direction away from the bonding layer 22.

[0051] In this embodiment, in order to improve signal transmission capability, multiple signal layers 23 are set and arranged sequentially along the direction away from the bonding layer 22 to reduce electromagnetic interference from the power layer 21 to each signal layer 23.

[0052] In one embodiment, the working component 2 further includes a pin lead layer 25, which is mounted on the base 11 and located on the side of the base 11 away from the enclosure portion 12, and is connected to the signal layer 23.

[0053] In this embodiment, a pin lead layer 25 is provided on the bottom side of the base 11 and connected to the signal layer 23. Specifically, the signal layer 23 is connected to the pins (connector pins) through bonding wires or leads to form an electrical path with external circuitry.

[0054] In one embodiment, the bonding layer 22 is at least partially located within the mounting space 1a for connecting the chip.

[0055] In this embodiment, the bonding layer 22 is partially led to the bottom wall of the mounting space 1a, and the bonding layer 22 serves as the physical interface between the package and the chip. Specifically, in this embodiment, a step 13 is provided on the bottom wall of the mounting space 1a for at least a partial placement of the bonding layer 22.

[0056] It should be understood that the bonding layer 22 connects the chip pads to the metal lines on the ceramic substrate through wire bonding or flip-chip bonding technology, forming a conductive path. For example, wire bonding connects the chip solder joints and the substrate pads through metal wires, while flip-chip bonding uses solder ball bumps to directly achieve the electrical connection between the chip and the substrate.

[0057] Furthermore, when the chip is fixed to the substrate 11 using adhesive or solder, the bonding layer 22 provides mechanical support and transfers the heat generated by the chip to the substrate 11. In addition, the design of the bonding layer 22 can also meet high-density packaging requirements. For example, a cross-shaped bonding structure enables complex signal transmission through multi-layer wiring while maintaining hermeticity and reliability.

[0058] Furthermore, this utility model also provides a packaging structure, which includes the ceramic tube shell as described above. It should be noted that the detailed structure of the ceramic tube shell in the packaging structure can be referred to the embodiments of the ceramic tube shell described above, and will not be repeated here. Since the ceramic tube shell described above is used in the packaging structure of this utility model, the embodiments of the packaging structure of this utility model include all the technical solutions of all the embodiments of the ceramic tube shell described above, and the achieved technical effects are exactly the same, and will not be repeated here.

[0059] To better understand this utility model, the following is combined with... Figures 1 to 11 The technical solution of this utility model is described in detail below:

[0060] In this design, the bonding layer 22, signal layer 23, and pin lead layer 25 are disposed on the base 11 and arranged sequentially away from the enclosure 121, while the power layer 21 and ground isolation layer 24 are placed within the enclosure 121 and arranged sequentially towards the base 11. This allows the electromagnetic interference of the power layer 21 on the signal layer 23 to be reduced by utilizing the ground isolation layer 24 and bonding layer 22. Simultaneously, signal lines do not need to pass through the power layer 21, effectively reducing electromagnetic interference from the power layer 21 on the signal lines. Furthermore, the thin-walled structure of the chip mounting space 1a is cleverly utilized to house the power layer 21 and ground isolation layer 24. This achieves maximum physical isolation between the power layer 21 and signal layer 23, increasing the isolation by at least -20dB, and significantly reducing the impact of electromagnetic interference from the power supply on the signal lines, thereby improving the stability of signal transmission.

[0061] Specifically, in this solution, the enclosure part 12 and the step 13 of the base 11 are combined to form a ceramic ring enclosure. That is, the ceramic ring enclosure is divided into two sub-steps from top to bottom, wherein the upper enclosure step is an airtight structure enclosure, that is, the upper enclosure part 12 is used to match the installation height of the bonding wire and the air suction plate, and the power layer 21 is set inside the airtight structure enclosure. In one embodiment, it is arranged from top to bottom as follows: a first power layer, a second power layer and an isolation ground layer 24.

[0062] The step 13 of the base 11 located on the lower side is used to match the mounting height of the chip. The bonding PAD is set on the exposed surface of the step 13 of the base 11. On the one hand, the bonding PAD is interconnected with the chip through bonding wire to realize the transmission of electrical signals with the chip; on the other hand, the bonding PAD is transmitted downward through the metallized solid hole and is connected to the PAD on the back of the base 11 to realize the transmission of electrical signals with the peripheral circuit. The inner layer of the base 1 is set as the signal layer 23 for signal routing.

[0063] Thus, the base 1 does not have a power layer inside. Power is transmitted upward from the back PAD through the metallized solid hole, passes through the step of the bonding layer 22, continues upward, and reaches the airtight structural enclosure. Inside the airtight structural enclosure, a power layer 21 and an isolation ground layer 24 are set. Then, a hole is drilled from the power layer 21 downward, passes through the isolation ground layer 24, and reaches the power PAD of the bonding layer 22.

[0064] The specific embodiments of this utility model described above do not constitute a limitation on the scope of protection of this utility model. Any other corresponding changes and modifications made based on the technical concept of this utility model should be included within the scope of protection of the claims of this utility model.

Claims

1. A ceramic package, characterized by, The ceramic base comprises a base and a surrounding part, the surrounding part is installed on one side of the base and forms an installation space with the base, the installation space is used for accommodating a chip, the base has a step inside the installation space; and The working assembly comprises a power supply layer, a bonding layer, a signal layer and a back PAD layer, the power supply layer is arranged inside the surrounding part, the bonding layer is arranged on the surface of the step, the signal layer is arranged inside the base and located on the side of the bonding layer away from the power supply layer, and the back PAD layer is located on the side of the base away from the surrounding part. The working assembly further comprises an isolation ground layer, the isolation ground layer is arranged inside the base or the surrounding part and located between the power supply layer and the signal layer.

2. The ceramic package of claim 1, wherein, The isolation ground layer is located between the power supply layer and the bonding layer and arranged inside the surrounding part.

3. The ceramic package of claim 2, wherein, The installation space is open on the side away from the base.

4. The ceramic package of claim 1, wherein, The surrounding part comprises a surrounding plate, the surrounding plate is installed on one side of the base and forms the installation space; 5. The ceramic package of claim 4, wherein, The power supply layer is arranged inside the surrounding plate. The surrounding part is integrally arranged with the base.

6. The ceramic package of any one of claims 1 to 5, wherein, The signal layer is arranged in plurality, and the plurality of signal layers are sequentially arranged in the direction away from the power supply layer.

7. The ceramic package of claim 1, wherein, The working assembly further comprises a pin lead layer, the pin lead layer is installed on the base and located on the side of the base away from the surrounding part and connected with the signal layer.

8. The ceramic package of claim 1, wherein, The bonding layer is at least partially located inside the installation space and used for connecting the chip.

9. The ceramic package of claim 1, wherein, The ceramic package comprises the ceramic base as claimed in any one of claims 1-9.

10. A package structure, characterized by, ​

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