Silicon carbide VDMOS groove type thermal diffusion terminal
By etching shallow trenches near the terminal structure of silicon carbide VDMOS devices and performing thermal diffusion of the P-type doped region, the breakdown problem caused by the concentration of electric field at the device edge is solved, thereby enhancing the stability and withstand voltage of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-15
- Publication Date
- 2026-04-07
AI Technical Summary
Silicon carbide VDMOS devices suffer from electric field concentration at the edges, leading to breakdown and affecting device stability.
Shallow trenches are etched near the device terminal structure, and thermal diffusion of the P-type doped region is performed to prepare the first P-type doped region, the second P-type doped region, and the third P-type doped region. Their depth and electric field strength are controlled to enhance the voltage withstand capability of the device edge.
By controlling the electric field strength, edge breakdown of the device can be avoided, thereby improving the device's stability and withstand voltage.
Smart Images
Figure CN224098055U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a silicon carbide VDMOS trench type heat diffusion terminal. BACKGROUND
[0002] The silicon carbide VDMOS is the typical representative of the silicon carbide power device, and has wide application in the electric automobile, aerospace, power conversion and other fields. SUMMARY
[0003] The utility model solves the technical problem, in order to provide a silicon carbide VDMOS trench type heat diffusion terminal, guarantee that the edge of device will not appear breakdown phenomenon, strengthened the stability of device.
[0004] First, the utility model provides a silicon carbide VDMOS trench type heat diffusion terminal, and it includes:
[0005] Silicon carbide substrate,
[0006] Drift layer, the drift layer lower side surface is connected to the silicon carbide substrate upper side, and the drift layer has P type trap area, main knot, first field limiting ring and second field limiting ring in it;The P type trap area is connected to main knot, and the distance between main knot and first field limiting ring is greater than the distance between first field limiting ring and second field limiting ring;
[0007] Insulating layer, the insulating layer lower side surface is connected to the drift layer, P type trap area, main knot, first field limiting ring and second field limiting ring respectively;
[0008] Source metal layer, the source metal layer is connected to P type trap area and insulating layer.
[0009] The utility model has the advantages of:
[0010] First, the utility model can increase and effectively control the depth of first P type doped area, second P type doped area and third P type doped area by etching shallow groove near device terminal structure and then preparing first P type doped area, second P type doped area and third P type doped area, improve the withstand voltage capability of device terminal structure;
[0011] Second, the distance between main knot, first field limiting ring and second field limiting ring is set in the utility model, so that the electric field intensity between first P type trench area, second P type trench area and third P type trench area is consistent, guarantee that the edge of device will not appear breakdown phenomenon, strengthened the stability of device. BRIEF DESCRIPTION OF DRAWINGS
[0012] The utility model will be further described below with reference to the drawings in combination with the embodiments.
[0013] Figure 1 It is the principle diagram of a kind of silicon carbide VDMOS trench type thermal diffusion terminal of the utility model.
[0014] Figure 2 It is the process section view of a kind of silicon carbide VDMOS trench type thermal diffusion terminal of the utility model Figure One .
[0015] Figure 3 It is the process section view of a kind of silicon carbide VDMOS trench type thermal diffusion terminal of the utility model Figure Two .
[0016] Figure 4 It is the process section view of a kind of silicon carbide VDMOS trench type thermal diffusion terminal of the utility model Figure Three .
[0017] Figure 5 It is the process section view of a kind of silicon carbide VDMOS trench type thermal diffusion terminal of the utility model Figure Four .
[0018] Figure 6 It is the process section view of a kind of silicon carbide VDMOS trench type thermal diffusion terminal of the utility model Figure Five .
[0019] Figure 7 It is the process section view of a kind of silicon carbide VDMOS trench type thermal diffusion terminal of the utility model Figure Six .
[0020] Figure 8 It is the process section view of a kind of silicon carbide VDMOS trench type thermal diffusion terminal of the utility model Figure Seven . Specific implementation
[0021] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein in the specification merely describe the specific embodiments of the present application for the purpose of the description and are not intended to limit the present application.
[0023] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
[0024] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein can be interpreted accordingly.
[0025] The singular form "a", "an", and "the" include plural references unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used herein, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
[0026] As Figure 1 shown in FIG. 1, the embodiment of the present application provides a silicon carbide VDMOS trench type heat diffusion terminal, which comprises:
[0027] a silicon carbide substrate 1,
[0028] a drift layer 2 connected to the upper side of the silicon carbide substrate 1, the drift layer 2 having a P-type well region 21, a main junction 22, a first field limiting ring 23 and a second field limiting ring 24;
[0029] an insulating layer 3 connected to the drift layer 2, the P-type well region 21, the main junction 22, the first field limiting ring 23 and the second field limiting ring 24 respectively;
[0030] a source metal layer 4 connected to the P-type well region 21 and the insulating layer 3;
[0031] a drain metal layer 5 provided on the lower side of the silicon carbide substrate 1.
[0032] In this embodiment, preferably, the main junction 22 comprises a first P-type doped region 221 connected to the P-type well region 21 and a first P-type trench region 222 provided in the first P-type doped region 221; the first field limiting ring 23 comprises a second P-type doped region 231 and a second P-type trench region 232 provided in the second P-type doped region 231; the second field limiting ring 24 comprises a third P-type doped region 241 and a third P-type trench region 242 provided in the third P-type doped region 241; the insulating layer 3 is connected to the drift layer 2, the P-type well region 21, the first P-type doped region 221, the first P-type trench region 222, the second P-type doped region 231, the second P-type trench region 232, the third P-type doped region 241 and the third P-type trench region 242 respectively.
[0033] In this embodiment, preferably, the distance between the first P-type trench region 222 and the second P-type trench region 232 is 28 μm; the distance between the second P-type trench region 232 and the third P-type trench region 242 is 16 μm.
[0034] In this embodiment, preferably, the width of the first P-type trench region 222 is 5 μm; the thickness of the first P-type doped region 221 is less than or equal to 3 μm, and the width of the first P-type doped region 221 is less than or equal to 1.2 μm.
[0035] In this embodiment, preferably, the width of the second P-type trench region 232 is 5 μm; the thickness of the second P-type doped region 231 is less than or equal to 3 μm, and the width of the second P-type doped region 231 is less than or equal to 1.2 μm.
[0036] In this embodiment, preferably, the third P-type trench region 242 has a width of 5 μm; the third P-type doped region 241 has a thickness of less than or equal to 3 μm, and a width of less than or equal to 1.2 μm.
[0037] As shown in Figure 1 The preparation method of the terminal comprises the following steps:
[0038] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 5; epitaxially growing on the upper side of the silicon carbide substrate 1 to obtain a drift layer 2;
[0039] Step 2: forming a barrier layer 6 above the drift layer 2, etching the barrier layer 6 to form a through hole, and ion implantation to form a P-type well region 21;
[0040] Step 3: removing the original barrier layer 6, re-forming the barrier layer 6, etching the barrier layer 6 to form a through hole, and etching to form a groove 7 in the drift layer;
[0041] Step 4: depositing silicon carbide material to form a first P-type trench region 222, a second P-type trench region 232, and a third P-type trench region 242;
[0042] Step 5: setting the temperature to 1200 degrees Celsius and the time to 80 minutes, and performing thermal diffusion and redistribution on the first P-type trench region 222, the second P-type trench region 232, and the third P-type trench region 242 to form a first P-type doped region 221, a second P-type doped region 231, and a third P-type doped region 241; the main junction 22 comprises the first P-type doped region 221 and the first P-type trench region 222; the first field limiting ring 23 comprises the second P-type doped region 231 and the second P-type trench region 232; the second field limiting ring 24 comprises the third P-type doped region 241 and the third P-type trench region 242; because thermal diffusion has no directionality and only diffuses along the concentration gradient, the doping concentration of the first P-type doped region 221, the second P-type doped region 221, and the third P-type doped region 231 decreases with the increase of the distance, but the difference in the doping concentration is small, and the concentration gradient is beneficial to the voltage resistance of the terminal structure of the device;
[0043] Step 6: removing the original barrier layer 6, re-forming the barrier layer 6, etching the barrier layer 6 to form a through hole, and depositing to form an insulating layer 3;
[0044] Step 7: removing the original barrier layer 6, re-forming the barrier layer 6, etching the barrier layer 6 to form a through hole, depositing metal to form a source metal layer 4, and removing the barrier layer 6.
[0045] In another embodiment of the utility model, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3, the doping concentration of the N-type drift layer 2 is 5-9e16cm -3 , the doping concentration of the first P-type doped region 221, the second P-type doped region 231 and the third P-type doped region 241 is 5-9e17cm -3 , the doping concentration of the P-type well region 21 is 1-6e17cm -3 , the doping concentration of the first P-type trench region 222, the second P-type trench region 232 and the third P-type trench region 242 is 1-6e18cm -3 , the material of the insulating layer can be silicon dioxide; the doping concentration of the N-type silicon carbide substrate 1, the N-type drift layer 2 and the P-type well region 21 is considered in the traditional design structure of the planar gate silicon carbide VDMOS device, the doping concentration of the first P-type trench region 222, the second P-type trench region 232 and the third P-type trench region 242 is for forming the first P-type doped region 221, the second P-type doped region 231 and the third P-type doped region 241, and the doping concentration of the first P-type doped region 221, the second P-type doped region 231 and the third P-type doped region 241 is for forming the gradual junction with the main junction 22, the first field limiting ring 23 and the third field limiting ring 24, so as to realize the voltage resistance of the device;
[0046] The width w of the first P-type trench region 222, the second P-type trench region 232 and the third P-type trench region 242 of the device is 5μm, the distance d1 between the first P-type trench region 222 and the second P-type trench region 232 is 28μm, the distance d2 between the second P-type trench region 232 and the third P-type trench region 242 is 16μm, with the expansion of the electric field, the distance between the trench regions first increases and then decreases, the maximum thickness of the first P-type doped region 221, the second P-type doped region 231 and the third P-type doped region 241 is 3μm, the maximum width is 1.2μm, and the doping concentration at the edge is 5-9e17cm -3 ;
[0047] The present embodiment can increase and effectively control the depth of the first P-type doped region 221, the second P-type doped region 231 and the third P-type doped region 241 by etching a shallow trench near the device terminal structure and then preparing the first P-type doped region 221, the second P-type doped region 231 and the third P-type doped region 241, so as to improve the voltage resistance of the device terminal structure;
[0048] The preparation method of the device terminal first P-type doped region 221, the second P-type doped region 231 and the third P-type doped region 241 adopts the heat diffusion method, the heat diffusion depth of the device can be ensured due to the etching of the trench, and compared with ion implantation, the heat diffusion has small lattice damage to the device, and the reliability and stability of the device are higher;
[0049] The device forms a doping concentration with a slowly-varying concentration gradient structure in the heat diffusion process, and the doping concentration gradually increases from the farthest to the trench region, which can ensure that the main withstand voltage structure of the terminal is distributed in the first P-type doped region 221, the second P-type doped region 231 and the third P-type doped region 241; and when close to the first P-type trench region 222, the second P-type trench region 232 and the third P-type trench region 242, the higher doping concentration can effectively inhibit the influence of the electric field diffusion on the insulating layer.
[0050] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.
Claims
1. A silicon carbide VDMOS trench-type thermal diffusion terminal, characterized in that: include: silicon carbide substrate, A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate, the drift layer having a P-type well region, a main junction, a first field limiting ring, and a second field limiting ring; the P-type well region is connected to the main junction, and the distance between the main junction and the first field limiting ring is greater than the distance between the first field limiting ring and the second field limiting ring; An insulating layer, the lower side of which is connected to the drift layer, the P-type well region, the main junction, the first field limiting ring, and the second field limiting ring, respectively. A source metal layer, which is connected to a P-type well region and an insulating layer.
2. The silicon carbide VDMOS trench-type thermal diffusion terminal as described in claim 1, characterized in that: The main junction includes a first P-type doped region and a first P-type trench region, the first P-type doped region being connected to a P-type well region, and the first P-type trench region being disposed within the first P-type doped region; the first field limiting ring includes a second P-type doped region and a second P-type trench region, the second P-type trench region being disposed within the second P-type doped region; the second field limiting ring includes a third P-type doped region and a third P-type trench region, the third P-type trench region being disposed within the third P-type doped region.
3. The silicon carbide VDMOS trench-type thermal diffusion terminal as described in claim 2, characterized in that: The distance between the first P-type trench region and the second P-type trench region is 28 μm; the distance between the second P-type trench region and the third P-type trench region is 16 μm.
4. The silicon carbide VDMOS trench-type thermal diffusion terminal as described in claim 2, characterized in that: The width of the first P-type trench region is 5 μm; the thickness of the first P-type doped region is less than or equal to 3 μm, and the width of the first P-type doped region is less than or equal to 1.2 μm.
5. A silicon carbide VDMOS trench-type thermal diffusion terminal as described in claim 2, characterized in that: The width of the second P-type trench region is 5 μm; the thickness of the second P-type doped region is less than or equal to 3 μm, and the width of the second P-type doped region is less than or equal to 1.2 μm.
6. The silicon carbide VDMOS trench-type thermal diffusion terminal as described in claim 2, characterized in that: The width of the third P-type trench region is 5 μm; the thickness of the third P-type doped region is less than or equal to 3 μm, and the width of the third P-type doped region is less than or equal to 1.2 μm.