Computing device and computing server
By introducing a switch module into the OAM architecture, all data interaction ports of the computing accelerator cards are connected to the switch module, enabling flexible adjustment of the interconnection relationship of the computing accelerator cards and parallel interconnection of multiple ports. This solves the problem of low data interaction efficiency between computing accelerator cards in the OAM architecture and improves computing efficiency and data communication rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-02-26
- Publication Date
- 2026-04-14
AI Technical Summary
In the existing OAM architecture, the data interaction efficiency between computing accelerator cards is low, especially the data interaction latency between accelerator cards with different CPUs is long, which makes it difficult to meet the needs of various computing tasks.
By using a switch module, all data interaction ports of the computing accelerator cards are connected to a single switch module. The switch module can be configured to flexibly adjust the interconnection between the computing accelerator cards, increasing configurability. Parallel interconnection can also be achieved through multiple data interaction ports, reducing latency.
It enhances the data interaction topology optimization capabilities between computing devices and servers, shortens the data interaction latency between computing accelerator cards, and improves data communication speed and overall computing efficiency.
Smart Images
Figure CN224122983U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computing servers, and more particularly to a computing device and a computing server. Background Technology
[0002] The OAM (OCP Accelerator Module) architecture is an open and standardized accelerator hardware form and interconnect specification defined by the OCP (Open Compute Project) organization. It is a standardized and modular hardware design specification for high-performance computing and artificial intelligence training.
[0003] The core of the OAM architecture is the integration of a fixed general-purpose CPU (Central Processing Unit), PCIe (Peripheral Component Interconnect Express) switch chip, and memory on a Universal Baseboard (UBB), forming a stable control and interconnect platform. Simultaneously, the UBB provides standardized high-speed interfaces, supporting the flexible insertion and removal of multiple OAM accelerator cards (such as GPUs (Graphics Processing Units)), creating a heterogeneous computing device with a fixed basic hardware and upgradeable computing power. The OAM architecture achieves high-density integration and efficient collaboration of computing resources. The CPU is responsible for system control, task scheduling, and general-purpose computing, while the OAM accelerator cards are dedicated to large-scale parallel computing. Low-latency data exchange is achieved between the CPU and OAM accelerator cards, and between OAM accelerator cards themselves, via optimized PCIe links.
[0004] A typical OAM architecture uses a dual-CPU and eight OAM accelerator card design. Each CPU is connected to four OAM accelerator cards through a PCIe switch module. The two CPUs are interconnected to form the main structure of the OAM architecture.
[0005] In the OAM architecture, OAM accelerator cards interact with each other via PCIe links. Particularly in typical OAM architectures, data interaction between two OAM accelerator cards running on different CPUs requires further traversal through both CPUs, hindering further improvements in data interaction efficiency. Furthermore, when computational tasks require specific data routing between OAM accelerator cards, the OAM architecture struggles to improve data interaction speed due to latency incurred when traversing hardware nodes such as PCIe switch modules and CPUs, creating a data waiting bottleneck during computation. Utility Model Content
[0006] In view of this, the present disclosure provides a computing device and a computing server to improve the flexibility of data interconnection between computing accelerator cards for various computing tasks, and to help shorten the data interaction latency between computing accelerator cards, thereby helping to improve the computing speed of computing servers and even computing clusters composed of multiple computing servers.
[0007] According to one aspect of the embodiments of this disclosure, a computing device is provided, comprising:
[0008] Universal substrate;
[0009] At least two computing accelerator cards are mounted on the universal baseboard;
[0010] A switch module is installed on the general-purpose baseboard and coupled to the at least two computing accelerator cards through data interconnection traces laid in the general-purpose baseboard. The data interaction path between any two computing accelerator cards includes the switch module, and there is no one-to-one data interconnection trace between any two computing accelerator cards that does not pass through the switch module.
[0011] The computing device further includes:
[0012] The central processing unit is mounted on the general-purpose substrate;
[0013] The PCIe switch module is installed on the general-purpose baseboard and is coupled to the at least two computing accelerator cards and the central processing unit through the PCIe data routing network laid out in the general-purpose baseboard. The at least two computing accelerator cards and the central processing unit exchange data through the PCIe switch module.
[0014] In one possible implementation, the switch module includes:
[0015] A switch circuit board, wherein the switch circuit board is fixed to the general-purpose board;
[0016] A switch chip is mounted on the switch circuit board and coupled to the at least two computing accelerator cards via data interconnect traces arranged in the switch circuit board and the general-purpose board.
[0017] In one possible implementation, the switch module further includes:
[0018] A routing configuration processor is installed on the switch circuit board and coupled to the switch chip through switch configuration traces laid in the switch circuit board.
[0019] In one possible implementation, the switch module further includes:
[0020] An external interface is fixed to the switch circuit board and coupled to the switch chip through data traces laid in the switch circuit board.
[0021] In one possible implementation, the at least two computing accelerator cards are arranged in two columns on the general-purpose substrate;
[0022] The switch module is located between the two rows of computing accelerator cards.
[0023] In one possible implementation, the at least two computing accelerator cards are located on the same side of the switch module.
[0024] In one possible implementation, the computing device further includes:
[0025] The switch module is mounted and fixed to the universal base plate via the connector.
[0026] In one possible implementation, the connector includes:
[0027] A first sub-connector is fixed to the general-purpose substrate. The first sub-connector includes a first connection terminal. The first connection terminal is coupled to the at least two computing accelerator cards through data interconnection traces laid out in the general-purpose substrate.
[0028] The second sub-connector is fixed to the switch module. The second sub-connector includes a second connection terminal, which is coupled to the switch module. The second sub-connector matches the first sub-connector. The switch module is installed and fixed to the universal base plate through the cooperation of the second sub-connector and the first sub-connector.
[0029] In one possible implementation, the central processing unit is coupled to the switch module via a switch configuration trace deployed in the general-purpose substrate.
[0030] In one possible implementation, the central processing unit and the PCIe switch module are separated by the at least two computing accelerator cards from a first arrangement area on the general-purpose substrate and a second arrangement area of the switch module on the general-purpose substrate.
[0031] In one possible implementation, the switch module is an Ethernet switch.
[0032] According to another aspect of the embodiments of this disclosure, a computing server is provided, including the computing device as described in any of the preceding claims.
[0033] As can be seen from the above scheme, the computing device and computing server disclosed herein do not adopt a pass-through interconnect structure between computing accelerator cards. Instead, all data interaction ports of all computing accelerator cards are connected to a switch module. Through the configuration of the switch module, the interconnection relationship of computing accelerator cards can be adaptively adjusted for specific computing tasks. This increases the configurability of the computing device and computing server for various computing tasks and improves the optimization capability of the data interaction topology of the computing device and computing server for computing tasks. At the same time, as needed, the one-to-one pass-through interconnect between two computing accelerator cards, which was originally achieved by a single data interaction port, can be expanded into a multi-port parallel interconnect between the two computing accelerator cards, which is achieved by multiple data interaction ports. This helps to improve the internal bandwidth between the computing accelerator cards of the computing device and computing server, helps to shorten the data interaction latency between computing accelerator cards, helps to improve the data communication rate between computing accelerator cards, and helps to maximize the overall computing efficiency of the computing architecture under various computing tasks. Attached Figure Description
[0034] Figure 1 This is a basic structural diagram of the OAM architecture in related technologies;
[0035] Figure 2 This is a schematic diagram of the OAM architecture containing OAM accelerator card pass-through interconnection in related technologies;
[0036] Figure 3 This is a schematic diagram of the structure of a computing device according to an illustrative embodiment;
[0037] Figure 4 This is a schematic diagram of the structure of a computing device based on the OAM architecture and employing embodiments of the present disclosure.
[0038] Figure 5 This is a schematic diagram of the structure of a switch module according to an illustrative embodiment;
[0039] Figure 6 This is a schematic diagram of an embodiment of a computing device applied to the OAM architecture;
[0040] Figure 7 This is a schematic diagram of another structure of a switch module according to an illustrative embodiment;
[0041] Figure 8 This is a schematic diagram illustrating the layout structure of a switch module and at least two computing accelerator cards according to an illustrative embodiment.
[0042] Figure 9 This is a schematic diagram illustrating another layout structure for the placement of a switch module and at least two computing accelerator cards, according to an illustrative embodiment.
[0043] Figure 10 This is a schematic diagram illustrating a layout structure of a switch module in an OAM architecture according to an illustrative embodiment;
[0044] Figure 11 This is a schematic diagram of a cross-sectional view of a computing device applied to an OAM architecture, as shown in an illustrative embodiment.
[0045] Figure 12 This is a schematic diagram of another embodiment of a computing device applied to an OAM architecture, shown from a cross-sectional perspective according to an illustrative embodiment;
[0046] Figure 13 This is a schematic diagram of a dual computing device connection structure applied to an OAM architecture, shown according to an illustrative embodiment.
[0047] Figure 14 This is a schematic diagram of a multi-computing device connection structure applied to an OAM architecture, shown according to an illustrative embodiment.
[0048] In the attached diagram, the component names represented by each number are as follows:
[0049] 1. General-purpose baseboard; 2. Computing accelerator card; 3. Switch module; 4. Central processing unit; 5. PCIe switch module; 21. First OAM accelerator card; 22. Second OAM accelerator card; 23. Third OAM accelerator card; 24. Fourth OAM accelerator card; 25. Fifth OAM accelerator card; 26. Sixth OAM accelerator card; 27. Seventh OAM accelerator card; 28. Eighth OAM accelerator card; 41. First central processing unit; 42. Second central processing unit; 51. First PCIe switch module. 52. Second PCIe switch module; 31. Switch circuit board; 32. Switch chip; 33. Routing configuration processor; 34. External interface; 101. First layout area; 102. Second layout area; 103. Third layout area; 6. Connector; A1. First general-purpose board; A21. First 1_1 OAM accelerator card; A22. First 1_2 OAM accelerator card; A23. First 1_3 OAM accelerator card; A24. First 1_4 OAM accelerator card; A25. First _5 OAM Accelerator Card, A26, 1_6 OAM Accelerator Card, A27, 1_7 OAM Accelerator Card, A28, 1_8 OAM Accelerator Card, A3, 1st Switch Module, A41, 1st Central Processing Unit, A42, 1st 2nd Central Processing Unit, A51, 1st PCIe Switch Module, A52, 1st 2nd PCIe Switch Module, B1, 2nd General Purpose Board, B21, 2nd OAM Accelerator Card, B22, 2nd 2nd OAM Accelerator Card, B23 B24, B25, B26, B27, B28, B29, B20, B3, B41, B42, B51, B52, B53, B54, B55, B56, B57, B28, B29, B20, B20, B21, B20, B20, B21, B20, B20, B21, B20, B20, B21, B52, B20, B20, B21 ... Detailed Implementation
[0050] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided with reference to the accompanying drawings and embodiments.
[0051] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0052] As used in the specification and claims of this disclosure, “coupled (or connected)” may refer to any direct or indirect means of connection. For example, if a first device is coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection.
[0053] Figure 1 This is a basic structural diagram of the OAM architecture in related technologies, such as... Figure 1 As shown, a standard OAM architecture includes two CPUs, two PCIe switch modules, and eight OAM accelerator cards. Each CPU interacts with four OAM accelerator cards through its corresponding PCIe switch module, and the two CPUs are directly interconnected. A CPU, a PCIe switch module, and four OAM accelerator cards form a group, and interaction between two groups is achieved through the CPU's direct interconnect. For different OAM accelerator cards within a group to interact, they need to traverse the PCIe switch modules within that group. Conversely, for different OAM accelerator cards between two groups to interact, they need to traverse the PCIe switch modules and CPUs of both groups. During data interaction, latency occurs as data passes through the PCIe switch modules and CPUs. This latency delays the overall computation time of the OAM architecture when performing complex calculations involving collaborative work between OAM accelerator cards.
[0054] To reduce latency during this data interaction process, related technologies have improved the OAM architecture by enabling direct interconnection between different OAM accelerator cards. Figure 2 This is a schematic diagram of an OAM architecture containing OAM accelerator card pass-through interconnection in related technologies. For example... Figure 2 As shown, in Figure 1 Based on the basic structure of the OAM architecture shown, each OAM accelerator card utilizes its own data exchange port to achieve a one-to-one straight-through interconnection between OAM accelerator cards. This straight-through interconnection wiring structure is fixed in the general-purpose substrate. Once the one-to-one straight-through interconnection topology between OAM accelerator cards is established, it cannot be modified. Therefore, it is impossible to specifically optimize the straight-through interconnection topology between OAM accelerator cards for all computing tasks. Furthermore, although OAM accelerator cards can interact with other OAM accelerator cards through multiple data exchange ports, considering that the OAM architecture needs to meet the needs of various computing tasks as much as possible, a compromise solution is... Figure 2As shown, any two OAM accelerator cards are interconnected one-to-one. Although this achieves full direct interconnection between OAM accelerator cards, they can only be interconnected through one data exchange port. When there is a large amount of data exchange between two OAM accelerator cards, it can easily lead to a bottleneck in data exchange, which will still affect the overall computing efficiency of the OAM architecture.
[0055] In view of this, the present disclosure provides a computing device and a computing server that no longer use a pass-through interconnect of OAM accelerator cards. Instead, all data interaction ports of all OAM accelerator cards are connected to a switch module. Through the configuration of the switch module, the interconnection relationship of OAM accelerator cards can be adaptively adjusted for specific computing tasks. This increases the configurability of the OAM architecture for various computing tasks and improves the optimization capability of the OAM architecture's data interaction topology for computing tasks. At the same time, as needed, the one-to-one pass-through interconnect between two OAM accelerator cards, which is currently implemented through a single data interaction port, can be expanded to be implemented through multiple data interaction ports. This helps to increase the internal bandwidth between the OAM accelerator cards of the computing device and the computing server, helps to shorten the data interaction latency between OAM accelerator cards, helps to increase the data communication rate between OAM accelerator cards, and helps to maximize the overall computing efficiency of the OAM architecture under various computing tasks.
[0056] Figure 3 This is a schematic diagram of the structure of a computing device according to an illustrative embodiment, such as... Figure 3 As shown, the computing device of this embodiment mainly includes a general-purpose substrate 1, computing accelerator cards 2, and a switch module 3. The number of computing accelerator cards 2 is at least two, and at least two computing accelerator cards 2 are mounted on the general-purpose substrate 1. The switch module 3 is mounted on the general-purpose substrate 1 and is coupled to the at least two computing accelerator cards 2 through data interconnect traces laid in the general-purpose substrate 1. In other words, the data interaction path between any two computing accelerator cards 2 includes the switch module 3, or the data interaction path between any two computing accelerator cards 2 passes through the switch module 3. There is no one-to-one data interconnect trace between any two computing accelerator cards 2 that does not pass through the switch module 3.
[0057] Based on the OAM architecture, in the illustrative embodiment, the computing accelerator card 2 can be an OAM accelerator card. Depending on different application needs, the computing accelerator card 2 can be any one of CPU, GPU, TPU (Tensor Processing Unit), NPU (Neural network Processing Unit), DPU (Deep learning Processing Unit), APU (Accelerated Processing Unit), and GPGPU (General-Purpose computing on Graphics Processing Unit).
[0058] In the illustrative embodiment, the data interaction ports of the computing accelerator card 2 used for connecting with other computing accelerator cards 2 are all connected to the data interconnect lines laid in the general-purpose substrate 1. That is to say, in the computing device of this embodiment, all the data interaction ports on the computing accelerator card 2 that were originally used for one-to-one direct interconnection between computing accelerator cards 2 are all connected to the switch module 3 through the data interconnect lines laid in the general-purpose substrate 1. See, for example, [link to example]. Figure 2 As shown, for each OAM accelerator card, the multiple (e.g., 7 or 8) data interaction ports that were originally used for one-to-one direct interconnection with other OAM accelerator cards are all changed to be connected to the switch module 3 through the data interconnection lines laid in the general substrate 1, and there is no longer any one-to-one direct interconnection path between any two OAM accelerator cards.
[0059] The computing device employing this embodiment connects all data interaction ports of all computing accelerator cards to a switch module via data interconnect traces laid in a universal substrate. This allows for targeted configuration of the interconnect topology between computing accelerator cards through the switch module, significantly enhancing the computing device's ability to personalize configurations for various computing tasks. This contributes to improving the overall data transmission efficiency between computing accelerator cards within the computing device, thereby improving the overall computing efficiency. Furthermore, through external interfaces further configured on the switch module, direct cross-device interconnection of computing accelerator cards can be achieved, enabling one-to-one connections between any computing accelerator card in a large computing node cluster, including multiple computing devices. This greatly expands the data interaction topology options for computing accelerator cards in large computing node clusters and enhances the cluster's optimization and adaptation capabilities for various computing tasks.
[0060] In conjunction with the OAM architecture, in an illustrative embodiment, such as Figure 3As shown, the computing device may further include a central processing unit 4 and a PCIe switch module 5. The central processing unit 4 is mounted on a general-purpose substrate 1. The PCIe switch module 5 is mounted on the general-purpose substrate 1 and coupled to at least two computing accelerator cards 2 and the central processing unit 4 via a PCIe data routing network laid out in the general-purpose substrate 1. Data exchange between the at least two computing accelerator cards 2 and the central processing unit 4 occurs through the PCIe switch module 5.
[0061] Figure 4 This is a schematic diagram of the structure of a computing device based on the OAM architecture and employing embodiments of this disclosure, as shown below. Figure 4 As shown, the OAM architecture behind the computing device in this embodiment mainly includes a general-purpose baseboard 1, OAM accelerator cards, and a switch module 3. There are eight OAM accelerator cards: a first OAM accelerator card 21, a second OAM accelerator card 22, a third OAM accelerator card 23, a fourth OAM accelerator card 24, a fifth OAM accelerator card 25, a sixth OAM accelerator card 26, a seventh OAM accelerator card 27, and an eighth OAM accelerator card 28. All eight OAM accelerator cards (21-28) are mounted on the general-purpose baseboard 1. The switch module 3 is installed on the general-purpose baseboard 1, and the switch module 3 is coupled to the first OAM accelerator card 21 to the eighth OAM accelerator card 28 through the data interconnection lines laid in the general-purpose baseboard 1. The data interaction path between any two OAM accelerator cards in the first OAM accelerator card 21 to the eighth OAM accelerator card 28 (including all cases such as between the first OAM accelerator card 21 and the second OAM accelerator card 22, and between the second OAM accelerator card 22 and the third OAM accelerator card 23) includes the switch module 3. In other words, the data interaction path between any two OAM accelerator cards in the first OAM accelerator card 21 to the eighth OAM accelerator card 28 (including all cases such as between the first OAM accelerator card 21 and the second OAM accelerator card 22, and between the second OAM accelerator card 22 and the third OAM accelerator card 23) all pass through the switch module 3. For example, the data interaction path between the first OAM accelerator card 21 and the second OAM accelerator card 22 includes the switch module 3, and the data interaction path between the second OAM accelerator card 22 and the third OAM accelerator card 23 includes the switch module 3, and so on. There is no one-to-one data interconnection between any two OAM accelerator cards that does not pass through the switch module 3, including all cases such as no one-to-one data interconnection between the first OAM accelerator card 21 and the second OAM accelerator card 22 that does not pass through the switch module 3, and no one-to-one data interconnection between the second OAM accelerator card 22 and the third OAM accelerator card 23 that does not pass through the switch module 3.
[0062] like Figure 4As shown in the illustrative embodiment, the OAM architecture includes two central processing units (CPUs) and two PCIe switch modules. The two CPUs are a first CPU 41 and a second CPU 42, and the two PCIe switch modules are a first PCIe switch module 51 and a second PCIe switch module 52. All three CPUs—CPU 41, CPU 42, PCIe switch module 51, and PCIe switch module 52—are mounted on a general-purpose substrate 1.
[0063] In an illustrative embodiment, the first PCIe switch module 51 is coupled to the first OAM accelerator card 21, the second OAM accelerator card 22, the third OAM accelerator card 23, the fourth OAM accelerator card 24, and the first central processing unit 41 via a PCIe data routing network laid out in the general-purpose substrate 1. Data exchange between the first OAM accelerator card 21, the second OAM accelerator card 22, the third OAM accelerator card 23, the fourth OAM accelerator card 24, and the first central processing unit 41 is performed through the first PCIe switch module 51; the second PCIe switch module... Block 52 is coupled to the fifth OAM accelerator card 25, the sixth OAM accelerator card 26, the seventh OAM accelerator card 27, the eighth OAM accelerator card 28 and the second central processing unit 42 through the PCIe data routing network laid in the general substrate 1. The fifth OAM accelerator card 25, the sixth OAM accelerator card 26, the seventh OAM accelerator card 27, the eighth OAM accelerator card 28 and the second central processing unit 42 exchange data through the second PCIe switch module 52; the first central processing unit 41 and the second central processing unit 42 are directly connected and interact.
[0064] Figure 5 This is a schematic diagram of the structure of a switch module according to an illustrative embodiment, such as... Figure 5 As shown, in an illustrative embodiment, the switch module 3 includes a switch circuit board 31 and a switch chip 32. Wherein, combined with... Figure 3 As shown, the switch circuit board 31 is fixed to the general-purpose board 1, and the switch chip 32 is mounted on the switch circuit board 31. It is coupled to at least two computing accelerator cards 2 via data interconnect traces routed in the switch circuit board 31 and the general-purpose board 1. The switch chip 32 is used to provide routing between the at least two computing accelerator cards 2 according to the configuration. Figure 5 The diagram omits the data interconnect wiring.
[0065] To configure routing between computing accelerator cards, such as Figure 5As shown in the illustrative embodiment, the switch module 3 may further include a routing configuration processor 33. The routing configuration processor 33 is mounted on the switch circuit board 31 and coupled to the switch chip 32 via switch configuration traces laid in the switch circuit board 31. The routing configuration processor 33 is used to configure the routing of the switch chip 32, so that the switch chip 32 can establish routes between various computing accelerator cards according to the configured routing information during operation, enabling data interaction paths between any two of the at least two computing accelerator cards to be implemented through the switch module 3.
[0066] In addition, when applied to the OAM architecture, the configuration of routing between computing accelerator cards can also be achieved using the central processing unit (CPU) in the OAM architecture. In this way, the CPU can be coupled to the switch module through the configuration wiring of the switch deployed in the general-purpose substrate. Correspondingly, the CPU is also used to configure the routing of the switch chip, so that the switch chip can establish the routing between each OAM accelerator card according to the configured routing information when it is working, so that the data interaction path between any two OAM accelerator cards can be realized through the switch module. Figure 6 This is a schematic diagram of an embodiment of a computing device applied to the OAM architecture, such as... Figure 6 And refer to Figure 5 As shown, in the illustrative embodiment, the routing configuration processor 33 may not be included in the switch module 3, and the routing configuration function of the routing configuration processor 33 can be implemented by any one or at least one of the two central processing units in the OAM architecture, for example... Figure 6 As shown, the second central processing unit 42 is coupled to the switch module 3 via a switch configuration trace deployed on the general-purpose substrate 1, and then coupled to the switch chip 32 of the switch module 3 via the switch circuit board 31 of the switch module 3. Accordingly, the second central processing unit 42 is also used to configure the routing of the switch chip 32, so that the switch chip 32 can establish routes between various OAM accelerator cards according to the configured routing information when it is working. In addition, the first central processing unit 41 can also be coupled to the switch module 3 to enable the first central processing unit 41 to configure the routing of the switch chip 32.
[0067] Based on the computing device of the present disclosure embodiments, the switch module can be further expanded to enable the switch module to interact with other devices (such as another computing device) outside the computing device to exchange computing data of the computing acceleration card, providing a hardware connection foundation for server clusters to achieve collaborative cooperation of multiple devices (equipment) to complete complex calculations. Figure 7 This is a schematic diagram illustrating another structural design of a switch module according to an exemplary embodiment. For example... Figure 7 As shown in the illustrative embodiment, in addition to the switch circuit board 31 and the switch chip 32, the switch module 3 may further include an external interface 34. The external interface 34 is fixed to the switch circuit board 31 and coupled to the switch chip 32 through data traces laid in the switch circuit board 31. Based on Figure 7 The illustrated embodiment enables data interaction between any specified data interaction port of any specified computing accelerator card in the computing device and other devices or equipment outside the computing device of this disclosure embodiment through routing configuration of the switch chip 32.
[0068] In the illustrative embodiment, when implementing the computing device of the present disclosure, the position of the switch module can be arranged according to different environmental requirements of spatial layout.
[0069] Figure 8 This is a schematic diagram illustrating the layout of a switch module and at least two compute accelerator cards according to an illustrative embodiment. Figure 8 As shown, in an illustrative embodiment, at least two computing accelerator cards 2 are arranged in two columns on a general-purpose substrate 1 (e.g., Figure 8 (As shown in the two horizontal columns), the switch module 3 is located between the two columns of computing accelerator cards 2. In this way, the distances from the two columns of computing accelerator cards 2 to the switch module 3 are equal or close, which helps to shorten the data interaction path between the individual computing accelerator cards 2 and the switch module 3 inside the computing device as a whole, and also helps to reduce the wiring complexity of the general-purpose board 1.
[0070] Figure 9 This is a schematic diagram illustrating another layout structure for the placement of a switch module and at least two compute accelerator cards, according to an illustrative embodiment. For example... Figure 9 As shown, in the illustrative embodiment, at least two computing accelerator cards 2 are located on the same side of the switch module 3. This arrangement allows the switch module 3 to be positioned near the side of the general-purpose substrate 1, which, when the switch module 3 includes external interfaces, facilitates the hardware routing layout for external connections.
[0071] When applying OAM architecture, considering the actual application scenario, it's also necessary to ensure that the switch module's location doesn't conflict with the CPU and PCIe switch modules in the OAM architecture. If the switch module is placed on the same side of at least two compute accelerator cards alongside the CPU and PCIe switch modules, it will directly affect the routing in the general-purpose board where the CPU and PCIe switch modules would be located, causing significant difficulties in the general-purpose board's wiring design. Therefore, the switch module is preferably placed in a different area from the CPU and PCIe switch modules. For example, refer to... Figure 8 The layout structure places the switch modules between two rows of compute accelerator cards. See also... Figure 10 The layout structure divides different arrangement areas on the general-purpose substrate 1, for example, dividing it into a first arrangement area 101 and a second arrangement area 102. The central processing unit and the PCIe switch module are placed in the first arrangement area 101, and the switch module 3 is placed in the second arrangement area 102. The central processing unit and the PCIe switch module in the first arrangement area 101 on the general-purpose substrate 1 and the switch module 3 in the second arrangement area 102 on the general-purpose substrate 1 are separated by at least two computing accelerator cards. Figure 10 This is a schematic diagram illustrating a layout structure of a switch module in an OAM architecture according to an illustrative embodiment. Figure 10 As shown, the general-purpose substrate 1 is divided into three arrangement areas: a first arrangement area 101, a second arrangement area 102, and a third arrangement area 103. The third arrangement area 103 is located between the first arrangement area 101 and the second arrangement area 102, with the first arrangement area 101 and the second arrangement area 102 located on opposite sides of the third arrangement area 103. The third arrangement area 103 is used to house the first OAM accelerator card 21 to the eighth OAM accelerator card 28. The first arrangement area 101 is used to house the central processing unit and the PCIe switch module (including the first central processing unit 41, the second central processing unit 42, the first PCIe switch module 51, and the second PCIe switch module 52). The second arrangement area 102 is used to house the switch module 3.
[0072] Depending on the design requirements, different connection methods can be used between the switch module and the general-purpose base plate.
[0073] Figure 11 This is a schematic diagram of a cross-sectional view of a computing device applied to an OAM architecture, shown according to an illustrative embodiment. Figure 11As shown, in the illustrative embodiment, the switch module 3 is fixed to the universal baseboard 1 by adhesive bonding or soldering. The various OAM accelerator cards, central processing unit 4, and PCIe switch module 5 belonging to the original OAM architecture can be installed on the universal baseboard 1 using their existing fixing methods. Figure 11 This fixing method facilitates the integrated production of the switch module 3 and the general-purpose substrate 1, and helps maintain high compatibility between the switch module 3 and the general-purpose substrate 1. In this case, the switch circuit board in the switch module 3 can be replaced by a portion of the general-purpose substrate 1, or the switch circuit board can be glued or soldered onto the general-purpose substrate 1.
[0074] Figure 12 This is a schematic diagram of another embodiment of a computing device applied to an OAM architecture, shown from a cross-sectional perspective, according to an illustrative embodiment. For example... Figure 12 As shown in the illustrative embodiment, the computing device of this disclosure may further include a connector 6. The switch module 3 is mounted and fixed to the universal baseboard 1 via the connector 6. The various OAM accelerator cards, central processing unit 4, and PCIe switch module 5 belonging to the original OAM architecture can be mounted on the universal baseboard 1 using the original fixing method.
[0075] In an illustrative embodiment, connector 6 may include a first sub-connector and a second sub-connector. The first sub-connector is fixed to the universal substrate 1 and includes a first connection terminal. The first connection terminal is coupled to at least two computing accelerator cards (e.g., [missing information]) via data interconnect traces laid out in the universal substrate 1. Figure 12 (OAM accelerator card shown). The second sub-connector is fixed to the switch module 3. The second sub-connector includes a second connection terminal, which is coupled to the switch module 3. The second sub-connector matches the first sub-connector. The switch module 3 is installed and fixed to the universal base plate 1 through the cooperation of the second sub-connector and the first sub-connector.
[0076] use Figure 12 The fixed method achieves decoupling between the switch module 3 and the general board 1, which helps to separate the design and production of the switch module 3 and the general board 1, and helps to reduce the difficulty of replacing the switch module 3. The switch module 3 can be disassembled and assembled on the general board 1 without the need for additional tools, which in turn helps to reduce the difficulty of maintenance and hardware modification and upgrade of the switch module 3.
[0077] To facilitate full connectivity across various topologies between at least two computing accelerator cards in a computing device and to improve data transmission bandwidth between them, the switch module in this illustrative embodiment is an Ethernet switch. Currently, OAM accelerator cards can achieve data transmission bandwidths of hundreds of Gbps (gigabits per second), and current Ethernet switches also have data transmission bandwidths in the hundreds of Gbps range. Therefore, using an Ethernet switch for the switch module fully meets the high-bandwidth data transmission requirements between OAM accelerator cards.
[0078] The computing device in this disclosure embodiment can also utilize a switch module to connect multiple computing devices together to achieve interconnection between larger-scale computing accelerator cards.
[0079] Figure 13 This is a schematic diagram illustrating a dual-computing device connection structure applied to an OAM architecture, based on an illustrative embodiment. Figure 13 As shown, the structure includes two computing devices, namely a first computing device and a second computing device, which have the same structure.
[0080] The first computing device includes a first general-purpose baseboard A1, a first-1 OAM accelerator card A21, a first-2 OAM accelerator card A22, a first-3 OAM accelerator card A23, a first-4 OAM accelerator card A24, a first-5 OAM accelerator card A25, a first-6 OAM accelerator card A26, a first-7 OAM accelerator card A27, a first-8 OAM accelerator card A28, a first-1 PCIe switch module A51, a first-2 PCIe switch module A52, a first-1 central processing unit A41, a first-2 central processing unit A42, and a first switch module A3. The 1_1 PCIe switch module A51 is coupled to the 1_1 OAM accelerator card A21, the 1_2 OAM accelerator card A22, the 1_3 OAM accelerator card A23, the 1_4 OAM accelerator card A24 and the 1_1 central processing unit A41 through the PCIe data routing network laid out in the 1st general-purpose substrate A1. The 1_2 PCIe switch module A52 is coupled to the 1_5 OAM accelerator card A25, the 1_6 OAM accelerator card A26, the 1_7 OAM accelerator card A27, the 1_8 OAM accelerator card A28 and the 1_2 central processing unit A42 through the PCIe data routing network laid out in the 1st general-purpose substrate A1. The 1_1 central processing unit A41 and the 1_2 central processing unit A42 are directly interconnected. The first switch module A3 is coupled to the first_1OAM accelerator card A21 to the first_8OAM accelerator card A28 via data interconnection traces laid in the first general-purpose baseboard A1.
[0081] The second computing device includes a second general-purpose baseboard B1, a second-1 OAM accelerator card B21, a second-2 OAM accelerator card B22, a second-3 OAM accelerator card B23, a second-4 OAM accelerator card B24, a second-5 OAM accelerator card B25, a second-6 OAM accelerator card B26, a second-7 OAM accelerator card B27, a second-8 OAM accelerator card B28, a second-1 PCIe switch module B51, a second-2 PCIe switch module B52, a second-1 central processing unit B41, a second-2 central processing unit B42, and a second switch module B3. The 2_1 PCIe switch module B51 is coupled to the 2_1 OAM accelerator card B21, the 2_2 OAM accelerator card B22, the 2_3 OAM accelerator card B23, the 2_4 OAM accelerator card B24 and the 2_1 central processing unit B41 through the PCIe data routing network laid out in the 2 general-purpose substrate B1. The 2_2 PCIe switch module B52 is coupled to the 2_5 OAM accelerator card B25, the 2_6 OAM accelerator card B26, the 2_7 OAM accelerator card B27, the 2_8 OAM accelerator card B28 and the 2_2 central processing unit B42 through the PCIe data routing network laid out in the 2 general-purpose substrate B1. The 2_1 central processing unit B41 and the 2_2 central processing unit B42 are directly interconnected. The second switch module B3 is coupled to the second_1OAM accelerator card B21 to the second_8OAM accelerator card B28 via data interconnection traces laid in the second general-purpose baseboard B1.
[0082] exist Figure 13 In the illustrated embodiment, the two computing devices are connected via their respective switch modules; specifically, the first computing device and the second computing device are connected via first switch module A3 and second switch module B3. Thus, by configuring the routing of first switch module A3 and second switch module B3, an on-demand interconnection topology can be achieved between the 16 OAM accelerator cards (first OAM accelerator card A21 to first OAM accelerator card A28 and second OAM accelerator card B21 to second OAM accelerator card B28) in the first and second computing devices.
[0083] Figure 14 This is a schematic diagram illustrating a multi-computing device connection structure applied to an OAM architecture, based on an illustrative embodiment. Figure 14 As shown, this structure includes N computing devices, where N ≥ 3. The structures of each computing device are identical, and can be found in the descriptions of the embodiments above. Specific structural descriptions will not be repeated here. Because the number of N computing devices exceeds two, Figure 14 In a preferred embodiment, an external switch device 300 is also included in addition to the N computing devices.
[0084] exist Figure 14 In the illustrated embodiment, the N computing devices are connected to each other via their respective switch modules 3 and external switch devices 300; that is, the switch modules 3 of each computing device are all connected to the switch device 300. Thus, by configuring the routing of the switch modules 3 and switch devices 300 in the N computing devices, an on-demand interconnection topology for 8×N OAM accelerator cards in the N computing devices can be achieved. In the illustrative embodiment, the switch modules 3 in the N computing devices are Ethernet switch modules 3, and the switch device 300 is an Ethernet switch device 300.
[0085] In an illustrative embodiment, a computing server is also provided, including a computing device as described in any of the preceding embodiments.
[0086] The computing device and computing server in this embodiment do not employ a pass-through interconnect structure between computing accelerator cards. Instead, all data interaction ports of all computing accelerator cards are connected to a single switch module. Through the configuration of the switch module, the interconnection relationship of the computing accelerator cards can be adaptively adjusted for specific computing tasks. This increases the configurability of the computing device and computing server for various computing tasks and enhances the optimization capability of the data interaction topology of the computing device and computing server for computing tasks. Furthermore, as needed, the one-to-one pass-through interconnect between two computing accelerator cards, which was originally implemented by a single data interaction port, can be expanded into a multi-port parallel interconnect between the two computing accelerator cards, which is implemented by multiple data interaction ports. This helps to improve the internal bandwidth between the computing accelerator cards of the computing device and computing server, shorten the data interaction latency between computing accelerator cards, improve the data communication rate between computing accelerator cards, and maximize the overall computing efficiency of the computing architecture under various computing tasks.
[0087] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A computing device, characterized in that, include: Universal substrate; At least two computing accelerator cards are mounted on the universal baseboard; A switch module is installed on the general-purpose baseboard and coupled to the at least two computing accelerator cards through data interconnection traces laid in the general-purpose baseboard. The data interaction path between any two computing accelerator cards includes the switch module, and there is no one-to-one data interconnection trace between any two computing accelerator cards that does not pass through the switch module. The computing device further includes: The central processing unit is mounted on the general-purpose substrate; The PCIe switch module is installed on the general-purpose baseboard and is coupled to the at least two computing accelerator cards and the central processing unit through the PCIe data routing network laid out in the general-purpose baseboard. The at least two computing accelerator cards and the central processing unit exchange data through the PCIe switch module.
2. The computing device according to claim 1, characterized in that, The switch module includes: A switch circuit board, wherein the switch circuit board is fixed to the general-purpose board; A switch chip is mounted on the switch circuit board and coupled to the at least two computing accelerator cards via data interconnect traces arranged in the switch circuit board and the general-purpose board.
3. The computing device according to claim 2, characterized in that, The switch module also includes: A routing configuration processor is installed on the switch circuit board and coupled to the switch chip through switch configuration traces laid in the switch circuit board.
4. The computing device according to claim 2, characterized in that, The switch module also includes: An external interface is fixed to the switch circuit board and coupled to the switch chip through data traces laid in the switch circuit board.
5. The computing device according to claim 1, characterized in that: The at least two computing accelerator cards are arranged in two columns on the general-purpose substrate; The switch module is located between the two rows of computing accelerator cards.
6. The computing device according to claim 1, characterized in that: The at least two computing accelerator cards are located on the same side of the switch module.
7. The computing device according to claim 1, characterized in that, The computing device further includes: The switch module is mounted and fixed to the universal base plate via the connector.
8. The computing device according to claim 7, characterized in that, The connector includes: A first sub-connector is fixed to the general-purpose substrate. The first sub-connector includes a first connection terminal. The first connection terminal is coupled to the at least two computing accelerator cards through data interconnection traces laid out in the general-purpose substrate. The second sub-connector is fixed to the switch module. The second sub-connector includes a second connection terminal, which is coupled to the switch module. The second sub-connector matches the first sub-connector. The switch module is installed and fixed to the universal base plate through the cooperation of the second sub-connector and the first sub-connector.
9. The computing device according to claim 1, characterized in that: The central processing unit is coupled to the switch module via a switch configuration wiring deployed in the general-purpose substrate.
10. The computing device according to claim 1, characterized in that: The central processing unit and the PCIe switch module are separated by the at least two computing accelerator cards between the first arrangement area of the switch module on the general-purpose substrate and the second arrangement area of the switch module on the general-purpose substrate.
11. The computing device according to claim 1, characterized in that: The switch module is an Ethernet switch.
12. A computing server, characterized in that, Includes the computing device as described in any one of claims 1 to 11.