Pre-charging circuit for non-volatile two-terminal memory and related product
By employing a precharge voltage generation module and a precharge module with a precharge circuit in a non-volatile two-terminal memory, bidirectional precharge of the target bit line is achieved, solving the problem of extended data read time and improving data read speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- INNOSTAR SEMICON (SHANGHAI) CO LTD
- Filing Date
- 2025-04-30
- Publication Date
- 2026-04-17
AI Technical Summary
The data read time of non-volatile two-terminal memory is affected by parasitic effects, which leads to a longer precharge time. Especially in the era of big data, when massive data is stored and read, the parasitic capacitance and parasitic resistance increase, which further prolongs the data read time.
A pre-charge circuit, including a pre-charge voltage generation module and a pre-charge module, is adopted. By simultaneously applying a pre-charge voltage to the first and second ends of the target bit line, bidirectional pre-charge of the non-volatile two-terminal memory is achieved, thereby shortening the pre-charge time.
It effectively shortens the precharge time of non-volatile end-to-end memory and improves data reading speed.
Smart Images
Figure CN224137908U_ABST
Abstract
Description
Technical Field
[0001] This application generally relates to the semiconductor field. More specifically, this application relates to a precharge circuit for a non-volatile two-terminal memory and related products. Background Technology
[0002] Non-volatile dual-end memory, such as resistive random access memory (RRAM), is a type of storage element that retains data even after power is off, and is therefore widely used for data storage. A non-volatile dual-end memory consists of multiple non-volatile dual-end memory cells. Data is typically read from a non-volatile dual-end memory by measuring the resistance value of the target non-volatile dual-end memory cell. Traditional non-volatile dual-end memory readout circuits use a current source to convert the RRAM's resistance value into a voltage, and then compare the voltage of the target non-volatile dual-end memory cell with a set reference voltage to obtain the data from the target non-volatile dual-end memory cell.
[0003] However, the data read time of non-volatile two-ended memory (NVHM) is affected by parasitic effects (additional electrical characteristics introduced by semiconductor materials, structural layout, or manufacturing processes, such as resistance, capacitance, and inductance, referred to as parasitic resistance, parasitic capacitance, and parasitic inductance for the sake of description). This means that before reading data, the NDHM needs to be pre-charged, and the presence of parasitic capacitance and resistance increases the pre-charge time. Furthermore, with the continuous development of the big data era, massive amounts of data need to be stored and retrieved. Therefore, the scale of NDHM will continue to expand, and the required circuit traces will become longer, leading to an increase in parasitic capacitance and resistance. This results in a longer pre-charge stage before the pre-charge voltage is reached during data reading, further extending the data read time.
[0004] In view of this, there is an urgent need to provide a precharge scheme for non-volatile end-to-end memory that can effectively shorten the precharge time of the memory and thus improve the data read speed of the memory. Utility Model Content
[0005] In order to at least solve one or more of the technical problems mentioned above, this application proposes a precharge circuit and related products for non-volatile end-to-end memory in several aspects.
[0006] In a first aspect, this application provides a precharge circuit for a non-volatile two-way memory, the non-volatile two-way memory comprising a memory array consisting of M*N non-volatile two-way memory units; each non-volatile two-way memory unit comprises: a non-volatile two-way memory cell and a switching device connected to the non-volatile two-way memory cell; in the memory array, each column of non-volatile two-way memory units is connected to the same bit line, where M and N are both integers greater than or equal to 1; the precharge circuit comprises: a precharge voltage generation module and a precharge module; the precharge voltage generation module is configured to generate a precharge voltage in response to a received precharge signal; an input terminal of the precharge module is connected to the precharge voltage generation module; a first output terminal of the precharge module is connected to a first end of each bit line in the memory array; a second output terminal of the precharge module is connected to a second end of each bit line in the memory array; the precharge module is configured to apply the precharge voltage to a target bit line through a first end and a second end of the target bit line in response to the precharge signal.
[0007] In some embodiments, the pre-charging module includes: M first switching units and M second switching units; wherein, the M first switching units correspond one-to-one with M bit lines, and the M second switching units correspond one-to-one with M bit lines; the output terminal of each first switching unit is connected to the first end of its corresponding bit line; the output terminal of each second switching unit is connected to the second end of its corresponding bit line; the first switching unit and the second switching unit connected at both ends of each bit line are used to control the on / off state of the bit line.
[0008] In some embodiments, the first output terminal of the pre-charge module is the output terminal of each first switch unit, and the second output terminal is the output terminal of each second switch unit; the pre-charge module is configured to, in response to the pre-charge signal, open the first target switch unit and the second target switch unit connected at both ends of the target bit line to make the target bit line conduct, and apply the pre-charge voltage to the target bit line through the first end and the second end of the target bit line.
[0009] In some embodiments, the first switching section is implemented by an N-type MOSFET or a P-type MOSFET; the second switching section is implemented by an N-type MOSFET or a P-type MOSFET.
[0010] In some embodiments, the pre-charging module further includes: a third switch section configured to control the on / off state of the pre-charging circuit; the input terminal of the pre-charging module is the first terminal of the third switch section; the number of the third switch sections is one; the first terminal of the third switch section is connected to the pre-charging voltage generation module, and the second terminal of the third switch section is connected to the input terminals of each first switch section and each second switch section respectively.
[0011] In some embodiments, the pre-charging module further includes: a third switch section configured to control the on / off state of the pre-charging circuit, wherein the input terminal of the pre-charging module is the first terminal of the third switch section; the number of third switches section is two; the first terminals of both third switches section are connected to the pre-charging voltage generation module; the second terminal of one third switch section is connected to the input terminal of each first switch section; and the second terminal of the other third switch section is connected to the input terminal of each second switch section.
[0012] In some embodiments, the third switching section is implemented by an N-type MOS transistor or a P-type MOS transistor.
[0013] In some embodiments, the non-volatile end-to-end memory further includes a control module configured to receive an external read enable signal and generate a precharge signal based on the read enable signal.
[0014] In some embodiments, the non-volatile two-ended memory further includes: a readout circuit connected to the input terminal of each first switch or the input terminal of each second switch; the readout circuit is configured to read data from the target non-volatile two-ended memory cell on the target bit line when the target bit line is turned on.
[0015] In some embodiments, the non-volatile dual-ended memory unit includes at least one of: RRAM unit, FeRAM unit, PCRAM unit, MRAM unit, and MTJ unit.
[0016] In some embodiments, when the non-volatile two-terminal memory cell is a unipolar memory cell, the precharge voltage is less than the absolute value of the set voltage of the non-volatile two-terminal memory cell and less than the absolute value of the reset voltage of the non-volatile two-terminal memory cell; when the non-volatile two-terminal memory cell is a bipolar memory cell, the precharge voltage is between the set voltage of the non-volatile two-terminal memory cell and the reset voltage of the non-volatile two-terminal memory cell.
[0017] In a second aspect, this application provides a non-volatile two-end memory, the non-volatile two-end memory including a pre-charge circuit for the non-volatile two-end memory as described in the first aspect or any of the embodiments of the first aspect.
[0018] In a third aspect, this application provides an electronic device comprising a precharge circuit for a non-volatile two-terminal memory as described in the first aspect or any embodiments thereof, or a non-volatile two-terminal memory as described in the second aspect.
[0019] The precharge circuit and related products for non-volatile two-way memory provided above, in this application embodiment, include a precharge voltage generation module and a precharge module. The input terminal of the precharge module is connected to the precharge voltage generation module, the first output terminal of the precharge module is connected to the first end of each bit line in the memory array, and the second output terminal of the precharge module is connected to the second end of each bit line in the memory array. When precharging the target bit line, a precharge voltage is applied to the target bit line simultaneously through the first and second ends of the target bit line to achieve bidirectional precharging of the non-volatile two-way memory, effectively shortening the precharge time of the non-volatile two-way memory and thereby improving the data reading speed of the non-volatile two-way memory. Attached Figure Description
[0020] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein:
[0021] Figure 1 Precharge circuitry for a non-volatile end-to-end memory according to some embodiments of this application is shown;
[0022] Figure 2 The diagram shows an example of the structure of a non-volatile dual-ended memory according to some embodiments of this application;
[0023] Figure 3A The diagram illustrates the switching characteristics of a unipolar non-volatile two-ended memory cell according to some embodiments of this application;
[0024] Figure 3B The following diagram illustrates the switching characteristics of a bipolar non-volatile two-ended memory cell according to some embodiments of this application;
[0025] Figure 4 A schematic diagram of a pre-charging circuit including a first switching section and a second switching section, according to some embodiments of this application, is shown.
[0026] Figure 5A A schematic diagram of a pre-charging circuit including a third switching section is shown for some embodiments of this application;
[0027] Figure 5B A schematic diagram of a pre-charging circuit including two third switching sections is shown for some embodiments of this application;
[0028] Figure 6 An exemplary flowchart of a pre-charge method for a non-volatile end-to-end memory according to some embodiments of this application is shown;
[0029] Figure 7 An exemplary flowchart of a data readout method for a non-volatile end-to-end memory according to some embodiments of this application is shown.
[0030] Figure description: First switch section 1210; Second switch section 1220; Third switch section 1230. Detailed Implementation
[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0032] It should be understood that the terms "comprising" and "including" as used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0033] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this specification and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.
[0034] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."
[0035] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0036] Figure 1 A precharge circuit 100 for a non-volatile end-to-end memory is shown according to some embodiments of this application.
[0037] In this embodiment, the aforementioned non-volatile two-terminal memory is a storage device that reads and writes data through both ends (e.g., top electrode and bottom electrode), and can still retain data after power failure. Compared with traditional volatile memory, it does not require power to maintain the stored data, and the data retention is more durable.
[0038] In the embodiments of this application, such as Figure 2 As shown, the non-volatile two-ended memory includes a row decoding module, a column decoding / column gating module, a write driver module, and a read circuit (i.e., ...). Figure 2 The system consists of a sensitive amplification module and an M*N non-volatile end-to-end storage array. The storage array is an M x N matrix structure, where M and N are both integers greater than or equal to 1. Figure 2 The fact that M and N are both 1023 is merely an example and is not intended to limit this application. The aforementioned non-volatile two-ended storage unit, as a basic unit of non-volatile two-ended memory, includes a non-volatile two-ended storage cell and a switching device connected in series with the non-volatile two-ended storage cell; wherein, the non-volatile two-ended storage cell is used for actual data storage, and the switching device is used to control access to the non-volatile two-ended storage cell connected to it, for example, by turning on or off the corresponding path during read / write operations.
[0039] In the embodiments of this application, the aforementioned non-volatile two-terminal storage unit may include at least one of resistive random access memory (RRAM) unit, ferroelectric random access memory (FeRAM) unit, phase change random access memory (PCRAM) unit, magnetoresistive random access memory (MRAM) unit, and magnetic tunnel junction (MTJ) unit.
[0040] The aforementioned Resistive Random Access Memory (RRAM) cells refer to storage units that utilize changes in the resistance of a material to store data. By applying different voltages, they switch between high-resistance and low-resistance states, thus representing different data information. Ferroelectric Random Access Memory (FeRAM) cells store data based on the polarization characteristics of ferroelectric materials. Ferroelectric materials can polarize under the influence of an electric field, and this characteristic is used to preserve data states. Phase-Change Random Access Memory (PCRAM) cells rely on the phase transition between crystalline and amorphous states of the material to achieve data storage. Different phase states have different electrical characteristics, which are used to distinguish data. Magnetoresistive Random Access Memory (MRAM) cells utilize the magnetoresistive effect of magnetic materials to store data; that is, different magnetization directions cause changes in resistance, and data can be read by detecting the resistance value. Magnetic Tunnel Junction (MTJ) cells are a special type of magnetoresistive storage structure, consisting of two layers of magnetic material sandwiching a thin insulating layer. They exhibit different resistance states through the electron tunneling effect and the relationship between magnetization directions to store data.
[0041] In the embodiments of this application, the switching device can be implemented in many ways, such as a transistor, a two-terminal selector, etc. Here, the transistor can be a P-type MOS transistor or an N-type MOS transistor. This application does not specifically limit this implementation. Based on the above description, when the switching device is a MOS transistor, the memory architecture of the non-volatile two-terminal memory section is 1T1R (i.e., one non-volatile two-terminal memory cell connected in series with one transistor); when the switching device is a two-terminal selector, the memory architecture of the non-volatile two-terminal memory section is 1S1R (i.e., one non-volatile two-terminal memory cell connected in series with one two-terminal selector).
[0042] In the embodiments of this application, in the above-described storage array, the non-volatile two-end storage units of each column are connected to the same bit line (BL). For the non-volatile two-end storage units on each column of non-volatile two-end storage units, data can be transmitted between the non-volatile two-end storage units on the bit line and the peripheral circuit (e.g., the readout circuit described in the following embodiments).
[0043] In this embodiment, when the switching device is a MOSFET, in the aforementioned memory array, in addition to each column's non-volatile two-sided memory being connected to the same bit line, each row's non-volatile two-sided memory also needs to be connected to the same word line (WL). Here, the word line is used to select the non-volatile two-sided memory of a specific row. When the word line is activated, all non-volatile two-sided memory in that row are in an operable state for data reading and writing. Based on the above description, the number of bit lines in this embodiment is M, and the number of word lines is N.
[0044] It should be noted that the connections involved in the above-mentioned storage arrays refer to the establishment of electrical connections between the non-volatile storage units at both ends and the bit lines or word lines through physical connection methods such as wires and circuits, so that data can be transmitted between them and the functions of storage and retrieval can be realized.
[0045] The row decoding module is used to select the corresponding word line based on the received address signal to activate the non-volatile two-end memory cell of the target row; the column decoding / column gating module is used to select the corresponding bit line based on the received address signal to activate the non-volatile two-end memory cell of the target column, and works with the row decoding module to determine the target non-volatile two-end memory cell.
[0046] During data writing, the write driver module drives the input data (Din) through the selected bit line (denoted as the target bit line) to the target non-volatile memory cells at both ends. During data reading, the readout circuit (sensitive amplification module) detects and amplifies the signal on the target bit line to output the final readout data.
[0047] like Figure 1As shown, the pre-charge circuit 100 includes a pre-charge voltage generation module 110 and a pre-charge module 120; wherein, the pre-charge voltage generation module 110 is configured to generate a pre-charge voltage in response to a received pre-charge signal; the input terminal of the pre-charge module 120 is connected to the pre-charge voltage generation module 110; the first output terminal of the pre-charge module is connected to the first end of each bit line in the memory array; the second output terminal of the pre-charge module 120 is connected to the second end of each bit line in the memory array; the pre-charge module 120 is configured to apply a pre-charge voltage to the target bit line through the first and second ends of the target bit line in response to the pre-charge signal.
[0048] For example, in this embodiment of the application, the pre-charge voltage generation module 110 functions to generate the voltage required for pre-charging. Specifically, when a pre-charge signal (e.g., a high-level enable signal) is received, a pre-charge voltage is generated in response to the pre-charge signal. The pre-charge signal here may be issued by the control module of the non-volatile dual-ended memory (described as an example in the following embodiments).
[0049] The precharge voltage requirements differ for different non-volatile two-terminal memory cells, as detailed below:
[0050] When a non-volatile two-terminal memory cell is a unipolar memory cell, the precharge voltage is less than the absolute value of the set voltage (Vset) and the absolute value of the reset voltage (Vreset) of the non-volatile two-terminal memory cell. Here, a unipolar memory cell refers to a non-volatile two-terminal memory cell that only has a positive magnetization or high-potential state to represent data, without a negative magnetization or low-potential state. A bipolar memory cell has two stable states; for example, positive magnetization represents "1", negative magnetization represents "0", or high and low potentials represent different data. The set voltage (Vset) refers to the minimum voltage required to switch a non-volatile two-terminal memory cell from a high-resistance state to a low-resistance state, and the reset voltage (Vreset) refers to the minimum voltage required to switch a non-volatile two-terminal memory cell from a low-resistance state to a high-resistance state.
[0051] For example, such as Figure 3A As shown, Figure 3A The non-volatile two-terminal memory cell in the memory is a unipolar memory cell with a reset voltage of 0.8V and a set voltage of 1.4V. Therefore, the precharge voltage should be less than the set voltage of 1.4V and also less than the reset voltage of 0.8V. For example, it can be 0.7V.
[0052] When the non-volatile two-terminal memory cell is a bipolar memory cell, the precharge voltage is between the set voltage of the non-volatile two-terminal memory cell and the reset voltage of the non-volatile two-terminal memory cell.
[0053] For example, such as Figure 3B As shown, Figure 3B The non-volatile two-terminal memory cell in the memory is a bipolar memory cell. Its reset voltage is, for example, -1.5V and its set voltage is 2V. Then the precharge voltage should be between the reset voltage -1.5V and the set voltage 2V, for example, it can be 1V.
[0054] This application embodiment sets requirements for the pre-charge voltage of unipolar and bipolar memory cells. Specifically, when the non-volatile two-terminal memory cell is a unipolar cell, the pre-charge voltage is less than the absolute value of the set voltage and the absolute value of the reset voltage of the non-volatile two-terminal memory cell. When the non-volatile two-terminal memory cell is a bipolar cell, the pre-charge voltage is between the set voltage and the reset voltage of the non-volatile two-terminal memory cell. This avoids erroneous changes to the storage state of the non-volatile two-terminal memory cell during pre-charging. If the pre-charge voltage is too high, reaching or exceeding the set or reset voltage, it could alter the state of the non-volatile two-terminal memory cell, thereby corrupting the originally stored data. Therefore, this setting is to ensure data integrity and accuracy, ensuring that the pre-charge operation only prepares the bit lines and does not interfere with the data state of the non-volatile two-terminal memory cell.
[0055] For example, in this embodiment of the application, the input terminal of the pre-charge module 120 is connected to the pre-charge voltage generation module 110; the first output terminal of the pre-charge module 120 is connected to the first end of each bit line in the memory array; and the second output terminal of the pre-charge module 120 is connected to the second end of each bit line in the memory array. Here, "connection" refers to a physical connection via wires, circuits, or other means.
[0056] Based on the description of the pre-charge circuit 100 above, the pre-charge module 120 is configured to apply a pre-charge voltage to the target bit line through the first and second terminals of the target bit line in response to a pre-charge signal. Here, the target bit line refers to the bit line for which pre-charge operation is currently required. In this embodiment, when pre-charging is performed by simultaneously applying a pre-charge voltage to the target bit line through the first and second terminals, the application of the pre-charge voltage can be stopped when a set time is reached, or the application of the pre-charge voltage can be stopped when the voltage of the target bit line is detected to be the aforementioned pre-charge voltage, thereby completing the pre-charge process.
[0057] The pre-charge circuit of this application embodiment includes a pre-charge voltage generation module and a pre-charge module. The input terminal of the pre-charge module is connected to the pre-charge voltage generation module, the first output terminal of the pre-charge module is connected to the first end of each bit line in the memory array, and the second output terminal of the pre-charge module is connected to the second end of each bit line in the memory array. When pre-charging the target bit line, a pre-charge voltage is applied to the target bit line simultaneously through the first and second ends of the target bit line to achieve bidirectional pre-charging, which effectively shortens the pre-charge time of the non-volatile two-ended memory and thus improves the data reading speed of the non-volatile two-ended memory.
[0058] The specific structure of the pre-charge module 120 is described below:
[0059] As an optional embodiment of this application, such as Figure 4 As shown, the pre-charging module 120 includes M first switching units 1210 and M second switching units 1220; wherein, the M first switching units 1210 correspond one-to-one with the M bit lines, and the M second switching units 1220 correspond one-to-one with the M bit lines; the output terminal of each first switching unit 1210 is connected to the first end of its corresponding bit line; the output terminal of each second switching unit 1220 is connected to the second end of its corresponding bit line; the first switching unit 1210 and the second switching unit 1220 connected at both ends of each bit line are used to control the on / off state of the bit line.
[0060] For example, in the embodiments of this application, the first switch portion 1210 and the second switch portion 1220 are switching components in the pre-charge module 120. The first switch portion 1210 can be implemented using an N-type MOSFET or a P-type MOSFET; the second switch portion 1220 can also be implemented using an N-type MOSFET or a P-type MOSFET. The embodiments of this application do not specifically limit the implementation method of the first switch portion 1210 and the second switch portion 1220.
[0061] In the embodiments of this application, the output terminal of each first switch section 1210 is connected to the first end of its corresponding bit line; the output terminal of each second switch section 1220 is connected to the second end of its corresponding bit line, that is, each bit line is connected to a switch section (i.e., the first switch section 1210 and the second switch section 1220) at both ends, and the first switch section 1210 and the second switch section 1220 connected to the two ends of each bit line are used to control the on / off state of the bit line.
[0062] As an optional embodiment of this application, the first output terminal of the pre-charge module 120 is the output terminal of each first switch 1210, and the second output terminal is the output terminal of each second switch 1220; the pre-charge module 120 is configured to, in response to a pre-charge signal, open the first target switch and the second target switch connected at both ends of the target bit line to make the target bit line conduct, and apply a pre-charge voltage to the target bit line through the first end and the second end of the target bit line.
[0063] For example, in this embodiment of the application, the pre-charge module 120 parses the target bit line from the pre-charge signal. For instance, if the i-th bit line needs to be pre-charged, the first target switch and the second target switch connected to both ends of the i-th bit line are turned on, while the first switch 1210 and the second switch 1220 connected to both ends of the remaining bit lines remain off to avoid voltage interference. Further, a pre-charge voltage is applied to the target bit line through its first and second ends to rapidly raise the voltage of the target bit line to the pre-charge voltage.
[0064] In a specific implementation, one non-gate terminal (e.g., drain or source terminal) of each first switch section 1210 is connected to the first end of its corresponding bit line, and the other non-gate terminal is connected to the pre-charge voltage generation module. One non-gate terminal (e.g., drain or source terminal) of each second switch section 1220 is connected to the second end of its corresponding bit line, and the other non-gate terminal is connected to the pre-charge voltage generation module. When a pre-charge signal is received, the gate terminals of the first target switch section and the second target switch section are activated, and the pre-charge voltage generation module 110 simultaneously applies a pre-charge voltage to the target bit line through the first and second target switch sections.
[0065] In the embodiments of this application, such as Figure 5A and Figure 5B As shown, the pre-charging module 120 may also be further provided with a third switch 1230 for controlling the on / off state of the pre-charging circuit. The number of third switch 1230 may be one or two, and this embodiment does not specifically limit the number. The two cases are described in detail below.
[0066] As an optional embodiment of this application, when the number of third switch sections 1230 is one, such as Figure 5A As shown, the pre-charge module 120 further includes: a third switch section 1230, which is configured to control the on / off state of the pre-charge circuit; the input terminal of the pre-charge module is the first terminal of the third switch section 1230; the first terminal of the third switch section 1230 is connected to the pre-charge voltage generation module 110, and the second terminal of the third switch section 1230 is connected to the input terminals of each first switch section 1210 and each second switch section 1220, respectively.
[0067] For example, in this embodiment, the third switch 1230 serves as the master switch for pre-charging, used to control the on / off state of the pre-charging circuit. The third switch 1230 can be implemented using an N-type MOSFET or a P-type MOSFET; this embodiment does not specifically limit its implementation.
[0068] Based on the above description, the input terminal of the pre-charge module 120 is the first terminal of the third switch section 1230. Here, the first terminal refers to a non-gate terminal, such as the source or drain terminal; this embodiment does not specifically limit this. When the first terminal of the third switch section 1230 is the source terminal, the second terminal of the third switch section 1230 is the drain terminal. Conversely, when the first terminal of the third switch section 1230 is the drain terminal, the second terminal of the third switch section 1230 is the source terminal.
[0069] In specific implementation, when no pre-charge signal is received, the third switch 1230 is in the open state, cutting off the connection between the charging voltage generation module 110 and the first switch 1210 and the second switch 1220 connected to both ends of all bit lines to avoid the influence of leakage current; when a pre-charge signal is received, the third switch 1230 is controlled to open, allowing the pre-charge voltage generated by the pre-charge generation module 110 to be transmitted to each first switch 1210 and each second switch 1220, and then the pre-charge voltage is applied to the target bit line through the first target switch and the second target switch connected to both ends of the target bit line.
[0070] The embodiments of this application, by setting a master control third switch, make the pre-charging circuit simple in structure, small in area, and low in power consumption.
[0071] As another optional embodiment of this application, when the number of third switch units is two, such as Figure 5B As shown, the pre-charge module 120 further includes: a third switch section 1230, which is configured to control the on / off state of the pre-charge circuit 100, and the input terminal of the pre-charge module 120 is the first terminal of the third switch section 1230; the first terminals of both third switch sections 1230 are connected to the pre-charge voltage generation module 110; the second terminal of one third switch section 1230 is connected to the input terminal of each first switch section 1210; and the second terminal of the other third switch section 1230 is connected to the input terminal of each second switch section 1220.
[0072] For example, in the embodiments of this application, the two third switch units 1230 are used to control the on / off state of the pre-charge circuit between the pre-charge voltage generation module 110 and the first switch unit 1210, and the on / off state of the pre-charge circuit between the pre-charge voltage generation module 110 and the second switch unit 1220, respectively. Both third switch units 1230 can be implemented using N-type MOSFETs or P-type MOSFETs; this embodiment of the application does not specifically limit their implementation.
[0073] Based on the above description, the input terminal of the pre-charge module 120 is the first terminal of each of the third switch sections 1230. Here, the first terminal refers to a non-gate terminal, such as the source terminal or the drain terminal, which is not specifically limited in this embodiment. When the first terminal of the third switch section 1230 is the source terminal, the second terminal of the third switch section 1230 is the drain terminal. When the first terminal of the third switch section 1230 is the drain terminal, the second terminal of the third switch section 1230 is the source terminal.
[0074] In specific implementation, when no pre-charge signal is received, both third switch sections 1230 are in an open state, disconnecting the charging voltage generation module 110 from the first switch sections 1210 and second switch sections 1220 connected to both ends of all bit lines. When a pre-charge signal is received, the two third switch sections 1230 can be controlled to open, allowing the pre-charge voltage generated by the pre-charge generation module 110 to be transmitted to each of the first switch sections 1210 and each of the second switch sections 1220, and then the pre-charge voltage is applied to the target bit line through the first target switch section and the second target switch section connected to both ends of the target bit line. When controlling the two third switch sections 1230 to open, both third switch sections 1230 can be controlled to open simultaneously, or one of the third switch sections 1230 can be opened first, and then the other third switch section 1230 can be opened. This application embodiment does not specifically limit this.
[0075] based on Figure 5B As shown in the example diagram, the number of pre-charge voltage generation modules 110 can also be two, with one pre-charge voltage generation module 110 connected to one of the third switch units 1230, and the other pre-charge voltage generation module 110 connected to the other third switch unit 1230.
[0076] This application embodiment uses two third switching units to control the on / off state between the pre-charge voltage generation module and the first switching unit, as well as between the pre-charge voltage generation module and the second switching unit, respectively, so that the pre-charge circuit supports asynchronous control and has greater flexibility.
[0077] As an optional embodiment of this application, the non-volatile end-to-end memory further includes a control module configured to receive an external read enable signal and generate a precharge signal based on the read enable signal.
[0078] For example, in this embodiment, the control module is a functional module of the non-volatile dual-ended memory (NDM). It receives an external signal (i.e., the read enable signal) and generates a corresponding control signal (i.e., a pre-charge signal) according to preset logic, triggering a pre-charge phase. The pre-charge signal is transmitted to the pre-charge voltage generation module 110 and the pre-charge module 120. After pre-charging is complete, a data readout phase is triggered to control the subsequent readout circuit to read data. Here, the read enable signal refers to an externally input read trigger signal used to read data from the NDM. When the NDM receives the read enable signal, it means that data reading is required, thus triggering a corresponding pre-charge operation to prepare for data reading.
[0079] As an optional embodiment of this application, it is also as follows Figure 2 As shown, the non-volatile two-ended memory further includes: a readout circuit, which is connected to the input terminal of each first switch or the input terminal of each second switch; the readout circuit is configured to read data from the target non-volatile two-ended memory cell on the target bit line when the target bit line is turned on.
[0080] Exemplarily, in this embodiment, the aforementioned readout circuit refers to a circuit that reads data from a non-volatile two-terminal memory cell. It is capable of sensing changes in the electrical characteristics of the non-volatile two-terminal memory cell and converting them into recognizable digital signals for subsequent data processing and transmission. In this embodiment, the readout circuit is typically composed of a sense amplifier to detect changes in bit line current / voltage. In this embodiment, the readout circuit is connected to the input terminals of either the first or second switches. This embodiment only describes the connection of the readout circuit to the input terminal of the second switch as an example. In specific implementation, after pre-charging is complete, the control module closes the third switch 1230 to cut off the input of the pre-charging voltage, and simultaneously controls the opening of the target switch connected to the target non-volatile two-terminal memory cell. Data is read from the target non-volatile two-terminal memory cell by detecting changes in current or voltage.
[0081] In addition, in some embodiments, this application also provides a non-volatile dual-ended memory, which includes a pre-charge circuit for the non-volatile dual-ended memory as described in the above embodiments, to optimize the data read operations of the non-volatile dual-ended memory and improve its storage performance. The description of this non-volatile dual-ended memory is the same as that in the above embodiments.
[0082] In addition, in some embodiments, this application also provides an electronic device, which includes a pre-charge circuit for non-volatile dual-ended memory as described in the above embodiments, or a non-volatile dual-ended memory as described above. This allows the advantages of the pre-charge circuit to be utilized during the operation of the electronic device to improve the efficiency and stability of data reading operations, thereby enhancing the performance of the electronic device and making it more reliable and efficient during use. Here, "electronic device" refers to a device that uses non-volatile dual-ended memory for storage, which can be of many types, such as smartphones, tablets, laptops, desktop computers, servers, smartwatches, smart bracelets, dashcams, digital cameras, solid-state drives, etc.
[0083] Figure 6 An exemplary flowchart of a precharge method 600 for a non-volatile end-to-end memory according to some embodiments of this application is shown.
[0084] like Figure 6 As shown, the precharge method 600 for non-volatile two-terminal memory is applied to the precharge circuit for non-volatile two-terminal memory as described in the above embodiment. The precharge method 600 includes: step S610: generating a precharge voltage based on a received precharge signal; step S620: applying the precharge voltage to the target bit line through the first and second ends of the target bit line based on the precharge signal.
[0085] For example, based on the above description of the precharge circuit for a non-volatile dual-ended memory, after the control module of the non-volatile dual-ended memory receives an externally input read enable signal, it generates a precharge signal and transmits it to the precharge voltage generation module and the precharge module of the precharge circuit for the non-volatile dual-ended memory. The precharge voltage generation module generates a precharge voltage based on the received precharge signal. The precharge module parses the address information from the precharge signal, then determines the target bit line, and opens the first target switch and the second target switch connected to both ends of the target bit line to make the target bit line conduct. Then, it applies a precharge voltage to the target bit line through the first and second ends of the target bit line to achieve bidirectional charging.
[0086] Pre-charging stops when the voltage of the target bit line reaches the pre-charging voltage. This can be confirmed using conventional voltage detection techniques; specific detection methods can be found in relevant documentation and will not be elaborated upon here. Upon detecting that the target bit line voltage has reached the pre-charging voltage, the control module sends a stop signal, closes the pre-charging switch (i.e., the third switch unit mentioned above), and stops pre-charging.
[0087] Figure 7 An exemplary flowchart of a data readout method 700 for a non-volatile end-to-end memory according to some embodiments of this application is shown.
[0088] The aforementioned non-volatile two-terminal memory is pre-charged using the pre-charge circuit for non-volatile two-terminal memory described in the above embodiment, such as... Figure 7 As shown, the data readout method 700 for a non-volatile two-ended memory includes: step S710: generating a pre-charge voltage based on a received pre-charge signal; step S720: applying a pre-charge voltage to a target bit line through a first and second end of the target bit line based on the pre-charge signal, and stopping pre-charging when the voltage of the target bit line reaches the pre-charge voltage; step S730: transferring the data stored in the target non-volatile two-ended memory cell on the target bit line to the readout circuit of the non-volatile two-ended memory.
[0089] For example, the implementation methods for pre-charging and stopping pre-charging can be found in the description of pre-charging for non-volatile two-ended memory in the above embodiments, and will not be repeated here. After pre-charging is completed, the control module activates the switching device of the target non-volatile two-ended memory cell, making the target non-volatile two-ended memory cell connected to the bit line. Since the target non-volatile two-ended memory cell is in a high-impedance or low-impedance state, the bit line will generate a corresponding weak current or voltage change. Therefore, the readout circuit collects the signal of this weak change and amplifies, decodes, etc., and finally obtains the data stored in the non-volatile two-ended memory.
[0090] While numerous embodiments of this application have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise for those skilled in the art without departing from the spirit and intent of this application. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.
Claims
1. A precharge circuit for a non-volatile two-terminal memory, characterized by, The non-volatile two-ended memory includes a memory array consisting of M*N non-volatile two-ended memory units; The non-volatile two-ended storage section includes: a non-volatile two-ended storage cell and a switching device connected to the non-volatile two-ended storage cell; in the storage array, the non-volatile two-ended storage sections in each column are connected to the same bit line, and M and N are both integers greater than or equal to 1; The pre-charging circuit includes: a pre-charging voltage generation module and a pre-charging module; The precharge voltage generation module is configured to generate a precharge voltage in response to a received precharge signal. The input terminal of the pre-charge module is connected to the pre-charge voltage generation module; the first output terminal of the pre-charge module is connected to the first terminal of each bit line in the storage array; the second output terminal of the pre-charge module is connected to the second terminal of each bit line in the storage array. The pre-charge module is configured to apply the pre-charge voltage to the target bit line through a first end and a second end of the target bit line in response to the pre-charge signal.
2. The pre-charge circuit of claim 1, wherein, The pre-charging module includes: M first switching units and M second switching units; wherein, the M first switching units correspond one-to-one with the M bit lines, and the M second switching units correspond one-to-one with the M bit lines; The output terminal of each first switch unit is connected to the first end of its corresponding bit line; the output terminal of each second switch unit is connected to the second end of its corresponding bit line; the first switch unit and the second switch unit connected at both ends of each bit line are used to control the on / off state of the bit line.
3. The pre-charge circuit of claim 2, wherein, The first output terminal of the pre-charge module is the output terminal of each first switch unit, and the second output terminal is the output terminal of each second switch unit; The pre-charge module is configured to, in response to the pre-charge signal, open the first target switch and the second target switch connected at both ends of the target bit line to turn on the target bit line, and apply the pre-charge voltage to the target bit line through the first end and the second end of the target bit line.
4. The pre-charge circuit of claim 2, wherein, The first switching section is implemented using an N-type MOSFET or a P-type MOSFET; the second switching section is implemented using an N-type MOSFET or a P-type MOSFET.
5. The pre-charge circuit of claim 2, wherein, The pre-charging module further includes: a third switch section configured to control the on / off state of the pre-charging circuit; the input terminal of the pre-charging module is the first terminal of the third switch section; the number of the third switch sections is one. The first end of the third switch section is connected to the pre-charge voltage generation module, and the second end of the third switch section is connected to the input ends of each first switch section and each second switch section, respectively.
6. The pre-charge circuit of claim 2, wherein, The pre-charging module further includes: a third switch section configured to control the on / off state of the pre-charging circuit; the input terminal of the pre-charging module is the first terminal of the third switch section; the number of third switch sections is two. The first ends of both third switch sections are connected to the pre-charge voltage generation module; the second end of one third switch section is connected to the input end of each first switch section; and the second end of the other third switch section is connected to the input end of each second switch section.
7. The pre-charge circuit of claim 5 or 6, wherein, The third switching section is implemented by an N-type MOS transistor or a P-type MOS transistor.
8. The pre-charge circuit of claim 1, wherein, The non-volatile two-terminal memory further includes a control module configured to receive an external read enable signal and generate a precharge signal based on the read enable signal.
9. The pre-charge circuit of claim 3, wherein, The non-volatile two-terminal memory further includes: a readout circuit, which is connected to the input terminal of each first switch or the input terminal of each second switch; the readout circuit is configured to read data from the target non-volatile two-terminal memory cell on the target bit line when the target bit line is turned on.
10. The pre-charge circuit of claim 1, wherein, The non-volatile two-terminal storage unit includes at least one of the following: RRAM unit, FeRAM unit, PCRAM unit, MRAM unit, and MTJ unit.
11. The pre-charging circuit according to claim 1, characterized in that, When the non-volatile two-terminal memory cell is a unipolar memory cell, the pre-charge voltage is less than the absolute value of the set voltage of the non-volatile two-terminal memory cell and less than the absolute value of the reset voltage of the non-volatile two-terminal memory cell. When the non-volatile two-terminal storage cell is a bipolar storage cell, the precharge voltage is between the set voltage of the non-volatile two-terminal storage cell and the reset voltage of the non-volatile two-terminal storage cell.
12. A non-volatile two-terminal memory, comprising: The non-volatile two-terminal memory includes a pre-charge circuit for a non-volatile two-terminal memory as described in any one of claims 1 to 11.
13. An electronic device, comprising: The electronic device includes a precharge circuit for a non-volatile two-terminal memory as described in any one of claims 1 to 11, or a non-volatile two-terminal memory as described in claim 12.