Sealing chip for high-precision current sampling

Abstract

The utility model discloses a sealing chip for high-precision current sampling, relates to the field of integrated circuit design, and solves the problem that the cost of components is increased due to the fact that output current is obtained through an external sampling resistor. The sealing chip comprises a first base island and a second base island, wherein a target chip is arranged on the first base island; the second base island is provided with a power tube; wherein the LX pin of the target chip and the drain electrode of the power tube are respectively connected to the LX pin of the sealed chip through bonding wires; the CSP pin and the CSN pin of the target chip are respectively connected to any two positions on a target bonding line through bonding lines, and the target bonding line is a bonding line between the LX pin of the sealed chip and the drain electrode of the power tube; and the resistor of the bonding line between any two positions is a sampling resistor and is used for collecting the output current.

Description

Technical Field

[0001] This utility model relates to the field of integrated circuit design, and in particular to a high-precision current sampling encapsulated chip. Background Technology

[0002] In power management and motor driver chips, it is necessary to collect the output current to reflect the current operating status. For example, collecting the output current can help determine whether there is an overcurrent or current-limiting condition, or to determine the magnitude of the output current.

[0003] Currently, a sampling node is typically set at the output end, and the output current is obtained through an external sampling resistor. However, obtaining the output current through an external sampling resistor increases the component cost. Summary of the Invention

[0004] This invention provides a high-precision current sampling packaged chip, which solves the problem of increasing component costs by obtaining the output current through an external sampling resistor.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] In a first aspect, this utility model provides a high-precision current sampling packaged chip, comprising:

[0007] The first base island, on which the target chip is installed;

[0008] The second base island is equipped with power transistors;

[0009] In this case, the LX pin of the target chip and the drain of the power transistor are connected to the LX pin of the packaged chip via bonding wires.

[0010] The CSP pin and CSN pin of the target chip are connected to any two positions on the target bonding line through bonding lines. The target bonding line is the bonding line between the LX pin of the packaged chip and the drain of the power transistor.

[0011] The resistance of the bonding line between any two positions is the sampling resistor, used to collect the output current.

[0012] In one possible implementation, the power transistors include a high-side power transistor and a low-side power transistor;

[0013] The target bonding line is the bonding line between the LX pin of the packaged chip and the drain of the high-side power transistor;

[0014] or,

[0015] The target bonding line is the bonding line between the LX pin of the packaged chip and the drain of the low-side power transistor.

[0016] In one possible implementation, the target chip includes a sampling circuit;

[0017] The sampling circuit is used to detect the output current through the sampling resistor.

[0018] In one possible implementation, the sampling circuit includes:

[0019] The first resistor and the second resistor are connected, with one end of the first resistor connected to the CSP pin of the target chip and one end of the second resistor connected to the CSN pin of the target chip.

[0020] A first protection circuit and a second protection circuit, wherein one end of the first protection circuit is connected to the other end of the first resistor, and one end of the second protection circuit is connected to the other end of the second resistor;

[0021] The differential circuit is connected to the first voltage and the second voltage, and is also connected to the other end of the first protection circuit and the other end of the second protection circuit. The output terminal is used to output the sampled voltage.

[0022] In one possible implementation, the differential circuit includes:

[0023] The current mirror is connected to the other end of the first protection circuit and the other end of the second protection circuit, respectively.

[0024] The first circuit is connected to the first voltage and is also connected to the current mirror;

[0025] The second circuit is connected to the second voltage and is also connected to the first circuit;

[0026] The output circuit is connected to the other end of the first protection circuit, and also to the current mirror and the first circuit, and is used to output the sampling voltage.

[0027] In one possible implementation, the first protection circuit includes a first diode, one end of which is connected to a first resistor and the other end of which is connected to a differential circuit.

[0028] The second protection circuit includes a second diode, one end of which is connected to a second resistor, and the other end is connected to a differential circuit.

[0029] In one possible implementation, the first diode and the second diode have the same voltage drop during current sampling.

[0030] Secondly, this utility model provides another type of high-precision current sampling packaged chip, comprising:

[0031] The first base island, on which the target chip is installed;

[0032] The second base island is equipped with a high-side power transistor;

[0033] The source of the high-side power transistor is connected to the VDD pin of the packaged chip via a bonding wire.

[0034] The CSP and CSN pins of the target chip are connected to any two positions on the bonding line between the VDD pin of the packaged chip and the source of the high-side power transistor PMOS via bonding lines.

[0035] The resistance of the bonding line between any two positions is the sampling resistor, used to collect the output current.

[0036] The high-precision current sampling chip provided by this invention utilizes the inherent resistance of the bonding line between any two points on the bonding line between the drain of the power transistor and the LX pin of the chip as a sampling resistor to acquire the output voltage. This eliminates the need for an external sampling resistor or an integrated sampling resistor within the target chip. It also reduces the number of pins CSP and CSN on the chip. In achieving high-precision current sampling, this invention not only reduces the number of components but also does not increase the chip area, thus saving costs. Attached Figure Description

[0037] Figure 1 This is a connection diagram of a packaged chip provided in related technologies;

[0038] Figure 2 This is a circuit equivalent diagram provided in related technologies;

[0039] Figure 3 A connection diagram of a high-precision current sampling encapsulated chip provided for an embodiment of this utility model;

[0040] Figure 4 An equivalent circuit diagram for high-precision current sampling provided in this embodiment of the present invention;

[0041] Figure 5 A circuit schematic diagram of a sampling circuit provided for an embodiment of this utility model;

[0042] Figure 6 A connection diagram of another high-precision current sampling encapsulated chip provided for an embodiment of this utility model;

[0043] Figure 7 The circuit equivalent diagram for another high-precision current sampling provided in this embodiment of the present invention is shown. Detailed Implementation

[0044] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0045] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0046] Figure 1 A connection diagram of a packaged chip is provided for related technologies, such as... Figure 1 As shown, the packaged chip includes two base islands, one of which is equipped with a wafer-level chip, and the other base island is equipped with a high-side power transistor (PMOS) and a low-side power transistor (NMOS).

[0047] The FB, CSN, CSP, VDD, LX, and GND pins of the wafer-level chip are connected to the FB, CSN, CSP, VDD, LX, and GND pins of the packaged chip via bonding lines, respectively.

[0048] The high-side power transistor PMOS is the drain on the back of the base island and is connected to the LX pin of the packaged chip via bonding lines. The PMOS is the gate and source on the front of the base island and is connected to the PG pin of the wafer-level chip and the VDD pin of the packaged chip via bonding lines, respectively.

[0049] The low-side power transistor NMOS is the drain on the back of the base island and is connected to the LX pin of the packaged chip via bonding lines. The NMOS is the gate and source on the front of the base island and is connected to the NG pin of the wafer-level chip and the GND pin of the packaged chip via bonding lines, respectively.

[0050] In related technologies, the CSP and CSN pins of the packaged chip are connected to external sampling resistors. Figure 2 This is a circuit equivalent diagram provided in related technologies, such as Figure 2 As shown, the sampling resistor R1 is used to collect the output current.

[0051] However, obtaining the output current through an external sampling resistor will increase the cost of components.

[0052] Figure 3 This is a connection diagram of a high-precision current sampling encapsulated chip provided for an embodiment of this utility model. (See diagram below.) Figure 3 As shown, the high-precision current sampling packaged chip may include: a first base island 31 and a second base island 32.

[0053] A target chip is mounted on the first base island 31. This target chip can be a power management chip, a motor drive chip, or other types of chips; no limitation is made here.

[0054] The second base island 32 is equipped with a power transistor.

[0055] In this configuration, the LX pin of the target chip and the drain of the power transistor are connected to the LX pin of the packaged chip via bonding lines.

[0056] The CSP and CSN pins of the target chip are connected to any two positions on the target bonding line via bonding lines. The target bonding line is the bonding line between the LX pin of the packaged chip and the drain of the power transistor.

[0057] The resistance of the bonding line between any two positions is the sampling resistor, used to collect the output current.

[0058] By utilizing the inherent resistance of the bonding line between any two points on the bonding line between the drain of the power transistor and the LX pin of the packaged chip as a sampling resistor to acquire the output voltage, no external sampling resistor is required, nor is it necessary to integrate a sampling resistor inside the target chip. It also reduces the number of pins CSP and CSN on the packaged chip. When achieving high-precision current sampling, it not only reduces the number of components but also does not increase the chip area, thus saving costs.

[0059] In one possible implementation, the power transistors on the second base island may include high-side power transistors (PMOS) and low-side power transistors (NMOS).

[0060] The aforementioned target bonding line can be the bonding line between the LX pin of the packaged chip and the drain of the high-side power transistor. In this case, the sampling resistor is used to acquire the current of the high-side power transistor PMOS. Figure 3 The example shown uses the sampling resistor as the resistance of the bonding line between the drain of the high-side power transistor PMOS and the LX pin of the packaged chip. Correspondingly, Figure 4An equivalent circuit diagram for high-precision current sampling provided in this embodiment of the present invention is shown below. Figure 4 As shown, R5 is the sampling resistor.

[0061] It should be noted that, since the drain of the high-side power transistor PMOS is located on the back side of the second base island 32, and adhering to the principle that bonding lines do not cross, therefore Figure 3 The bonding line between the PMOS drain and the LX pin of the packaged chip is not shown in the diagram. Figure 3 In the diagram, the CSP and CSN pins of the target chip are connected to two positions on the second base island 32 via bonding lines, which serves as a schematic of the sampling resistor R5. It can be understood that the sampling resistor R5 is the line resistance between two points on the bonding line between the drain of the PMOS and the LX pin of the packaged chip.

[0062] or,

[0063] The target bonding line mentioned above can be the bonding line between the LX pin of the packaged chip and the drain of the low-side power transistor. In this case, the sampling resistor is used to collect the current of the low-side power transistor NMOS.

[0064] Furthermore, the FB, VDD, and GND pins of the target chip are connected to the FB, VDD, and GND pins of the packaged chip via bonding lines. The high-side power transistor (PMOS) has its gate and source on the front side of the second base island 32, and is connected to the PG pin of the target chip and the VDD pin of the packaged chip via bonding lines. The low-side power transistor (NMOS) has its gate and source on the front side of the second base island 32, and is connected to the NG pin of the target chip and the GND pin of the packaged chip via bonding lines.

[0065] Furthermore, the selection of the two bonding points on the bonding line between the drain of the PMOS and the LX pin of the packaged chip can be determined according to the actual application scenario. Selecting different bonding points can yield sampling resistors with different resistance values.

[0066] The CSP and CSN pins of the target chip are connected to the internal sampling circuit of the target chip to acquire the output current and output the sampled voltage through the sampling resistor. However, in the above embodiment, one end of the sampling resistor, the CSN node, i.e. the LX pin of the packaged chip, will frequently switch between high and low levels (VDD-GND), causing the MOSFET in the sampling circuit inside the target chip to be damaged under such a large voltage difference, thus making it impossible to achieve the current sampling function.

[0067] Optionally, in this embodiment of the invention, the target chip may further include a sampling circuit. This sampling circuit is used to detect the output current through a sampling resistor and can protect the MOSFET in the sampling circuit from damage under large voltage differences, thereby ensuring that current sampling can be completed smoothly.

[0068] Optional, Figure 5 A circuit schematic diagram of a sampling circuit provided for an embodiment of this utility model is shown below. Figure 5 As shown, the sampling circuit may include: a first resistor R1, a second resistor R2, a first protection circuit, a second protection circuit, and a differential circuit.

[0069] The first resistor R1 and the second resistor R2 are connected. One end of the first resistor R1 is connected to the CSP pin of the target chip, and one end of the second resistor R2 is connected to the CSN pin of the target chip.

[0070] The first protection circuit and the second protection circuit are connected, with one end of the first protection circuit connected to the other end of the first resistor R1 and one end of the second protection circuit connected to the other end of the second resistor R2.

[0071] The differential circuit is connected to the first voltage V1 and the second voltage V2, and is also connected to the other end of the first protection circuit and the other end of the second protection circuit. The output terminal is used to output the sampling voltage.

[0072] Optionally, in embodiments of this utility model, such as Figure 5 As shown, the differential circuit described above may include: a current mirror, a first circuit, a second circuit, and an output circuit.

[0073] The current mirror is connected to the other end of the first protection circuit and the other end of the second protection circuit.

[0074] The first circuit is connected to the first voltage V1 and is also connected to the current mirror.

[0075] The second circuit is connected to the second voltage V2 and is also connected to the first circuit.

[0076] The output circuit is connected to the other end of the first protection circuit, and also to the current mirror and the first circuit, for outputting the sampling voltage.

[0077] Optional, such as Figure 5 As shown, the current mirror includes two PMOS transistors, PM5 and PM6. The gate and drain of PM5 are connected to the gate of PM6. The source of PM5 is connected to the other end of the first protection circuit, and the source of PM6 is connected to the other end of the second protection circuit. The drains of PM5 and PM6 are respectively connected to the first circuit.

[0078] The first circuit may include two NMOS transistors, NM7 and NM8. The gates of NM7 and NM8 are connected to a first voltage V1. The drain of NM7 is connected to the drain of PM5, and the drain of NM8 is connected to the drain of PM6. The sources of NM7 and NM8 are respectively connected to the second circuit.

[0079] The second circuit may include two NMOS transistors, NM9 and NM10. The gates of NM9 and NM10 are connected to a second voltage V2. The drain of NM9 is connected to the source of NM7, and the drain of NM10 is connected to the source of NM8. The sources of NM9 and NM10 are grounded.

[0080] The output circuit may include a PMOS transistor PM15 and a resistor R3. The gate of PM15 is connected to the drain of PM6 and the drain of NM8, the source of PM15 is connected to the source of PM5, and the drain of PM15 is connected to one end of R3 for outputting the sampling voltage. The other end of R3 is grounded.

[0081] The above sampling voltage can be: , where R PM5 The internal resistance of PM5.

[0082] Optional, such as Figure 5 As shown, the first protection circuit includes a first diode D1, one end of which is connected to a first resistor R1, and the other end is connected to a differential circuit.

[0083] The second protection circuit includes a second diode D2, one end of which is connected to a second resistor R2, and the other end is connected to a differential circuit.

[0084] It is worth noting that the first diode D1 and the second diode D2 need to be size-matched beforehand to ensure that the voltage drop is the same during current sampling, thereby avoiding the introduction of errors. Furthermore, the first diode D1 and the second diode D2 need to be selected as diodes with a voltage rating within the maximum possible voltage difference range. This way, when the upper diode is turned off, the second diode D2 will bear the large voltage difference, thus protecting PM6 from breakdown and ensuring that current sampling can be completed successfully.

[0085] Figure 6 This is a connection diagram of another high-precision current sampling encapsulated chip provided as an embodiment of the present invention. (See diagram below.) Figure 6 As shown, the high-precision current sampling packaged chip may include: a first base island 61 and a second base island 62.

[0086] The first base island 61 has a target chip mounted on it.

[0087] The second base island 62 has a high-side power transistor (PMOS) and a low-side power transistor (NMOS).

[0088] The source of the high-side power transistor PMOS is connected to the VDD pin of the packaged chip via a bonding line.

[0089] The CSP and CSN pins of the target chip are connected to any two positions on the bonding line between the VDD pin of the packaged chip and the source of the high-side power transistor PMOS via bonding lines. Figure 6 In the example shown, the CSP pin of the target chip is connected to the VDD pin of the packaged chip via a bonding line, and the CSN pin of the target chip is connected to the source of the high-side power transistor PMOS via a bonding line. In this case, the line resistance of the bonding line between these two points is the sampling resistor. Correspondingly, Figure 7 An equivalent circuit diagram for high-precision current sampling provided in this embodiment of the present invention is shown below. Figure 7 As shown, R5 is the sampling resistor.

[0090] The resistance of the bonding line between any two positions is the sampling resistor, used to collect the output current.

[0091] By utilizing the inherent resistance of the bonding line between any two points on the bonding line between the VDD of the packaged chip and the source of the high-side power transistor as a sampling resistor to acquire the output voltage, no external sampling resistor is required, nor is it necessary to integrate a sampling resistor inside the target chip. It also reduces the number of pins CSP and CSN of the packaged chip. When achieving high-precision current sampling, it not only reduces the number of components but also does not increase the chip area, thus saving costs.

[0092] Furthermore, the FB, VDD, and GND pins of the target chip are connected to the FB, VDD, and GND pins of the encapsulated chip via bonding lines. The high-side power transistor PMOS has its gate and source on the front side of the second base island 62, and is connected to the PG pin of the target chip and the VDD pin of the encapsulated chip via bonding lines. The low-side power transistor NMOS has its gate and source on the front side of the second base island 62, and is connected to the NG pin of the target chip and the GND pin of the encapsulated chip via bonding lines. The high-side power transistor PMOS has its drain on the back side of the second base island 62 and is connected to the LX pin of the encapsulated chip. Figure 6 The bonding line is not shown in the diagram. The low-side power transistor NMOS has its drain on the back of the second base island 62 and is connected to the LX pin of the packaged chip. Figure 6 The bonding line is not shown in the image.

[0093] The above description is merely a specific embodiment of this utility model, but the protection scope of this utility model is not limited thereto. Any changes or substitutions within the technical scope disclosed in this utility model should be included within the protection scope of this utility model. Therefore, the protection scope of this utility model should be determined by the protection scope of the claims.

Claims

1. A hermetically sealed chip for high-precision current sampling, characterized by, include: The first base island, on which the target chip is mounted; The second base island is equipped with power transistors; The LX pin of the target chip and the drain of the power transistor are respectively connected to the LX pin of the encapsulated chip via bonding lines. The CSP pin and CSN pin of the target chip are respectively connected to any two positions on the target bonding line through bonding lines. The target bonding line is the bonding line between the LX pin of the packaged chip and the drain of the power transistor. The resistance of the bonding line between any two positions is the sampling resistor, used to collect the output current.

2. The high-precision current sampling packaged chip according to claim 1, characterized in that, The power transistors include high-side power transistors and low-side power transistors; The target bonding line is the bonding line between the LX pin of the encapsulated chip and the drain of the high-side power transistor; or, The target bonding line is the bonding line between the LX pin of the encapsulated chip and the drain of the low-side power transistor.

3. The high-precision current sampling packaged chip according to claim 1 or 2, characterized in that, The target chip includes a sampling circuit; The sampling circuit is used to detect the output current through the sampling resistor.

4. The hermetically sealed chip for high-precision current sampling according to claim 3, characterized in that, The sampling circuit includes: A first resistor and a second resistor, one end of the first resistor is connected to the CSP pin of the target chip, and one end of the second resistor is connected to the CSN pin of the target chip; A first protection circuit and a second protection circuit, wherein one end of the first protection circuit is connected to the other end of the first resistor, and one end of the second protection circuit is connected to the other end of the second resistor; A differential circuit is connected to a first voltage and a second voltage, and is also connected to the other end of the first protection circuit and the other end of the second protection circuit. The output terminal is used to output the sampled voltage.

5. The hermetically sealed chip for high-precision current sampling according to claim 4, characterized in that, The differential circuit includes: A current mirror, which is connected to the other end of the first protection circuit and the other end of the second protection circuit respectively; A first circuit is connected to the first voltage and is also connected to the current mirror; The second circuit is connected to the second voltage and is also connected to the first circuit; The output circuit is connected to the other end of the first protection circuit, and also to the current mirror and the first circuit, for outputting the sampling voltage.

6. The high-precision current sampling packaged chip according to claim 4, characterized in that, The first protection circuit includes a first diode, one end of which is connected to the first resistor and the other end of which is connected to the differential circuit; The second protection circuit includes a second diode, one end of which is connected to the second resistor, and the other end of which is connected to the differential circuit.

7. The high-precision current sampling packaged chip according to claim 6, characterized in that, The first diode and the second diode have the same voltage drop during current sampling.

8. A hermetically sealed chip for high-precision current sampling, characterized by, include: The first base island, on which the target chip is mounted; The second base island is equipped with a high-side power transistor; The source of the high-side power transistor is connected to the VDD pin of the encapsulated chip via a bonding wire. The CSP pin and CSN pin of the target chip are respectively connected to any two positions on the bonding line between the VDD pin of the packaged chip and the source of the high-side power transistor via bonding lines. The resistance of the bonding line between any two positions is the sampling resistor, used to collect the output current.

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