BMC (Baseboard Management Controller) module based on E2000S, chip and electronic equipment

Abstract

The utility model discloses an E2000S-based BMC module, a chip and an electronic device, the E2000S-based BMC module comprises an E2000S master control module, a storage module, a power management module and a DDR4 expansion module, the power management module is provided with a power switch chip and a plurality of post-stage LDO chips, the power switch chip receives a first input voltage input by the DDR4 expansion module, and the first input voltage is output by the DDR4 expansion module. And the plurality of rear-stage LDO chips are controlled to supply power to different power supply modules in a grading manner. According to the technical scheme, on one hand, the domestic E2000S main control module is adopted, and all domestic devices such as the DDR4 expansion module, the power management module and the LPDDR4 storage module are adopted, so that the dependence on an imported chip is remarkably reduced, full-domestic integration is realized, and the safety of a supply chain is ensured; and furthermore, required working voltages are provided for different functional modules (such as SerDes, LPDDR4 and ADC) through a plurality of post-stage LDO chips, so that the time sequence power-on requirements of various voltage rails in the system are met, and multi-voltage-domain stable power supply is supported.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a BMC module, chip and electronic device based on E2000S. Background Technology

[0002] The BMC (Baseboard Management Controller) is a key component in servers and high-end computing devices. It is widely used to implement low-level management functions such as remote monitoring of device operating status, abnormal alarms, environmental parameter collection, log management, and hardware restart. It is a core module for achieving system stability and maintainability.

[0003] In related technologies, mainstream BMC modules typically use dedicated main control chips (such as the ASPEEDAST2500 series) provided by international manufacturers, along with multiple peripheral functional chips, including imported power management chips (such as PMICs from TI or ADI), memory chips (such as LPDDR4 provided by Micron or Samsung), and communication control chips (such as PCIe / USB controllers provided by Broadcom). While this type of BMC solution possesses a certain level of functional maturity, it suffers from the following serious problems in the context of domestic production:

[0004] The reliance on imported core chips poses a high risk to the supply chain: Key components such as main control chips, power management chips, and communication interface chips are heavily dependent on foreign manufacturers, making it impossible to guarantee continuous supply in critical scenarios. This creates a risk of being "strangled" by foreign suppliers and hinders the construction of an independent and controllable information system architecture. Low system integration, complex design, and high power consumption: Existing BMC solutions mostly adopt discrete chip design structures. The main control chip has limited functionality and requires multiple external chips to work together to achieve functions such as communication, storage, and interface expansion. This results in complex system circuits, difficult wiring, high overall power consumption, and large size, which is not conducive to high-density integration and low-power optimization.

[0005] Poor interface compatibility and weak domestic adaptation capabilities: Existing BMC modules mainly use foreign standards for interfaces such as PCIe, USB, and I2C, and lack the ability to adapt to domestic CPU platforms, domestic memory chips, and domestic sensor modules, thus failing to meet the overall compatibility requirements of domestic information systems.

[0006] Therefore, the BMC module in related technologies has significant shortcomings in terms of supply chain security, system integration efficiency, and domestic compatibility. Utility Model Content

[0007] The main objective of this invention is to provide a BMC module, chip, and electronic device based on E2000S, so as to at least partially solve one of the problems in the related technologies.

[0008] To achieve the above objectives, this utility model provides the following technical solution:

[0009] In a first aspect, this utility model provides a BMC module based on E2000S, the BMC module based on E2000S including an E2000S main control module, a storage module, a power management module and a DDR4 expansion module.

[0010] The storage module, the power management module, and the DDR4 expansion module are all electrically connected to the E2000S main control module, which integrates multiple interfaces, including a memory interface, a communication interface, a network interface, and a control interface.

[0011] The power management module includes a power switch chip and multiple downstream LDO chips. The power switch chip is used to receive the first input voltage input through the DDR4 expansion module and control the multiple downstream LDO chips to provide graded power supply to different power modules.

[0012] A second aspect of this utility model provides a chip, including a chip body and a BMC module based on E2000S as described in the first aspect.

[0013] A third aspect of this utility model provides an electronic device, including a device body and a chip as described in the second aspect.

[0014] This utility model discloses a BMC module, chip, and electronic equipment based on E2000S. On the one hand, it adopts a domestically produced E2000S main control module and uses all domestically produced components such as DDR4 expansion modules, power management modules, and LPDDR4 storage modules, significantly reducing reliance on imported chips, effectively improving system controllability and domestic adaptability, meeting the requirements of key industries for information security and independent controllability, achieving full domestic integration, and ensuring supply chain security. On the other hand, it achieves voltage input control through the power switch chip in the power management module, and further provides the required operating voltage for different functional modules (such as SerDes, LPDDR4, and ADC) through multiple downstream LDO chips, meeting the timing power-up requirements of multiple voltage rails in the system, supporting stable power supply in multiple voltage domains, which helps improve system startup stability and reliability, and supports stable power supply in multiple voltage domains. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of the BMC module based on E2000S provided for embodiments of this application;

[0017] Figure 2 A schematic diagram of the module connection of the BMC module based on E2000S provided for embodiments of this application;

[0018] Figure 3 This is a schematic diagram illustrating the connection between the E2000S main control chip and the Flash memory in an embodiment of this application.

[0019] Figure 4 This is a schematic diagram illustrating the connection between the E2000S main control chip and the LPDDR4 memory chip in an embodiment of this application.

[0020] Figure 5 This is a schematic diagram of the module connection of the power management module in an embodiment of this application;

[0021] Figure 6 This is a timing diagram of the power management module in an embodiment of this application. Detailed Implementation

[0022] To make the inventive objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] In the description of the embodiments of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The term "multiple" means two or more, unless otherwise explicitly specified. The term "comprising" indicates the presence of the described feature, whole, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or sets thereof. The term "and / or" describes the relationship between related objects, indicating that three relationships may exist. For example, A and / or B may include three cases: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship.

[0025] Unless otherwise defined, all technical terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art; the terms used in the embodiments of this application are for the purpose of describing specific embodiments only and are not intended to limit this application; the terms "comprising" and "having" and any variations thereof in the specification, claims and foregoing description of the drawings of this application are intended to cover non-exclusive inclusion.

[0026] Furthermore, terms such as "exemplary," "for example," and "optional" are used to indicate illustrative purposes. Any technical solution described by the above terms in the embodiments of this application should not be construed as being more preferred or advantageous than other technical solutions. Specifically, these terms are intended to present the relevant technical concepts in terms of specific implementation methods.

[0027] The following explains the English terms used in the embodiments of this application:

[0028] BMC: Baseboard Management Controller

[0029] PCIe: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard.

[0030] LPDDR4: LPDDR4 SDRAM

[0031] USB: Universal Serial Bus

[0032] SGMII: Serial Gigabit Media Independent Interface, a serial physical layer interface for Gigabit Ethernet; I2C: Inter-Integrated Circuit, a low-speed, short-range, two-wire synchronous serial communication protocol.

[0033] GPIO: General Purpose Serial Input / Output

[0034] CPU: Central Processing Unit

[0035] RC: Root Complex

[0036] EP: End point

[0037] PMIC: Power Management IC

[0038] This application aims to address technical issues such as reliance on imported chips (due to insufficient compatibility with domestically produced chips), low integration, and low compatibility. Please refer to [link / reference]. Figure 1 and Figure 2 This embodiment provides a BMC module based on E2000S, which includes an E2000S main control module 10, a storage module 20, a power management module 30, and a DDR4 expansion module 40.

[0039] In this BMC module, the storage module 20, power management module 30, and DDR4 expansion module 40 are electrically connected to the E2000S main control module 10, achieving a high degree of integration of control, power supply, storage, and external communication functions. The following describes each component module:

[0040] The E2000S main control module 10 can be a domestically produced E2000S chip (Tenglong E2000S chip), featuring high integration and multi-protocol support capabilities. It can run BMC firmware and perform functions such as remote management, status monitoring, device control, and communication interaction for the server system. The aforementioned E2000S main control module 10 integrates multiple interfaces for signal interaction and data communication with memory, peripherals, the motherboard, and sensor devices, specifically including memory interfaces, communication interfaces, network interfaces, and control interfaces.

[0041] The storage module 20 provides high-speed data read / write and firmware runtime space for the E2000S main control module 10. Preferably, the storage module 20 can be a domestically produced LPDDR4 memory chip, supporting a dual-channel topology, and connected to the LPDDR4 interface signal group (such as DQ[0:31], DM[0:3], CA, CS, DQS, etc.) on the main control module. This module uses a 1.1V power supply and features high speed, low power consumption, and high integration, meeting the performance requirements of BMC firmware operation and data cache management.

[0042] The power management module 30 provides multi-stage power supply to the entire BMC module, ensuring that the E2000S main control module 10 and its external interfaces start up and operate stably within a specified time sequence. Specifically, the power management module 30 includes a power switch chip 301 and multiple downstream LDO chips 302. The power switch chip 301 receives the first input voltage (3.3V_STB) from the DDR4 expansion module 40 and controls the multiple downstream LDO chips 302 to convert the first input voltage into different output voltage rails, such as 1.2V, 1.1V, and 1.8V, to provide staged power supply to different power modules (SerDes module, LPDDR4 memory, ADC analog interface, etc.).

[0043] The DDR4 expansion module 40 is used to realize the electrical connection and signal output between the E2000S main control module 10 and the external motherboard. This DDR4 expansion module 40 can be a DDR4 gold finger terminal, bringing out various interfaces integrated into the E2000S main control module (such as PCIe Gen3, USB 2.0, SGMII, I2C, GPIO, etc.), thereby facilitating signal interface and functional interaction with the CPU, memory controller, or other system resources on the motherboard. Simultaneously, this module is also used to input the main power supply voltage (such as 3.3V_STB) to the power management module 30, serving as the power supply input for the entire BMC system.

[0044] Thus, the BMC module based on E2000S of this utility model, on the one hand, adopts the domestic E2000S main control module and uses all domestically produced components such as DDR4 expansion module, power management module, and LPDDR4 storage module, significantly reducing the dependence on imported chips, effectively improving the system's controllability and domestic adaptability, meeting the requirements of key industries for information security and independent controllability, achieving full domestic integration, and ensuring supply chain security; on the other hand, it realizes voltage input control through the power switch chip in the power management module, and further provides the required operating voltage for different functional modules (such as SerDes, LPDDR4, ADC) through multiple downstream LDO chips, meeting the timing power-up requirements of multiple voltage rails in the system, supporting stable power supply in multiple voltage domains, which helps improve the system's startup stability and reliability, and supports stable power supply in multiple voltage domains.

[0045] In some optional embodiments of this application, the memory interface includes an LPDDR4 interface, the communication interface includes a PCIe Gen3 interface and a USB 2.0 interface, the network interface includes an SGMII Ethernet interface, and the control interface includes a multi-channel I2C interface and / or a GPIO interface.

[0046] Specifically, the LPDDR4 interface is used to connect to external high-speed memory modules, supporting a dual-channel access structure to meet the operation and data buffering requirements of the BMC firmware; the PCIe Gen3 interface supports high-speed peripheral expansion; the USB 2.0 interface is used for serial data communication with external devices; the SGMII Ethernet interface is used to connect to domestic Ethernet PHY chips to realize remote management data channels; and multiple I2C and GPIO interfaces are used to acquire status and output control signals to peripheral devices such as temperature and humidity sensors, fan controllers, and indicator lights.

[0047] The aforementioned interfaces are connected to the DDR4 expansion module via PCB wiring to enable unified output of main control module function signals and interconnection of the motherboard system.

[0048] Please see Figure 3 The E2000S main control module 10 can integrate an SPI (Serial Peripheral Interface) controller for communication with external Flash memory. To meet the requirements of BMC firmware operation and configuration initialization, this embodiment adopts a Flash configuration boot mode, selecting a GigaDevice GD25B512YIGR NOR Flash memory as the data storage medium for the main control chip. This memory has advantages such as a 512Mbit capacity, high non-volatility, fast read / write speed, and no data loss upon power failure, making it suitable for embedded system firmware storage requirements.

[0049] The Flash memory is electrically connected to the E2000S main control module 10 via an SPI interface, as shown in the specific connection relationship below. Figure 3 As shown, and including at least the following signal channels:

[0050] CS (Chip Select Signal): Output by the E2000S main control module, used to select the target Flash device;

[0051] CLK (clock signal): The clock source signal provided by the main control module, which drives the Flash synchronous operation;

[0052] SI / IO0 (Serial Input): The main controller writes data to the Flash memory;

[0053] SO / IO1 (Serial Output): Flash sends read data back to the main controller;

[0054] WP# / IO2 (write protection) and HOLD / IO3 (pause control): used to control write enable and operation interruption of Flash, enhancing data security and communication stability.

[0055] In this embodiment, the Flash memory is powered by a 3.3V supply, provided by an LDO voltage regulator chip in the power management module, ensuring its operational stability. Simultaneously, the E2000S main control module can load the BMC boot firmware from the Flash memory via the SPI interface after power-on, initializing its internal functional modules and communication bus, thereby completing the system boot process.

[0056] Please see Figure 4 In some optional embodiments of this application, the E2000S main control module 10 mentioned above integrates an LPDDR4 interface controller, which is used to establish a high-speed data communication connection with domestic LPDDR4 memory chips.

[0057] To meet the high-speed read / write requirements of the BMC module for data caching and firmware execution, this implementation uses domestically produced LPDDR4 memory chips in the storage module 20, with a preferred model such as Changxin Memory CXDB4CBAM-MK-A. This memory chip supports dual-channel topology configuration and is electrically connected to the main control chip via multiple dedicated signal lines. The specific connection structure is as follows:

[0058] Data lines DQ[0:31]: used to implement 32-bit bidirectional data transmission, connecting to the data pins of two memory channels respectively;

[0059] Data mask signals DM[3:0]: used to identify the valid bits of data, corresponding to channels A and B respectively;

[0060] Data signal sampling reference clock DQS_P / N[3:0]: Provides a clock reference for data sampling;

[0061] Command / address signals CA[5:0] and CS_N, CK, CKE, ODT, ZQ: used for memory initialization, addressing, and command transmission;

[0062] The reset signal LPDDR4_RESET_N is used for memory reset control.

[0063] Clock signals DDR_CLK_P / N and VDDQ / VDDQ_CK: provide high-speed clock source and power support.

[0064] The LPDDR4 memory is connected to the E2000S main control module through two logical channels (Channel A / B) to achieve dual-channel parallel access, effectively improving data read / write bandwidth and system response speed.

[0065] In terms of power supply, the LPDDR4 interface is powered by the second-stage LDO chip in the power management module, which outputs 1.1V to ensure stable operation of the storage module.

[0066] Through the above structural design, this embodiment can achieve high-speed and reliable data interaction between the LPDDR4 memory chip and the E2000S main control module, meeting the BMC control system's requirements for low-power, high-performance memory.

[0067] Please see Figure 5 In some optional embodiments of this application, the plurality of post-stage LDO chips include a first post-stage LDO chip, a second post-stage LDO chip, and a third post-stage LDO chip.

[0068] The first post-stage LDO chip is used to output the first output voltage to supply the SerDes power module; the aforementioned SerDes power module provides the necessary operating voltage for the high-speed serial interface, specifically for powering the SerDes driver section of the PCIe Gen3 interface and SGMII Ethernet interface, ensuring stable operation of the high-speed data link.

[0069] The second-stage LDO chip is used to output the second output voltage to supply the LPDDR4 power module; the aforementioned LPDDR4 power module is used to provide a stable operating voltage for the external domestic LPDDR4 memory chip, thereby supporting high-speed data interaction between the E2000S main control module and the memory module through its LPDDR4 interface.

[0070] The third-stage LDO chip is used to output the third output voltage to supply the ADC power module; the aforementioned ADC power module is used to provide power to external analog signal sources (such as temperature, voltage or pressure sensors) connected through the ADC interface of the E2000S main control module, ensuring voltage accuracy and electrical isolation during the analog signal sampling process.

[0071] In this embodiment, each of the aforementioned downstream LDO chips serves different voltage domains and different functional modules, forming a power supply architecture with multiple voltage rails operating in parallel and power supply in different domains. At the same time, it works in conjunction with the power switch chip to achieve unified control over the power start-up and shutdown sequence, thereby improving the startup stability and operational reliability of the entire BMC module.

[0072] Please continue reading. Figure 5 The power management module may also include a primary LDO chip and a DC / DC chip.

[0073] The first-level LDO chip receives a first input voltage (3.3V) from the DDR4 expansion module and outputs a fourth output voltage (e.g., 1.8V). This fourth output voltage powers the CPU I / O, LPDDR4, USB, PLL, and clock chip MSC1422IM.

[0074] The DC / DC chip receives the first input voltage from the DDR4 expansion module and outputs a fifth output voltage (e.g., 0.8V). This fifth output voltage can power the CPU core voltage, SerDes power supply, USB power supply, and PLL power supply.

[0075] In a preferred embodiment, the DC / DC chip can be a domestically produced model (e.g., BPD60306A), which has high current output capability to meet the power consumption requirements of multiple high-performance subsystems within the BMC module.

[0076] Through the collaborative operation of the LDO chip and the DC / DC chip, the power management module 30 can achieve precise power supply to different operating voltage domains, meet the stability requirements of high-speed interfaces and timing control, and realize power supply isolation and noise suppression between modules, effectively improving system reliability and power consumption control capabilities.

[0077] Please see Figure 6 The power management module is further configured to enable multiple voltage rails sequentially according to a preset power-on sequence, so as to ensure that each voltage domain is powered on as needed before the main control module starts up, thus meeting the system timing and logic requirements.

[0078] Specifically, the multiple voltage rails include:

[0079] The 0.8V voltage rail is used to power the CPU core voltage (Core VDD) and the phase-locked loop (PLL) module;

[0080] The 1.8V voltage rail is used to power the I / O units, LPDDR4 power supply, clock chip MSC1422IM, USB module and some analog power domains of the E2000S main control module.

[0081] The 3.3V voltage rail is used to power external Flash memory, UART, GPIO and other bus level interfaces and peripherals.

[0082] The 1.1V voltage rail is used to provide operating voltage for the memory connected to the LPDDR4 interface, ensuring the timing integrity of high-speed data transmission.

[0083] Furthermore, in order to ensure stable power-on of the system, this embodiment controls the power-on sequence to satisfy the following relationship:

[0084] Phase 1 (before t1): First, start the 0.8V voltage rail to power on the core module and PLL;

[0085] Second stage (after t1): Start the 1.8V voltage rail to power peripheral units such as IO interface, LPDDR4, clock chip MSC1422IM, and USB module;

[0086] Phase 3 (after t2): Start the 3.3V voltage rail to power peripherals and memory;

[0087] Phase 4 (after t3): Start the 1.1V voltage rail to power the LPDDR4 interface;

[0088] Final stage (after t2): After all the voltage rails have stabilized, release the system reset signal POR_N and enter normal operation.

[0089] In this embodiment, by setting a clear voltage rail sequence and timing interval, startup anomalies caused by voltage conflicts and timing mismatches are effectively avoided, thus improving the overall stability and reliability of the device. This power supply timing can be automatically executed by the reset circuit or the internal control logic of the power switch chip, without external intervention.

[0090] In some optional embodiments of this example, the LPDDR4 interface includes a signal connection structure that supports dual-channel configuration, the signal connection structure being used to connect LPDDR4 memory chips that support dual-channel operation.

[0091] In some optional implementations of this embodiment, the BMC module based on E2000S also includes a clock module.

[0092] The clock module can be a domestically produced programmable clock chip (such as MSC1422IM), which is configured to receive a reference clock signal (such as 25MHz) from an external crystal oscillator, and perform clock multiplication or division operations through an internal phase-locked loop (PLL) and frequency synthesis technology to output multiple clock signals that meet the system requirements.

[0093] The multi-channel clock output signals include:

[0094] The first clock signal is used to provide a 50MHz system reference clock for the E2000S main control module;

[0095] The second clock signal is used to provide a 25MHz reference clock for the Ethernet PHY module;

[0096] The third clock signal is used to provide a 100MHz reference clock for the PCIe Gen3 interface;

[0097] The fourth clock signal is used to provide a 100MHz reference clock for the SGMII interface.

[0098] The aforementioned clock signals are routed through electrical isolation and differential transmission paths to ensure stable operation of all modules within the system under low jitter and low bit error rate conditions. Preferably, the clock module is programmable and configurable in terms of phase offset and output level to meet the timing accuracy and drive capability requirements of different interfaces. In other words, by configuring the aforementioned clock module, the system integration can be effectively improved, the dependence on the number of external crystal oscillators can be reduced, board space can be optimized, and the system's anti-interference capability can be enhanced.

[0099] It should be noted that the E2000S main control module in this embodiment can be replaced with the E2000Q of the same series, supporting the higher-speed PCIe Gen4. Furthermore, the power management module can be replaced with the domestically produced SGM6130 from Saint-Gobain Microelectronics, supporting the same voltage regulation logic. Additionally, the storage interface can be replaced with a domestically produced NAND Flash + DRAM combination solution. The communication protocol can be replaced with a domestically produced RGMII protocol PHY chip.

[0100] This application also provides a chip, including a chip body and a BMC module based on E2000S as described in the first aspect.

[0101] This application also provides an electronic device, including a device body and a chip as described in the second aspect.

[0102] This utility model discloses a BMC module, chip, and electronic equipment based on E2000S. On the one hand, it adopts a domestically produced E2000S main control module and uses all domestically produced components such as DDR4 expansion modules, power management modules, and LPDDR4 storage modules, significantly reducing reliance on imported chips, effectively improving system controllability and domestic adaptability, meeting the requirements of key industries for information security and independent controllability, achieving full domestic integration, and ensuring supply chain security. On the other hand, it achieves voltage input control through the power switch chip in the power management module, and further provides the required operating voltage for different functional modules (such as SerDes, LPDDR4, and ADC) through multiple downstream LDO chips, meeting the timing power-up requirements of multiple voltage rails in the system, supporting stable power supply in multiple voltage domains, which helps improve system startup stability and reliability, and supports stable power supply in multiple voltage domains.

[0103] In addition, it also has the following beneficial effects: 1) Self-reliance and controllability: The entire chain is domestically produced, avoiding the risk of being "strangled". 2) High integration: The E2000S main controller integrates multiple protocol interfaces, reducing the number of peripheral chips and lowering costs by 20%. 3) High efficiency: The LPDDR4 dual-channel design improves data processing speed, and PCIe Gen3 supports high-speed device expansion. 4) Low power consumption: Dynamic power management technology makes standby power consumption ≤2W, which is better than imported solutions (3.5W).

[0104] The specific embodiments of the utility model have been described in detail above, but they are only examples, and the utility model is not limited to the specific embodiments described above. For those skilled in the art, any equivalent modifications or substitutions to the utility model are also within the scope of the utility model. Therefore, all equivalent transformations, modifications, and improvements made without departing from the spirit and principles of the utility model should be covered within the scope of the utility model.

Claims

1. An E2000S-based BMC module, characterized in that, The BMC module based on E2000S includes an E2000S main control module, a storage module, a power management module, and a DDR4 expansion module. The storage module, the power management module, and the DDR4 expansion module are all electrically connected to the E2000S main control module, which integrates multiple interfaces, including a memory interface, a communication interface, a network interface, and a control interface. The power management module includes a power switch chip and multiple downstream LDO chips. The power switch chip is used to receive the first input voltage input through the DDR4 expansion module and control the multiple downstream LDO chips to provide graded power supply to different power modules.

2. The BMC module based on E2000S as described in claim 1, characterized in that, The memory interface includes an LPDDR4 interface, the communication interface includes a PCIe Gen3 interface and a USB 2.0 interface, the network interface includes an SGMII Ethernet interface, and the control interface includes a multi-channel I2C interface and / or a GPIO interface.

3. The E2000S-based BMC module of claim 2, wherein, The DDR4 expansion module includes DDR4 gold finger terminals; The various interfaces integrated on the E2000S main control module are led out to the DDR4 gold finger terminals through PCB wiring.

4. The E2000S-based BMC module of claim 3, wherein, The plurality of said post-stage LDO chips include a first post-stage LDO chip, a second post-stage LDO chip and a third post-stage LDO chip; The first post-stage LDO chip is used to output a first output voltage to power the SerDes power module; wherein, the SerDes power module is used to power the PCIe Gen3 interface and the SGMII Ethernet interface; The second post-stage LDO chip is used to output a second output voltage to power the LPDDR4 power module; wherein, the LPDDR4 power module is used to power the LPDDR4 interface; The third post-stage LDO chip is used to output a third output voltage to power the ADC power module; wherein, the ADC power module is used to provide operating voltage for an external analog signal source connected through the ADC interface.

5. The E2000S-based BMC module of claim 4, wherein, The power management module includes a primary LDO chip and a DC / DC chip; The first-level LDO chip is used to receive the first input voltage input through the DDR4 expansion module and output the fourth output voltage to power the LPDDR4 power supply, CPU IO power supply, USB power supply, PLL power supply and clock chip MSC1422IM. The DC / DC chip is used to receive the first input voltage from the DDR4 expansion module and output the fifth output voltage to power the CPU core voltage, SerDes power supply, USB power supply and PLL power supply.

6. The E2000S-based BMC module of claim 5, wherein, The power management module is configured to sequentially enable multiple voltage rails according to a preset power-on sequence. The multiple voltage rails include a 0.8V voltage rail, a 1.8V voltage rail, a 3.3V voltage rail, and a 1.1V voltage rail; wherein, the 0.8V voltage rail is used to power the CPU core voltage and the PLL module; the 1.8V voltage rail is used to power the I / O unit of the main control module, the LPDDR4 power supply, the clock chip MSC1422IM, and the USB module; the 3.3V voltage rail is used to power peripherals and bus level interfaces; and the 1.1V voltage rail is used to power the LPDDR4 interface; Furthermore, the power-on timing is controlled to satisfy the following relationships: the 0.8V voltage rail is started before the first time t1; the 1.8V voltage rail is started after the first time t1; the 3.3V voltage rail is started after the second time t2; the 1.1V voltage rail is started after the third time t3; and the reset signal is released after the second time t2.

7. The E2000S-based BMC module of claim 1, wherein, The E2000S-based BMC module also includes a clock module; The clock module is used to receive external reference clock signals and perform frequency multiplication or division to generate multiple clock output signals. The multi-channel clock output signals include: The first clock signal is used to provide a 50MHz system reference clock for the E2000S main control module; The second clock signal is used to provide a 25MHz reference clock for the Ethernet PHY module; The third clock signal is used to provide a 100MHz reference clock for the PCIe Gen3 interface; The fourth clock signal is used to provide a 100MHz reference clock for the SGMII interface.

8. The E2000S-based BMC module of claim 2, wherein, The LPDDR4 interface includes a signal connection structure that supports dual-channel configuration; The signal connection structure is used to connect LPDDR4 memory chips that support dual-channel operation.

9. A chip, characterized by It includes the chip body and the BMC module based on E2000S as described in any one of claims 1 to 8.

10. An electronic device, comprising: It includes the main body of the device and the chip as described in claim 9.

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