Reading circuit of resistive random access memory array and memory

Abstract

The utility model provides a reading circuit of a resistive random access memory array and a memory. The reading circuit comprises a reading enable signal end, a pre-charging end, a reference array, N first delay chains, a comparator, a second delay chain and a latch comparator, wherein the reference array comprises a reference bit line, a reference source line, a reference word line, N-1 redundant units and one reference unit. According to the reading circuit disclosed by the utility model, the reading accuracy and the reading speed of the resistive random access memory array can be improved.

Description

Technical Field

[0001] This utility model relates to the field of memory technology, and in particular to a read circuit for a resistive variable memory array and a memory. Background Technology

[0002] A resistive random access memory (RRAM) array is a two-dimensional or three-dimensional array structure formed by arranging a large number of resistive random access memory cells (RRAMs) through word lines and bit lines. A word line (WL) is a wire in the RRAM array that directly connects to the enable terminal of a RRAM cell. Its core function is to activate the row containing the target cell through a signal, creating a path between the target cell and the bit line to complete data access. A bit line (BL) is a wire in the RRAM array that directly connects to the read / write terminals of the RRAM cells. It is responsible for transmitting storage signals during read / write operations and serves as the physical channel for data input / output. A resistive random access memory cell (RRAM) is a memory cell whose resistance state can be changed by applying different voltage or current signals, thereby enabling data storage. The steps for reading data stored in a resistive random access memory array typically include: first, selecting the target memory cell by activating the word line and bit line, and applying a read voltage; then, acquiring the storage voltage generated on the bit line of the target memory cell; finally, comparing the storage voltage with a reference voltage in a comparator to determine whether the target memory cell is in a high-resistance or low-resistance state, thus completing the reading of the data stored in the target memory cell. Since word line activation requires decoding and driving steps, which takes time, to prevent the comparator from prematurely comparing the storage voltage with the reference voltage before the memory cell is activated, thus causing read data errors, existing technologies often use a delay chain control comparator scheme to read resistive variable memory arrays.

[0003] Figure 1 The circuit structure corresponding to the prior art delay chain control comparator scheme is shown. (Refer to...) Figure 1 The operation steps of the delay chain control comparator circuit are as follows: First, the bit line BL is pre-charged to the read voltage; then, when the bit line address signal ADD arrives, the read enable signal RE is pulled high and split into two paths, one entering the word line drive path R1 to activate the word line WL, and the other entering the delay path R2 for delay; finally, the word line WL enables the memory cell S, causing the read memory cell on the bit line BL to discharge. After the delay chain R2 delays, the comparator SA is enabled. The comparator SA compares the voltage on the bit line at that moment (i.e., the voltage at the read / write terminal of the read memory cell) with the reference voltage V. ref Complete the data reading.

[0004] Existing delay chain control comparator schemes control the read timing by designing the number of delay devices in the delay chain to adjust the delay time from the read enable signal RE to the enable terminal of comparator SA. When the delay time from the read enable signal RE to the enable terminal of comparator SA ensures that the read memory cell has been fully discharged and meets the read requirements when comparator SA reads the voltage at the read / write terminal, the read result of the read memory cell is accurate.

[0005] However, Figure 1 The delay chain control comparator scheme shown in the diagram suffers from significant fluctuations in the comparison time of the comparator due to the influence of process technology, voltage, and temperature on the delay chain inverter, as well as inconsistencies with the memory array. Regardless of whether the RRAM is in a high-resistance or low-resistance state, if the comparison time is too early, incomplete BL discharge will cause the BL voltage to be higher than Vref; if the comparison time is too late, excessive BL discharge will cause the BL voltage to be lower than Vref, both resulting in read data errors. Furthermore, excessive BL discharge also incurs additional power consumption and delay overhead.

[0006] To address the aforementioned problems, this invention provides a read circuit for a resistive variable memory array and a memory. Utility Model Content

[0007] In order to overcome the above-mentioned defects, the present invention aims to provide a read circuit for a resistive variable memory array and a memory.

[0008] According to one aspect of the present invention, a read circuit for a resistive variable memory array is provided.

[0009] In one embodiment, the resistive random access memory array includes N word lines. The read circuit includes: a read enable signal terminal, a precharge terminal, a reference array, N first delay chains, a comparator, a second delay chain, and a latch comparator. The reference array includes a reference bit line, a reference source line, a reference word line, N-1 redundant cells, and 1 reference cell. The enable and reference terminals of the redundant cells are grounded through the reference source line. The read / write terminals of the redundant cells and the read / write terminals of the reference cell are connected to the reference bit line. One end of the reference bit line is connected to the precharge terminal, and the other end of the reference bit line is connected to the negative input terminal of the comparator. The positive input terminal of the comparator is connected to a first reference voltage. The output terminal of the comparator is connected to the enable terminal of the latch comparator through the second delay chain. The read enable signal terminal is connected to the enable terminal of the reference cell and the N word lines through the reference source line and the N first delay chains, respectively. One input terminal of the latch comparator is connected to the bit line of the read memory cell in the resistive random access memory array.

[0010] Furthermore, any redundant unit or reference unit has the same structure as the memory cell in the resistive switching memory array, and the transistors in any redundant unit or reference unit have the same parameters as the transistors in the memory cell in the resistive switching memory array.

[0011] Preferably, the first delay chain and the second delay chain have the same delay duration.

[0012] Furthermore, the first delay chain and the second delay chain include the same number of delay devices, and each delay device has the same delay time.

[0013] Optionally, each first delay chain and second delay chain consists of an even number of NOT gates connected in series.

[0014] In one embodiment, each first delay chain includes a main delay chain and a branch delay chain. N first delay chains share the main delay chain, and N word lines are connected to the main delay chain through their respective branch delay chains.

[0015] In one embodiment, each branch delay chain includes at least one NAND gate, with the first input and output of the NAND gate connected in series in the branch delay chain, and the second input of the NAND gate connected to the address signal of the word line corresponding to the branch delay chain.

[0016] In one embodiment, one end of the reference bit line is connected to the precharge terminal via a switching transistor, and the bit line of the read memory cell is connected to the precharge terminal via a switching transistor.

[0017] In one embodiment, the equivalent resistance of the reference cell is Among them, R H For the high-resistivity state resistance of the resistive switching memory array, R L The low-resistance value of the resistive variable memory array is used, and the reference voltage of the latch comparator is the first reference voltage.

[0018] In one embodiment, the read circuit further includes a negative feedback switching unit, which includes a first terminal, a second terminal, and an output terminal. The first terminal is connected to the read enable signal terminal, and the output terminal of the comparator is also connected to the second terminal. The output terminal of the negative feedback switching unit is connected to the enable terminal of the reference unit and the input terminals of N first delay chains. When the second terminal is in the first state, the negative feedback switching unit is turned on, and when the second terminal is in the second state, the negative feedback switching unit is turned off.

[0019] In one embodiment, the negative feedback switching unit includes an inverter and a NOR gate. The two input terminals of the NOR gate are the first terminal and the second terminal. The read enable signal terminal is connected to the first terminal through the inverter.

[0020] In another embodiment, the negative feedback switching unit is a switching transistor, the input terminal of the switching transistor is the first terminal, the enable terminal of the switching transistor is the second terminal, the read enable signal terminal is connected to the input terminal of the switching transistor, and the switching transistor is a logic control device that is active low.

[0021] In one embodiment, the reference array is a column of memory cells in a resistive switching memory array.

[0022] According to another aspect of the present invention, a memory is also included, which includes a resistive switching memory array and the read circuit of any of the foregoing embodiments.

[0023] This invention matches the parasitic capacitance of the buffer line (BL) in the RRAM array using a reference array, making it possible to control the discharge time of the read memory cell by adjusting the parameters of the reference array. By adjusting the components and number of the first and second delay chains, this invention ensures that the delay durations of the first and second delay chains are identical. This allows the discharge time of the reference array to completely determine the discharge time of the bit line containing the read memory cell after the bit lines in both the reference array and the RRAM array are pre-charged to the same voltage. Furthermore, this invention can achieve fast read speeds by setting the reference voltage value of the latch comparator to generate the minimum differential voltage required for comparison at its two input terminals. By simulating the discharge behavior of the resistance of the memory cells in the RRAM array using a reference array to generate the enable signal for the latch comparator, the read circuit disclosed in this invention is less affected by variations in process technology, temperature, or power supply voltage compared to traditional delay chain structures. This invention also uses a negative feedback switching unit to stop the discharge of the memory column where the read memory cell is located in the reference array and the resistive variable memory array in a timely manner, saving read power consumption. In particular, as the read bandwidth increases, the read circuit can read more bit lines at the same time, and the effect of reducing read power consumption is even more significant. Attached Figure Description

[0024] The above-described features and advantages of this invention will be better understood after reading the detailed description of the embodiments of this disclosure in conjunction with the following accompanying drawings.

[0025] Figure 1 This is a circuit diagram illustrating a prior art delay chain readout circuit according to one aspect of the present invention;

[0026] Figure 2 This is a prior art resistive switching memory array circuit illustrated according to one aspect of the present invention;

[0027] Figure 3 This is a schematic diagram of a reading circuit in one embodiment according to one aspect of the present invention;

[0028] Figure 4This is a schematic diagram of the discharge curve of a storage cell according to one aspect of the present invention;

[0029] Figure 5 This is a schematic diagram of a reading circuit according to one aspect of the present invention;

[0030] Figure 6 This is a schematic diagram of a reading circuit according to one aspect of the present invention, illustrating another embodiment. Detailed Implementation

[0031] The following description is provided to enable those skilled in the art to implement and use the present invention and to incorporate it into specific application contexts. Various modifications and uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein are applicable to a wide range of embodiments. Therefore, the present invention is not limited to the embodiments given herein, but should be granted the broadest scope consistent with the principles and novel features disclosed herein.

[0032] In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that practice of the present invention is not necessarily limited to these specific details. In other words, well-known structures and devices are shown in block diagram form without detailed representation to avoid obscuring the present invention.

[0033] Readers should note all documents and references submitted concurrently with this specification and open to public inspection, the contents of which are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any appended claims, abstracts, and drawings) may be replaced by alternative features for the same, equivalent, or similar purposes. Therefore, unless explicitly stated otherwise, each disclosed feature is merely one example of a set of equivalent or similar features.

[0034] Note that, where used, the markings "first," "second," "left," "right," "front," "back," "top," "bottom," "positive," "negative," "clockwise," and "counterclockwise" are used merely for convenience and do not imply any specific, fixed direction. In fact, they are used to reflect the relative position and / or orientation between different parts of an object. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] Note that, in practice, "further," "preferably," "even further," and "more preferably" are simply starting points for describing another embodiment based on the foregoing embodiments. The combination of the content following "further," "preferably," "even further," or "more preferably" with the foregoing embodiments constitutes the complete configuration of another embodiment. Any combination of several "further," "preferably," "even further," or "more preferably" settings following the same embodiment can form yet another embodiment.

[0036] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the aspects described below with reference to the accompanying drawings and specific embodiments are merely exemplary and should not be construed as limiting the scope of protection of the present invention in any way.

[0037] According to one aspect of the present invention, a read circuit for a resistive variable memory array is provided.

[0038] The resistive variable memory array includes N word lines. Those skilled in the art will understand that the resistive variable memory array includes N word lines, meaning that the resistive variable memory array includes N rows of memory cells, and the enable terminals of the N rows of memory cells are connected to the N word lines one by one.

[0039] This invention does not limit the circuit structure of the resistive random access memory (RRAM) array. The RRAM array can be considered as an array circuit structure with several bit lines and several word lines. The word lines and bit lines are used to control the row address and column address of the RRAM array, respectively. Therefore, by selecting the word lines and bit lines, any memory cell in the RRAM array can be selected. This invention discloses a read circuit for any column of memory cells (memory cells connected to the same bit line) in the RRAM array, but does not limit the internal structure of the RRAM array.

[0040] Figure 2 The circuit structure of a resistive switching memory array in a specific embodiment is shown. For example... Figure 2 As shown, this resistive switching memory array includes: M*N memory cells S, N word lines WL, M source lines SL, M bit lines BL, and a multiplexer MUX. Each memory cell S typically consists of a 1T1R (one transistor + one resistive switching element) structure, storing data by changing the resistance value of the resistive switching element. The word line WL is connected to the enable terminal of the transistor, the bit line BL is connected to the read / write terminal of the transistor, and the source line SL is connected to the reference terminal of the transistor and grounded.

[0041] The reading circuit provided by this utility model can be used to read... Figure 2 The memory cells in any column of the resistive variable memory array shown can also be selected by using a multiplexer to select any column of the resistive variable memory array to read each column of memory cells in the resistive variable memory array.

[0042] In the selected reading embodiment, such as Figure 2 As shown, the resistive variable memory array may also include a multiplexer MUX. The M input terminals of the multiplexer MUX are respectively connected to M bit lines BL, and the output terminal is connected to the bit line connected to the selected column of memory cells.

[0043] It should be noted that, Figure 2 Only a common layout of resistive variable memory array is shown. The read circuit provided by this utility model is also applicable to resistive variable memory arrays with existing or future layouts such as single-ended layout, cross-point layout, and 3D vertical layout.

[0044] For any resistive random access memory (RRAM) array, assuming that each bit line of the RRAM array has N memory cells, the RRAM array includes N word lines. Correspondingly, the read circuit of any bit line of the RRAM array may include a read enable signal terminal, a precharge terminal, a reference array, N first delay chains, a comparator, a second delay chain, and a latch comparator.

[0045] Figure 3 A schematic diagram of the read circuit of a resistive switching memory array in a specific embodiment is shown. For example... Figure 3 As shown, the read circuit of the resistive random access memory array includes: a read enable signal terminal RE, a precharge terminal Vread, a reference array, and N first delay chains C. 11 ~C 1N The system includes a comparator COM, a second delay chain C2, and a latch comparator SA.

[0046] The read enable signal RE is used to input a read enable signal to the read circuit to trigger a read operation.

[0047] The pre-charge terminal Vread is used to provide pre-charge power or read signal power to the reference array or resistive switching memory array, so as to provide energy storage or read voltage for the reference array or resistive switching memory array.

[0048] A reference array is a reference circuit structure designed to match the parasitic characteristics of a resistive random access memory (RRAM) array. By replicating the physical structure (such as cell size, materials, and fabrication process) of the RRAM array, the reference array cancels out the parasitic capacitance in the RRAM array, thereby enabling accurate reading of the stored signals in the RRAM array.

[0049] like Figure 3 As shown, the reference array of the read circuit includes a reference bit line RBL, a reference source line RSL, a reference word line RWL, one reference cell RC, and N-1 redundant cells DC.

[0050] It can be understood that the reference bit line RBL corresponds to the bit line BL connected to the read memory cell in the resistive variable memory column, the reference source line RSL corresponds to the source line SL connected to the read memory cell in the resistive variable memory column, and the reference word line RWL corresponds to the word line WL connected to the read memory cell.

[0051] The reference cell corresponds to the read memory cell in the resistive random access memory array, and there is one reference cell. The redundant cells correspond to the other memory cells on the bit line connected to the read memory cell in the resistive random access memory array, and there are N-1 redundant cells.

[0052] The read / write terminal of the reference cell RC is connected to the reference bit line RBL, the enable terminal of the reference cell RC is connected to the read enable signal terminal RE through the reference word line RWL, and the reference terminal of the reference cell RC is connected to the reference source line RSL.

[0053] The enable and reference terminals of the redundant unit DC are shorted together and grounded through the reference source line RSL. The read and write terminals of the redundant unit DC are connected to the reference bit line.

[0054] One end of the reference bit line RBL is connected to the pre-charge terminal, and the other end is connected to the negative input terminal of comparator COM. The positive input terminal of comparator COM is connected to the first reference voltage. It can be understood that the comparator outputs an electrical signal only when the voltage at the negative input terminal of comparator COM is less than the voltage at its positive input terminal. Therefore, the first reference voltage determines the output signal timing of the comparator. The output terminal of comparator COM is connected to the enable terminal of latch comparator SA via the second delay chain C2.

[0055] A comparator is a circuit element that compares two input signals and outputs a corresponding logic level based on the comparison result. A comparator typically includes a positive input terminal, a negative input terminal, and an output terminal.

[0056] The latch comparator SA includes two input terminals for comparing the input signals at those two terminals. One input terminal of the latch comparator SA is connected to the bit line BL of the memory cell being read, and the other input terminal can be connected to a second reference voltage V2. The voltage comparison result of the two input terminals of the latch comparator SA can be used as the read result of the storage signal of the memory cell being read. When the electrical signal at the output terminal of the comparator COM is output to the enable terminal of the latch comparator SA through the second delay chain C2, the latch comparator SA latches the input voltages at its two input terminals and compares them.

[0057] N first delay chains C 11 ~C 1N With the N word lines WL1~WL of the resistive random access memory array N Corresponding. N first delay chains C 11 ~C1N N word lines WL1 to WL are used to connect the read enable signal RE and the resistive switching memory array, respectively. N When any memory cell is read, the first delay chain corresponding to the word line to which the read memory cell is connected is turned on to drive the read memory cell.

[0058] Preferably, the redundant cell DC or reference cell RC has the same structure as the memory cell in the resistive random access memory (RRAM) array, and the transistors in any redundant cell or reference cell have the same parameters as the transistors in the memory cell in the RRAM array. It can be understood that the reference array provides matching parasitic capacitance to the bit lines connected to the memory cell being read, thereby improving the read accuracy of the memory cell. Therefore, the N-1 redundant cells and 1 reference cell in the RRAM array can be configured to have the same structure as the memory cell in the RRAM array and the same transistor parameters can be selected to improve the matching degree between the reference array and the RRAM array.

[0059] It should be noted that a resistive random access memory (RRAM) array typically comprises multiple RRAM cells, each consisting of one transistor and one resistive switching element. The parasitic capacitance of the RRAM array is primarily composed of the parasitic capacitance of the transistors. The statement that any redundant unit (DC) or reference unit (RC) has the same structure as the memory cells in the RRAM array means that any redundant unit, reference unit, and memory cell in the RRAM array all consist of one transistor and one resistive switching element. Furthermore, to match the parasitic capacitance of the memory cells in the RRAM array, the transistor parameters of any redundant unit, reference unit, and RRAM cell in the RRAM array are identical. However, the connection method between the redundant unit or reference unit and the peripheral circuitry can differ from the connection method between the memory cells and the peripheral circuitry in the RRAM array.

[0060] Reference Figure 3 The enable and reference terminals of the redundant unit DC are grounded through the reference source line RSL, so that the enable terminal is kept at a low level, ensuring that it is never activated and avoiding its influence on the voltage on the reference bit line RBL.

[0061] exist Figure 3 In the illustrated embodiment, during the pre-charging of the read circuit, the pre-charging terminal Vread provides pre-charging power to charge the memory cells in the reference array and the resistive switching memory array.

[0062] During the read operation, the read enable signal RE provides a read enable electrical signal. This signal enables the reference cell RC via the reference word line RWL. The reference cell RC then conducts and begins to discharge. As the reference cell RC discharges, the voltage at the negative input terminal of the comparator COM gradually decreases. Assuming that after the first discharge duration T1, the voltage at the negative input terminal of the comparator COM decreases to the voltage at the positive input terminal of the comparator COM (the first reference voltage), at this point, the output terminal of the comparator COM... The output electrical signal is delayed for a second duration T2 by the second delay chain C2 and then reaches the enable terminal of the latch comparator SA. The latch comparator SA latches the electrical signals at its two input terminals and begins comparison. At the same time, the read enable electrical signal is also delayed for a third duration T3 by the first delay chain connected to the read memory cell and then reaches the enable terminal of the read memory cell. The read memory cell is turned on and begins to discharge. After the read memory cell discharges for T1+T2-T3, the electrical signal at the read and write terminals of the read memory cell is read by the latch comparator SA.

[0063] Figure 4 The discharge curves of the resistive switching memory cell are shown in the high-resistivity (RH) state and the low-resistivity state. The dashed horizontal line represents the reference voltage V. ref When the voltage at the read / write terminal of the resistive switching memory cell is higher than the reference voltage V... ref When the voltage at the read / write terminal of the resistive variable memory cell is lower than the reference voltage V, the resistive variable memory cell is read as 1, corresponding to a low-impedance state; when the voltage at the read / write terminal of the resistive variable memory cell is lower than the reference voltage V, the resistive variable memory cell is read as 1. ref When the resistive variable memory cell is read as 0, it corresponds to a high-impedance state. From Figure 4 As shown in the discharge curves, when the read time is too early, the voltage at the read / write terminals of the memory cells in both high-impedance and low-impedance states may be higher than the reference voltage V. ref When the read time is too late, the voltage at the read / write terminals of the memory cells in both high-impedance and low-impedance states may be lower than the reference voltage V. ref When the resistive switching memory cell is fully discharged but not for an excessively long period, the voltage at the read / write terminals of the memory cell in the high-resistance and low-resistance states will differ from the reference voltage V. ref There is a significant ±ΔV voltage difference, which is understandable given that the voltage presented in the high-resistance and low-resistance states differs from the reference voltage V. ref When there is a significant voltage difference, the reading results are more accurate and less prone to misreading. Assuming the lower limit of the time required for the resistive switching memory cell to fully discharge is t1 and the upper limit is t2, then according to... Figure 4 As shown in the discharge curve, when the discharge time of the read memory cell is greater than t1 and less than t2, the storage signal of the read memory cell is not easily misread.

[0064] according to Figure 3In the illustrated embodiment, the discharge duration of the read memory cell is T1 + T2 - T3. Therefore, the discharge duration of the read memory cell can be controlled by setting the discharge duration T1 of the reference cell RC, the delay duration T2 of the second delay chain C2, and the delay duration T3 of the first delay chain. Specifically, the discharge duration T1 of the reference cell RC is related to the resistance value R of the reference cell RC and the first reference voltage V1 at the positive input terminal of the comparator COM; the delay duration T2 of the second delay chain C2 is related to the number of delay devices on the second delay chain C2 and the delay duration of each delay device; and the delay duration T3 of the first delay chain is related to the number of delay devices on the first delay chain and the delay duration of each delay device. Those skilled in the art can adjust the discharge duration of the read memory cell by setting the resistance value of the reference resistor R of the reference cell RC, the first reference voltage V1, the number of delay devices on the first delay chain, the number of delay devices on the second delay chain C2, and the delay duration of each delay device, so that the discharge duration of the read memory cell is greater than t1 and less than t2.

[0065] A delay chain is a circuit structure that precisely controls the signal transmission time by connecting multiple delay devices in series. The delay devices in a delay chain can consist of existing or future delay-capable devices such as inverter chains, buffer chains, digitally controlled delay lines, or voltage-controlled delay units.

[0066] In a relatively simple way, the number of delay devices on the first delay chain, the number of delay devices on the second delay chain C2, and the delay duration of each delay device can be selected first, so that the delay duration of the first delay chain and the second delay chain are the same. Then the discharge duration of the read memory cell is equal to the discharge duration of the reference cell RC. The discharge duration of the read memory cell can be adjusted by controlling the resistance value of the reference cell RC and the first reference voltage.

[0067] In some specific embodiments, each delay device in the first delay chain and the second delay chain has the same delay time, and the number of delay devices included in the first delay chain and the second delay chain is the same, so as to achieve the same delay time between the first delay chain and the second delay chain.

[0068] Preferably, the first delay chain and the second delay chain can be constructed by an even number of NOT gates connected in series. It can be understood that an even number of NOT gates does not change the polarity of the electrical signal in the circuit.

[0069] More preferably, each first delay chain can also contain a NAND gate connected in series. One input and one output of the NAND gate are connected in series in the first delay chain, while the other input is connected to the address signal of the word line corresponding to that first delay chain. When the address signal is on and the read enable signal is also on, the first delay chain outputs the level signal input to its input after a delay. Therefore, when any first delay chain is on, the address signal can be used to verify whether the memory cell being read is connected to the word line corresponding to that first delay chain, further improving the read accuracy of the read circuit.

[0070] Furthermore, in some embodiments, each first delay chain can be divided into a main delay chain and a branch delay chain. N first delay chains share the main delay chain, and N word lines are connected to the main delay chain through their respective branch delay chains.

[0071] like Figure 3 As shown, the first delay chain C 11 ~C 1N Each circuit includes four delay units S1 to S4. Delay units S1 and S2 are connected in series to form the main delay chain, and delay units S3 and S4 are connected in series to form the branch delay chain. The first delay chain C... 11 ~C 1N A common main delay chain (delay units S1 and S2 connected in series). Delay units S1 and S2 on the main delay chain are NOT gate delay units; delay unit S4 on the branch delay chain is a NOT gate delay unit; delay unit S3 on the branch delay chain is a NAND gate delay unit; the first delay chain C... 11 ~C 1N The other input of the NAND gate delay is connected to the first delay chain C. 11 ~C 1N The corresponding character lines are WL1~WL N Address signals ADD1 to ADD N connect.

[0072] like Figure 3 As shown, the input of the main delay chain is connected to the read enable signal, and the output is connected to the input of N branch delay chains. The output of each branch delay chain is connected to its corresponding word line. Those skilled in the art will understand that in other embodiments, the main delay chain may be either not shared or partially shared.

[0073] exist Figure 3 In the embodiment shown, to match the delay duration of the first delay chain, the second delay chain C2 can be configured as four cascaded NOT gate delayers R1, R2, R3 and R4.

[0074] Preferably, the second reference voltage V2 is set to Figure 4 The V shown ref .

[0075] Preferably, to facilitate control and comparison of the discharge time of the reference cell, the resistance R of the reference cell can be set to... The first reference voltage V1 at the positive input terminal of comparator COM is set to Figure 4 The V shown ref .

[0076] Preferably, the read circuit of the resistive switching memory array provided by this invention may further include a negative feedback switching unit, so as to ensure that the discharge time of the read memory cell reaches... Figure 4 As shown in t1, a feedback signal is generated to disconnect the read enable signal, thereby disconnecting the enable terminals of the reference cell and the read memory cell, stopping the discharge of the reference cell and the read memory cell, thereby reducing the power consumption of the reference cell and the read memory cell during the discharge process. At the same time, it can reduce the power required by the reference cell and the read memory cell in the next charging cycle, effectively reducing read power consumption.

[0077] Figure 5 A circuit diagram of a readout circuit with a negative feedback switching unit is shown in a specific embodiment. For example... Figure 5 As shown, this read circuit is relative to Figure 3 The difference in the illustrated readout circuit lies in the inclusion of a negative feedback switch unit FB1. The negative feedback switch unit FB1 includes a first terminal 1, a second terminal 2, and an output terminal 3. The first terminal 1 is connected to the read enable signal terminal RE, and the output terminal of the comparator COM is connected to the second terminal 2 to form a feedback loop. The output terminal 3 of the negative feedback switch unit FB1 is connected to the enable terminal of the reference unit and the input terminals of the N first delay chains. This negative feedback switch unit is configured such that when the second terminal is in the first state, the negative feedback switch unit is turned on, and when the second terminal is in the second state, the negative feedback switch unit is turned off.

[0078] exist Figure 5In the specific embodiment shown, the negative feedback switching unit FB1 is implemented as including an inverter F1 and a NOR gate F2. The NOR gate F2 includes two input terminals and one output terminal. The output terminal of the inverter F1 is connected to one of the input terminals of the NOR gate F2. The input terminal of the inverter F1 constitutes the first terminal 1 of the negative feedback switching unit FB1, the other input terminal of the NOR gate F2 constitutes the second terminal 2 of the negative feedback switching unit FB1, and the output terminal of the NOR gate F2 constitutes the output terminal 3 of the negative feedback switching unit FB1. When the output of comparator COM is not outputting an electrical signal (low level), the second terminal of NOR gate F2 is at a low level (first state), the negative feedback switch unit FB1 is turned on, and the output terminal 3 of the negative feedback switch unit FB1 directly outputs the signal of the first terminal 1 of the negative feedback switch unit FB1. That is, at this time, when RE is at a high level, the negative feedback switch unit FB1 outputs a high level, and when RE is at a low level, the negative feedback switch unit FB1 outputs a low level. When the output of comparator COM outputs an electrical signal (high level), the second input terminal of NOR gate F2 is at a high level (second state), and NOR gate F2 outputs a low level. That is, at this time, regardless of whether the first terminal 1 of the negative feedback switch unit FB1 is at a high level or a low level, the output terminal 3 of the negative feedback switch unit FB1 outputs a low level, which is equivalent to the negative feedback switch unit FB1 being turned off.

[0079] exist Figure 5 In the illustrated embodiment, when the read enable signal RE is first powered on, the comparator COM has not yet output a comparison result, and the negative feedback switch unit FB1 is equivalent to being turned on. The read enable signal is output to the reference word line RWL to enable the reference unit RC and simultaneously output to the input terminals of the N first delay chains. When the read enable signal is output to the reference word line RWL, the reference unit RC begins to discharge. After the voltage at the read / write terminal of the reference unit RC is less than the first reference voltage V1 after discharging for a period of time, the comparator COM outputs a high-level comparison result. Then, the second delay chain enables the latch comparator SA after a delay period of time. At the same time, the comparator COM outputs a high level to the second terminal 2 of the negative feedback switch unit FB1, and the negative feedback switch unit FB1 is turned off. When the read enable signal is output to the input of the N first delay chains, when the address signal is connected to the NAND gate in any of the first delay chains, the corresponding word line is enabled after the first delay chain is delayed, thereby enabling the memory cell to be read. The memory cell to be read starts to discharge until the negative feedback switch unit FB1 is turned off, the enable terminal of the memory cell to be read is pulled low, the memory cell to be read stops discharging, and the latch comparator SA reads the signal of the read and write terminals of the memory cell when it is enabled.

[0080] Figure 6A circuit diagram of the read circuit in another specific embodiment is shown. In this embodiment, the negative feedback switching unit FB1 is implemented as a switching transistor M1. The input terminal of the switching transistor M1 is the first terminal 1 of the negative feedback switching unit FB1, the enable terminal of the switching transistor M1 is the second terminal 2 of the negative feedback switching unit FB1, the read enable signal terminal RE is connected to the input terminal of the switching transistor M1, and the output terminal of the switching transistor M1 constitutes the output terminal 3 of the negative feedback switching unit FB1. The switching transistor M1 is a logic control device active low, such as a PMOS transistor or a PNP transistor. When the output terminal of the comparator COM does not output an electrical signal, the switching transistor M1 is turned on, and the signal of the read enable signal terminal RE is directly output to the input terminals of the reference word line RWL and the N first delay chains; when the output terminal of the comparator COM outputs a high level, the switching transistor M1 is turned off, and the input terminals of the reference word line RWL and the N first delay chains are pulled low. The specific working process is the same as... Figure 5 The operation of the reading circuit shown is similar and will not be described again here.

[0081] Preferably, in some specific embodiments, reference is made to Figure 3 The reference bit line RBL can also be connected to the precharge terminal V via a switching transistor. read The bit line BL of the read memory cell can also be connected to the precharge terminal V via a switching transistor. read The connection enables control over the pre-charge process of the reference array and the resistive switching memory array.

[0082] like Figure 5 or Figure 6 As shown, the reference bit line RBL is connected to the precharge terminal V through the switching transistor M2. read The bit line BL of the read memory cell is connected to the precharge terminal V through the switching transistor M3. read connect.

[0083] According to another aspect of the present invention, a memory is also provided. The memory includes a resistive switching memory array and a read circuit for the resistive switching memory array in any of the foregoing embodiments.

[0084] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. However, it should be understood that the scope of protection of this utility model should be determined by the appended claims and should not be limited to the specific structures and components of the embodiments described above. Those skilled in the art can make various changes and modifications to the embodiments, and these changes and modifications also fall within the scope of protection of this utility model.

Claims

1. A read circuit for a resistive switching memory array, the resistive switching memory array comprising N word lines, characterized in that, The read circuit includes: a read enable signal terminal, a precharge terminal, a reference array, N first delay chains, a comparator, a second delay chain, and a latch comparator. The reference array includes a reference bit line, a reference source line, a reference word line, N-1 redundant cells, and one reference cell. The enable and reference terminals of the redundant cells are grounded through the reference source line. The read / write terminals of the redundant cells and the reference cell are connected to the reference bit line. One end of the reference bit line is connected to the precharge terminal, and the other end is connected to the negative input terminal of the comparator. The positive input terminal of the comparator is connected to a first reference voltage. The output terminal of the comparator is connected to the enable terminal of the latch comparator through the second delay chain. The read enable signal terminal is connected to the enable terminal of the reference cell and the N word lines through the reference source line and the N first delay chains, respectively. One input terminal of the latch comparator is connected to the bit line of the read memory cell in the resistive variable memory array.

2. The read circuit for resistive switching memory array of claim 1, wherein, Any redundant unit or the reference unit has the same structure as the memory cell in the resistive switching memory array, and the transistors in any redundant unit or the reference unit have the same parameters as the transistors in the memory cell in the resistive switching memory array.

3. The read circuit for resistive switching memory array of claim 1, wherein, The first delay chain and the second delay chain have the same delay duration.

4. The read circuit for resistive switching memory array of claim 3, wherein, The first delay chain and the second delay chain include the same number of delay devices, and each delay device has the same delay time.

5. The read circuit for resistive switching memory array of claim 3, wherein, Each of the first delay chain and the second delay chain consists of an even number of NOT gates connected in series.

6. The read circuit for resistive switching memory array of claim 1, wherein, Each first delay chain includes a main delay chain and branch delay chains. The N first delay chains share the main delay chain, and the N word lines are respectively connected to the main delay chain through their corresponding branch delay chains.

7. The read circuit for resistive switching memory array of claim 6, wherein, Each branch delay chain includes at least one NAND gate, the first input and output of which are connected in series in the branch delay chain, and the second input of which is connected to the address signal of the word line corresponding to the branch delay chain.

8. The read circuit for resistive switching memory array as claimed in claim 1, wherein, One end of the reference bit line is connected to the precharge terminal via a switching transistor, and the bit line of the read memory cell is connected to the precharge terminal via a switching transistor.

9. The read circuit for resistive switching memory array as claimed in claim 1, wherein, An equivalent resistance of the reference unit is wherein R H is a high resistance state resistance value of the resistive random access memory array, R L is a low resistance state resistance value of the resistive random access memory array, and the reference voltage of the latch comparator is the first reference voltage.

10. The read circuit for resistive switching memory array of claim 1, wherein, It also includes a negative feedback switching unit, which includes a first terminal, a second terminal, and an output terminal. The first terminal is connected to the read enable signal terminal, and the output terminal of the comparator is also connected to the second terminal. The output terminal of the negative feedback switching unit is connected to the enable terminal of the reference unit and the input terminals of the N first delay chains. When the second terminal is in the first state, the negative feedback switching unit is turned on, and when the second terminal is in the second state, the negative feedback switching unit is turned off.

11. The read circuit for resistive switching memory array of claim 10, wherein, The negative feedback switching unit includes an inverter and a NOR gate. The two input terminals of the NOR gate are the first terminal and the second terminal. The read enable signal terminal is connected to the first terminal through the inverter.

12. The read circuit for resistive switching memory array of claim 10, wherein, The negative feedback switch unit is a switch tube, an input end of the switch tube is the first end, an enable end of the switch tube is the second end, the read enable signal end is connected to the input end of the switch tube, and the switch tube is a low-level effective logic control device.

13. The read circuit for resistive switching memory array as claimed in claim 1, wherein, The reference array is a column of memory cells in the resistive switching memory array.

14. A memory, comprising: The read circuit comprises a resistive switching memory array and is as claimed in any one of claims 1-13.

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