Solar charging pile circuit and device

Abstract

The utility model provides a solar charging pile circuit and device, and relates to the field of charging piles. The circuit comprises an input overcurrent protection unit, a countercurrent overcurrent protection unit, a voltage reduction unit, a first power supply generation unit, an input power detection unit, a relay control unit and a charging management unit which are connected in series, and further comprises a second power supply generation unit which is connected with the first power supply generation unit in parallel. According to the circuit, signals are cut off through the input over-current protection unit and the reverse current over-current protection unit when power supply signals are in forward or reverse over-current; the voltage reduction unit is used for reducing the voltage of the power signal; the first and second power generation units are respectively stabilized to different voltages; the input power detection unit is used for monitoring the output power of the solar panel in real time; the relay control unit is used for receiving the trigger signal to cut off the charging loop; the charging management unit is used for adjusting charging current / voltage. According to the scheme, the performance level of the solar charging pile can be maintained and even improved while the circuit structure is simplified and the cost is reduced.

Description

Technical Field

[0001] This application relates to the field of charging piles, and more specifically, to a solar charging pile circuit and device. Background Technology

[0002] Solar charging stations, due to their clean and sustainable characteristics, have become an important component of electric vehicle charging infrastructure. Their core function is to efficiently and safely convert solar energy into electrical energy and to achieve intelligent charging and discharging management of the battery. However, current solar charging stations, in order to enhance their advantages in overcurrent protection, power stability, power detection, and charging management, mostly employ extremely complex structures. While increased complexity improves the performance and safety of solar charging stations, it also leads to increased costs and maintenance difficulties. Therefore, how to simplify the structure, reduce costs, while maintaining or even improving existing performance levels has become a pressing technical problem to be solved. Utility Model Content

[0003] To address the aforementioned issues, this application provides a solar charging pile circuit and device that can maintain or even improve the performance level of the solar charging pile while simplifying the circuit structure and reducing costs.

[0004] This application is implemented as follows:

[0005] In a first aspect, this application provides a solar charging pile circuit, which includes an input overcurrent protection unit, a reverse overcurrent protection unit, a step-down unit, a first power generation unit, an input power detection unit, a relay control unit, and a charging management unit connected in series, and also includes a second power generation unit connected in parallel with the first power generation unit. The input terminal of the input overcurrent protection unit is used to receive the power signal output from the solar panel. The input overcurrent protection unit and the reverse overcurrent protection unit are used to cut off the power signal when the received power signal experiences forward and reverse overcurrent, respectively. The step-down unit is used to step down the received power signal to obtain a stepped-down voltage. The first power generation unit is used to stabilize the stepped-down voltage to a first voltage, and the second power generation unit is used to stabilize the stepped-down voltage to a second voltage. The input power detection unit is used to detect the output power of the solar panel in real time. The relay control unit is used to receive trigger signals output by the input overcurrent protection unit and the reverse overcurrent protection unit and cut off the charging circuit. The charging management unit is used to adjust the charging current / voltage.

[0006] Secondly, this application provides a solar charging pile device, which includes any of the solar charging pile circuits described in the first aspect.

[0007] Compared with the prior art, this application has at least the following advantages or beneficial effects:

[0008] This application optimizes the circuit topology, simplifying the circuit structure and reducing costs while maintaining or even improving the performance of solar charging piles. Specifically, by setting up a series input overcurrent protection unit and a reverse overcurrent protection unit, it can quickly cut off the signal when the power signal experiences forward or reverse overcurrent, effectively preventing equipment damage or safety accidents caused by overcurrent and significantly improving the safety performance of the charging pile.

[0009] Secondly, the introduction of the step-down unit, the first power generation unit, and the second power generation unit enables this application to efficiently step down and stabilize the power signal output from the solar panel to different voltage levels, meeting the power voltage requirements of different circuit modules within the charging pile. Simultaneously, this graded voltage regulation design also improves power stability, further ensuring the reliable operation of the charging pile.

[0010] Furthermore, the real-time detection function of the input power detection unit enables this application to accurately determine the output power of the solar panel, providing an important basis for formulating charging strategies. This helps to maximize the utilization efficiency of solar energy and avoid energy waste.

[0011] In addition, the introduction of the relay control unit enables the charging pile to quickly cut off the charging circuit when it receives the trigger signal of the overcurrent protection unit, preventing the fault from spreading and improving the overall safety of the system.

[0012] Finally, the adjustment function of the charging management unit enables this application to flexibly adjust the charging current and voltage according to the actual state of the battery and user needs, thereby extending battery life, improving charging efficiency, and optimizing user experience. Attached Figure Description

[0013] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a circuit block diagram of one embodiment of a solar charging pile circuit according to this application;

[0015] Figure 2 This is a circuit schematic diagram of the input overcurrent protection unit in one embodiment of the circuit of this application;

[0016] Figure 3 This is a circuit schematic diagram of the reverse current overcurrent protection unit in one embodiment of the circuit of this application;

[0017] Figure 4AThis is a partial circuit schematic diagram of the step-down unit in one embodiment of the circuit of this application;

[0018] Figure 4B This is a partial circuit schematic diagram of the step-down unit in one embodiment of the circuit of this application;

[0019] Figure 4C This is a partial circuit schematic diagram of the step-down unit in one embodiment of the circuit of this application;

[0020] Figure 5A This is a partial circuit schematic diagram of the first power generation unit in one embodiment of the circuit of this application;

[0021] Figure 5B This is a partial circuit schematic diagram of the first power generation unit in one embodiment of the circuit of this application;

[0022] Figure 6A This is a partial circuit schematic diagram of the second power generation unit in one embodiment of the circuit of this application;

[0023] Figure 6B This is a partial circuit schematic diagram of the second power generation unit in one embodiment of the circuit of this application;

[0024] Figure 7 This is a circuit schematic diagram of the input power detection unit in one embodiment of the circuit of this application;

[0025] Figure 8 This is a circuit schematic diagram of a relay control unit in one embodiment of the circuit of this application;

[0026] Figure 9 This is a circuit schematic diagram of the charging management unit in one embodiment of the circuit of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] Example:

[0030] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the various embodiments and features described below can be combined with each other.

[0031] Please refer to Figure 1 The solar charging pile circuit includes an input overcurrent protection unit, a reverse overcurrent protection unit, a step-down unit, a first power generation unit, an input power detection unit, a relay control unit, and a charging management unit connected in series. It also includes a second power generation unit connected in parallel with the first power generation unit. The input overcurrent protection unit receives the power signal output from the solar panel. The input overcurrent protection unit and the reverse overcurrent protection unit cut off the power signal when the received power signal experiences forward and reverse overcurrent, respectively. The step-down unit reduces the voltage of the received power signal to a stepped-down voltage. The first power generation unit stabilizes the stepped-down voltage to a first voltage, and the second power generation unit stabilizes the stepped-down voltage to a second voltage. The input power detection unit detects the output power of the solar panel in real time. The relay control unit receives trigger signals from the input overcurrent protection unit and the reverse overcurrent protection unit and cuts off the charging circuit. The charging management unit adjusts the charging current / voltage.

[0032] In the above embodiment, the input overcurrent protection unit is located at the very beginning of the circuit and is directly connected to the power signal output by the solar panel. When the current in the power signal exceeds a preset threshold (i.e., forward overcurrent), it immediately cuts off the power signal to prevent equipment damage or safety accidents. The reverse overcurrent protection unit is similar to the input overcurrent protection unit, but focuses on detecting and cutting off reverse overcurrent. When the current direction in the power signal is abnormal (i.e., reverse flow) and exceeds a certain threshold, this unit quickly cuts off the power signal. The step-down unit is responsible for receiving the power signal after overcurrent protection and converting it into a step-down voltage suitable for subsequent circuit processing through a step-down circuit. This ensures that other units in the circuit can operate within a safe voltage range, avoiding equipment damage caused by excessive voltage. The first power generation unit and the second power generation unit are connected in parallel, respectively stabilizing the step-down voltage output by the step-down unit to different voltage levels (first voltage and second voltage). These stable power supply voltages provide the required power to different circuit modules inside the charging pile. This hierarchical voltage regulation design improves the stability of the power supply and ensures the normal operation of each component of the charging pile. This design also increases circuit flexibility, allowing the charging station to adapt to different voltage requirements. The input power detection unit monitors the solar panel's output power in real time and feeds the detected data back to the charging station's control system. This provides crucial information for developing charging strategies, helping to maximize solar energy utilization efficiency and avoid energy waste. The relay control unit receives trigger signals from the input overcurrent protection unit and the reverse overcurrent protection unit. When these units detect an overcurrent condition, they send a signal to the relay control unit. Upon receiving the signal, the relay control unit immediately cuts off the charging circuit to prevent the fault from spreading. This improves overall circuit safety and prevents further damage to equipment or escalation of safety accidents caused by overcurrent. The charging management unit intelligently manages the battery's charging and discharging by adjusting the charging current and voltage according to the battery's actual state and user needs. This includes the selection and implementation of various charging strategies such as constant current charging and constant voltage charging.

[0033] In other words, this application firstly sets up a series input overcurrent protection unit and a reverse overcurrent protection unit, which can quickly cut off the signal when the power signal experiences forward or reverse overcurrent, effectively preventing equipment damage or safety accidents caused by overcurrent and significantly improving the safety performance of the charging pile. This design directly solves the problems of slow response or incomplete protection that may exist in the overcurrent protection mechanism of the prior art.

[0034] Secondly, the introduction of the step-down unit, the first power generation unit, and the second power generation unit enables this application to efficiently step down and stabilize the power signal output from the solar panel to different voltage levels, meeting the power voltage requirements of different circuit modules within the charging pile. Simultaneously, this graded voltage regulation design also improves power stability, further ensuring the reliable operation of the charging pile.

[0035] Furthermore, the real-time detection function of the input power detection unit enables this application to accurately determine the output power of the solar panel, providing an important basis for formulating charging strategies. This helps to maximize the utilization efficiency of solar energy and avoid energy waste.

[0036] In addition, the design of the relay control unit enables the charging pile to quickly cut off the charging circuit when it receives the trigger signal from the overcurrent protection unit, preventing the fault from spreading and improving the overall safety of the system.

[0037] Finally, the adjustment function of the charging management unit enables this application to flexibly adjust the charging current and voltage according to the actual state of the battery and user needs, thereby extending battery life, improving charging efficiency, and optimizing user experience.

[0038] Please refer to Figure 2 Based on the aforementioned scheme, in some implementations of this application, the input overcurrent protection unit includes an LM393 voltage comparator chip U32.2, resistors R70 and R69, and diode D22. Pin 5 of the comparator chip U32.2 is connected to resistor R70, and pin 5 of the comparator chip U32.2 is also connected to the power signal output from the solar panel via resistor R69. Pin 7 of the comparator chip U32.2 is connected to the cathode of diode D22.

[0039] In the above implementation, pin 5 of the voltage comparator chip U32.2 is connected to resistor R70 to form a reference voltage input terminal. Pin 5 of the voltage comparator chip U32.2 is also connected to the power signal output by the solar panel through resistor R69 to monitor the input current. When the input current exceeds a preset threshold, pin 7 of the voltage comparator chip U32.2 outputs a high-level signal. This signal triggers a subsequent protection mechanism through diode D22, cutting off the power signal.

[0040] Please refer to Figure 3Based on the aforementioned scheme, in some implementations of this application, the reverse current overcurrent protection unit includes an LM393 voltage comparator chip U32.1, resistors R53 and R55, and diode D23. Specifically, pin 3 of voltage comparator chip U32.1 is connected to resistor R55, and pin 3 of voltage comparator chip U32.1 is also connected to pin 8 of voltage comparator chip U32.1 via resistor R53. Pin 1 of voltage comparator chip U32.1 is connected to the cathode of diode D23, and pin 4 of voltage comparator chip U32.1 is grounded and connected to pin 6 of comparator chip U32.2.

[0041] In the above implementation, pin 3 of voltage comparator chip U32.1 is connected to resistor R55 to receive the voltage input from the power supply signal; pin 3 is also connected to pin 8 through resistor R53 to form a reference voltage input terminal; pin 1 is connected to the cathode of diode D23 to output a protection signal; pin 4 is grounded and connected to pin 6 of voltage comparator chip U32.2 to form a corresponding interlocking mechanism. When the power supply signal flows in reverse and the current exceeds a preset threshold, pin 1 of voltage comparator chip U32.1 outputs a high-level signal, which triggers the subsequent protection circuit through diode D23 to cut off the power supply signal.

[0042] Please refer to Figure 4A , Figure 4B and Figure 4CBased on the aforementioned scheme, in some implementations of this application, the step-down unit includes MOSFETs Q3, Q4, Q9, and Q10, fuses F1 and F2, terminal blocks CN5, U4, and U5, half-bridge driver chips U6 and U11, diodes D3 and D7, transistors Q1 and Q11, MOSFETs Q5, Q6, Q12, and Q13, inductor L3, diodes D10, D2, D8, D6, D5, D4, D20, D9, D19, D18, D1, and resistors. Resistors R30, R41, R42, R43, R48, R11, R17, R22, R49, R50, R23, R40, R10, R9, R37, R39, R34, R44, R26, R27, R35, R24, R25, R33, R32, R28, R29, R31, C30, C11, C17, C18, C16, C31, C24, C14, C15, C21, C22, C42, C43, and C36. Specifically, pin 1 of terminal block U4 is connected to the anode of diode D7, pin 1 of terminal block U4 is connected to the cathode of diode D10 through fuse F1, the anode of diode D10 is connected to pin 2 of terminal block U4 through resistor R30, pin 2 of terminal block U4 is connected to resistor R55, capacitors C30 and C11 are connected in parallel with diode D10, the common terminal of capacitor C30 and fuse F1 is connected to the drain of field-effect transistor Q9, the cathode of diode D7 is connected to the cathode of diode D3, and the anode of diode D3 is connected to pin 2 of terminal block CN5. Pin 1 of terminal block U5 is connected to pin COM of half-bridge driver chip U11 through resistor R31. Pin 2 of terminal block U5 is connected to the anode of diode D2. The cathode of diode D2 is connected to the cathode of diode D7. Pin 2 of terminal block U5 is connected to the cathode of diode D8 through fuse F2. The anode of diode D8 is connected to pin COM of half-bridge driver chip U11. Capacitors C17 and C18 are connected in parallel with diode D8.The VCC pin of half-bridge driver chip U11 is connected to the VB pin of half-bridge driver chip U11 through diode D6. The VCC pin of half-bridge driver chip U11 is connected to the COM pin of half-bridge driver chip U11 through parallel capacitors C16 and C31. The IN pin of half-bridge driver chip U11 is connected to resistor R32. The IN pin of half-bridge driver chip U11 is connected to the COM pin of half-bridge driver chip U11 through resistor R29. The VB pin of half-bridge driver chip U11 is connected to the VS pin of half-bridge driver chip U11 through capacitor C24. The HO pin of half-bridge driver chip U11 is connected to the cathode of diode D4. The anode of diode D4 is connected to the VS pin of half-bridge driver chip U11 through resistor R26. The LO pin of half-bridge driver chip U11 is connected to the anode of diode D5 through resistor R25. The anode of diode D5 is connected to the base of transistor Q1. The cathode of diode D5 is connected to the emitter of transistor Q1. Resistor R24 ​​is connected in parallel with diode D4. The anode of diode D4 is connected to the gate of MOSFET Q5. The source of MOSFET Q5 is connected to the collector of transistor Q1 via resistor R34, capacitor C14, resistor R44, capacitor C15, and resistor R35. Resistors R37 and R34 are connected in parallel, as are resistors R44 and R39. The common terminal of capacitor C15 and resistor R35 is connected to the source of MOSFET Q6. The common terminal of capacitor C15 and resistor R35 is connected to the source of MOSFET Q6 via diode D20. The drain of MOSFET Q6 is connected to the source of MOSFET Q5. The gate of MOSFET Q6 is connected to the emitter of transistor Q1. The gate of MOSFET Q6 is connected to the collector of transistor Q1 via resistor R27. The drain of MOSFET Q6 is connected to the common terminal of capacitor C14 and resistor R44. The drain of MOSFET Q6 is connected to pin VS of half-bridge driver chip U11. The common terminal of capacitor C14 and resistor R44 is connected to pin VS of half-bridge driver chip U6 through inductor L3. Pin IN of half-bridge driver chip U6 is connected to resistor R42. Pin IN of half-bridge driver chip U6 is connected to the source of MOSFET Q12 through resistor R43. Pin VCC of half-bridge driver chip U6 is connected to the source of MOSFET Q12 through parallel capacitors C36 and C43. Pin SD# of half-bridge driver chip U6 is connected to the source of MOSFET Q12 through resistor R48. Pin SD# of half-bridge driver chip U6 is connected to resistor R41. Pin VCC of half-bridge driver chip U6 is connected to the anode of diode D1. The cathode of diode D1 is connected to pin VB of half-bridge driver chip U6. Pin VB of half-bridge driver chip U6 is connected to pin VS of half-bridge driver chip U6 through capacitor C42.Pin HO of half-bridge driver chip U6 is connected to the gate of MOSFET Q13 through resistor R17. Resistor R17 and diode D19 are connected in parallel. The gate of MOSFET Q13 is connected to pin VS of half-bridge driver chip U6 through resistor R50. Pin LO of half-bridge driver chip U6 is connected to the base of transistor Q11 through resistor R11. The base of transistor Q11 is connected to the emitter of transistor Q11 through diode D18. The emitter of transistor Q11 is connected to the collector of transistor Q11 through resistor R49. The emitter of transistor Q11 is connected to the gate of MOSFET Q12. The drain of MOSFET Q12 is connected to the source of MOSFET Q13. The source of MOSFET Q12 is connected to the drain of MOSFET Q13 in sequence through capacitor C22, resistor R23, capacitor C21 and resistor R40. The source of MOSFET Q12 is connected to the COM pin of half-bridge driver chip U6. Resistors R9 and R23 are connected in parallel, and resistors R10 and R40 are connected in parallel. The anode of diode D9 is connected to the drain of MOSFET Q12, and the cathode of diode D9 is connected to the drain of MOSFET Q13. The common terminal of capacitor C21 and resistor R23 is connected to the anode of diode D9. The drain of MOSFET Q3 is connected to the drain of MOSFET Q5, the gate of MOSFET Q3 is connected to the gate of MOSFET Q5, the source of MOSFET Q3 is connected to the drain of MOSFET Q4, the source of MOSFET Q4 is grounded, the gate of MOSFET Q4 is connected to the emitter of transistor Q1, the gate of MOSFET Q9 is connected to the gate of MOSFET Q13, the source of MOSFET Q9 is connected to the drain of MOSFET Q12, the source of MOSFET Q9 is connected to the drain of MOSFET Q10, the gate of MOSFET Q10 is connected to the emitter of transistor Q11, and the source of MOSFET Q10 is grounded.

[0043] In the above implementation, the input power signal is connected to the circuit through terminal blocks U4 and U5, and after being protected by fuses F1 and F2, it enters the step-down circuit. Half-bridge driver chips U6 and U11, according to control signals, drive MOSFETs Q5, Q6, Q12, and Q13 to switch, respectively, thus stepping down the input high-voltage power signal. Field-effect transistors Q3, Q4, Q9, and Q10 act as auxiliary switching elements, working in conjunction with the main switching elements to achieve circuit switching. Diodes D3, D7, and D10 are used for rectification and protection circuits to ensure stable operation under normal working conditions. Resistors and capacitors are used for voltage division, current limiting, and filtering to improve power quality and stability. Inductor L3, together with nearby capacitors, forms an LC filter circuit to reduce output voltage ripple.

[0044] Please refer to Figure 5A and Figure 5BBased on the aforementioned scheme, in some implementations of this application, the first power generation unit includes a voltage regulator chip U2 of type MP9486A, a voltage regulator chip U8 of type STI3470, a voltage regulator chip U35 of type AMS1117-3.3, an inductor L1, an inductor L4, a diode D14, a diode D12, a diode D36, a resistor R18, a resistor R19, a resistor R51, a resistor R52, a capacitor C20, a capacitor C26, a capacitor C33, a capacitor C23, a capacitor C37, a capacitor C12, a capacitor C38, a capacitor C8, a capacitor C53, a capacitor C59, a capacitor C60, a capacitor C40, and a capacitor C54. In this configuration, the pin of voltage regulator chip U2 is connected to the cathode of diode D2. The pin of voltage regulator chip U2 is grounded through a series of capacitors C26, C33, and C20 connected in parallel. Pin 4 of voltage regulator chip U2 is connected to pin 5 through capacitor C23. Pin 1 of voltage regulator chip U2 is connected to the anode of diode D12 through resistor R19. Pin 1 of voltage regulator chip U2 is then connected to the cathode of diode D12 through resistor R18 and inductor L1. Pin 5 of voltage regulator chip U2 is connected to the cathode of diode D12. The anode of diode D12 is grounded. Capacitor C37 and resistor R18 are connected in parallel. The common terminal of inductor L1 and capacitor C37 is grounded through a series of capacitors D14, C12, C38, C8, and C53 connected in parallel. The cathode of diode D14 is connected to voltage regulator chip U8. Pin 5 of voltage regulator chip U8 is connected to pin 6 of voltage regulator chip U8 via capacitor C40. Pin 3 of voltage regulator chip U8 is grounded via resistor R51. Pin 3 of voltage regulator chip U8 is connected to pin 6 of voltage regulator chip U8 via resistor R52 and inductor L4 in sequence. Pin 3 of voltage regulator chip U35 is connected to the common terminal of inductor L4 and resistor R52. Pin 3 of voltage regulator chip U35 is connected to pin 1 of voltage regulator chip U35 via capacitor C54. Pin 3 of voltage regulator chip U35 is connected to the cathode of diode D36. The anode of diode D36 is connected to pin 1 of voltage regulator chip U35. Pin 1 of voltage regulator chip U35 is grounded. Pin 2 of voltage regulator chip U35 is connected to pin 4 of voltage regulator chip U35. Pin 4 of voltage regulator chip U35 is grounded via parallel capacitors C59 and C60.

[0045] In the above implementation, voltage regulator chip U2 acts as the main regulator, responsible for converting the input voltage into a stable intermediate voltage. Voltage regulator chip U8 further stabilizes the voltage, providing the necessary power for specific circuits. Voltage regulator chip U35 generates a stable 3.3V output, powering low-voltage circuits. Inductors L1 and L4, together with capacitors, form a filter circuit to reduce output voltage ripple. Diodes D12, D14, and D36 are used for rectification and protection circuits, ensuring circuit stability and safety. Resistors R18, R19, R51, and R52 are used for voltage division, current limiting, and providing necessary bias voltage. Capacitors C20, C26, C33, C23, C37, C12, C38, C8, C53, C40, C54, C59, and C60 are used for filtering, energy storage, and voltage stabilization, ensuring a smooth and accurate output voltage.

[0046] The input voltage is first initially regulated by the MP9486A voltage regulator chip U2 to generate a stable intermediate voltage. This regulation process is filtered by capacitors C26, C33, and C20 connected in parallel to reduce voltage fluctuations. The output of the voltage regulator chip U2 forms a step-down and rectification circuit together with a diode D12 through a circuit consisting of a resistor R18 and an inductor L1. Capacitor C37 is connected in parallel with resistor R18 for further filtering. The stepped-down voltage is filtered and protected by a diode D14 and a series of capacitors in parallel (capacitors C12, C38, C8, and C53), and then sent to the STI3470 voltage regulator chip U8 for further regulation. The output voltage of the voltage regulator chip U8 is filtered by a resistor R52 and an inductor L4, and then sent to the AMS1117-3.3 voltage regulator chip U35 to generate a final stable 3.3V output. The output of the voltage regulator chip U35 is filtered by capacitors C59 and C60 connected in parallel to ensure a stable and accurate output voltage. Meanwhile, diode D36 is used for protection circuitry to prevent reverse voltage from damaging the voltage regulator chip U35.

[0047] Please refer to Figure 6A and Figure 6BBased on the aforementioned scheme, in some implementations of this application, the second power generation unit includes an ESP32-S chip U1, terminal blocks CN1, CN2, CN3, CN6, and H1, an EC11 encoder SW5, a MOSFET Q7, LED1, LED3, a diode D21, capacitors C1, C2, C3, C25, C50, C32, C34, and C35, and resistors R38, R12, R15, R16, R5, R6, R7, R4, R1, R2, R14, and R20. Specifically, pin 1 of chip U1 is connected to pin 3 of chip U1 through capacitor C2; pin 1 of chip U1 is connected to pin 2 of chip U1 through parallel capacitors C1 and C25; pin 2 of chip U1 is connected to pin 6 of chip U1 through resistor R14; pin 2 of chip U1 is connected to pin 7 of chip U1 through resistor R20; pin 2 of chip U1 is connected to pin 5 of chip U1 through resistor R1; pin 2 of chip U1 is connected to terminal 1 of terminal block CN3; terminal 2 of terminal block CN3 is connected to pin 5 of chip U1; pin 5 of chip U1 is grounded through parallel resistor R2 and capacitor C3; pin 8 of chip U1 is connected to resistor R33; pin 9 of chip U1 is connected to resistor R32; and pin 14 of chip U1 is connected to terminal block CN6. Terminal 8 is connected. Pin 13 of chip U1 is connected to terminal 7 of terminal block CN6. Pin 11 of chip U1 is connected to terminal 6 of terminal block CN6. Pin 10 of chip U1 is connected to terminal 5 of terminal block CN6. Pin 16 of chip U1 is connected to terminal 4 of terminal block CN6. Pin 24 of chip U1 is connected to terminal 3 of terminal block CN6. Terminal 2 of terminal block CN6 is connected to pin 4 of voltage regulator chip U35. Pin 25 of chip U1 is connected to pin 36 of chip U1 after passing through resistors R5 and R6. Pin 33 of chip U1 is connected to pin 4 of voltage regulator chip U35 through resistor R7. The common terminal of resistors R5 and R6 is connected to pin 4 of voltage regulator chip U35. Pin 26 of chip U1 is connected to resistor R41.Pin 27 of chip U1 is connected to the gate of MOSFET Q7. The gate of MOSFET Q7 is connected to the source of MOSFET Q7 through resistor R38. The source of MOSFET Q7 is grounded. The drain of MOSFET Q7 is connected to terminal 1 of terminal block CN1. Terminal 1 of terminal block CN1 is connected to terminal 2 of terminal block CN1 through a parallel capacitor C50 and diode D21. Pin 30 of chip U1 is connected to pin 1 of encoder SW5. Pin 1 of encoder SW5 is connected to pin 3 of encoder SW5 through capacitors C32 and C34 connected in series. The common terminal of capacitors C32 and C34 is grounded. Pin 5 of encoder SW5 is connected to pin 4 of encoder SW5 through capacitor C35. Pin 5 of encoder SW5 is connected to pin 37 of chip U1. Pin 1 of encoder SW5 is connected to pin 30 of chip U1. Pin 3 of encoder SW5 is connected to pin 31 of chip U1. Pin 34 of chip U1 is connected to terminal 2 of terminal block H1 through resistor R16. Pin 35 of chip U1 is connected to terminal 3 of terminal block H1 through resistor R15. Terminal 3 of terminal block H1 is connected to the anode of LED3 through resistor R12. The cathode of LED3 is connected to pin 4 of voltage regulator chip U35. Terminal 1 of terminal block H1 is connected to pin 4 of voltage regulator chip U35. Terminal 1 of terminal block CN2 is connected to pin 4 of voltage regulator chip U35. Terminal 2 of terminal block CN2 is connected to pin 33 of chip U1. Terminal 3 of terminal block CN2 is connected to pin 36 of chip U1.

[0048] In the above implementation, the ESP32-S chip U1 serves as the core control unit, responsible for handling logic control, data communication, and other functions in the circuit. The ESP32-S chip supports dual-mode Wi-Fi and Bluetooth communication and can communicate with external devices via various interfaces such as I2C, SPI, and UART. Terminal blocks CN1, CN2, CN3, CN6, and H1 are used to connect external circuits or devices, providing power input and signal output functions. The EC11 encoder SW5 is used to control fan speed or other devices requiring speed adjustment. The encoder outputs pulse signals, which are then processed by the ESP32-S chip to achieve precise control of the device. The MOSFET Q7 acts as a switching element, controlling the circuit's on / off state. In this application, the MOSFET Q7 is controlled by the ESP32-S chip to switch the power supply to the fan or other loads. Light-emitting diodes (LED1, LED3) are used to indicate the circuit's operating status or provide error alarms. The on / off state of the LEDs is controlled by the ESP32-S chip through the control of relevant pin levels. Diode D21 is used to protect the circuit from damage caused by reverse current. Capacitors C1, C2, C3, C25, C50, C32, C34, and C35 are used for filtering, energy storage, and voltage stabilization to ensure normal circuit operation. Resistors R38, R12, R15, R16, R5, R6, R7, R4, R1, R2, R14, and R20 are used for current limiting, voltage division, and providing necessary bias voltage.

[0049] The input power supply is connected to the circuit via terminal block CN3, and filtered by capacitors (C1 and C2) to reduce power supply noise and ripple, providing a stable power supply for the ESP32-S chip and other components. The ESP32-S chip connects and communicates with external components through its multiple GPIO pins. For example, by controlling the gate level of MOSFET Q7, power switching for fans or other loads can be achieved; by reading the output pulse signal of encoder SW5, precise control of fan speed or other equipment can be achieved. The on / off state of LEDs LED1 and LED3 indicates the circuit's operating status or provides an alarm. For example, LED1 is constantly lit when the circuit is working normally; LED3 flashes as an alarm when an error occurs. The inclusion of protective components such as diode D21 effectively prevents damage to the circuit from reverse current and overcurrent, improving the circuit's reliability and safety.

[0050] Please refer to Figure 7Based on the aforementioned scheme, in some implementations of this application, the input power detection unit includes an INA226 chip U14, capacitors C10 and C19, resistors R3 and R13. Pin 3 of chip U14 is connected to pin 7 of chip U1, pin 4 of chip U14 is connected to pin 33 of chip U1, pin 5 of chip U14 is connected to pin 36 of chip U1, pin 6 of chip U14 is connected to pin 7 of chip U14 via capacitor C10, pin 7 of chip U14 is connected to pin 8 of chip U14 via resistor R3, pin 8 of chip U14 is connected to the drain of MOSFET Q5, and pin 10 of chip U14 is connected to pin 9 of chip U14 via capacitor C19.

[0051] Chip U14 is a high-precision, low-power current and voltage monitoring chip. It converts monitored voltage and current signals into digital signals via an internally integrated ADC (Analog-to-Digital Converter) and transmits them to the microcontroller via an I2C interface. In the above implementation, chip U14 is responsible for monitoring the voltage and current values ​​of the input power. Capacitors C10 and C19 are used for filtering, reducing noise and ripple in the voltage and current signals and improving monitoring accuracy. Resistors R3 and R13 are used for voltage division, reducing the high input voltage signal to an acceptable range for chip U14 and providing the necessary bias voltage. MOSFET Q5 is used for current sampling; its drain is connected to the current monitoring pin of chip U14 to obtain the current signal.

[0052] The input voltage signal is divided by a resistor divider network (including resistors R3 and R13, etc.) and then connected to the voltage monitoring pins (pins 3 and 7) of chip U14. The internal ADC of chip U14 converts the analog voltage signal into a digital signal and transmits it to the microcontroller via the I2C interface. The current signal, after being acquired (sampled using MOSFET Q5), is connected to the current monitoring pins of chip U14 (e.g., pin 8). Chip U14 also converts the analog current signal into a digital signal and transmits it via the I2C interface. After receiving the voltage and current digital signals transmitted from chip U14, the microcontroller can perform simple multiplication to calculate the input power.

[0053] Please refer to Figure 8Based on the aforementioned scheme, in some implementations of this application, the relay control unit includes a voltage regulator chip U36 of model MP9486A, terminal blocks OUT1, OUT2, and OUT, relays U18 and U17, inductor L7, MOSFETs Q14 and Q8, inductor L7, diodes D35, D24, and D25, capacitor C61, resistors R56 and R57. In this circuit, pin 5 of voltage regulator chip U36 is connected to pin 4 of chip U14 via capacitor C61. Pin 5 of voltage regulator chip U36 is connected to the cathode of diode D35. The cathode of diode D35 is connected to the cathode of diode D3. The anode of diode D35 is grounded. The cathode of diode D35 is connected to the cathode of diode D24 via inductor L7. The cathode of diode D24 is connected to the cathode of diode D25. The cathode of diode D24 is connected to pin 1 of relay U17. The anode of diode D24 is connected to pin 6 of relay U17. Pin 2 of relay U17 is connected to terminal 2 of terminal block OUT1. Pin 3 of relay U17 is connected to terminal 1 of terminal block OUT1. The anode of diode D24 is connected to the drain of MOSFET Q8. The gate of MOSFET Q8 is connected to the source of MOSFET Q8 through resistor R56. The gate of MOSFET Q8 is connected to terminal 2 of terminal block OUT. Terminal 2 of terminal block OUT is connected to pin 28 of chip U1. Terminal 3 of terminal block OUT is connected to the gate of MOSFET Q14. The gate of MOSFET Q14 is connected to the source of MOSFET Q14 through resistor R57. The drain of MOSFET Q14 is connected to the anode of diode D25. The anode of diode D25 is connected to pin 6 of relay U18. The cathode of diode D25 is connected to pin 1 of relay U18. Pin 2 of relay U18 is connected to terminal 2 of terminal block OUT2. Pin 3 of relay U18 is connected to terminal 1 of terminal block OUT2.

[0054] In the above implementation, the voltage regulator chip U36, as a high-voltage step-down switching regulator, is responsible for stabilizing the input voltage to a level suitable for relay operation. Through its internal feedback mechanism and switching control, it outputs a stable voltage, providing reliable power to subsequent circuits. Terminal blocks OUT1, OUT2, and OUT are used to connect the relays and external circuits, enabling power transmission and control signal delivery. Relays U18 and U17 control two different circuit paths. Inductor L7 stores and releases energy, smooths the current waveform, and reduces electromagnetic interference. Diodes D35 and D3 form a simple reverse connection protection circuit, while diodes D24 and D25 protect relays U17 and U18, respectively. Capacitor C61 filters, reducing voltage fluctuations and noise, and improving circuit stability. Resistors R56 and R57 limit current, protect MOSFETs Q14 and Q8, and adjust their switching characteristics.

[0055] The input voltage is regulated by the MP9486A chip U36, providing a stable output voltage to power the relay control circuit. The microcontroller (such as ESP32-S) outputs control signals through its GPIO pins. These signals, after passing through resistors R56 and R57, drive the gates of MOSFETs Q14 and Q8, respectively. When MOSFET Q14 or Q8 is turned on, current flows through the corresponding diodes (diode D24 or D25) into the relay coil, causing the relay contacts to close or open, thus controlling the on / off state of the external circuit. Diodes D35, D24, D25, and D3 together form a protection circuit to prevent damage to components from reverse current and overvoltage. Simultaneously, inductor L7 and capacitor C61 also smooth the current waveform and reduce electromagnetic interference.

[0056] Please refer to Figure 9 Based on the aforementioned scheme, in some implementations of this application, the charging management unit includes an INA226 chip U15, capacitors C7, C27, and C28, and resistors R45 and R46. Pin 3 of chip U15 is connected to pin 6 of chip U1, pin 4 of chip U15 is connected to pin 6 of chip U1, pin 10 of chip U15 is connected to pin 2 of terminal block U4, pin 10 of chip U15 is connected to pin 9 of chip U15 via capacitor C27, pin 8 of chip U15 is connected to the drain of MOSFET Q13 via resistor R45, pin 8 of chip U15 is connected to pin 7 of chip U15 via resistor R46, pin 7 of chip U15 is grounded, and pin 8 of chip U15 is grounded via parallel capacitors C7 and C28.

[0057] Chip U15 is a high-precision, low-power current and voltage monitoring chip. It converts monitored voltage and current signals into digital signals via its integrated ADC (Analog-to-Digital Converter) and transmits them to the microcontroller via I2C or other communication interfaces. In the above implementation, chip U15 is responsible for monitoring voltage and current values ​​during the charging process, ensuring safety and efficiency. Capacitors C7, C27, and C28 are used for filtering and decoupling, reducing noise and ripple in the voltage and current signals and improving monitoring accuracy. Capacitor C27 is specifically used to connect pins 10 and 9 of chip U15, forming a low-pass filter to further smooth the current signal. Capacitors C7 and C28 are connected in parallel and grounded to provide a stable reference potential for chip U15.

[0058] Resistors R45 and R46 are used for voltage division and current limiting. Resistor R45 converts the current signal monitored by chip U15 into a voltage signal suitable for controlling MOSFET Q13, while resistor R46 is connected to pin 7 (ground potential) and pin 8 (current monitoring output) of chip U15, forming a feedback network to adjust the sensitivity of current monitoring. The drain of MOSFET Q13 receives the voltage signal from resistor R45, the gate is driven by a control signal, and the source is grounded or connected to other circuits. Terminal block U4 is used to connect an external charging power supply or battery, and as an interface with other circuit modules. Pin 2 of terminal block U4 is connected to pin 10 of chip U15 for transmitting charging current or as an input for current monitoring.

[0059] During charging, the input voltage and current are monitored by chip U15. Pins 3 and 4 of chip U15 receive voltage signals, while pin 10 receives current signals (input via pin 2 of U4). The internal ADC of chip U15 converts these analog signals into digital signals and transmits them to the microcontroller via a communication interface (such as I2C). Based on the voltage and current data transmitted by chip U15, the microcontroller determines the charging status and may adjust the on / off state of the charging circuit or the magnitude of the charging current by controlling the gate voltage of MOSFET Q13. For example, when an overcurrent condition is detected, the microcontroller can turn off MOSFET Q13, cutting off the charging circuit to protect the battery and the circuit system.

[0060] This application also provides a solar charging pile device, which includes the solar charging pile circuit described above. The device can be constructed by encapsulating the circuit board containing the solar charging pile circuit within a housing, thus facilitating user operation and providing convenience.

[0061] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A solar charging pile circuit, characterized in that, It includes an input overcurrent protection unit, a reverse overcurrent protection unit, a step-down unit, a first power generation unit, an input power detection unit, a relay control unit, and a charging management unit connected in series, and also includes a second power generation unit connected in parallel with the first power generation unit; The system includes an input overcurrent protection unit for receiving the power signal output from the solar panel, and an input overcurrent protection unit and a reverse overcurrent protection unit for cutting off the power signal when it experiences overcurrent in the forward and reverse directions, respectively. A step-down unit reduces the input power signal to a step-down voltage. A first power generation unit stabilizes the step-down voltage to a first voltage, and a second power generation unit stabilizes the step-down voltage to a second voltage. An input power detection unit detects the output power of the solar panel in real time. A relay control unit receives trigger signals from the input overcurrent protection unit and the reverse overcurrent protection unit and cuts off the charging circuit. A charging management unit adjusts the charging current / voltage.

2. The circuit of claim 1, wherein, The input overcurrent protection unit includes an LM393 voltage comparator chip U32.2, resistors R70 and R69, and diode D22; Specifically, pin 5 of the comparator chip U32.2 is connected to resistor R70, and pin 5 of the comparator chip U32.2 is also connected to the power signal output by the solar panel through resistor R69. Pin 7 of the comparator chip U32.2 is connected to the cathode of diode D22.

3. The circuit of claim 2, wherein, The reverse current overcurrent protection unit includes an LM393 voltage comparator chip U32.1, resistors R53 and R55, and diode D23; In this circuit, pin 3 of the voltage comparator chip U32.1 is connected to resistor R55, pin 3 of the voltage comparator chip U32.1 is also connected to pin 8 of the voltage comparator chip U32.1 through resistor R53, pin 1 of the voltage comparator chip U32.1 is connected to the cathode of diode D23, pin 4 of the voltage comparator chip U32.1 is grounded and connected to pin 6 of comparator chip U32.

2.

4. The circuit of claim 3, wherein, The step-down unit includes MOSFETs Q3, Q4, Q9, and Q10; fuses F1 and F2; terminal blocks CN5, U4, and U5; half-bridge driver chips U6 and U11; diodes D3 and D7; transistors Q1 and Q11; MOSFETs Q5, Q6, Q12, and Q13; inductor L3; diodes D10, D2, D8, D6, D5, D4, D20, D9, D19, D18, and D1; resistors R30 and R41; and a circuit breaker. Resistors R42, R43, R48, R11, R17, R22, R49, R50, R23, R40, R10, R9, R37, R39, R34, R44, R26, R27, R35, R24, R25, R33, R32, R28, R29, R31; Capacitors C30, C11, C17, C18, C16, C31, C24, C14, C15, C21, C22, C42, C43, and C36; Wherein, pin 1 of terminal block U4 is connected to the anode of diode D7, pin 1 of terminal block U4 is connected to the cathode of diode D10 through fuse F1, the anode of diode D10 is connected to pin 2 of terminal block U4 through resistor R30, pin 2 of terminal block U4 is connected to resistor R55, capacitor C30 and capacitor C11 are connected in parallel with diode D10, the common terminal of capacitor C30 and fuse F1 is connected to the drain of field-effect transistor Q9, the cathode of diode D7 is connected to the cathode of diode D3, and the anode of diode D3 is connected to pin 2 of terminal block CN5; Pin 1 of the terminal block U5 is connected to pin COM of the half-bridge driver chip U11 through resistor R31. Pin 2 of the terminal block U5 is connected to the anode of diode D2. The cathode of diode D2 is connected to the cathode of diode D7. Pin 2 of the terminal block U5 is connected to the cathode of diode D8 through fuse F2. The anode of diode D8 is connected to pin COM of the half-bridge driver chip U11. Capacitors C17 and C18 are connected in parallel with diode D8. The VCC pin of the half-bridge driver chip U11 is connected to the VB pin of the half-bridge driver chip U11 through the diode D6. The VCC pin of the half-bridge driver chip U11 is connected to the COM pin of the half-bridge driver chip U11 through the parallel capacitors C16 and C31. The IN pin of the half-bridge driver chip U11 is connected to the resistor R32. The IN pin of the half-bridge driver chip U11 is connected to the COM pin of the half-bridge driver chip U11 through the resistor R29. Pin VB of chip U11 is connected to pin VS of half-bridge driver chip U11 through capacitor C24. Pin HO of half-bridge driver chip U11 is connected to the cathode of diode D4. The anode of diode D4 is connected to pin VS of half-bridge driver chip U11 through resistor R26. Pin LO of half-bridge driver chip U11 is connected to the anode of diode D5 through resistor R25. The anode of diode D5 is connected to the base of transistor Q1, and the cathode of diode D5 is connected to the emitter of transistor Q1. The resistor R24 ​​is connected in parallel with the diode D4. The anode of the diode D4 is connected to the gate of the MOSFET Q5. The source of the MOSFET Q5 is connected to the collector of the transistor Q1 via the resistor R34, the capacitor C14, the resistor R44, the capacitor C15, and the resistor R35 in sequence. The resistors R37 and R34 are connected in parallel, and the resistors R44 and R39 are connected in parallel. The common terminal of the capacitor C15 and the resistor R35 is connected to the source of the MOSFET Q6. The common terminal of resistor R35 is connected to the source of MOSFET Q6 through diode D20. The drain of MOSFET Q6 is connected to the source of MOSFET Q5. The gate of MOSFET Q6 is connected to the emitter of transistor Q1. The gate of MOSFET Q6 is connected to the collector of transistor Q1 through resistor R27. The drain of MOSFET Q6 is connected to the common terminal of capacitor C14 and resistor R44. The drain of MOSFET Q6 is connected to pin VS of half-bridge driver chip U11. The common terminal of capacitor C14 and resistor R44 is connected to pin VS of half-bridge driver chip U6 through inductor L3. Pin IN of half-bridge driver chip U6 is connected to resistor R42. Pin IN of half-bridge driver chip U6 is connected to the source of MOSFET Q12 through resistor R43. Pin VCC of half-bridge driver chip U6 is connected to the source of MOSFET Q12 through capacitors C36 and C43 connected in parallel. Pin SD# of half-bridge driver chip U6 is connected to the source of MOSFET Q12 through resistor R48. Pin SD# of half-bridge driver chip U6 is connected to resistor R41. Pin VCC of half-bridge driver chip U6 is connected to the anode of diode D1. The cathode of diode D1 is connected to pin VB of half-bridge driver chip U6. Pin VB of half-bridge driver chip U6 is connected to pin VS of half-bridge driver chip U6 through capacitor C42. Pin HO of the half-bridge driver chip U6 is connected to the gate of the MOSFET Q13 through resistor R17. Resistor R17 and diode D19 are connected in parallel. The gate of the MOSFET Q13 is connected to pin VS of the half-bridge driver chip U6 through resistor R50. Pin LO of the half-bridge driver chip U6 is connected to the base of transistor Q11 through resistor R11. The base of transistor Q11 is connected to the emitter of transistor Q11 through diode D18. The emitter of transistor Q11 is connected to the collector of transistor Q11 through resistor R49. The emitter of transistor Q11 is connected to the gate of the MOSFET Q12. The drain of MOSFET Q12 is connected to the source of MOSFET Q13. The source of MOSFET Q12 is connected to the drain of MOSFET Q13 via capacitor C22, resistor R23, capacitor C21, and resistor R40. The source of MOSFET Q12 is connected to pin COM of half-bridge driver chip U6. Resistor R9 is connected in parallel with resistor R23, and resistor R10 is connected in parallel with resistor R40. The anode of diode D9 is connected to the drain of MOSFET Q12, and the cathode of diode D9 is connected to the drain of MOSFET Q13. The common terminal of capacitor C21 and resistor R23 is connected to the anode of diode D9. The drain of the field-effect transistor Q3 is connected to the drain of the MOSFET Q5, the gate of the field-effect transistor Q3 is connected to the gate of the MOSFET Q5, the source of the field-effect transistor Q3 is connected to the drain of the field-effect transistor Q4, the source of the field-effect transistor Q4 is grounded, the gate of the field-effect transistor Q4 is connected to the emitter of the transistor Q1, the gate of the field-effect transistor Q9 is connected to the gate of the MOSFET Q13, the source of the field-effect transistor Q9 is connected to the drain of the MOSFET Q12, the source of the field-effect transistor Q9 is connected to the drain of the field-effect transistor Q10, the gate of the field-effect transistor Q10 is connected to the emitter of the transistor Q11, and the source of the field-effect transistor Q10 is grounded.

5. The circuit of claim 4, wherein, The first power generation unit includes a voltage regulator chip U2 of model MP9486A, a voltage regulator chip U8 of model STI3470, a voltage regulator chip U35 of model AMS1117-3.3, an inductor L1, an inductor L4, a diode D14, a diode D12, a diode D36, a resistor R18, a resistor R19, a resistor R51, a resistor R52, a capacitor C20, a capacitor C26, a capacitor C33, a capacitor C23, a capacitor C37, a capacitor C12, a capacitor C38, a capacitor C8, a capacitor C53, a capacitor C59, a capacitor C60, a capacitor C40, and a capacitor C54; In this configuration, the pin of the voltage regulator chip U2 is connected to the cathode of the diode D2. The pin of the voltage regulator chip U2 is grounded through a series of capacitors C26, C33, and C20 connected in parallel. Pin 4 of the voltage regulator chip U2 is connected to pin 5 through capacitor C23. Pin 1 of the voltage regulator chip U2 is connected to the anode of the diode D12 through resistor R19. Pin 1 of the voltage regulator chip U2 is connected to the cathode of the diode D12 through resistor R18 and inductor L1. Pin 5 of the voltage regulator chip U2 is connected to the cathode of the diode D12. The anode of the diode D12 is grounded. Capacitor C37 is connected in parallel with resistor R18. The common terminal of inductor L1 and capacitor C37 is grounded through a series of capacitors D14, C12, C38, C8, and C53 connected in parallel. The cathode of diode D14 is connected to the cathode of the diode D2. Pin 5 of voltage regulator chip U8 is connected. Pin 1 of voltage regulator chip U8 is connected to pin 6 of voltage regulator chip U8 through capacitor C40. Pin 3 of voltage regulator chip U8 is grounded through resistor R51. Pin 3 of voltage regulator chip U8 is connected to pin 6 of voltage regulator chip U8 through resistor R52 and inductor L4 in sequence. Pin 3 of voltage regulator chip U35 is connected to the common terminal of inductor L4 and resistor R52. Pin 3 is connected to pin 1 of the voltage regulator chip U35 through capacitor C54. Pin 3 of the voltage regulator chip U35 is connected to the cathode of diode D36. The anode of diode D36 is connected to pin 1 of the voltage regulator chip U35. Pin 1 of the voltage regulator chip U35 is grounded. Pin 2 of the voltage regulator chip U35 is connected to pin 4 of the voltage regulator chip U35. Pin 4 of the voltage regulator chip U35 is grounded through capacitors C59 and C60 connected in parallel.

6. The circuit of claim 5, wherein, The second power generation unit includes an ESP32-S chip U1, terminal blocks CN1, CN2, CN3, CN6, and H1, an EC11 encoder SW5, a MOSFET Q7, LED1, LED3, a diode D21, capacitors C1, C2, C3, C25, C50, C32, C34, and C35, and resistors R38, R12, R15, R16, R5, R6, R7, R4, R1, R2, R14, and R20. Specifically, pin 1 of chip U1 is connected to pin 3 of chip U1 through capacitor C2; pin 1 of chip U1 is connected to pin 2 of chip U1 through capacitors C1 and C25 connected in parallel; pin 2 of chip U1 is connected to pin 6 of chip U1 through resistor R14; pin 2 of chip U1 is connected to pin 7 of chip U1 through resistor R20; pin 2 of chip U1 is connected to pin 5 of chip U1 through resistor R1; pin 2 of chip U1 is connected to terminal 1 of terminal block CN3; terminal 2 of terminal block CN3 is connected to pin 5 of chip U1; pin 5 of chip U1 is grounded through resistor R2 and capacitor C3 connected in parallel; pin 8 of chip U1 is connected to resistor R33; pin 9 of chip U1 is connected to resistor R32; and pin 14 of chip U1 is connected to the terminal block... Terminal 8 of terminal block CN6 is connected; pin 13 of chip U1 is connected to terminal 7 of terminal block CN6; pin 11 of chip U1 is connected to terminal 6 of terminal block CN6; pin 10 of chip U1 is connected to terminal 5 of terminal block CN6; pin 16 of chip U1 is connected to terminal 4 of terminal block CN6; pin 24 of chip U1 is connected to terminal 3 of terminal block CN6; terminal 2 of terminal block CN6 is connected to pin 4 of voltage regulator chip U35; pin 25 of chip U1 is connected to pin 36 of chip U1 via resistors R5 and R6; pin 33 of chip U1 is connected to pin 4 of voltage regulator chip U35 via resistor R7; the common terminal of resistors R5 and R6 is connected to pin 4 of voltage regulator chip U35; and pin 26 of chip U1 is connected to resistor R41. Pin 27 of chip U1 is connected to the gate of MOSFET Q7. The gate of MOSFET Q7 is connected to the source of MOSFET Q7 through resistor R38. The source of MOSFET Q7 is grounded. The drain of MOSFET Q7 is connected to terminal 1 of terminal block CN1. Terminal 1 of terminal block CN1 is connected to terminal 2 of terminal block CN1 through capacitor C50 and diode D21 connected in parallel. Pin 30 of chip U1 is connected to pin 1 of encoder SW5. Pin 1 of encoder SW5 is connected to pin 3 of encoder SW5 through capacitors C32 and C34 connected in series. The common terminal of capacitors C32 and C34 is grounded. Pin 4 of encoder SW5 is connected to pin 37 of chip U1 through capacitor C35. Pin 1 of encoder SW5 is connected to pin 30 of chip U1, pin 3 of encoder SW5 is connected to pin 31 of chip U1, pin 34 of chip U1 is connected to terminal 2 of terminal block H1 through resistor R16, pin 35 of chip U1 is connected to terminal 3 of terminal block H1 through resistor R15, terminal 3 of terminal block H1 is connected to the anode of light-emitting diode LED3 through resistor R12, the cathode of light-emitting diode LED3 is connected to pin 4 of voltage regulator chip U35, terminal 1 of terminal block H1 is connected to pin 4 of voltage regulator chip U35, terminal 2 of terminal block CN2 is connected to pin 33 of chip U1, and terminal 3 of terminal block CN2 is connected to pin 36 of chip U1.

7. The circuit of claim 6, wherein, The input power detection unit includes an INA226 chip U14, capacitors C10 and C19, resistors R3 and R13. Specifically, pin 3 of chip U14 is connected to pin 7 of chip U1, pin 4 of chip U14 is connected to pin 33 of chip U1, pin 5 of chip U14 is connected to pin 36 of chip U1, pin 6 of chip U14 is connected to pin 7 of chip U14 through capacitor C10, pin 7 of chip U14 is connected to pin 8 of chip U14 through resistor R3, pin 8 of chip U14 is connected to the drain of MOSFET Q5, and pin 10 of chip U14 is connected to pin 9 of chip U14 through capacitor C19.

8. The circuit of claim 7, wherein, The relay control unit includes a voltage regulator chip U36 of model MP9486A, terminal blocks OUT1, OUT2, and OUT, relays U18 and U17, inductor L7, MOSFETs Q14 and Q8, inductor L7, diodes D35, D24, and D25, capacitor C61, resistors R56 and R57; In this configuration, pin 5 of the voltage regulator chip U36 is connected to pin 4 of the chip U14 via capacitor C61. Pin 5 of the voltage regulator chip U36 is connected to the cathode of diode D35. The cathode of diode D35 is connected to the cathode of diode D3. The anode of diode D35 is grounded. The cathode of diode D35 is connected to the cathode of diode D24 via inductor L7. The cathode of diode D24 is connected to the cathode of diode D25. The cathode of diode D24 is connected to pin 1 of relay U17. The anode of diode D24 is connected to pin 6 of relay U17. Pin 2 of relay U17 is connected to terminal 2 of terminal block OUT1. Pin 3 of relay U17 is connected to terminal 1 of terminal block OUT1. The anode of diode D24 is connected to the drain of MOSFET Q8. The gate of the MOSFET Q8 is connected to the source of the MOSFET Q8 through the resistor R56. The gate of the MOSFET Q8 is connected to terminal 2 of the terminal block OUT. Terminal 2 of the terminal block OUT is connected to pin 28 of the chip U1. Terminal 3 of the terminal block OUT is connected to the gate of the MOSFET Q14. The gate of the MOSFET Q14 is connected to the source of the MOSFET Q14 through the resistor R57. The drain of the MOSFET Q14 is connected to the anode of the diode D25. The anode of the diode D25 is connected to pin 6 of the relay U18. The cathode of the diode D25 is connected to pin 1 of the relay U18. Pin 2 of the relay U18 is connected to terminal 2 of the terminal block OUT2. Pin 3 of the relay U18 is connected to terminal 1 of the terminal block OUT2.

9. A circuit according to claim 8, characterised in that, The charging management unit includes an INA226 chip U15, capacitors C7, C27, and C28, and resistors R45 and R46. Specifically, pin 3 of chip U15 is connected to pin 6 of chip U1, pin 4 of chip U15 is connected to pin 6 of chip U1, pin 10 of chip U15 is connected to pin 2 of terminal block U4, pin 10 of chip U15 is connected to pin 9 of chip U15 through capacitor C27, pin 8 of chip U15 is connected to the drain of MOSFET Q13 through resistor R45, pin 8 of chip U15 is connected to pin 7 of chip U15 through resistor R46, pin 7 of chip U15 is grounded, and pin 8 of chip U15 is grounded through capacitors C7 and C28 connected in parallel.

10. A solar charging station device, characterized by, Includes a solar charging pile circuit as described in any one of claims 1-9.

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