High linearity voltage-time converter for mixed domain ADC
By using a constant current source to charge the common-mode capacitor, the current source mismatch problem is solved, ensuring the linearity and power consumption of the voltage-time converter, and realizing a high-linearity voltage-time converter design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NO 24 RES INST OF CETC
- Filing Date
- 2026-01-14
- Publication Date
- 2026-04-21
AI Technical Summary
Traditional constant current voltage-time converters are susceptible to current mismatch between current sources, and the charge stored on the sampling capacitor is kicked back to the input voltage source at the beginning of each sampling phase, affecting the next sampling and resulting in low linearity.
A constant current VTC structure is adopted, which uses a constant current source to charge the common mode capacitor to ensure that the voltage on the two sampling capacitors rises or falls at the same rate, generating a ramp signal with the same slope, and generating a time difference signal through a threshold comparison circuit.
It improves the linearity of the voltage-time converter, reduces power consumption, has a simple structure, low design complexity, is easy to implement with integrated circuits, and has a low manufacturing cost.
Smart Images
Figure CN121907249A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog-to-digital converter circuits, and in particular relates to a high linearity voltage-time converter for mixed-domain ADCs. Background Technology
[0002] Analog-to-digital converters (ADCs) are a crucial bridge connecting the analog natural world and the digital computational world, and are an essential step in computers processing analog signals from the natural world. With the development of wireless communication networks, the market demand for ADCs is constantly expanding, and their performance requirements are continuously increasing.
[0003] In a voltage-to-time mixed-domain ADC, the voltage-to-time converter (VTC) is responsible for converting the residual voltage signal in the voltage domain into a time signal, which is then provided to the subsequent time-domain quantizer for quantization. Therefore, the VTC acts as a bridge between the voltage and time domains, and a high-linearity VTC is crucial for ensuring the accuracy of subsequent time-domain quantization, making it a key module for the overall performance of the mixed-domain ADC.
[0004] Constant current type VTCs charge and discharge the sampling capacitor using a constant current source, ensuring a constant rate of voltage change across the sampling capacitor. This results in high linearity, high robustness, and low power consumption, and is currently widely used. However, traditional constant current type VTCs typically use two independent constant current sources to charge and discharge two sampling capacitors, which is susceptible to the effects of current mismatch between the current sources. Furthermore, the charge stored on the sampling capacitor is kicked back to the input voltage source at the beginning of each sampling phase, potentially affecting the next sample. Therefore, it is necessary to design a constant current type VTC that uses only a single constant current source, thereby eliminating the problem of current source mismatch while maintaining low power consumption and high robustness, and improving linearity. Summary of the Invention
[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is to provide a high linearity voltage-time converter for mixed-domain ADCs.
[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A high linearity voltage-time converter for mixed-domain ADCs, comprising A constant current source circuit is used to output a constant charging current; A ramp generation circuit is used to generate a common-mode ramp signal with a corresponding slope based on the charging current output by a constant current source circuit. The common-mode ramp signal is used to generate a first ramp signal and a second ramp signal based on the positive residual signal Vresp and the negative residual signal Vresn, respectively. A threshold comparison circuit is used to compare the first ramp signal and the second ramp signal with a preset reference voltage, and generate a first rising edge signal and a second rising edge signal based on the comparison result. The time difference between the first rising edge signal and the second rising edge signal is proportional to the voltage difference between the first ramp signal and the second ramp signal.
[0007] Furthermore, the constant current source circuit includes a constant current source I1, a current mirror, and an output switch. The first end of the current mirror is electrically connected to the constant current source I1, the second end of the current mirror is electrically connected to the first end of the output switch, the second end of the output switch serves as the output end of the constant current source circuit and is electrically connected to the ramp generation circuit, and the control end of the output switch is connected to the clock signal CLK.
[0008] Furthermore, the current mirror is a common-source common-gate current mirror, the output switch is defined as a PMOS transistor PM5, the source of the PMOS transistor PM5 is the first terminal of the output switch, the drain of the PMOS transistor PM5 is the second terminal of the output switch, and the gate of the PMOS transistor PM5 is the control terminal of the output switch.
[0009] Furthermore, the current mirror includes PMOS transistors PM1, PM2, PM3, and PM4; the sources of PMOS transistors PM1 and PM3 are both connected to the power supply voltage VDD; the gate of PMOS transistor PM1 is electrically connected to its drain, the gate of PMOS transistor PM3, and the source of PMOS transistor PM2; the gate of PMOS transistor PM2, after being electrically connected to its drain and the gate of PMOS transistor PM4, serves as the first terminal of the current mirror and is electrically connected to the first terminal of a constant current source I1, the second terminal of which is grounded; the drain of PMOS transistor PM3 is electrically connected to the source of PMOS transistor PM4, and the drain of PMOS transistor PM4 serves as the second terminal of the current mirror and is electrically connected to the source of PMOS transistor PM5.
[0010] Furthermore, the hole mobility, gate oxide capacitance per unit area, threshold voltage, and channel length modulation coefficient of the PMOS transistors PM1, PM2, PM3, and PM4 are all equal.
[0011] Furthermore, the width-to-length ratios of PMOS transistors PM1 and PM3 are equal, and the width-to-length ratios of PMOS transistors PM2 and PM4 are equal.
[0012] Furthermore, the ramp generation circuit includes a common-mode capacitor Ccm, a sampling capacitor Cs1, a sampling capacitor Cs2, an operational amplifier AMP1, an operational amplifier AMP2, a switch SW1, a switch SW2, and a switch SW3; The positive input terminal of the operational amplifier AMP1 is used to connect to the positive residual signal Vresp. The negative input terminal of the operational amplifier AMP1 is electrically connected to its output terminal and the first terminal of the switch SW1 respectively. The second terminal of the switch SW1 is electrically connected to the first terminal of the sampling capacitor Cs1 and then serves as the first output terminal of the ramp generation circuit and is electrically connected to the first input terminal of the threshold comparison circuit. The positive input terminal of the operational amplifier AMP2 is used to connect the negative residual signal Vresn. The negative input terminal of the operational amplifier AMP2 is electrically connected to its output terminal and the first terminal of the switch SW2. The second terminal of the switch SW2 is electrically connected to the first terminal of the sampling capacitor Cs2 and then serves as the second output terminal of the ramp generation circuit and is electrically connected to the second input terminal of the threshold comparison circuit. The second terminal of the sampling capacitor Cs1 is electrically connected to the second terminal of the sampling capacitor Cs2 and the first terminal of the common-mode capacitor Ccm, respectively, and then serves as the input terminal of the ramp generation circuit and is electrically connected to the constant current source circuit; the second terminal of the common-mode capacitor Ccm is grounded, and the switch SW3 is connected in parallel with the common-mode capacitor Ccm.
[0013] Furthermore, the threshold comparison circuit includes two threshold comparison units. The positive input terminals of the two threshold comparison units are respectively connected to the first and second input terminals of the threshold comparison circuit and electrically connected to the first and second output terminals of the ramp generation circuit. The negative input terminals of the two threshold comparison units are both connected to a preset reference voltage Vref. The output terminals of the two threshold comparison units are respectively used as the first and second output terminals of the threshold comparison circuit to output a first rising edge signal and a second rising edge signal.
[0014] Furthermore, the threshold comparison unit includes PMOS transistors PM6, PM7, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, capacitor C1, inverter INV1, and inverter INV2. The source of PMOS transistor PM6 and the source of PMOS transistor PM7 are both connected to the power supply voltage VDD. The gate of PMOS transistor PM6 is electrically connected to its drain, the gate of PMOS transistor PM7 and the drain of NMOS transistor NM1, respectively. The gate of NMOS transistor NM1 serves as the input terminal of the threshold comparison unit. The drain of PMOS transistor PM7 is electrically connected to the drain of NMOS transistor NM2, the first terminal of capacitor C1, the drain of NMOS transistor NM5, and the input terminal of inverter INV1, respectively; the gate of NMOS transistor NM2 is connected to the reference voltage Vref; the source of NMOS transistor NM1 and the source of NMOS transistor NM2 are both electrically connected to the drain of NMOS transistor NM3, and the gate of NMOS transistor NM3 is connected to the common-mode voltage Vcm; The source of NMOS transistor NM3 is electrically connected to the drain of NMOS transistor NM4, the gate of NMOS transistor NM4 is connected to the clock signal CLK, and the source of NMOS transistor NM4 is grounded. The second terminal of capacitor C1 is grounded, and the gate of NMOS transistor NM5 is connected to the input inverted clock signal. The source of the NMOS transistor NM5 is grounded; the inverted clock signal This is the inverted signal of the clock signal CLK; The output terminal of inverter INV1 is connected to the input terminal of inverter INV2; the output terminal of inverter INV2 serves as the output terminal of the threshold comparison unit.
[0015] Furthermore, the common-mode voltage Vcm is half of the power supply voltage VDD.
[0016] This invention provides a novel constant-current VTC structure. By charging a common-mode capacitor with a constant current source, the voltages on the two sampling capacitors rise or fall at the same rate, thereby generating ramp signals with the same slope on both sampling capacitors. This not only reduces power consumption but also solves the problem of current mismatch between independent current sources, improving linearity. Furthermore, this invention features a simple structure, low design complexity, small footprint, and is easy to implement in integrated circuits, resulting in lower manufacturing costs. Attached Figure Description
[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a circuit diagram of an embodiment of the high linearity voltage-time converter for a mixed-domain ADC according to the present invention.
[0018] Figure 2 This is the circuit diagram of the threshold comparison unit.
[0019] Figure 3 Transient simulation diagram of voltage-time converter circuit.
[0020] Figure 4This is a frequency domain analysis diagram of a voltage-time converter in a specific example. Detailed Implementation
[0021] The following specific examples illustrate the implementation of the present invention. The illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0022] Please see Figure 1 , Figure 1 This is a circuit diagram of an embodiment of a high linearity voltage-time converter for a mixed-domain ADC according to the present invention. The high linearity voltage-time converter for a mixed-domain ADC in this embodiment includes a constant current source circuit 100, a ramp generation circuit 200, and a threshold comparison circuit 300. The constant current source circuit 100 outputs a constant charging current. The ramp generation circuit 200 generates a common-mode ramp signal with a corresponding slope based on the charging current output by the constant current source circuit 100. The common-mode ramp signal generates a first ramp signal and a second ramp signal based on the positive residual signal Vresp and the negative residual signal Vresn, respectively. The threshold comparison circuit 300 compares the first ramp signal and the second ramp signal with a preset reference voltage, and generates a first rising edge signal and a second rising edge signal based on the comparison result. The time difference between the first rising edge signal and the second rising edge signal is proportional to the voltage difference between the positive residual ramp signal and the negative residual ramp signal.
[0023] The constant current source circuit 100 may include a constant current source I1, a current mirror, and an output switch. The first end of the current mirror is electrically connected to the constant current source I1, and the second end of the current mirror is electrically connected to the first end of the output switch. The second end of the output switch serves as the output end of the constant current source circuit 100 and is electrically connected to the ramp generation circuit 200. The control end of the output switch is connected to the clock signal CLK.
[0024] In this embodiment, the current mirror is a common-source, common-gate current mirror, and the output switch is defined as a PMOS transistor PM5. The source of the PMOS transistor PM5 is the first terminal of the output switch, the drain of the PMOS transistor PM5 is the second terminal of the output switch, and the gate of the PMOS transistor PM5 is the control terminal of the output switch.
[0025] Specifically, the current mirror may include PMOS transistors PM1, PM2, PM3, and PM4. The hole mobility, gate oxide capacitance per unit area, threshold voltage, and channel length modulation coefficient of PMOS transistors PM1, PM2, PM3, and PM4 are generally equal. In this embodiment, the hole mobility of PMOS transistors PM1, PM2, PM3, and PM4 is all... The gate oxide capacitance per unit area is Both threshold voltages are The channel length modulation coefficient is 1. .
[0026] The sources of PMOS transistors PM1 and PM3 are both connected to the power supply voltage VDD. The gate of PMOS transistor PM1 is electrically connected to its drain, the gate of PMOS transistor PM3, and the source of PMOS transistor PM2. The gate of PMOS transistor PM2 is electrically connected to its drain and the gate of PMOS transistor PM4, and then serves as the first terminal of a current mirror, which is electrically connected to the first terminal of a constant current source I1. The second terminal of the constant current source I1 is grounded. The drain of PMOS transistor PM3 is electrically connected to the source of PMOS transistor PM4, and the drain of PMOS transistor PM4 serves as the second terminal of a current mirror, which is electrically connected to the source of PMOS transistor PM5.
[0027] Using the above structure, the current calculation formula for the reference current source I1 is: = (1) When the output switch is turned on (i.e., PMOS transistor PM5 is turned on), the charging current output by the constant current source circuit 100 is... The calculation formula is: = (2) In the formula, This indicates the width-to-length ratio of PMOS transistor PM1; This indicates the width-to-length ratio of PMOS transistor PM3; VDD is the power supply voltage. This is the gate-source voltage of PMOS transistor PM1; This is the gate-source voltage of PMOS transistor PM3; This is the drain-source voltage of PMOS transistor PM1; This is the drain-source voltage of PMOS transistor PM3.
[0028] In this embodiment, the width-to-length ratios of PMOS transistors PM1 and PM3 are equal, and the width-to-length ratios of PMOS transistors PM2 and PM4 are equal; that is: ; .
[0029] pass Figure 1 Therefore, the formula for calculating the drain-source voltage of PMOS transistor PM3 is: = (3) The formula for calculating the gate voltage of PMOS transistor PM2 is: (4) In the formula, This represents the gate voltage of PMOS transistor PM2; This represents the gate-source voltage of PMOS transistor PM1; This represents the gate-source voltage of PMOS transistor PM2; This represents the gate-source voltage of the PMOS transistor PM4.
[0030] Substituting equation (4) into equation (3), we get = (5) In this embodiment, the width-to-length ratio of PMOS transistors PM2 and PM4 is set to be equal, that is: (6) Thus, the following can be achieved: = (7) Substituting equation (7) into equation (5), we get: = = (8) In this embodiment, the width-to-length ratios of PMOS transistors PM1 and PM3 are also set to be equal, that is: (9) Thus, the following can be achieved: = (10) Substituting equations (8), (9), and (10) into equation (2), we get: = This eliminates the current mismatch problem caused by the channel length modulation effect between PMOS transistors PM1 and PM3, resulting in a higher output charging current. Capable of accurately replicating the reference current source current .
[0031] The ramp generation circuit includes a common-mode capacitor Ccm, a sampling capacitor Cs1, a sampling capacitor Cs2, an operational amplifier AMP1, an operational amplifier AMP2, a switch SW1, a switch SW2, and a switch SW3.
[0032] The positive input terminal of the operational amplifier AMP1 is used to connect to the positive residual signal Vresp. The negative input terminal of the operational amplifier AMP1 is electrically connected to its output terminal and the first terminal of the switch SW1 to form node P. The second terminal of the switch SW1 is electrically connected to the first terminal of the sampling capacitor Cs1 and then serves as the first output terminal of the ramp generation circuit, which is electrically connected to the first input terminal of the threshold comparison circuit 300.
[0033] The positive input terminal of the operational amplifier AMP2 is used to connect to the negative residual signal Vresn. The negative input terminal of the operational amplifier AMP2 is electrically connected to its output terminal and the first terminal of the switch SW2 to form node N. The second terminal of the switch SW2 is electrically connected to the first terminal of the sampling capacitor Cs2 and then serves as the second output terminal of the ramp generation circuit, which is electrically connected to the second input terminal of the threshold comparison circuit 300.
[0034] The second terminal of the sampling capacitor Cs1 is electrically connected to the second terminal of the sampling capacitor Cs2 and the first terminal of the common-mode capacitor Ccm to form node C. Node C serves as the input terminal of the ramp generation circuit and is electrically connected to the constant current source circuit 100. The second terminal of the common-mode capacitor Ccm is grounded, and the switch SW3 is connected in parallel with the common-mode capacitor Ccm.
[0035] Please see Figure 3 When switches SW1 and SW2 are closed, the residual signals in the voltage domain (including the positive residual signal Vresp and the negative residual signal Vresn) are supplied to sampling capacitors Cs1 and Cs2, respectively; simultaneously, switch SW3 is also closed, clearing the charge on the common-mode capacitor Ccm. When switches SW1 and SW2 are open, switch SW3 is also opened simultaneously, and the charging current... As charging of the common-mode capacitor Ccm begins, the voltage Vc at node C will rise at a certain rate, generating a common-mode slope with a constant gradient. Due to charge conservation, the voltages across sampling capacitors Cs1 and Cs2 remain constant, so the voltages Vp at node P and Vn at node N will also rise at the same rate; their initial voltages are the positive residual signal Vresp and the negative residual signal Vresn sampled and held across the sampling capacitors. Therefore, two slope signals, Vp and Vn, with different initial voltages but the same gradient, are generated at nodes P and N. After these two slope signals are compared with the reference voltage Vref in the threshold comparison circuit 300, two rising edge signals with a certain time difference are output. Since the slopes of the two slope signals are determined by the same charging current... The generated current does not have a mismatch problem, which reduces power consumption and improves the linearity of the overall system.
[0036] The threshold comparison circuit 300 includes two threshold comparison units, namely threshold comparison unit T1 and threshold comparison unit T2. The positive input terminals of the two threshold comparison units are respectively connected to the first and second input terminals of the threshold comparison circuit 300 and electrically connected to the first and second output terminals of the ramp generation circuit. The negative input terminals of the two threshold comparison units are both connected to a preset reference voltage Vref. The output terminals of the two threshold comparison units are respectively connected to the first and second output terminals of the threshold comparison circuit 300 to output a first rising edge signal and a second rising edge signal. Specifically, the positive input terminal of threshold comparison unit T1 is electrically connected to the first output terminal of the ramp generation circuit as the first input terminal of the threshold comparison circuit 300, and the output terminal of threshold comparison unit T1 is used as the first output terminal of the threshold comparison circuit 300 to output the first rising edge signal. The positive input terminal of threshold comparison unit T2 is electrically connected to the second output terminal of the ramp generation circuit as the second input terminal of the threshold comparison circuit 300, and the output terminal of threshold comparison unit T2 is used as the second output terminal of the threshold comparison circuit 300 to output the second rising edge signal.
[0037] The circuit structures of the threshold comparison unit T1 and the threshold comparison unit T2 can be identical. Please refer to [link / reference]. Figure 2 The threshold comparison units (T1, T2) include PMOS transistors PM6, PM7, NMOS transistors NM1, NMOS transistors NM2, NMOS transistors NM3, NMOS transistors NM4, NMOS transistors NM5, capacitor C1, inverter INV1, and inverter INV2.
[0038] The sources of PMOS transistors PM6 and PM7 are both connected to the power supply voltage VDD. The gate of PMOS transistor PM6 is electrically connected to its drain, the gate of PMOS transistor PM7, and the drain of NMOS transistor NM1 to form node A. The gate of NMOS transistor NM1 serves as the input terminal of the threshold comparison unit. Specifically, the input terminal VIN of threshold comparison unit T1 is connected to the first ramp signal Vp, and the input terminal VIN of threshold comparison unit T2 is connected to the second ramp signal Vn.
[0039] The drain of PMOS transistor PM7 is electrically connected to the drain of NMOS transistor NM2, the first terminal of capacitor C1, the drain of NMOS transistor NM5, and the input terminal of inverter INV1. The gate of NMOS transistor NM2 is connected to the reference voltage Vref. The sources of NMOS transistors NM1 and NM2 are both electrically connected to the drain of NMOS transistor NM3. The gate of NMOS transistor NM3 is connected to the common-mode voltage Vcm. The common-mode voltage Vcm is preferably half of the power supply voltage VDD, i.e., Vcm = 1 / 2VDD.
[0040] The source of NMOS transistor NM3 is electrically connected to the drain of NMOS transistor NM4. The gate of NMOS transistor NM4 is connected to the clock signal CLK, and the source of NMOS transistor NM4 is grounded. The second terminal of capacitor C1 is grounded, and the gate of NMOS transistor NM5 is connected to the input inverted clock signal. The source of the NMOS transistor NM5 is grounded. The inverting clock signal... It is the inverted signal of the clock signal CLK.
[0041] The output terminal of inverter INV1 is connected to the input terminal of inverter INV2; the output terminal of inverter INV2 serves as the output terminal of the threshold comparison unit for outputting the signal Tout. Specifically, the output signal Tout generated by threshold comparison unit T1 is the first rising edge signal Tp, and the output signal Tout generated by threshold comparison unit T2 is the second rising edge signal Tn.
[0042] In the above circuit structure, PMOS transistors PM6 and PM7, and NMOS transistors NM1, NM2, and NM3 form a five-transistor operational amplifier circuit. NMOS transistors NM1 and NM2 serve as input transistors to provide the transconductance gm; PMOS transistors PM6 and PM7 act as current mirror loads to provide a large output impedance; and NMOS transistor NM3 serves as a tail current source to provide the quiescent current during operation. NMOS transistors NM4 and NM5 act as switching transistors.
[0043] Please continue reading. Figure 3When the clock signal CLK is low, NMOS transistor NM4 is off, the current of the tail current transistor NM3 is 0, and the five-transistor operational amplifier circuit does not work. NMOS transistor NM5 is on, pulling the voltage at node A down to GND. After passing through inverters INV1 and INV2, the output signal Tout is low. When the clock signal CLK is high, NMOS transistor NM5 is off, NMOS transistor NM4 is on, the tail current transistor NM3 generates current, and the five-transistor operational amplifier circuit enters the working state. It begins to compare the input voltage VIN on the gate of NMOS transistor NM1 with the reference voltage Vref on the gate of NMOS transistor NM2. The voltage VIN of the ramp signal (i.e., the first ramp signal Vp connected to threshold comparison unit T1 and the second ramp signal Vn connected to threshold comparison unit T2) gradually increases.
[0044] Initially, the input voltage VIN is much smaller than the reference voltage Vref, so NMOS transistor NM1 is off. The current in the tail current transistor NM3 flows entirely into NMOS transistor NM2, the load capacitor C1 is discharged, and the voltage Va at node A is 0, as is the output signal Tout. As the input voltage VIN gradually approaches the reference voltage Vref, NMOS transistor NM1 turns on. The PMOS current mirror load replicates the current from NMOS transistor NM1 into NMOS transistor NM4. The current from NMOS transistor NM4 flows into the load capacitor C1, causing the voltage Va at node A to rise. When the voltage Va at node A rises to the threshold voltage Vth1 of inverter INV1, the output of INV1 flips, and the output of INV2 also flips, causing the output signal Tout to rise from low to high, thus outputting a rising edge signal.
[0045] The working principle of this embodiment is as follows: Please see Figure 1 Figure 2 and Figure 3 The constant current source circuit 100 replicates the current of the reference current source I1 through a common-source cascode current mirror and outputs a constant charging current. The constant current source circuit 100 outputs a charging current. Previously, after the voltage domain transformation, the positive residual signal Vresp and the negative residual signal Vresn were sampled onto sampling capacitors Cs1 and Cs2 respectively by operational amplifiers AMP1 and AMP2. At this time, the voltages at nodes P and N are Vresp and Vresn, respectively, and their difference is... After sampling, the residual voltage remains across sampling capacitors Cs1 and Cs2, and the charging current... The common-mode capacitor Ccm begins to charge, and the voltage Vc at node C is... The voltage Vp and voltage Vn across sampling capacitors Cs1 and Cs2 rise at the same rate due to charge conservation. When voltage Vp rises to the reference voltage Vref set in the threshold comparison circuit 300, threshold comparison unit T1 outputs a rising edge signal Tp; when voltage Vn rises to the reference voltage Vref set in the threshold comparison circuit 300, threshold comparison unit T2 outputs a rising edge signal Tn. The time difference between the two rising edges is... We can obtain:
[0046] Therefore, by charging the common-mode capacitor Ccm through the same current source, the voltages on the upper and lower plates of the two sampling capacitors (i.e., sampling capacitor Cs1 and sampling capacitor Cs2) change at the same rate under the effect of charge conservation, generating two ramp signals with the same slope. Their initial difference is the difference of the residual voltage in the voltage domain. Two ramp signals are compared with the reference voltage Vref in two threshold comparators (i.e., threshold comparison unit T1 and threshold comparison unit T2). When the ramp signal approaches Vref, the corresponding threshold comparator outputs a rising edge. The time difference between the rising edges output by the two threshold comparators is... The difference is proportional to the residual voltage held by the two sampling capacitors. Since only one current source is used for charging, the current mismatch problem between current sources is eliminated, improving the linearity of the voltage-time converter.
[0047] Please see Figure 4 The diagram shows the frequency domain analysis of a voltage-time converter in a specific example. The clock frequency used is 80MHz. Under Nyquist input conditions, the voltage-time converter in this embodiment achieves an SNDR of 94.02dB and an ENOB of 15.32 bits, exhibiting high signal-to-noise ratio and high linearity.
[0048] This embodiment provides a novel constant-current VTC structure. By using a constant current source to charge the common-mode capacitor, the voltages on the two sampling capacitors rise or fall at the same rate, thereby generating ramp signals with the same slope on the two sampling capacitors. This not only reduces power consumption but also solves the problem of current mismatch between independent current sources, improving linearity. Furthermore, the structure employed in this invention is simple, has low design complexity, occupies a small area, is easy to implement in integrated circuits, and has low manufacturing costs.
[0049] The above embodiments merely illustrate preferred implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention should be determined by the appended claims.
Claims
1. A high linearity voltage-time converter for a mixed-domain ADC, characterized in that: include A constant current source circuit is used to output a constant charging current; A ramp generation circuit is used to generate a common-mode ramp signal with a corresponding slope based on the charging current output by the constant current source circuit. The common-mode ramp signal generates a first ramp signal and a second ramp signal based on the positive residual signal Vresp and the negative residual signal Vresn, respectively. as well as A threshold comparison circuit is used to compare the first ramp signal and the second ramp signal with a preset reference voltage, and generate a first rising edge signal and a second rising edge signal based on the comparison result. The time difference between the first rising edge signal and the second rising edge signal is proportional to the voltage difference between the first ramp signal and the second ramp signal.
2. The high linearity voltage-time converter for a mixed-domain ADC as described in claim 1, characterized in that: The constant current source circuit includes a constant current source I1, a current mirror, and an output switch. The first end of the current mirror is electrically connected to the constant current source I1, and the second end of the current mirror is electrically connected to the first end of the output switch. The second end of the output switch serves as the output end of the constant current source circuit and is electrically connected to the ramp generation circuit. The control end of the output switch is connected to the clock signal CLK.
3. The high linearity voltage-time converter for a mixed-domain ADC as described in claim 2, characterized in that: The current mirror is a common-source common-gate current mirror, and the output switch is defined as a PMOS transistor PM5. The source of the PMOS transistor PM5 is the first terminal of the output switch, the drain of the PMOS transistor PM5 is the second terminal of the output switch, and the gate of the PMOS transistor PM5 is the control terminal of the output switch.
4. The high linearity voltage-time converter for a mixed-domain ADC as described in claim 3, characterized in that: The current mirror includes PMOS transistors PM1, PM2, PM3, and PM4. The sources of PMOS transistors PM1 and PM3 are both connected to the power supply voltage VDD. The gate of PMOS transistor PM1 is electrically connected to its drain, the gate of PMOS transistor PM3, and the source of PMOS transistor PM2. The gate of PMOS transistor PM2 is electrically connected to its drain and the gate of PMOS transistor PM4, and then serves as the first terminal of the current mirror, which is electrically connected to the first terminal of a constant current source I1. The second terminal of the constant current source I1 is grounded. The drain of PMOS transistor PM3 is electrically connected to the source of PMOS transistor PM4, and the drain of PMOS transistor PM4 serves as the second terminal of the current mirror, which is electrically connected to the source of PMOS transistor PM5.
5. The high linearity voltage-time converter for a mixed-domain ADC as described in claim 4, characterized in that: The hole mobility, gate oxide capacitance per unit area, threshold voltage, and channel length modulation coefficient of the PMOS transistors PM1, PM2, PM3, and PM4 are all equal.
6. The high linearity voltage-time converter for a mixed-domain ADC as described in claim 5, characterized in that: The width-to-length ratios of PMOS transistors PM1 and PM3 are equal, and the width-to-length ratios of PMOS transistors PM2 and PM4 are equal.
7. The high linearity voltage-time converter for a mixed-domain ADC as described in any one of claims 1 to 6, characterized in that: The ramp generation circuit includes a common-mode capacitor Ccm, a sampling capacitor Cs1, a sampling capacitor Cs2, an operational amplifier AMP1, an operational amplifier AMP2, a switch SW1, a switch SW2, and a switch SW3. The positive input terminal of the operational amplifier AMP1 is used to connect to the positive residual signal Vresp. The negative input terminal of the operational amplifier AMP1 is electrically connected to its output terminal and the first terminal of the switch SW1 respectively. The second terminal of the switch SW1 is electrically connected to the first terminal of the sampling capacitor Cs1 and then serves as the first output terminal of the ramp generation circuit and is electrically connected to the first input terminal of the threshold comparison circuit. The positive input terminal of the operational amplifier AMP2 is used to connect the negative residual signal Vresn. The negative input terminal of the operational amplifier AMP2 is electrically connected to its output terminal and the first terminal of the switch SW2. The second terminal of the switch SW2 is electrically connected to the first terminal of the sampling capacitor Cs2 and then serves as the second output terminal of the ramp generation circuit and is electrically connected to the second input terminal of the threshold comparison circuit. The second terminal of the sampling capacitor Cs1 is electrically connected to the second terminal of the sampling capacitor Cs2 and the first terminal of the common-mode capacitor Ccm, respectively, and then serves as the input terminal of the ramp generation circuit and is electrically connected to the constant current source circuit; the second terminal of the common-mode capacitor Ccm is grounded, and the switch SW3 is connected in parallel with the common-mode capacitor Ccm.
8. The high linearity voltage-time converter for a mixed-domain ADC as described in claim 7, characterized in that: The threshold comparison circuit includes two threshold comparison units. The positive input terminals of the two threshold comparison units are respectively used as the first input terminal and the second input terminal of the threshold comparison circuit and electrically connected to the first output terminal and the second output terminal of the ramp generation circuit. The negative input terminals of the two threshold comparison units are both connected to a preset reference voltage Vref. The output terminals of the two threshold comparison units are respectively used as the first output terminal and the second output terminal of the threshold comparison circuit to output the first rising edge signal and the second rising edge signal.
9. The high linearity voltage-time converter for a mixed-domain ADC as described in claim 8, characterized in that: The threshold comparison unit includes PMOS transistor PM6, PMOS transistor PM7, NMOS transistor NM1, NMOS transistor NM2, NMOS transistor NM3, NMOS transistor NM4, NMOS transistor NM5, capacitor C1, inverter INV1, and inverter INV2; The source of PMOS transistor PM6 and the source of PMOS transistor PM7 are both connected to the power supply voltage VDD. The gate of PMOS transistor PM6 is electrically connected to its drain, the gate of PMOS transistor PM7 and the drain of NMOS transistor NM1, respectively. The gate of NMOS transistor NM1 serves as the input terminal of the threshold comparison unit. The drain of PMOS transistor PM7 is electrically connected to the drain of NMOS transistor NM2, the first terminal of capacitor C1, the drain of NMOS transistor NM5, and the input terminal of inverter INV1, respectively; the gate of NMOS transistor NM2 is connected to the reference voltage Vref; the source of NMOS transistor NM1 and the source of NMOS transistor NM2 are both electrically connected to the drain of NMOS transistor NM3, and the gate of NMOS transistor NM3 is connected to the common-mode voltage Vcm; The source of NMOS transistor NM3 is electrically connected to the drain of NMOS transistor NM4, the gate of NMOS transistor NM4 is connected to the clock signal CLK, and the source of NMOS transistor NM4 is grounded. The second terminal of capacitor C1 is grounded, and the gate of NMOS transistor NM5 is connected to the input inverted clock signal. The source of the NMOS transistor NM5 is grounded; the inverted clock signal This is the inverted signal of the clock signal CLK; The output terminal of inverter INV1 is connected to the input terminal of inverter INV2; the output terminal of inverter INV2 serves as the output terminal of the threshold comparison unit.
10. The high linearity voltage-time converter for a mixed-domain ADC as described in claim 9, characterized in that: The common-mode voltage Vcm is half of the power supply voltage VDD.