Low-delay level signal quality enhancement and waveform shaping module

Abstract

The utility model discloses a low-delay level signal quality enhancement and waveform shaping module. Comprising a CMOS differential line driver used for converting a single-ended input level signal into a differential LVDS signal, an LVDS differential line receiver used for converting the differential LVDS signal into a CMOS output level signal, and a non-reverse buffer used for converting the CMOS output level signal into a single-ended output level signal. The LVDS differential line receiver is connected between the output end of the CMOS differential line driver and the input end of the non-reverse buffer. According to the utility model, by simplifying a signal chain and optimizing the collaborative design of filtering and shaping, low-delay and high-stability signal quality enhancement and waveform shaping functions are realized.

Description

Technical Field

[0001] This utility model relates to the field of electronic signal processing technology, and more specifically, to a low-delay level signal quality enhancement and waveform shaping module. Background Technology

[0002] In digital circuits or communication systems, level signals (such as square waves and pulse signals) are susceptible to external interference or circuit coupling, resulting in glitches, noise, or waveform distortion, leading to system misjudgments or timing errors. To eliminate these problems, current level signal processing solutions typically employ the following methods:

[0003] ①RC filtering for denoising: High-frequency noise is suppressed by RC filtering, but this method introduces signal delay and is difficult to meet the requirements of high-speed systems;

[0004] ② Digital signal shaping: This method relies on software filtering using FPGA or processor, but it is costly and has a certain signal delay due to the real-time nature of the algorithm.

[0005] ③ Complex shaping circuits: such as multi-stage filtering + Schmitt trigger combination, although it can improve the waveform, the circuit of this method is complex and the delay accumulation is significant.

[0006] Therefore, there is an urgent need for a hardware solution that balances low latency, high reliability, and low cost. Utility Model Content

[0007] To overcome the shortcomings of existing technologies and address the problems of high delay and complex circuitry in existing level signal processing, this invention proposes a low-delay level signal quality enhancement and waveform shaping module. By simplifying the signal chain and optimizing the collaborative design of filtering and shaping, it achieves low-delay and high-stability signal quality enhancement and waveform shaping functions.

[0008] The objective of this utility model is achieved through the following technical solution.

[0009] This utility model discloses a low-delay level signal quality enhancement and waveform shaping module, which includes a CMOS differential line driver for converting a single-ended input level signal into a differential LVDS signal, an LVDS differential line receiver for converting the differential LVDS signal into a CMOS output level signal, and a non-inverting buffer for converting the CMOS output level signal into a single-ended output level signal. The LVDS differential line receiver is connected between the output terminal of the CMOS differential line driver and the input terminal of the non-inverting buffer.

[0010] Furthermore, the CMOS differential line driver employs a four-channel LVDS driver chip; one of the data input pins of the four-channel LVDS driver chip is connected to a single-ended input level signal via resistor number four, and a set of differential data output pins corresponding to this data input pin is connected to the input terminal of the LVDS differential line receiver; the enable pin of the four-channel LVDS driver chip is connected to a 3.3V voltage source via resistor number one, the complementary pin of the enable pin is grounded via resistor number six, the power input pin is connected to a 3.3V voltage source, and the ground pin is grounded.

[0011] Furthermore, the LVDS differential line receiver employs a four-channel LVDS receiver chip; one set of differential data input pins of the four-channel LVDS receiver chip is connected to one set of differential data output pins of the four-channel LVDS driver chip, and a resistor of number five is connected between these differential data input pins; the output pin corresponding to this set of differential data input pins is connected to the input terminal of the non-inverting buffer; the enable pin of the four-channel LVDS receiver chip is connected to a 3.3V voltage source via a resistor of number two, the complementary pin of the enable pin is grounded via a resistor of number three, the power input pin is connected to a 3.3V voltage source, and the ground pin is grounded.

[0012] Furthermore, the non-reverse buffer adopts a single-channel non-reverse buffer chip; the output enable control pin of the single-channel non-reverse buffer chip is grounded through resistor No. 8, the input signal pin is connected to the output pin of the four-channel LVDS receiver chip, the ground pin is grounded, the power input pin is connected to a 3.3V voltage source, and the output signal pin is used to output a single-ended output level signal.

[0013] Compared with the prior art, the beneficial effects of the technical solution of this utility model are:

[0014] (1) This utility model has the effect of enhancing the signal by removing glitches, overshoot, backtracking, and ringing from the level signal. It also has the function of optimizing and shaping the distorted waveform to restore it into a near-ideal square wave. The signal delay between the single-ended input signal and the single-ended output signal is low, and the impact on the integrity of the signal transmission is very small. The delay of the specific implementation method has been verified to be 5.6ns, which is lower than the delay of using FPGA signal shaping, RC filtering and other methods.

[0015] (2) In this invention, the single-ended input level is converted into a differential LVDS signal by a CMOS differential line driver, and the differential LVDS signal is then converted into a single-ended CMOS output level signal by an LVDS differential line receiver. Both the CMOS differential line driver and the LVDS differential line receiver can meet the low latency requirement of this invention. This design also has the following advantages:

[0016] ① Glitches Suppressed: Glitches are usually high-frequency spikes on signal lines. LVDS differential line receivers perform differential operations on the signals of two lines. If a glitch appears on both differential pairs simultaneously, it will be filtered out as a common-mode signal by the LVDS differential line receiver due to its common-mode characteristics. If external transient interference is coupled to only a single differential line, it will also be partially canceled out in the difference calculation. Combined with the threshold hysteresis of the LVDS differential line receiver, narrow pulse glitch can be further filtered out. However, when CMOS signals are transmitted in a single-ended manner, glitch is more difficult to remove through simple filtering.

[0017] ② Noise filtering: Noise is generally random, wide-spectrum interference signals. Differential signal transmission uses balanced lines, and both lines are similarly affected by external noise, which exists in common-mode form. LVDS differential line receivers use difference calculations to cancel common-mode noise and effectively filter noise through high common-mode rejection ratio (CMRR).

[0018] ③ Mitigation of overshoot and ringing: Overshoot is the phenomenon where the signal exceeds the target level at the moment of transition. The differential pairs of the differential signal are coupled to each other during transmission, which can slow down the rapid transition of the signal and thus reduce the overshoot amplitude. In addition, the impedance matching design of the differential pair can reduce signal reflection, and the differential LVDS signal reduces voltage jumps, thereby suppressing overshoot and ringing.

[0019] ④ Waveform Shaping: The LVDS differential line receiver has Schmitt trigger circuit characteristics, which filters out edge noise through threshold hysteresis and shapes the distorted signal into a steep square wave. At the same time, the symmetry decision of the differential pair can repair the waveform asymmetry caused by transmission loss.

[0020] (3) In this utility model, the CMOS output level signal output by the LVDS differential line receiver is generated into a single-ended output level signal by a non-inverting buffer. The non-inverting buffer has the characteristic of enhancing the driving capability of the level signal. This characteristic is used to reduce the distortion of the signal during transmission, increase the edge steepness of the level signal, and make the signal closer to the ideal square wave to achieve waveform shaping. In addition, the non-inverting buffer also has the characteristic of isolating the front and rear circuits, which can avoid the feedback effect of the rear circuit on the front circuit, thereby reducing noise. Attached Figure Description

[0021] Figure 1 This is a block diagram of the low-delay level signal quality enhancement and waveform shaping module of this utility model.

[0022] Figure 2 This is the schematic diagram of the differential line driver chip in this utility model.

[0023] Figure 3 This is a schematic diagram of the LVDS differential line receiver chip in this utility model.

[0024] Figure 4 This is a schematic diagram of the non-reverse buffer chip in this utility model.

[0025] Figure 5 This is a comparison diagram of the signal enhancement and reshaping effects before and after using the module of this utility model.

[0026] Figure reference numerals: U1 - Quad-channel LVDS receiver chip, U2 - Quad-channel LVDS driver chip, U3 - Single-channel non-reverse buffer chip, R1 - Resistor 1, R2 - Resistor 2, R3 - Resistor 3, R4 - Resistor 4, R5 - Resistor 5, R6 - Resistor 6, R8 - Resistor 8, GND - Ground. Detailed Implementation

[0027] The present invention will now be further described with reference to the accompanying drawings.

[0028] This invention proposes a low-delay level signal quality enhancement and waveform shaping module to eliminate glitches, overshoots, and backtracking in level signals, thereby improving signal quality and achieving low-delay waveform shaping. Figure 1 As shown, the low-delay level signal quality enhancement and waveform shaping module of this invention mainly consists of a CMOS differential line driver, an LVDS differential line receiver, and a non-inverting buffer. The LVDS differential line receiver is connected between the output terminal of the CMOS differential line driver and the input terminal of the non-inverting buffer. The single-ended input level is converted into a differential LVDS signal by the CMOS differential line driver, and then converted into a single-ended CMOS output level signal by the LVDS differential line receiver. The CMOS output level signal is then passed through the non-inverting buffer to finally generate a single-ended output level signal. At this point, the signal quality of the single-ended output level signal is enhanced and the waveform is optimized.

[0029] (1) CMOS differential line driver

[0030] In this invention, the CMOS differential line driver uses a four-channel LVDS driver chip U2, which can be Texas Instruments' DSLVDS1047PWR. It is a four-channel CMOS pass-through differential line driver that can convert low-voltage TTL / CMOS input signals into low-swing differential LVDS output signals, supporting data rates of 400Mbps (200MHz). Its design optimizes the PCB layout, adopts a pass-through pin arrangement, reduces signal path complexity, and features low power consumption, low propagation delay, and low cost. The static power consumption is only 13mW and the maximum propagation delay is only 1.7ns, meeting the low delay requirements of this invention.

[0031] like Figure 2As shown, one data input pin (e.g., pin 2) of the four-channel LVDS driver chip U2 is connected to a single-ended input level signal (S3-V5 TX IO35) via resistor R4. A set of differential data output pins (pins 15 and 16) corresponding to this data input pin are connected to the input of the LVDS differential line receiver. That is, the negative differential LVDS signal (S3-V5 TX IO35 N) and the positive differential LVDS signal (S3-V5 TX IO35 P) are emitted from pins 16 and 15. The enable pin (pin 1) of the four-channel LVDS driver chip U2 is connected to a 3.3V voltage source via resistor R1. The complementary pin of the enable pin (pin 8) is grounded to GND via resistor R6. The power input pin (pin 4) is connected to a 3.3V voltage source, and the ground pin (pin 5) is grounded to GND. Preferably, R1 = 1KΩ, R4 = 0Ω, and R6 = 1KΩ.

[0032] (2) LVDS differential line receiver

[0033] The LVDS differential line receiver in this invention uses a four-channel LVDS receiver chip U1, which can be the Texas Instruments DSLVDS1048PWT. It is a four-channel differential line receiver that is compatible with the DSLVDS1047PWR and can convert the input differential LVDS signal into a 3V CMOS output level signal. Its design also adopts a through-pin arrangement to simplify the layout and supports input fault protection. It features low power consumption, low propagation delay, and low cost. The static power consumption is only 40mW and the maximum propagation delay is only 2.7ns, which meets the low delay requirement of this invention.

[0034] like Figure 3 As shown, a set of differential data input pins (such as pins 1 and 2) of the four-channel LVDS receiver chip U1 is connected to a set of differential data output pins (pins 16 and 15) of the four-channel LVDS driver chip U2. A resistor R5 is also connected between these differential data input pins. The output pin (pin 15) corresponding to these differential data input pins (pins 1 and 2) is connected to the input of a non-inverting buffer. The CMOS output level signal S3 TX IO35, generated by the differential LVDS signal converted by the four-channel LVDS receiver chip U1, is emitted from pin 15. The enable pin (pin 16) of the four-channel LVDS receiver chip U1 is connected to a 3.3V voltage source via resistor R2. The complementary pin (pin 9) of the enable pin is grounded to GND via resistor R3. The power input pin (pin 13) is connected to a 3.3V voltage source, and the ground pin (pin 12) is grounded to GND. Preferably, R2 = 1KΩ, R3 = 1KΩ, and R5 = 100Ω.

[0035] (3) Non-reverse buffer

[0036] The non-inverting buffer in this invention uses a single-channel non-inverting buffer chip U3, which can be selected from Texas Instruments' SN74LVC1G125DBVR. It is a single-channel non-inverting buffer designed with low-voltage CMOS technology, supports tri-state output function, has an operating voltage range of 1.65V-5.5V, an output current of 32mW, a typical transmission delay of 4.3ns, and a minimum static power consumption of 32mA. It is mainly used for signal enhancement, level shifting, and multiplexing scenarios, and is suitable for digital logic circuits in high-noise environments.

[0037] like Figure 4 As shown, the input signal pin (pin 2) of the single-channel non-inverting buffer chip U3 is connected to the output pin (pin 15) of the four-channel LVDS receiver chip U1, and the output signal pin (pin 4) outputs the buffered single-ended output level signal IO35. The output enable control pin (pin 1) of the single-channel non-inverting buffer chip U3 is grounded to GND through resistor R8, the ground pin (pin 3) is grounded to GND, and the power input pin (pin 5) is connected to a 3.3V voltage source. Preferably, R8 = 1KΩ.

[0038] The non-reverse buffer in this invention has the characteristic of enhancing the driving capability of level signals. This characteristic reduces signal distortion during transmission, increases the edge steepness of level signals, and makes the signal closer to the ideal square wave to achieve waveform shaping. In addition, the non-reverse buffer also has the characteristic of isolating the preceding and following circuits, which can prevent the following circuit from having feedback effects on the preceding circuit, thereby reducing noise.

[0039] This invention primarily utilizes a CMOS differential line driver, an LVDS differential line receiver, and a non-inverting buffer to optimize signal quality and shape waveforms. For example... Figure 5 This is an example diagram showing the effect comparison before and after signal enhancement and reshaping using the module of this utility model.

[0040] Although the functions and working processes of this utility model have been described above in conjunction with the accompanying drawings, this utility model is not limited to the specific functions and working processes described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this utility model without departing from the spirit and scope of the claims, and all of these are within the protection scope of this utility model.

Claims

1. A low latency level signal quality enhancement and waveform shaping module, characterized by, It includes a CMOS differential line driver for converting a single-ended input level signal into a differential LVDS signal, an LVDS differential line receiver for converting the differential LVDS signal into a CMOS output level signal, and a non-inverting buffer for converting the CMOS output level signal into a single-ended output level signal. The LVDS differential line receiver is connected between the output terminal of the CMOS differential line driver and the input terminal of the non-inverting buffer.

2. The low latency level signal quality enhancement and waveform shaping module of claim 1, wherein, The CMOS differential line driver uses a four-channel LVDS driver chip. One of the data input pins of the four-channel LVDS driver chip is connected to a single-ended input level signal via resistor number four. A set of differential data output pins corresponding to this data input pin is connected to the input terminal of the LVDS differential line receiver. The enable pin of the four-channel LVDS driver chip is connected to a 3.3V voltage source via resistor number one. The complementary pin of the enable pin is grounded via resistor number six. The power input pin is connected to a 3.3V voltage source, and the ground pin is grounded.

3. The low latency level signal quality enhancement and waveform shaping module of claim 1, wherein, The LVDS differential line receiver uses a four-channel LVDS receiver chip. One set of differential data input pins of the four-channel LVDS receiver chip is connected to a set of differential data output pins of the four-channel LVDS driver chip. A resistor (number 5) is connected between these differential data input pins. The output pin corresponding to this set of differential data input pins is connected to the input of the non-inverting buffer. The enable pin of the four-channel LVDS receiver chip is connected to a 3.3V voltage source via a resistor (number 2). The complementary pin of the enable pin is grounded via a resistor (number 3). The power input pin is connected to a 3.3V voltage source, and the ground pin is grounded.

4. The low latency level signal quality enhancement and waveform shaping module of claim 1, wherein, The non-reverse buffer uses a single-channel non-reverse buffer chip; the output enable control pin of the single-channel non-reverse buffer chip is grounded through resistor 8, the input signal pin is connected to the output pin of the four-channel LVDS receiver chip, the ground pin is grounded, the power input pin is connected to a 3.3V voltage source, and the output signal pin is used to output a single-ended output level signal.

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