A pulse driving optimization circuit

Abstract

This application relates to the field of integrated optoelectronic technology, and more specifically, to a pulse drive optimization circuit, including a rising edge detection circuit, a subtraction circuit, a monostable trigger circuit, and a signal superposition circuit. The rising edge detection circuit extracts the rising edge positive pulse of the input signal, converts it into a falling edge pulse under the reference voltage through the subtraction circuit, triggers the monostable trigger circuit to generate a high-amplitude short pulse, and finally the signal superposition circuit superimposes the high-amplitude short pulse onto the rising edge of the original input signal to output a drive signal adapted to the thermo-optical tuning optoelectronic integrated chip. This can significantly improve the thermo-optical tuning response speed of the chip without significantly increasing the average power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated optoelectronic technology, and more specifically, to a pulse-driven optimized circuit. Background Technology

[0002] Thermo-optical tuning is a core technology for controlling the phase, wavelength, and intensity of light in optoelectronic integrated chips, and it is widely used in optical communication, optical computing, and other fields. Its principle involves applying a driving voltage through electrical pads at the edge of the optical chip to the heater resistor of the optoelectronic integrated chip (the heater covers the optical waveguide). By electrically heating the waveguide and changing its refractive index, precise control of the optical signal is achieved.

[0003] Compared to electro-optic tuning, thermo-optical tuning requires significantly more power and necessitates applying a higher voltage to the heater resistor on the optoelectronic integrated chip. Therefore, traditional thermo-optical tuning methods using DC or ordinary square wave drive suffer from slow tuning response, high power consumption, and severe thermal crosstalk. These problems severely restrict the achievement of goals such as scaling up optoelectronic integrated chips, improving tuning accuracy, and continuous control. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of slow tuning response in existing DC or ordinary square wave driving schemes, and to provide a pulse driving optimization circuit that can improve the tuning response speed of thermo-optical tuning optoelectronic integrated chips without increasing power consumption.

[0005] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A pulse-driven optimization circuit is provided, including a rising edge detection circuit, a subtraction circuit, a monostable trigger circuit, and a signal superposition circuit. The input terminal of the rising edge detection circuit is connected to an input signal, and its output terminal is connected to the input terminal of the subtraction circuit. The output terminal of the subtraction circuit is connected to the input terminal of the monostable trigger circuit. The output terminal of the monostable trigger circuit is connected to the second input terminal of the signal superposition circuit. The first input terminal of the signal superposition circuit is connected to the input signal, and its output terminal is used to output a signal. The rising edge detection circuit extracts the rising edge positive pulse of the input signal, converts it into a falling edge pulse under a reference voltage via the subtraction circuit, triggers the monostable trigger circuit to generate a high-amplitude short pulse, and finally, the signal superposition circuit superimposes the high-amplitude short pulse onto the rising edge of the original input signal to output a driving signal adapted to a thermo-optically tuned optoelectronic integrated chip.

[0006] This invention discloses a pulse drive optimization circuit to improve the response speed of the drive circuit of a thermo-optical tuned optoelectronic integrated chip, while not significantly increasing the average power consumption compared to the original drive circuit. The circuit involves an edge detection circuit that extracts the rising edge positive pulse of the input signal, converts it into a falling edge pulse at a reference voltage via a subtraction circuit, triggers a monostable trigger circuit to generate a high-amplitude short pulse, and finally, a signal superposition circuit superimposes this high-amplitude short pulse onto the rising edge of the original input signal to output a drive signal adapted to the thermo-optical tuned optoelectronic integrated chip. This significantly improves the thermo-optical tuning response speed of the chip without significantly increasing the average power consumption.

[0007] Furthermore, the input signal is detected by the RC differentiating circuit composed of capacitor C1 and resistor R1 in the rising edge detection circuit to detect the rising edge and falling edge, and generates brief positive and negative pulses at the rising and falling edges. The negative pulse at the falling edge is then filtered out by diode D1, and the corresponding positive pulse at the rising edge is extracted, thereby realizing the rising edge detection of the input signal.

[0008] Furthermore, the rising edge detection circuit includes a capacitor C1, a resistor R1, a resistor R2, and a diode D1; one end of the capacitor C1 is connected to the input signal, and the other end is connected to one end of the resistor R1 and the anode of the diode D1; the other end of the resistor R1 is grounded; the cathode of the diode D1 is connected to one end of the resistor R2 and serves as the output terminal of the rising edge detection circuit; the other end of the resistor R2 is grounded.

[0009] Furthermore, the subtraction circuit can perform subtraction on the input signal at a preset voltage baseline, and the input positive pulse signal can output a falling edge short pulse signal with the preset voltage as the baseline after passing through the subtraction circuit.

[0010] Further, the subtraction circuit includes resistors R3, R4, R5, and R6, and operational amplifier U1; one end of resistor R3 serves as the input terminal of the subtraction circuit, and the other end is connected to the inverting input terminal of operational amplifier U1 and the input terminal of resistor R5; one end of resistor R4 is connected to the power supply, and the other end is connected to the non-inverting input terminal of operational amplifier U1 and one end of resistor R6, with the other end of resistor R6 grounded; the output terminal of resistor R5 is connected to the output terminal of operational amplifier U1; the output terminal of operational amplifier U1 is used as the output terminal of the subtraction circuit.

[0011] Furthermore, the monostable trigger circuit can identify the falling edge of the output pulse signal and generate a brief positive pulse signal that changes from zero to a high amplitude at the falling edge.

[0012] Furthermore, the monostable trigger circuit includes a resistor R7, a capacitor C2, a capacitor Cf, and a timer chip U2; the timer chip U2 includes at least 8 pins; pin 1 VCC and pin 2 RST of the timer chip U2 are connected to the power supply and one end of the resistor R7; pin 3 DIS and pin 4 THR are both connected to the other end of the resistor R7 and one end of the capacitor C2; pin 5 TRI is used as the input terminal of the monostable trigger circuit; pin 6 CON is connected to one end of the capacitor Cf; pin 7 GND is grounded; pin 8 OUT is used as the output terminal of the monostable trigger circuit; the other end of the capacitor C2 and the other end of the capacitor Cf are both grounded.

[0013] Furthermore, the signal superposition circuit can proportionally superimpose the two input signals from the first input terminal and the second input terminal, and the output signal includes: a brief high-amplitude pulse signal at the rising edge superimposed on the overall circuit input signal.

[0014] Further, the signal superposition circuit includes resistors R8, R9, R10, and R11, and operational amplifier U3; the input terminal of resistor R8 is used as the first input terminal of the signal superposition circuit, and its output terminal is connected to the non-inverting input terminal of operational amplifier U3 and the output terminal of resistor R9. The output terminal of resistor R9 is connected to the non-inverting input terminal of operational amplifier U3, and its input terminal is used as the second input terminal of the signal superposition circuit; one end of resistor R10 is connected to the inverting input terminal of operational amplifier U3 and one end of resistor R11, and the other end of resistor R10 is grounded; the other end of resistor R11 is connected to the output terminal of operational amplifier U3, and the output terminal of operational amplifier U3 is used as the output terminal of the signal superposition circuit.

[0015] Furthermore, when R8 / / R9=R10 / / R11, the output voltage... , This is the original input drive signal for the first input terminal. The second input terminal is a high-amplitude, short-duration pulse signal; by adjusting the resistance values ​​of resistors R8, R9, R10, and R11, the superposition ratio of the two input signals can be adjusted.

[0016] Compared with the prior art, the beneficial effects of the present invention are: The present invention discloses a pulse drive optimization circuit in which a rising edge detection circuit extracts the rising edge positive pulse of the input signal, converts it into a falling edge pulse under the reference voltage through a subtraction circuit, triggers a monostable trigger circuit to generate a high-amplitude short pulse, and finally a signal superposition circuit superimposes the high-amplitude short pulse onto the rising edge of the original input signal to output a drive signal adapted to the thermo-optical tuning optoelectronic integrated chip. This can significantly improve the thermo-optical tuning response speed of the chip without significantly increasing the average power consumption. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the overall connection relationship of the pulse drive optimization circuit in one embodiment; Figure 2 This is a schematic diagram of the rising edge detection circuit connection in one embodiment; Figure 3 This is a schematic diagram of the subtraction circuit connection in one embodiment; Figure 4 This is a schematic diagram of the monostable trigger circuit connection in another embodiment; Figure 5 This is a schematic diagram of the signal superposition circuit connection relationship in one embodiment; Figure 6 This is a connection block diagram of an embodiment of the pulse drive optimization circuit; Figure 7 This is a simulation waveform diagram of the output signals of each circuit in one embodiment. Detailed Implementation

[0018] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only, representing schematic diagrams rather than actual physical objects, and should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0019] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0020] Example 1 This embodiment is a first embodiment of a pulse-driven optimization circuit, such as... Figure 1 and Figure 6 As shown, the circuit includes a rising edge detection circuit, a subtraction circuit, a monostable trigger circuit, and a signal superposition circuit. The input terminal of the rising edge detection circuit is connected to the input signal, and the output terminal is connected to the input terminal of the subtraction circuit. The output terminal of the subtraction circuit is connected to the input terminal of the monostable trigger circuit. The output terminal of the monostable trigger circuit is connected to the second input terminal of the signal superposition circuit. The first input terminal of the signal superposition circuit is connected to the input signal, and the output terminal is used to output the signal. The rising edge detection circuit extracts the rising edge positive pulse of the input signal, converts it into a falling edge pulse under the reference voltage by the subtraction circuit, triggers the monostable trigger circuit to generate a high-amplitude short pulse, and finally the signal superposition circuit superimposes the high-amplitude short pulse onto the rising edge of the original input signal to output a drive signal adapted to the thermo-optical tuned optoelectronic integrated chip.

[0021] In this embodiment, the input signal is detected by the RC differentiating circuit composed of capacitor C1 and resistor R1 in the rising edge detection circuit. Brief positive and negative pulses are generated at the rising and falling edges. The negative pulse at the falling edge is then filtered out by diode D1, and the corresponding positive pulse at the rising edge is extracted, thus realizing the rising edge detection of the input signal. The structure is simple and the cost is low.

[0022] In this embodiment, the input terminal of the subtraction circuit is connected to the output of the rising edge detection circuit. The subtraction circuit can perform subtraction on the input signal on a preset voltage (e.g., 25V, which can be adjusted as needed). After the input positive pulse signal passes through the subtraction circuit, it can output a falling edge short pulse signal with the preset voltage as the reference line.

[0023] In this embodiment, the monostable trigger circuit can identify the falling edge of the output pulse signal and generate a brief positive pulse signal that changes from zero to a high amplitude at the falling edge. The signal superposition circuit can proportionally superimpose the two input signals at the first input terminal and the second input terminal, and the output signal includes: a brief high-amplitude pulse signal at the rising edge superimposed on the overall circuit input signal.

[0024] This embodiment provides a pulse drive optimization circuit. The rising edge detection circuit extracts the rising edge positive pulse of the input signal, converts it into a falling edge pulse under the reference voltage through a subtraction circuit, triggers a monostable trigger circuit to generate a high-amplitude short pulse, and finally the signal superposition circuit superimposes the high-amplitude short pulse onto the rising edge of the original input signal to output a drive signal adapted to the thermo-optical tuning optoelectronic integrated chip. Without significantly increasing the average power consumption, this greatly improves the thermo-optical tuning response speed of the chip.

[0025] The simulated waveforms of the output signals of each circuit module of the pulse drive optimization circuit in this embodiment are shown in the attached figure. Figure 7 As shown, ① is the original input drive signal, ② is the output positive pulse signal of the rising edge detection circuit, ③ is the output falling edge pulse signal of the subtraction circuit, ④ is the output high-amplitude short pulse signal of the monostable trigger circuit, and ⑤ is the final output composite drive signal of the signal superposition circuit. The simulation waveform clearly shows that the final output signal is precisely superimposed with a high-amplitude short pulse at the rising edge of the original input signal.

[0026] The pulse drive optimization circuit provided in this embodiment is built using general-purpose resistors, capacitors, diodes, operational amplifiers, and timers. It has a simple structure, low cost, and is easy to debug. The parameters of each functional module can be flexibly adjusted according to the actual needs of the thermo-optical tunable optoelectronic integrated chip (such as replacing resistors with different resistance values, capacitors with different capacitance values, and adjusting the reference power supply voltage and the power supply voltage of the timer). It is compatible with thermo-optical tunable optoelectronic integrated chips with different heat capacities and different tuning power requirements. It has good versatility and compatibility and can be widely used in optoelectronic integrated systems in fields such as optical communication and optical computing.

[0027] Example 2 This embodiment is a second embodiment of a pulse-driven optimization circuit. This embodiment is similar to the first embodiment, except that, as shown in the following... Figure 1 and Figure 2 As shown, this embodiment provides a specific implementation of a rising edge detection circuit. The rising edge detection circuit includes a capacitor C1, a resistor R1, a resistor R2, and a diode D1; one end of the capacitor C1 is connected to the input signal, and the other end is connected to one end of the resistor R1 and the anode of the diode D1; the other end of the resistor R1 is grounded; the cathode of the diode D1 is connected to one end of the resistor R2 and serves as the output terminal of the rising edge detection circuit; the other end of the resistor R2 is grounded. In this embodiment, the capacitor C1 is a 1nF ceramic capacitor, the resistors R1 and R2 are both 1kΩ precision resistors, and the diode D1 is a 1N914 high-speed switching diode.

[0028] In this embodiment, the core of the rising edge detection circuit is an RC differentiating circuit composed of capacitor C1 and resistor R1, which can detect the rising and falling edges of the input signal and generate brief high-amplitude positive and negative pulses at the corresponding edges. The pulse width is determined by the formula t1=R1*C1. In this embodiment, the pulse width is 1µs. Diode D1 is a unidirectional conducting device that can filter out the negative pulse corresponding to the falling edge and only allow the positive pulse corresponding to the rising edge to pass through, thereby achieving accurate detection and extraction of the rising edge of the input signal. The rising edge positive pulse output by the circuit output terminal is transmitted to the subsequent subtraction circuit.

[0029] Example 3 This embodiment is a third embodiment of a pulse drive optimization circuit. This embodiment is similar to Embodiment 1, except that, as shown in the following... Figure 1 and Figure 3 As shown, this embodiment provides a specific implementation of a subtraction circuit, which includes resistors R3, R4, R5, and R6, and an operational amplifier U1. One end of resistor R3 serves as the input terminal of the subtraction circuit, and the other end is connected to the inverting input terminal of operational amplifier U1 and the input terminal of resistor R5. One end of resistor R4 is connected to an 18.5V reference DC power supply, and the other end is connected to the non-inverting input terminal of operational amplifier U1 and one end of resistor R6. The other end of resistor R6 is grounded. The output terminal of resistor R5 is connected to the output terminal of operational amplifier U1. The output terminal of operational amplifier U1 is used as the output terminal of the subtraction circuit. In this embodiment, resistors R3, R4, R5, and R6 are all 1kΩ precision resistors, and operational amplifier U1 is an AD8055AN high-speed broadband operational amplifier. Its positive and negative power supply terminals are connected to 25V and -25V DC power supplies, respectively, to ensure the high bandwidth and slew rate of the operational amplifier and avoid pulse signal distortion.

[0030] In this embodiment, the amplitude of the falling edge pulse of the rising edge detection circuit can be adjusted by the resistors R3, R4, R5, and R6 of the subtraction circuit. When R4 / / R6 = R3 / / R5, , It is 25V (can be adjusted according to needs). The input signal to the subtraction circuit is the positive pulse signal input by the rising edge detection circuit. After processing by this circuit, the input positive pulse is converted into a short falling edge pulse with 25V as the reference line. This falling edge pulse is transmitted to the subsequent monostable trigger circuit as a trigger signal.

[0031] Example 4 This embodiment is a fourth embodiment of a pulse-driven optimization circuit. This embodiment is similar to Embodiment 1, except that, as shown in the following... Figure 1 and Figure 4As shown in this embodiment, a specific implementation of a monostable trigger circuit is provided. The monostable trigger circuit includes a resistor R7, a capacitor C2, a capacitor Cf, and a timer chip U2. The timer chip U2 includes at least 8 pins. Pin 1 (VCC) and pin 2 (RST) of the timer chip U2 are connected to an 18.5V DC power supply and one end of the resistor R7. Pin 3 (DIS) and pin 4 (THR) are both connected to the other end of the resistor R7 and one end of the capacitor C2. Pin 5 (TRI) is used as the input terminal of the monostable trigger circuit. Pin 6 (CON) is connected to one end of the capacitor Cf. Pin 7 (GND) is grounded. Pin 8 (OUT) is used as the output terminal of the monostable trigger circuit. The other ends of capacitor C2 and capacitor Cf are both grounded. In this embodiment, capacitor Cf is used as a compensation capacitor and is a 10nF ceramic capacitor. The timer chip U2 is an LM555CM general-purpose timer chip, which is an 8-pin device.

[0032] In this embodiment, the monostable trigger circuit is triggered by the falling edge pulse output from the subtraction circuit. After triggering, pin 8 OUT generates a brief high-amplitude positive pulse with a pulse amplitude equal to the 18.5V power supply voltage. The pulse width is determined by the formula t2=1.1×R7×C2. In this embodiment, the pulse width is 3.5μs. The compensation capacitor Cf is used to stabilize the threshold of the internal comparator of the 555 timer, reduce noise interference, ensure the stability and consistency of the pulse output, and avoid problems such as repeated triggering and pulse widening.

[0033] Example 5 This embodiment is the fifth embodiment of a pulse-driven optimization circuit. This embodiment is similar to Embodiment 1, except that, as shown in the following... Figure 1 and Figure 5As shown in the figure, this embodiment provides a specific implementation of a signal superposition circuit. The signal superposition circuit includes resistors R8, R9, R10, and R11, and operational amplifier U3. The input terminal of resistor R8 is used as the first input terminal of the signal superposition circuit, and its output terminal is connected to the non-inverting input terminal of operational amplifier U3 and the output terminal of resistor R9. The output terminal of resistor R9 is connected to the non-inverting input terminal of operational amplifier U3, and its input terminal is used as the second input terminal of the signal superposition circuit. One end of resistor R10 is connected to the inverting input terminal of operational amplifier U3 and one end of resistor R11, and the other end of resistor R10 is grounded. The other end of resistor R11 is connected to the output terminal of operational amplifier U3, and the output terminal of operational amplifier U3 is used as the output terminal of the signal superposition circuit. In this embodiment, resistors R8, R9, R10, and R11 are all 500Ω precision resistors, and operational amplifier U3 is an AD8055AN high-speed broadband operational amplifier. Its positive and negative power supply terminals are connected to 25V and -25V DC power supplies, respectively, to ensure the matching of signal transmission with the operational amplifier model of the subtraction circuit. The output of operational amplifier U3 serves as the final output of the entire pulse drive optimization circuit and is connected to the heater resistor input of the thermo-optical tuned optoelectronic integrated chip.

[0034] In this embodiment, the output voltage of the signal superposition circuit satisfies the formula: when R8 / / R9=R10 / / R11, the output voltage... , This is the original input drive signal for the first input terminal. The second input terminal is a high-amplitude, short-duration pulse signal. By adjusting the resistance values ​​of resistors R8, R9, R10, and R11, the superposition ratio of the two input signals can be adjusted. In this embodiment, since the resistance values ​​are equal, proportional superposition is achieved. The final output signal is a composite drive signal consisting of a high-amplitude, short-duration pulse superimposed on the rising edge of the original input drive signal, as shown in the attached diagram. Figure 7 As shown in the simulation waveform, the signal is applied to the heater of the thermo-optical tuning optoelectronic integrated chip. The instantaneous high power accelerates the thermal response process of the heater, greatly improving the thermo-optical tuning speed of the chip. Moreover, because the pulse duration is extremely short, it does not significantly increase the average power consumption of the circuit.

[0035] In the specific implementation of the above embodiments, the technical features can be combined in any non-contradictory way. For the sake of brevity, not all possible combinations of the above technical features are described. However, as long as the combination of these technical features is not contradictory, it should be considered to be within the scope of this specification.

[0036] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A pulse-driven optimization circuit, characterized in that, The system includes a rising edge detection circuit, a subtraction circuit, a monostable trigger circuit, and a signal superposition circuit. The input terminal of the rising edge detection circuit is connected to the input signal, and the output terminal is connected to the input terminal of the subtraction circuit. The output terminal of the subtraction circuit is connected to the input terminal of the monostable trigger circuit. The output terminal of the monostable trigger circuit is connected to the second input terminal of the signal superposition circuit. The first input terminal of the signal superposition circuit is connected to the input signal, and the output terminal is used to output the signal. The rising edge detection circuit extracts the rising edge positive pulse of the input signal, converts it into a falling edge pulse under a reference voltage by the subtraction circuit, triggers the monostable trigger circuit to generate a high-amplitude short pulse, and finally the signal superposition circuit superimposes the high-amplitude short pulse onto the rising edge of the original input signal to output a drive signal adapted to the thermo-optical tuned optoelectronic integrated chip.

2. The pulse drive optimization circuit according to claim 1, characterized in that, The input signal is detected by the RC differentiating circuit composed of capacitor C1 and resistor R1 in the rising edge detection circuit to detect the rising edge and falling edge, and generates brief positive and negative pulses at the rising and falling edges. After passing through diode D1, the negative pulse at the falling edge is filtered out and the corresponding positive pulse at the rising edge is extracted, thereby realizing the rising edge detection of the input signal.

3. The pulse drive optimization circuit according to claim 2, characterized in that, The rising edge detection circuit includes a capacitor C1, a resistor R1, a resistor R2, and a diode D1; one end of the capacitor C1 is connected to the input signal, and the other end is connected to one end of the resistor R1 and the anode of the diode D1; the other end of the resistor R1 is grounded; the cathode of the diode D1 is connected to one end of the resistor R2 and serves as the output terminal of the rising edge detection circuit; the other end of the resistor R2 is grounded.

4. The pulse drive optimization circuit according to claim 1, characterized in that, The subtraction circuit can perform subtraction on the input signal on a preset voltage baseline. After the input positive pulse signal passes through the subtraction circuit, it can output a falling edge short pulse signal with the preset voltage as the baseline.

5. The pulse drive optimization circuit according to claim 4, characterized in that, The subtraction circuit includes resistors R3, R4, R5, and R6, and operational amplifier U1. One end of resistor R3 serves as the input terminal of the subtraction circuit, and the other end is connected to the inverting input terminal of operational amplifier U1 and the input terminal of resistor R5. One end of resistor R4 is connected to a power supply, and the other end is connected to the non-inverting input terminal of operational amplifier U1 and one end of resistor R6. The other end of resistor R6 is grounded. The output terminal of resistor R5 is connected to the output terminal of operational amplifier U1. The output terminal of operational amplifier U1 is used as the output terminal of the subtraction circuit.

6. The pulse drive optimization circuit according to claim 1, characterized in that, The monostable trigger circuit can identify the falling edge of the output pulse signal and generate a brief positive pulse signal that changes from zero to a high amplitude at the falling edge.

7. The pulse drive optimization circuit according to claim 6, characterized in that, The monostable trigger circuit includes a resistor R7, a capacitor C2, a capacitor Cf, and a timer chip U2. Pin 1 (VCC) and pin 2 (RST) of the timer chip U2 are connected to the power supply and one end of the resistor R7. Pin 3 (DIS) and pin 4 (THR) are both connected to the other end of the resistor R7 and one end of the capacitor C2. Pin 5 (TRI) is used as the input of the monostable trigger circuit. Pin 6 (CON) is connected to one end of the capacitor Cf. Pin 7 (GND) is grounded. Pin 8 (OUT) is used as the output of the monostable trigger circuit. The other ends of capacitors C2 and Cf are both grounded.

8. The pulse drive optimization circuit according to claim 1, characterized in that, The signal superposition circuit can superimpose the two input signals at the first input terminal and the second input terminal in a proportional manner, and the output signal includes: a short high-amplitude pulse signal at the rising edge superimposed on the overall circuit input signal.

9. The pulse drive optimization circuit according to claim 8, characterized in that, The signal superposition circuit includes resistors R8, R9, R10, and R11, and operational amplifier U3. The input terminal of resistor R8 is used as the first input terminal of the signal superposition circuit, and its output terminal is connected to the non-inverting input terminal of operational amplifier U3 and the output terminal of resistor R9. The output terminal of resistor R9 is connected to the non-inverting input terminal of operational amplifier U3, and its input terminal is used as the second input terminal of the signal superposition circuit. One end of resistor R10 is connected to the inverting input terminal of operational amplifier U3 and one end of resistor R11, and the other end of resistor R10 is grounded. The other end of resistor R11 is connected to the output terminal of operational amplifier U3, and the output terminal of operational amplifier U3 is used as the output terminal of the signal superposition circuit.

10. The pulse drive optimization circuit according to claim 9, characterized in that, When R8 / / R9=R10 / / R11, the output voltage , This is the original input drive signal for the first input terminal. The second input terminal is a high-amplitude, short-duration pulse signal; by adjusting the resistance values ​​of resistors R8, R9, R10, and R11, the superposition ratio of the two input signals can be adjusted.

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