Semiconductor structure

Abstract

The utility model provides a semiconductor structure, comprising a first semiconductor tube core or wafer comprising a first bonding crack detection structure part, and the first bonding crack detection structure part comprises discrete bonding crack detection structure parts which are electrically isolated; and a second semiconductor die or wafer bonded to the first semiconductor die, the second semiconductor die or wafer comprising a second bonding crack detection structure portion, the second bonding crack detection structure portion comprising discrete bonding crack detection structure portions, wherein the first bonding crack detection structure part and the second bonding crack detection structure part are bonded together to form the bonding crack detection structure.

Description

Technical Field

[0001] This utility model relates to a semiconductor structure. Background Technology

[0002] The following is about semiconductor devices, die and wafer bonding interface crack detectors and their formation methods. Utility Model Content

[0003] In one embodiment, a semiconductor structure includes: a first semiconductor die including a first bonding crack detection structure portion, the first bonding crack detection structure portion including a first set of metal bonding pads operably connected to a bonding interface side of the first semiconductor die and a second set of metal bonding pads operably connected to a bonding interface side of the first semiconductor die, the second set of metal bonding pads being electrically isolated from the first set of metal bonding pads; and a second semiconductor die bonded to the first semiconductor die, the second semiconductor die including a second bonding crack detection structure portion bonded to the first bonding crack detection structure portion. The second bonding crack detection structure includes a third set of metal bonding pads operably connected to the bonding interface side of the second semiconductor die and a fourth set of metal bonding pads operably connected to the bonding interface side of the second semiconductor die. The fourth set of metal bonding pads is electrically isolated from the third set of metal bonding pads. The first bonding crack detection structure and the second bonding crack detection structure are bonded together to form a bonding crack detection structure. The first set of metal bonding pads is electrically connected to the third set of metal bonding pads, and the second set of metal bonding pads is electrically connected to the fourth set of metal bonding pads.

[0004] In another embodiment, a semiconductor structure includes: a first semiconductor wafer including a first bonding crack detection structure portion, the first bonding crack detection structure portion including a first set of metal bonding pads operably connected to a bonding interface side of the first semiconductor wafer and a second set of metal bonding pads operably connected to a bonding interface side of the first semiconductor wafer, the second set of metal bonding pads being electrically isolated from the first set of metal bonding pads; and a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer including a second bonding crack detection structure portion bonded to the first bonding crack detection structure portion. The second bonding crack detection structure includes a third set of metal bonding pads operably connected to the bonding interface side of the second semiconductor wafer and a fourth set of metal bonding pads operably connected to the bonding interface side of the second semiconductor wafer. The fourth set of metal bonding pads is electrically isolated from the third set of metal bonding pads. The first bonding crack detection structure and the second bonding crack detection structure are bonded together to form the bonding crack detection structure. The first set of metal bonding pads is electrically connected to the third set of metal bonding pads, and the second set of metal bonding pads is electrically connected to the fourth set of metal bonding pads.

[0005] In another embodiment, a method for processing a semiconductor stack includes: measuring the electrical characteristics of a bonding crack detection structure disposed at the interface between a first semiconductor wafer or die of the semiconductor stack and a second semiconductor wafer or die of the semiconductor stack bonded to the first semiconductor wafer or die of the semiconductor stack, the bonding crack detection structure comprising: a first conductor including a first set of metal bonding bumps of the first semiconductor wafer or die and a third set of metal bonding bumps of the second semiconductor wafer or die, the third set of metal bonding bumps being bonded to the first set of metal bonding bumps of the first semiconductor wafer or die; and a second conductor including the first semiconductor wafer or die. The second set of metal bonding bumps and the fourth set of metal bonding bumps of the second semiconductor wafer or die are bonded to the second set of metal bonding bumps of the first semiconductor wafer or die, wherein the first conductor and the second conductor are electrically isolated from each other in the absence of bonding cracks; the bonding cracks are determined to be absent at the interface between the first semiconductor wafer or die and the second semiconductor wafer or die of the semiconductor stack based on the measured electrical characteristics of the bonding crack detection structure; and the semiconductor stack is cut in response to determining that there are no bonding cracks at the interface between the first semiconductor wafer or die and the second semiconductor wafer or die of the semiconductor stack. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A and Figure 1B A semiconductor chip stack including mixed bonding cracks is shown according to an exemplary embodiment of the present disclosure;

[0008] Figures 2A to 2C This illustrates a semiconductor die stack including a bond crack detection structure according to an exemplary embodiment (Example 3) of the present disclosure. Figure 2A It is a perspective view. Figure 2B It is a top view and Figure 2C It is a cross-sectional view;

[0009] Figures 3A to 3C Various operational details of a bond crack detection structure according to exemplary embodiments of the present disclosure are shown;

[0010] Figure 4 A bonding crack detection system according to an exemplary embodiment of the present disclosure is shown, the system including a bonding crack detection structure and a leakage current detector E test (electrical test) device for measuring the leakage current IV (current-voltage) representing a bonding interface crack;

[0011] Figure 5A and Figure 5B Further details of a semiconductor die stack including a bond crack detection structure 2001 according to an exemplary embodiment (Example 1) of the present disclosure are shown;

[0012] Figure 6A and Figure 6B Further details of a semiconductor die stack including a bond crack detection structure 2002 according to an exemplary embodiment (Embodiment 2) of the present disclosure are shown;

[0013] Figure 7A and Figure 7B This illustrates another semiconductor die stack including a bond crack detection structure 2003 according to an exemplary embodiment (Example 3) of the present disclosure;

[0014] Figures 8A to 8C Further operational and design details associated with a bond crack detection structure according to exemplary embodiments of the present disclosure are shown;

[0015] Figure 9A This illustration shows multiple bond crack detection structures integrated into a SoC (System-on-a-Chip) package according to exemplary embodiments of the present disclosure, and Figure 9B This illustration shows multiple bond crack detection structures integrated into a wafer according to exemplary embodiments of the present disclosure, the wafer including multiple SoCs;

[0016] Figure 10 This illustration shows a process for manufacturing a semiconductor die stack including multiple bond crack detection structures according to exemplary embodiments of the present disclosure;

[0017] Figure 11 The present disclosure illustrates a process for manufacturing a semiconductor wafer stack including multiple bond crack detection structures, according to an exemplary embodiment of the present disclosure.

[0018] Explanation of icon numbers

[0019] 11: Bottom semiconductor die;

[0020] 12, 22: IMD;

[0021] 21: Top semiconductor die;

[0022] 31: Key interface;

[0023] 41, 51: Metal bonding pads;

[0024] 61: Unbonded region / Unbonded and layered region / Layered region;

[0025] 62: Cracks / bonded interface cracks / bonded cracks;

[0026] 63: Bonding crack;

[0027] 101: First semiconductor die / bottom semiconductor die / bottom die;

[0028] 102, 202: IMD layer / IMD material / IMD;

[0029] 110, 210: Conductor / Conductor A section;

[0030] 111: First set of metal bonding pads / metal bonding pads;

[0031] 112, 122, 212, 222: Through-holes for metal bonding pads;

[0032] 113: Conductor / Electrical Connection;

[0033] 114, 124: IMD layer;

[0034] 115, 125: First horizontal interconnection;

[0035] 120, 220: Conductor / Conductor B section;

[0036] 121: Second set of metal bonding pads / metal bonding pads;

[0037] 123: Conductor;

[0038] 201: Second semiconductor die / Top semiconductor die / Top die;

[0039] 201A, 201B: SoC chips;

[0040] 211: Third group of metal bonding pads / metal bonding pads;

[0041] 212A, 212B, 212C, 213A, 213B, 213C: Through holes;

[0042] 213: Conductor / Through Hole / Electrical Connection;

[0043] 221: Fourth group of metal bonding pads / metal bonding pads;

[0044] 222A, 222B, 222C, 223A, 223B, 223C: Metallization layers;

[0045] 223: Conductor / Through Hole;

[0046] 301: Keying interface;

[0047] 311: Crack detection zone / detection area;

[0048] 401: Leakage Current Detector / Leakage Current Detector E Test Unit / Unit / Current Detector / Automatic Test Equipment / ATE;

[0049] 411: First potential;

[0050] 412: Second potential;

[0051] 461, 462: Current path / leakage current path / leakage current;

[0052] 1001, 2001, 2002: Bond crack detection structures;

[0053] 1001A, 1001B: Bond crack detection structure;

[0054] 1002: SoC / SoC chip / integrated circuit / IC;

[0055] 1003: Wafer;

[0056] 1004: First horizontal interconnect;

[0057] 1005: Pore / isolation area;

[0058] 1011, 1012: Metallization layers;

[0059] 1101: Bottom wafer;

[0060] 1102: Top wafer;

[0061] BPMPITCHx1, BPMPITCHx2: Bonding pad pitch;

[0062] BPMPITCHy1, BPMPITCHy2: BPM pitch;

[0063] oS: substrate;

[0064] S101, S102, S201, S202, S203, S301, S302, S303, S1101, S1201, S1301, S1302, S1303: Steps;

[0065] TDL: Length;

[0066] VDRh: Metal bonding pad thickness / BPM thickness / length;

[0067] x, y: Direction. Detailed Implementation

[0068] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in the various examples of this disclosure. Such repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0069] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “above” to describe the relationship between one component or feature and another, as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device or operation in use. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein can be interpreted accordingly.

[0070] As used herein, the term "layer" can include a single layer or multiple layers.

[0071] As used herein, the term "intermetallic dielectric" (IMD) film or layer refers to a dielectric / insulating material layer between two metal or other conductive layers. As some non-limiting illustrative examples, IMD materials may include polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), spin-coated glass (SOG), fluoride-doped silicate glass (FSG), carbon-doped silicon oxide (SiCOH), polyimide, amorphous fluorinated carbon, bisbenzocyclobutene (BCB), silsesquioxane, fluorinated silicon oxide (SiOF), and / or combinations thereof.

[0072] As used herein, the term "interlayer dielectric" (ILD) refers to an insulating structure of material placed between two conductive layers. As some non-limiting illustrative examples, the ILD layer may include polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), spin-coated glass (SOG), fluoride-doped silicate glass (FSG), carbon-doped silicon oxide (SiCOH), polyimide, amorphous fluorinated carbon, bisbenzocyclobutene (BCB), hydrogen silsesquioxane, fluorinated silicon oxide (SiOF), and / or combinations thereof.

[0073] As used herein, the term "hybrid bonding" refers to a bonding process that simultaneously incorporates dielectric and metal bonding pads in a single bonding step, wherein semiconductor dies and / or semiconductor wafer stacks are bonded to an interface (e.g., a metal-oxide interface). Hybrid bonding is a permanent bonding process, and in some embodiments, dielectric bonding (e.g., SiO2) is used. x Hybrid bonding is combined with embedded metal (e.g., Cu) to form interconnects. In some embodiments, hybrid bonding extends fusion bonding with embedded metal pads in the bonding interface, which allows the die and wafer to be connected face-to-face.

[0074] The terms “bonding pad,” “bonding pad structure,” “hybrid bonding pad,” and “metal bonding bump” are used interchangeably to refer to a metal bonding pad connected to a bonding pad via. The metals used herein may include elemental metals (e.g., copper, aluminum), metal alloys, or other suitable conductive materials such as titanium nitride or tantalum nitride.

[0075] As used herein, the term "bond crack detection structure" refers to a structure integrated or incorporated into a semiconductor structure for detecting cracks within the semiconductor structure. Alternatively, "bond crack detection structure" may also be referred to as, and includes, a "bond crack detection sensor" for detecting cracks within a semiconductor structure.

[0076] As used herein, the terms “metallization layer” and “conductor” describe the bond crack detection structures disclosed herein, including conductors, layers, traces, or tracks made of copper, aluminum (Al), and other conductive metals.

[0077] In some embodiments, a bonding crack detection structure for testing cracks in the bond between a first semiconductor wafer or die and a second semiconductor wafer or die is constructed as follows. The first conductor of the bonding crack detection structure includes a first set of metal bonding bumps disposed on the first semiconductor wafer or die and a third set of metal bonding bumps disposed on the second semiconductor wafer or die, wherein the third set of metal bonding bumps is bonded to the first set of metal bonding bumps on the first semiconductor wafer or die. The second conductor of the bonding crack detection structure includes a second set of metal bonding bumps disposed on the first semiconductor wafer or die and a fourth set of metal bonding bumps disposed on the second semiconductor wafer or die, wherein the fourth set of metal bonding bumps is bonded to the second set of metal bonding bumps on the first semiconductor wafer or die. The first conductor and the second conductor constitute a capacitor structure, and the first conductor and the second conductor are electrically isolated from each other in the absence of bonding cracks. Therefore, the electrical bias applied between the first conductor and the second conductor should generate a low current (ideally zero). However, in the presence of a bond crack, the electrical isolation between the first and second conductors is disrupted, and a larger current will be measured, indicating a crack. If water ingress occurs at the interface due to a crack (in this example, an incomplete or non-hermetic bond between wafers), this will also be detected as an increased measurement current. Therefore, the disclosed bond crack detection structure provides a convenient electrical test for cracks. While measuring the current in response to an applied voltage is a convenient measurement, other electrical characteristics of the capacitive bond crack detection structure, such as resistance, can also be measured. Furthermore, since a crack must penetrate or otherwise impact the bond crack detection structure to be detected, in some embodiments, the bond crack detection structure is designed to have an increased total area.

[0078] This disclosure provides a semiconductor die and wafer bonding interface / crack detection test structure and system for detecting cracks at the semiconductor die and wafer bonding interface. According to an exemplary embodiment, the disclosed semiconductor die and wafer test structure and system are used to detect bonding interface cracks by measuring leakage current representing a bonding interface crack during die and / or wafer processing. Alternatively, the resistance of the bonding interface crack detection structure can be measured to determine the bonding interface crack. The disclosed bonding interface test structure can be used as part of an E-testing process associated with one or more of the WAT / WLCP / FT (Wafer Acceptance Testing / Wafer-Level Chip Packaging / Final Testing) stages. Some exemplary application areas include 3DIC products formed by stacking and attaching semiconductor dies and wafers using hybrid bonding interfaces.

[0079] Based on some embodiments disclosed herein, a bonding film crack detection structure for incorporation in semiconductor stacked dies and / or semiconductor stacked wafer arrangements is provided below. Bonding interface cracks, such as bonding film cracks, may occur during the fabrication process of stacked semiconductor dies and / or wafers. For the purposes of this disclosure, bonding interface cracks and their detection are described in the context of hybrid bonding processes, which may include simultaneously bonding dielectric and metal bonding pads in a single bonding step, wherein the semiconductor die and semiconductor wafer stack are bonded via metal and oxide interfaces. However, the disclosed crack detection structure is not limited to hybrid bonding.

[0080] Bond interface cracks can cause mechanical breakage of metal traces, leading to electrical shunting or open-circuit electrical connection failures in semiconductor components. Furthermore, relatively large bond interface cracks can cause intermetallic leakage if moisture penetrates the chip through them. Traditional methods for identifying bond interface cracks typically only occur after the crack has caused a catastrophic failure, such as an electrical open circuit or a conductor associated with the chip being tested during the manufacturing process. Some methods for identifying bond interface cracks include using scanning electron microscopy (SEM) or IR to analyze cross-sectional portions of the chip to confirm the presence of the crack. This failure testing and analysis usually occurs late in the packaging assembly process or reliability testing, making it impossible to identify initial bond interface cracks early in the process. This paper discloses a bond interface crack detection structure and an E-test structure to detect bond interface cracks, such as mixed bond interface cracks, during one or more semiconductor chip manufacturing processes.

[0081] According to an exemplary embodiment of the disclosed bond interface crack detector structure, the interdigitated comb-like metal-oxide-metal (MOM) capacitor structure is formed from BEOL (back-end process) metal and a hybrid bonding metal. To improve the bond interface crack detection sensitivity, the crack detection structure utilizes a hybrid bonding metal layer (metal and vias in the top and bottom dies or wafers) to form relatively thick capacitor sidewalls. These thick sidewalls introduce more crack detection areas for leakage current testing using IVE test cells. For stacked and bonded die arrangements, the bond interface crack detection structure is locally formed from the top die and locally from the bottom die, wherein the bond interface crack detection structure is embedded in the bond interface close to the potential crack location, thereby increasing the likelihood that bond interface faults are detected.

[0082] Some features and advantages of the disclosed bonding interface structure and E-test structure are that electrical testing of mixed bonding cracks does not require the use of time-consuming physical failure analysis (PFA), which in fact cannot be performed for each semiconductor die, wafer, and / or chip. Other advantages may include: (1) relatively quick and simple current leakage testing via IV measurement (leakage indicates the presence of a crack); (2) bond crack detection or lack thereof can be performed at one or more of several manufacturing stages (e.g., WAT / WLCP / FT), so that when bond interface cracks occur, they can be identified through a step-by-step process to locate the appropriate manufacturing process step to improve / correct the cause of the detected bond interface cracks; (3) the bond interface test structure requires only a relatively small area compared to the overall size of the semiconductor die and the wafer it comprises, which allows the disclosed bond interface test structure to be placed in the dicing channel for testing during the WAT stage; (4) the relatively small size of the bond interface crack detection structure allows the crack detection structure to be located at die or chip corners where crack formation is at a high risk.

[0083] The following detailed description will primarily describe the disclosed bond interface crack detection structure and its formation method, which is integrated into a top semiconductor die portion and a bottom semiconductor die portion, and the top and bottom semiconductor dies are subsequently mixed and bonded to form a complete bond interface crack detection structure. However, the disclosed bond interface crack detection structure and its formation method can also be integrated into a top semiconductor wafer portion and a bottom semiconductor wafer portion, and the top and bottom semiconductor wafers are subsequently mixed and bonded to form a complete bond interface crack detection structure.

[0084] refer to Figure 1A and Figure 1B The formation of bonding cracks during the hybrid bonding of the top semiconductor die (or wafer) 21 and the bottom semiconductor die (or wafer) 11, and the use of bonding cracks for testing leakage current, will now be described in more detail in this disclosure. As shown, initially, the stacked bottom semiconductor die 11 is fabricated to include metal bonding pad 41, and the top semiconductor die 21 is fabricated to include metal bonding pad 51. Metal bonding pads 41 and 51 are bonded (e.g., fused) during the die bonding process to form a hybrid bond of the bottom and top semiconductor dies. The hybrid bonding process also includes dielectric bonding (IMD 12 and IMD 22) of the semiconductor dies at the bonding interface 31.

[0085] Now for reference Figure 1BFurthermore, as previously discussed, during the manufacturing process, cracks 62 may develop in the bonding interface 31 due to unbonded and delaminated areas of the bonding interface 31. As shown, die failures are caused by non-electrical contact of one or more of any metal bonding pads 41 and 51 that are not electrically contacted (i.e., not fused).

[0086] because Figure 1B The illustrated semiconductor stack shows delamination and unbonded regions 61. When a crack forms during the bonding process of the bottom semiconductor die 12 and the top semiconductor die 22, moisture permeates into the crack 62 at the bonding interface. This disclosure and the exemplary embodiments described herein utilize the cracked moisture to test for leakage current between one or more metal bonding pads by applying a high / low voltage potential to normally electrically isolated metal bonding pads. If leakage current exists from one metal bonding pad to another normally electrically isolated bonding pad, the leakage current is caused by the crack 62 at the bonding interface and the conductive moisture contained therein. In this regard, it can be noted that the crack can form during bonding or during a later fabrication process, such as a subsequent process involving heating the bonded wafer stack, where heat can cause delamination. Advantageously, the E test disclosed herein can be repeated at multiple points during the fabrication process to detect initial or later-initiated cracks.

[0087] Now for reference Figures 2A to 2C This illustrates a semiconductor die stack including a bond crack detection structure 1001 according to an exemplary embodiment (Example 3) of the present disclosure, wherein the bond crack detection structure 1001 includes an interdigitated MOM capacitor structure. Reference is made below. Figure 5A and Figure 5B (Example 1) and Figure 6A and Figure 6B (Example 2) Describes Example 1 and Example 2.

[0088] like Figures 2A to 2C As shown, the bonding interface crack detection structure includes a first (or bottom) semiconductor die 101 and a second (or top) semiconductor die 201. The bottom semiconductor die 101 includes a first bonding crack detection structure portion formed in the IMD layer 102, and the top semiconductor die 201 includes a second bonding crack detection structure portion formed in the IMD layer 202. The top semiconductor die 201 and the bottom semiconductor die 101 are co-bonded together to form a stacked die arrangement, wherein the bonding crack detection structure portion of the top semiconductor die 201 is bonded to the bonding crack detection structure portion of the bottom semiconductor die. Figures 2A to 2COne or more functional circuits (e.g., including MOSFETs, diodes, and / or other semiconductor devices) formed on the top semiconductor die 101 and / or the bottom semiconductor die 201 are not shown, which provide functional features of the completed chip. The bond crack detection structure disclosed and described herein is electrically isolated from any functional circuitry on the semiconductor die or wafer. However, depending on the design of the functional circuitry, the bond crack detection structure may potentially be integrated within the functional circuitry, which is also within the scope of this disclosure.

[0089] Refer again Figures 2A to 2C The bonding crack detection structure of the bottom semiconductor die 101 includes a first set of metal bonding pads 111 operably connected to the bonding interface 301 side of the bottom semiconductor die and a second set of metal bonding pads 121 parallel to and laterally offset from the first set of metal bonding pads 111. The second set of metal bonding pads 121 is operably connected to the bonding interface 301 side of the bottom semiconductor die and is electrically isolated from the first set of metal bonding pads by an IMD material 102, which acts as an insulator in the gap or lateral offset between the first set of metal bonding pads 111 and the second set of metal bonding pads 121. The bonding crack detection structure of the top semiconductor die 201 includes a third set of metal bonding pads 211 operably connected to the bonding interface 301 side of the top semiconductor die and a fourth set of metal bonding pads 221 parallel to and laterally offset from the third set of metal bonding pads 211. The fourth set of metal bonding pads 221 is operatively connected to the bonding interface 301 side of the top semiconductor die 201, and the fourth set of metal bonding pads 221 is electrically isolated from the third set of metal bonding pads 211 by an IMD material 202, which acts as an insulator in the gap or lateral offset between the third set of metal bonding pads 211 and the fourth set of metal bonding pads 221.

[0090] The bottom bonding crack detection structure portion (first group of metal bonding pads 111 and second group of metal bonding pads 121) and the second bonding crack detection structure portion (third group of metal bonding pads 211 and fourth group of metal bonding pads 221) are bonded together to form a bonding crack detection structure. The first group of metal bonding pads 111 and the third group of metal bonding pads 211 are electrically connected to form conductor A (conductor 110 is electrically connected to conductor 210), and the second group of metal bonding pads 121 and the fourth group of metal bonding pads 221 are electrically connected to form conductor B (conductor 120 is electrically connected to conductor 220). Furthermore, after bonding, the first group of metal bonding pads 111 and the bonded / electrically connected third group of metal bonding pads 211 are electrically isolated from the second group of metal bonding pads 121 and the bonded / electrically connected fourth group of metal bonding pads 221.

[0091] Figures 2A to 2CFurther details of the bond crack detection structure shown include vias (e.g., tungsten vias or vias of another conductive material) formed in the bottom semiconductor die 101 and the top semiconductor die 202. These vias are formed in IMD layers 102 and 202 and provide electrical connections between the metal bonding pads and connected conductors 220 or metallization layers, which include traces or tracks electrically interconnecting the metal bonding pads to form chains or segments of the bond crack detection structure. Figures 2A to 2C As shown, these conductive strings or segments are arranged as multiple fingers that intersect each other to provide an intersecting MOM capacitor structure.

[0092] More specifically, the bonded and completed bond crack detection structure includes a bottom semiconductor die crack detection portion, which includes two electrically isolated conductor portions or legs (such as conductor A portion 110 and conductor B portion 120). Conductor A portion 110 includes a metal bonding pad 111 electrically connected to conductor 113 via a metal bonding pad via 112, and conductor B portion 120 includes a metal bonding pad 121 electrically connected to conductor 123 via a metal bonding pad via 122. The bonded and completed bonding crack detection structure also includes a top semiconductor die crack detection section, which includes two electrically isolated conductor portions or legs (such as conductor A portion 210 and conductor B portion 220). Conductor A portion 210 includes a metal bonding pad 211 electrically connected to conductor 213 via a metal bonding pad via 212, and conductor B portion 220 includes a metal bonding pad 221 electrically connected to conductor 223 via a metal bonding pad via 222.

[0093] The following will be referenced Figures 8A to 8C More fully, the sensitivity of the disclosed bond crack detection structure is affected by factors including, but not limited to, the following:

[0094] (1) Metal bonding pad count (BPM count), where the higher the BPM count, the greater the crack detection sensitivity / accuracy of the bonding crack detection structure for bonding cracks present in the bonding interface.

[0095] (2) Pitch or spacing of metal bonding pads (BPM pitch), where the lower the BPM pitch, the greater the crack detection sensitivity of the bonding crack detection structure for bonding cracks present in the bonding interface.

[0096] (3) Finger counts (FC), where a higher FC indicates greater crack detection sensitivity for bond cracks present at the bonding interface; and

[0097] (4) Routing layer count (RLC), wherein routing layers (e.g., vias 213 and 223) can be extended to provide a multilayer interdigitated MOM capacitor arrangement comprising multiple stacked conductor portions (e.g., conductor A portion 210 and conductor B portion 220). This stacked multilayer arrangement extends the vertical crack detection region to the height of the IMD (e.g., IMD layer 202), thereby providing complete vertical crack detection up to the height of the IMD layer.

[0098] refer to Figures 3A to 3C and Figure 4 This illustrates various operational details of a crack detection structure according to an exemplary embodiment (Example 2) of this disclosure, which is also applicable to other embodiments described herein. Specifically, Figures 3A to 3C The current flowing through the leakage current path present in the bond crack detection structure disclosed herein is shown.

[0099] refer to Figure 3A This illustrates a stacked and bonded semiconductor die arrangement (including a bottom semiconductor die 101 and a top semiconductor die 201) that does not contain any bonding interface cracks. In other words, Figure 3A This demonstrates an acceptable, bonded pair of semiconductor dies without any cracks. The bond crack detection structure is as previously referenced. Figures 2A to 2C As described, the bottom semiconductor die 101 includes a first string of electrically connected metal bonding pads 111 and a second string of electrically connected metal bonding pads 121, the second string of electrically connected metal bonding pads 121 being electrically isolated from the first string of electrically connected metal bonding pads 111. The top semiconductor die 201 includes a third string of electrically connected metal bonding pads 211 and a fourth string of electrically connected metal bonding pads 221, the fourth string of electrically connected metal bonding pads 221 being electrically isolated from the third string of electrically connected metal bonding pads 211. As previously described, the bottom bonding crack detection structure portion (first group of metal bonding pads 111 and second group of metal bonding pads 121) and the second bonding crack detection structure portion (third group of metal bonding pads 211 and fourth group of metal bonding pads 221) are bonded together to form a bonding crack detection structure. The first group of metal bonding pads 111 and the third group of metal bonding pads 211 are electrically connected to form conductor A, and the second group of metal bonding pads 121 and the fourth group of metal bonding pads 221 are electrically connected to form conductor B. Furthermore, after bonding, the first group of metal bonding pads 111 and the bonded / electrically connected third group of metal bonding pads 211 are electrically isolated from the second group of metal bonding pads 121 and the bonded / electrically connected fourth group of metal bonding pads 221.

[0100] refer to Figure 3BThe image shows a stacked and bonded semiconductor die arrangement (including a bottom semiconductor die 101 and a top semiconductor die 201) that includes a bonding interface crack 62 caused by manufacturing inconsistencies, resulting in unbonded and delaminated areas at the bonding interface. In other words, Figure 3B This diagram illustrates an unacceptable, bonded pair of semiconductor dies that includes a crack and is rejected for any further manufacturing process. As shown, moisture from the bonding process enters the unbonded and delaminated region 61 of interface region 301 and permeates into the crack 62. The moisture contained in the unbonded region 61 and the crack 62 provides current paths 461 and 462 from a V-source (not shown) from metal bonding pad 211 to metal bonding pad 221. Without the crack 62 and the unbonded region 61, metal bonding pads 211 and 221 would typically be electrically isolated.

[0101] refer to Figure 4 This illustrates an exemplary embodiment of the present disclosure for measuring data as referenced above. Figure 3C The E-test system described above is used for detecting leakage current from unbonded / delaminated regions and bond cracks, and the E-test system includes, as described above... Figures 3A to 3C The shown bonding crack detection structure includes an electrical connection 113 to the metal bonding pad 111 of the bottom semiconductor die and an electrical connection 213 to the metal bonding pad 211 of the top semiconductor die.

[0102] Leakage current detector 401 generates a voltage difference, wherein a first potential (e.g., positive) 411 is applied to metal bonding pads 111 and 211, and a second potential (e.g., negative) 412 is applied to metal bonding pads 121 and 221. Figure 4 As can be seen, the voltage difference provides leakage current paths 461 and 462 from metal bonding pad 211 to metal bonding pad 221, which are typically electrically isolated if the crack 62 and unbonded region 61 are not present. For Figure 4As shown, the unbonded delamination region 61 (or water ingress at the delamination region 61) causes leakage current 461, and the bonding crack 62 also causes leakage current 462. Leakage current detector 401 monitors the current supplied by the leakage current detector E test unit 401. If a leakage current exceeding a threshold (e.g., 80 pA) is detected, the output of unit 401 notifies the appropriate system that a fault detection has been detected. Indeed, during test runs, it was found that the disclosed capacitive bonding crack detection structure provided a significant difference in measured current between examples where the measured current was below 100 picoamperes (no crack) and examples where a crack was present and the measured current was much larger (1 microampere or greater). In some of these tests, a difference of more than 10,000 was observed between the current amplitude measured during crack testing and no-crack testing.

[0103] It is worth noting that the E test can be performed using DC (direct current), thus simplifying the current detector 401. (However, AC (alternating current) testing is also conceivable). According to another exemplary embodiment, the E test system measures the resistance of the bond crack detection structure, where resistance below a threshold indicates bond interface cracks.

[0104] refer to Figures 5A to 5B This illustrates another exemplary embodiment of a semiconductor die stack including a bond crack detection structure according to an exemplary embodiment of the present disclosure (Embodiment 1). Figure 5A It is a top view. Figure 5B This is a cross-sectional view. According to this exemplary embodiment, the crack detection structure includes a single pair of metal bonding pads (including metal bonding pad 111 and metal bonding pad 211) providing conductor A and a pair of metal bonding pads (including metal bonding pad 121 and metal bonding pad 221) providing conductor B. Crack detection is limited to the region of IMD layers 102 and 202 between conductors A (121 and 221) and conductors B (102 and 202). This embodiment does not include the previously referenced... Figures 2A to 2C The metal bonding pad string under discussion. Automated Test Equipment (ATE) 401 provides automated VI testing of the semiconductor stack and bonding structure to determine the presence of any bonding interface cracks. Separate IMD layers 114 and 115, and IMD layers 124 and 125 provide external electrical connections from the bonding crack detection structure to ATE 401.

[0105] refer to Figure 6A and Figure 6B This illustrates another exemplary embodiment of a semiconductor die stack including a bond crack detection structure according to an exemplary embodiment of the present disclosure (Embodiment 2). Figure 6A It is a top view. Figure 6B This is a cross-sectional view. According to this exemplary embodiment, the crack detection structure includes a string of metal bonding pad pairs (including metal bonding pad 111 and metal bonding pad 211) for conductor A, and a string of metal bonding pad pairs (including metal bonding pad 121 and metal bonding pad 221) for conductor B. Crack detection is limited to the region of IMD layers 102 and 202 between conductors A (121 and 221) and conductors B (102 and 202). The embodiment includes, as previously referenced... Figures 2A to 2C The series of metal bonding pads discussed, however, does not include those described in the references. Figures 2A to 2C The described interdigitated fingers. Automated Test Equipment (ATE) 401 provides automated VI testing of semiconductor stacks and bonding structures to determine the presence of any bonding interface cracks. Separate IMD layers 114 and 115, and IMD layers 124 and 125 provide external electrical connections from the bonding crack detection structure to ATE 401.

[0106] refer to Figures 7A to 7B This illustrates exemplary embodiments according to the present disclosure (similar to previous references). Figures 2A to 2C Another exemplary embodiment of the semiconductor die stack including the bonding crack detection structure in the described embodiment 3). Figure 7A It is a top view. Figure 7B This is a cross-sectional view. According to this exemplary embodiment, the bond crack detection structure includes a previously referenced... Figures 2A to 2C All the features described will not be repeated here. Furthermore, the Automated Test Equipment (ATE) 401 provides automated VI testing of the semiconductor stack and bonding structure to determine the presence of any bonding interface cracks. Separate IMD layers 114 and 115, and IMD layers 124 and 125 provide external electrical connections from the bonding crack detection structure to the ATE 401.

[0107] refer to Figures 8A to 8C Further operational and design details associated with the crack detection structure according to an exemplary embodiment (Example 2) of this disclosure are shown.

[0108] refer to Figure 8A The diagram shows a top view of the bond crack detection structure, including a first crack detection area 311 (top) and a second crack detection area (bottom), which are related to the bond crack detection sensitivity and finger count.

[0109] Specifically, as shown in the figure, as the number of metal bonding pad fingers increases, the size of the crack detection zone 311 increases, resulting in an increase in the bonding crack detection sensitivity of the bonding crack detection structure. For comparison, Figure 8AThe smaller detection area 311 at the top includes one FC for conductor A (conductors 210 and 110 (not shown)) and one FC for conductor B (conductors 220 and 120 (not shown)). Figure 8A The bottom includes FC of 3 for conductor A (conductors 210 and 110 (not shown)) and FC of 2 for conductor B (conductors 220 and 120 (not shown)).

[0110] refer to Figure 8B The diagram shows a top view of the bond crack detection structure, including a first crack detection area 311 (top) and a second crack detection area (bottom), which are related to the bond crack detection sensitivity and the finger count / BPM pitch (i.e., the width of the metal bond pad).

[0111] Specifically, as shown in the figure, as the FC / BPM pitch ratio increases, the coverage density of the crack detection zone 311 increases, thereby increasing the bond crack detection sensitivity of the bond crack detection structure. In other words, as the coverage density of the crack detection zone 311 increases, the minimum detectable crack length decreases, thus providing detection of smaller cracks relative to the larger coverage density of the crack detection zone 311. Figure 8B top)

[0112] For comparison, Figure 8B The top detection area 311 includes one FC for conductor A (conductor 210 and conductor 110 (not shown)) and one FC for conductor B (conductor 220 and conductor 120 (not shown)). Figure 8B The bottom includes one FC for conductor A (conductors 210 and 110 (not shown)) and one FC for conductor B (conductors 220 and 120 (not shown)). However, in the embodiment at the bottom of the figure, the spacing width (i.e., minimum detectable length) between conductors 210 and 220 (and 110 and 120 (not shown)) is smaller (i.e. closer). Figure 8B The spacing width (i.e., minimum detectable length) of conductors 210 and 220 (and 110 and 120 (not shown)) in the top embodiment. In other words, the bonding pad pitch BPMPITCHx2 is less than the bonding pad pitch BPMPITCHx1. The BPM pitches BPMPITCHy1 and BPMPITCHy2 are equal in the top and bottom figures.

[0113] According to an exemplary embodiment, the BPM pitch in the x and y directions is 1µm to 100µm. Alternatively, the BPM pitch in the x direction is in the range of 0.001% to 10% of the die or chip width, and the BPM pitch in the y direction is in the range of 0.001% to 10% of the die or chip height.

[0114] According to an exemplary embodiment, the BPM count is in the range of 1 to 1975 BPM. Alternatively, the BPM count is shown to be in the range of 1 to chip width divided by BPM pitch (i.e., chip width / BPM pitch) in both the x and y directions.

[0115] Other factors affecting the sensitivity of bond crack detection structures include the thickness of the metal bond pads in the vertical direction, which is... Figure 8A and Figure 8B The z-axis (outside the paper) is shown. As the BPM thickness increases, the sensitivity of the bond crack detection structure increases because, as previously mentioned, more vertical areas of the IMD layer 202 are covered by conductors A and B. The BPM or metal bond pad thickness is equivalent and further shown as... Figure 8C VDRh(311) in the example. According to an exemplary embodiment, the BPM thickness or alternatively the BPM height is in the range of 1% to 100% of the thickness of the IMD layer 102 and / or the IMD layer 202, such as Figure 8C As shown.

[0116] refer to Figure 8C The diagram shows a top view of a bond crack detection structure, including a first crack detection region 311 (top) and a second crack detection region (bottom), which are related to the bond crack detection sensitivity and the metallization stack, such as the wiring of conductors A and B through the length of IMD 202, for example to the Si BEOL metal layer.

[0117] Specifically, as shown in the figure, with the increase of the number of metallization stacks, the vertical detection region (VDRh) extends vertically and the sensitivity of the bond crack detection structure increases. For example... Figure 8C As shown at the bottom, the metallization stack is formed by a series of interconnected vias 212A, 212B, 212C / 213A, 213B, 213C (conductor A) and metallization layers 222A, 222B, 222C / 223A, 223B, 223C (conductor B), thereby relative to Figure 8C The vertical detection area shown at the top (which is smaller than TDL) extends the vertical bond crack detection area vertically to the length TDL of the IMD layer 202. Figure 8C A second bonding crack 63 was detected in the extended vertical detection area at the bottom, while... Figure 8C No cracks were detected in the relatively short vertical crack detection zone at the top.

[0118] Other design considerations associated with the disclosed bond crack detection structure include the shape of the metal bond pads, which can be circular, elliptical, and / or polygonal. The placement of the bond crack detection structure on the die or wafer region also affects the effectiveness of bond crack detection. Some suitable locations for the crack detection structure are described below.

[0119] refer to Figure 9A This illustrates multiple bond crack detection structures integrated into a SoC (System-on-a-Chip) package according to exemplary embodiments of the present disclosure, and refers to... Figure 9B This illustrates multiple bond crack detection structures integrated into a wafer comprising multiple SoCs according to exemplary embodiments of the present disclosure.

[0120] like Figure 9A As shown, according to this exemplary embodiment, as previously described, a plurality of bond crack detection structures 1001 are formed outside or just inside the peripheral region of the SoC 1002, excluding functional MOSFETs or other functional circuitry of the SoC. By positioning the bond crack detection structures at the locations shown, the overall likelihood of detecting bond cracks can be increased, as bond cracks are more likely to occur at these locations. Furthermore, the location of the bond crack detection structures 1001 at these peripheral locations may be practical due to their association with the location of the SoC in the central region of the semiconductor die. However, it should be understood that the location of the bond crack detection structures is not limited to... Figure 9A The location shown can be in other areas of the SoC 1002.

[0121] After forming the SoC 1002 including the bond crack detection structure 1001, the SoC die 1002 is subjected to E test (ATE 401) to determine whether any bond cracks are present, as previously described.

[0122] like Figure 9B As shown, according to this exemplary embodiment, the wafer or die is a complete wafer 1003, and an array of integrated circuits (ICs) 1002 is fabricated on the wafer 1003. Here, as previously described, a plurality of bond crack detection structures 1001 are formed on the peripheral regions of a plurality of ICs 1002 formed on the wafer 1003. In some embodiments, the bond crack detection structures 1001 are disposed in dicing channels extending between the ICs 1002 (wherein the dicing channels are predetermined to cut the wafer 1003 as individual ICs 1002 are diced to form IC dies). By positioning the bond crack detection structures at the locations shown, the overall probability of detecting bond cracks can be increased, as bond cracks are more likely to occur at these locations. Furthermore, it is feasible to locate the bond crack detection structures 1001 at these peripheral locations for reasons associated with forming the bond crack detection structures 1001 in the dicing channels of the wafer 1003.

[0123] After forming a wafer 1003 including a bond crack detection structure 1001, the wafer 1003 is subjected to an E test (ATE401) to determine whether any bond cracks are present, as previously described.

[0124] refer to Figure 10This illustrates a process for manufacturing a semiconductor die stack including multiple bond crack detection structures, according to an exemplary embodiment of the present disclosure, within the context of a high-level graphical display of the entire semiconductor manufacturing workflow. In this example, die-to-wafer bonding is performed.

[0125] First, in step S101, the bottom die 101 is manufactured, and in step S102, one or more bond crack detection structure portions 1001A are attached and bonded to the metallization layer 1011 of the bottom die 101 using a hybrid bonding forming process.

[0126] Independent of steps S101 and S102, in step S201, the top die 201 is fabricated and processed to include the SoC and the metallization layer 1012. Then, in step S202, one or more bond crack detection structure portions 1001B are attached and bonded to the top die 201 using a hybrid bonding formation process. Next, in step S203, a die monolithization process is used to isolate (i.e., separate) multiple SoC dies (201A and 201B) and the bond crack detection structure 1001 associated with the trench or via 1005.

[0127] Next, in step S301, the bottom die 101 is bonded to the top die 201 using a hybrid bonding process, and a filler material (e.g., a polymer) is deposited onto the isolation region 1005. It is during this bonding process that the complete bonded crack detection structure 1001 is formed, thereby creating a bonded crack detection vertical detection region of length VDRh. Furthermore, further processing includes forming a plurality of first horizontal interconnects 1004 within the metallization layer 1011.

[0128] Next, at step S302, the substrate (oS) is diced, i.e., die monolithization, and the chip is packaged for transport (step S303). Advantageously, the bond crack detection structure 1001 can be tested at any time after step S301, as previously described. For example, the diced die can be crack tested during the wafer-level chip packaging (WLCP) testing phase and / or during final testing (FT).

[0129] refer to Figure 11 This illustrates a process for manufacturing a semiconductor wafer stack including multiple bond crack detection structures 1001, according to an exemplary embodiment of the present disclosure, within the context of a high-level graphical display of the entire semiconductor manufacturing workflow. In this example, wafer-to-wafer bonding is performed.

[0130] First, in step S1101, the bottom wafer 1101 is fabricated, and one or more bond crack detection structure portions 1001A are attached and bonded to the metallization layer of the bottom wafer 1101 using a hybrid bonding formation process.

[0131] Independent of step S1101, at step S1201, the top wafer 1102 is manufactured and processed to include a plurality of SoCs 1002 and one or more bond crack detection structure portions 1001B are attached and bonded to the top wafer 1102.

[0132] Next, in step S1301, a hybrid bonding process is used to bond the bottom wafer 1101 to the top wafer 1102. It is during this bonding process that the complete bonding crack detection structure 1001 is formed, as shown in the reference... Figure 10 The subject of discussion.

[0133] Next, at step S1302, the substrate (oS) is diced, i.e., die monolithization, and used to isolate (i.e., separate) multiple SoC dies (1002) and the associated bond crack detection structure 1001. The chip is then packaged for transport (step S1303). The bond crack detection structure 1001 can be tested at any time after step S1301 as described above. For example, crack testing can be performed on the diced dies during the wafer-level chip packaging (WLCP) testing phase and / or during final testing (FT).

[0134] The following provides another method for processing semiconductor stacks (e.g., dies or wafers, said dies or wafers including the bond crack detection structure as described above).

[0135] Methods for handling semiconductor stacks include:

[0136] (a) Measuring the electrical characteristics of a bonding crack detection structure disposed at the interface between a first semiconductor wafer or die of a semiconductor stack and a second semiconductor wafer or die of a semiconductor stack bonded to the first semiconductor wafer or die of the semiconductor stack, the bonding crack detection structure comprising:

[0137] The first conductor includes a first set of metal bonding bumps on a first semiconductor wafer or die and a third set of metal bonding bumps on a second semiconductor wafer or die, the third set of metal bonding bumps being bonded to the first set of metal bonding bumps on the first semiconductor wafer or die; and the second conductor includes a second set of metal bonding bumps on a first semiconductor wafer or die and a fourth set of metal bonding bumps on a second semiconductor wafer or die, the fourth set of metal bonding bumps being bonded to the second set of metal bonding bumps on the first semiconductor wafer or die, wherein the first conductor and the second conductor are electrically isolated from each other in the absence of bonding cracks;

[0138] (b) Based on the measured electrical characteristics of the bond crack detection structure, determining that the bond crack does not exist at the interface between the first semiconductor wafer or die and the second semiconductor wafer or die in the semiconductor stack, wherein the electrical characteristics include, but are not limited to, the current flowing between the first and second conductors in response to a voltage applied across the first and second conductors; and

[0139] (c) In response to determining that there are no bonding cracks at the interface between the first semiconductor wafer or die and the second semiconductor wafer or die of the semiconductor stack, the semiconductor stack is cut.

[0140] Based on the above discussion, it is clear that this disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, nor are all embodiments required to have specific advantages. One advantage is that the disclosed bond crack detection structure prevents time-consuming physical failure analysis to determine whether bond stack dies and / or stacked wafers have failed due to one or more bond interface cracks.

[0141] Below, some further embodiments are described.

[0142] In a non-limiting illustrative embodiment, the semiconductor structure includes: a first semiconductor die including a first bonding crack detection structure portion, the first bonding crack detection structure portion including a first set of metal bonding pads operably connected to a bonding interface side of the first semiconductor die and a second set of metal bonding pads operably connected to a bonding interface side of the first semiconductor die, the second set of metal bonding pads being electrically isolated from the first set of metal bonding pads; and a second semiconductor die bonded to the first semiconductor die, the second semiconductor die including a second bonding crack detection structure bonded to the first bonding crack detection structure portion. In one embodiment, the second bond crack detection structure includes a third set of metal bonding pads operably connected to the bonding interface side of the second semiconductor die, and a fourth set of metal bonding pads operably connected to the bonding interface side of the second semiconductor die. The fourth set of metal bonding pads is electrically isolated from the third set of metal bonding pads. The first and second bond crack detection structures are bonded together to form the bond crack detection structure, wherein the first and third sets of metal bonding pads are electrically connected, and the second and fourth sets of metal bonding pads are electrically connected. In some embodiments, the bond crack detection structure includes a capacitor, comprising: a first conductor of the capacitor including the first and third sets of metal bonding pads electrically connected together; a second conductor of the capacitor including the second and fourth sets of metal bonding pads electrically connected together; and an insulator of the capacitor including a gap between the first and second conductors of the capacitor. In some embodiments, the bond crack detection structure includes an interdigitated capacitor. In some embodiments, the interdigitated bond crack detection structure further includes: a first group of metal bond pads arranged as a plurality of electrically connected, parallel-extending first group of metal bond pad fingers, each of the first group of metal bond pad fingers being laterally offset from each other by a lateral offset distance; and a second group of metal bond pads arranged as a plurality of electrically connected, parallel-extending second group of metal bond pad fingers, each of the second group of metal bond pad fingers being laterally offset from each other by a lateral offset distance, and the second group of metal bond pad fingers intersecting each other between and / or adjacent to the first group of metal bond pad fingers. A set of metal bonding pad fingers; and a third set of metal bonding pads arranged as a plurality of electrically connected, parallel-extending third set of metal bonding pad fingers, each of the third set of metal bonding pad fingers being laterally offset from each other by a lateral offset distance; and a fourth set of metal bonding pads arranged as a plurality of electrically connected, parallel-extending fourth set of metal bonding pad fingers, each of the fourth set of metal bonding pad fingers being laterally offset from each other by a lateral offset distance, and the fourth set of metal bonding pad fingers intersecting each other between and / or adjacent to the third set of metal bonding pad fingers.In some embodiments, bonding pad vias interconnect a first set of metal bonding pad fingers, a second set of metal bonding pad fingers, a third set of metal bonding pad fingers, and a fourth set of metal bonding pad fingers to their respective metal bonding pads. In some embodiments, a bond crack detection structure is formed in a first intermetallic dielectric (IMD) layer of a first semiconductor die or wafer and a second IMD layer associated with a second semiconductor die or wafer; each of the metal bonding pads of the first group of metal bonding pads, the second group of metal bonding pads, the third group of metal bonding pads, and the fourth group of metal bonding pads has a BPM thickness associated with the thickness of the sidewalls of the metal bonding pad, wherein the BPM thickness of each metal bonding pad in the first IMD layer is equal to 1% to 100% of the height of the first IMD layer, and the BPM thickness of each metal bonding pad in the second IMD layer is equal to 1% to 100% of the height of the second IMD layer; and each of the first group of metal bonding pads, the second group of metal bonding pads, the third group of metal bonding pads, and the fourth group of metal bonding pads is defined to have a BPM count and a BPM pitch, wherein the BPM pitch is associated with the spacing of the metal bonding pads, and the BPM count is equal to 1 to the width of the semiconductor structure divided by the BPM pitch. In some embodiments, the first semiconductor die or wafer includes a first intermetallic dielectric (IMD) electrically connected to a first set of metal bonding pads and a second IMD electrically connected to a second set of metal bonding pads, the second IMD being electrically isolated from the first IMD. The first and second IMDs are each connected to a first horizontal interconnect, which is configured to be operatively connected to a leakage current testing unit to measure leakage current and detect bonding cracks based on the measured leakage current. In some embodiments, the metal bonding pads are circular, elliptical, or polygonal. In some embodiments, the bonding crack detection structure is positioned along one or more edges of the semiconductor structure, or along one or more edges of the first semiconductor die or wafer and the second semiconductor die or wafer.

[0143] In another non-limiting illustrative embodiment, the semiconductor structure includes: a first semiconductor wafer including a first bonding crack detection structure portion, the first bonding crack detection structure portion including a first set of metal bonding pads operably connected to a bonding interface side of the first semiconductor wafer and a second set of metal bonding pads operably connected to a bonding interface side of the first semiconductor wafer, the second set of metal bonding pads being electrically isolated from the first set of metal bonding pads; and a second semiconductor wafer bonded to the first semiconductor wafer, the second semiconductor wafer including a second bonding crack detection structure bonded to the first bonding crack detection structure portion. In terms of structure, the second bonding crack detection structure includes a third set of metal bonding pads operably connected to the bonding interface side of the second semiconductor wafer, and a fourth set of metal bonding pads operably connected to the bonding interface side of the second semiconductor wafer. The fourth set of metal bonding pads is electrically isolated from the third set of metal bonding pads. The first and second bonding crack detection structures are bonded together to form the bonding crack detection structure, wherein the first and third sets of metal bonding pads are electrically connected, and the second and fourth sets of metal bonding pads are electrically connected. In some embodiments, the bonding crack detection structure includes a capacitor, which includes: a first conductor of the capacitor comprising the first and third sets of metal bonding pads electrically connected together; and a second conductor of the capacitor comprising the second and fourth sets of metal bonding pads electrically connected together. In some embodiments, the bonding crack detection structure includes an interdigitated capacitor. In some embodiments, the interdigitated bond crack detection structure further includes: a first group of metal bond pads arranged as a plurality of electrically connected, parallel-extending first group of metal bond pad fingers, each of the first group of metal bond pad fingers being laterally offset from each other by a lateral offset distance; and a second group of metal bond pads arranged as a plurality of electrically connected, parallel-extending second group of metal bond pad fingers, each of the second group of metal bond pad fingers being laterally offset from each other by a lateral offset distance, and the second group of metal bond pad fingers intersecting each other between and / or adjacent to the first group of metal bond pad fingers. A first set of metal bonding pad fingers; and a third set of metal bonding pads arranged as a plurality of electrically connected, parallel-extending third set of metal bonding pad fingers, each of the third set of metal bonding pad fingers being laterally offset from each other by a lateral offset distance; and a fourth set of metal bonding pads arranged as a plurality of electrically connected, parallel-extending fourth set of metal bonding pad fingers, each of the fourth set of metal bonding pad fingers being laterally offset from each other by a lateral offset distance, and the fourth set of metal bonding pad fingers intersecting each other between and / or adjacent to the third set of metal bonding pad fingers. In some embodiments, bonding pad vias interconnect the first set of metal bonding pad fingers, the second set of metal bonding pad fingers, the third set of metal bonding pad fingers, and the fourth set of metal bonding pad fingers to their respective metal bonding pads.In some embodiments, a bond crack detection structure is formed in a first intermetallic dielectric (IMD) layer of a first semiconductor wafer and a second IMD layer associated with a second semiconductor wafer; each of the metal bonding pads of the first group of metal bonding pads, the second group of metal bonding pads, the third group of metal bonding pads, and the fourth group of metal bonding pads has a BPM thickness associated with the thickness of the sidewalls of the metal bonding pad, wherein the BPM thickness of each metal bonding pad in the first IMD layer is equal to 1% to 100% of the height of the first IMD layer, and the BPM thickness of each metal bonding pad in the second IMD layer is equal to 1% to 100% of the height of the second IMD layer; and each of the first group of metal bonding pads, the second group of metal bonding pads, the third group of metal bonding pads, and the fourth group of metal bonding pads is defined to have a BPM count and a BPM pitch, wherein the BPM pitch is associated with the spacing of the metal bonding pads, and the BPM count is equal to 1 to the width of the semiconductor structure divided by the BPM pitch. In some embodiments, the first semiconductor wafer includes a first intermetallic dielectric (IMD) electrically connected to a first set of metal bonding pads and a second IMD electrically connected to a second set of metal bonding pads, the second IMD being electrically isolated from the first IMD. The first and second IMDs are each connected to a first horizontal interconnect, which is configured to be operatively connected to a leakage current testing unit to measure leakage current and detect bonding cracks based on the measured leakage current. In some embodiments, the metal bonding pads are circular, elliptical, or polygonal. In some embodiments, the bonding crack detection structure is located along one or more edges of the semiconductor structure, along one or more edges of a plurality of dies located on the first and second semiconductor wafers, or located in one or more dices on the first and second semiconductor wafers.

[0144] In another non-limiting illustrative embodiment, a method for processing a semiconductor stack includes: measuring the electrical characteristics of a bonding crack detection structure disposed at an interface between a first semiconductor wafer or die of the semiconductor stack and a second semiconductor wafer or die of the semiconductor stack bonded to the first semiconductor wafer or die of the semiconductor stack, the bonding crack detection structure comprising: a first conductor including a first set of metal bonding bumps of the first semiconductor wafer or die and a third set of metal bonding bumps of the second semiconductor wafer or die, the third set of metal bonding bumps being bonded to the first set of metal bonding bumps of the first semiconductor wafer or die; and a second conductor including the first semiconductor wafer or die. A second set of metal bonding bumps on a wafer or die and a fourth set of metal bonding bumps on a second semiconductor wafer or die, the fourth set of metal bonding bumps being bonded to the second set of metal bonding bumps on a first semiconductor wafer or die, wherein the first conductor and the second conductor are electrically isolated from each other in the absence of bonding cracks; determining, based on the measured electrical characteristics of the bonding crack detection structure, that bonding cracks do not exist at the interface between the first semiconductor wafer or die and the second semiconductor wafer or die in the semiconductor stack; and, in response to determining that there are no bonding cracks at the interface between the first semiconductor wafer or die and the second semiconductor wafer or die in the semiconductor stack, dicing the semiconductor stack. In some embodiments, the electrical characteristics are the current flowing between the first conductor and the second conductor in response to a voltage applied across the first conductor and the second conductor.

[0145] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized by, include: A first semiconductor die or wafer includes a first bonding crack detection structure portion, the first bonding crack detection structure portion including a first set of metal bonding pads operably connected to the bonding interface side of the first semiconductor die or wafer and a second set of metal bonding pads operably connected to the bonding interface side of the first semiconductor die or wafer, the second set of metal bonding pads being electrically isolated from the first set of metal bonding pads. as well as A second semiconductor die or wafer is bonded to a first semiconductor die or wafer. The second semiconductor die or wafer includes a second bonding crack detection structure portion bonded to the first bonding crack detection structure portion. The second bonding crack detection structure portion includes a third set of metal bonding pads operably connected to the bonding interface side of the second semiconductor die or wafer, and a fourth set of metal bonding pads operably connected to the bonding interface side of the second semiconductor die or wafer. The fourth set of metal bonding pads is electrically isolated from the third set of metal bonding pads. The first bond crack detection structure and the second bond crack detection structure are bonded together to form a bond crack detection structure, wherein the first group of metal bonding pads and the third group of metal bonding pads are electrically connected together, and the second group of metal bonding pads and the fourth group of metal bonding pads are electrically connected together.

2. The semiconductor structure of claim 1, wherein, The bond crack detection structure includes a capacitor, the capacitor comprising: The first conductor of the capacitor includes a first set of metal bonding pads and a third set of metal bonding pads that are electrically connected together; The second conductor of the capacitor includes a second set of metal bonding pads and a fourth set of metal bonding pads electrically connected together; and The insulator of the capacitor includes the gap between the first conductor and the second conductor of the capacitor.

3. The semiconductor structure of claim 1, wherein, The bonding crack detection structure includes interdigitated capacitors.

4. The semiconductor structure of claim 3, wherein, The interdigitated bond crack detection structure further includes: The first set of metal bonding pads is arranged as a plurality of electrically connected, parallel-extending first set of metal bonding pad fingers, each of the first set of metal bonding pad fingers being laterally offset from each other by a lateral offset distance. The second set of metal bonding pads is arranged as a plurality of electrically connected, parallel-extending second set of metal bonding pad fingers, each of the second set of metal bonding pad fingers being laterally offset from the lateral offset distance of the first set of fingers. The second set of metal bonding pad fingers intersects with each other between and / or adjacent to the first set of metal bonding pad fingers. The third group of metal bonding pads is arranged as a plurality of electrically connected, parallel-extending third group of metal bonding pad fingers, each of the third group of metal bonding pad fingers being laterally offset from each other by a lateral offset distance. The fourth group of metal bonding pads is arranged as a plurality of electrically connected, parallel-extending fourth group of metal bonding pad fingers, each of the fourth group of metal bonding pad fingers being laterally offset from each other by a lateral offset distance. The fourth group of metal bonding pad fingers intersects between and / or is adjacent to the third group of metal bonding pad fingers.

5. The semiconductor structure of claim 4, wherein, Bond pad vias (BPVs) interconnect the first set of metal bond pad fingers, the second set of metal bond pad fingers, the third set of metal bond pad fingers, and the fourth set of metal bond pad fingers to their respective metal bond pads.

6. A semiconductor structure, characterized by include: A first semiconductor wafer includes a first bonding crack detection structure portion, the first bonding crack detection structure portion including a first set of metal bonding pads operably connected to the bonding interface side of the first semiconductor wafer and a second set of metal bonding pads operably connected to the bonding interface side of the first semiconductor, the second set of metal bonding pads being electrically isolated from the first set of metal bonding pads. as well as A second semiconductor wafer is bonded to the first semiconductor wafer. The second semiconductor wafer includes a second bond crack detection structure portion bonded to the first bond crack detection structure portion. The second bond crack detection structure portion includes a third set of metal bonding pads operably connected to the bonding interface side of the second semiconductor wafer and a fourth set of metal bonding pads operably connected to the bonding interface side of the second semiconductor wafer. The fourth set of metal bonding pads is electrically isolated from the third set of metal bonding pads. The first and second bonded crack detection structures are bonded together to form a bonded crack detection structure, wherein the first group of metal bonding pads and the third group of metal bonding pads are electrically connected together, and the second group of metal bonding pads and the fourth group of metal bonding pads are electrically connected together.

7. The semiconductor structure of claim 6, wherein, The bond crack detection structure includes a capacitor, the capacitor comprising: The first conductor of the capacitor includes a first set of metal bonding pads and a third set of metal bonding pads electrically connected together; and The second conductor of the capacitor includes a second set of metal bonding pads and a fourth set of metal bonding pads that are electrically connected together.

8. The semiconductor structure of claim 6, wherein, The bonding crack detection structure includes interdigitated capacitors.

9. The semiconductor structure of claim 8, wherein, The interdigitated bond crack detection structure further includes: The first set of metal bonding pads is arranged as a plurality of electrically connected, parallel-extending first set of metal bonding pad fingers, each of the first set of metal bonding pad fingers being laterally offset from each other by a lateral offset distance. The second set of metal bonding pads is arranged as a plurality of electrically connected, parallel-extending second set of metal bonding pad fingers, each of the second set of metal bonding pad fingers being laterally offset from the lateral offset distance of the first set of fingers. The second set of metal bonding pad fingers intersects with each other between and / or adjacent to the first set of metal bonding pad fingers. The third group of metal bonding pads is arranged as a plurality of electrically connected, parallel-extending third group of metal bonding pad fingers, each of the third group of metal bonding pad fingers being laterally offset from each other by a lateral offset distance. The fourth group of metal bonding pads is arranged as a plurality of electrically connected, parallel-extending fourth group of metal bonding pad fingers, each of the fourth group of metal bonding pad fingers being laterally offset from each other by a lateral offset distance. The fourth group of metal bonding pad fingers intersects between and / or is adjacent to the third group of metal bonding pad fingers.

10. The semiconductor structure of claim 9, wherein, Bond pad vias (BPVs) interconnect the first set of metal bond pad fingers, the second set of metal bond pad fingers, the third set of metal bond pad fingers, and the fourth set of metal bond pad fingers to their respective metal bond pads.

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